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X-OriginatorOrg: phytec.de X-MS-Exchange-CrossTenant-OriginalArrivalTime: 24 Sep 2025 11:59:11.7323 (UTC) X-MS-Exchange-CrossTenant-Network-Message-Id: d68159af-44c7-4629-a2d2-08ddfb61c68d X-MS-Exchange-CrossTenant-Id: e609157c-80e2-446d-9be3-9c99c2399d29 X-MS-Exchange-CrossTenant-OriginalAttributedTenantConnectingIp: TenantId=e609157c-80e2-446d-9be3-9c99c2399d29;Ip=[91.26.50.189];Helo=[Postix.phytec.de] X-MS-Exchange-CrossTenant-AuthSource: DB1PEPF000509EB.eurprd03.prod.outlook.com X-MS-Exchange-CrossTenant-AuthAs: Anonymous X-MS-Exchange-CrossTenant-FromEntityHeader: HybridOnPrem X-MS-Exchange-Transport-CrossTenantHeadersStamped: AM9P195MB1079 The same displays that can be connected directly to the imx8mp-phyboard-pollux can also be connected to the expansion board PEB-AV-10. For displays connected to the expansion board, a second LVDS channel of the i.MX 8M Plus SoC is used and only a single display connected to the SoC LVDS display bridge at a given time is supported. Signed-off-by: Yannic Moog --- arch/arm64/boot/dts/freescale/Makefile | 6 +++ ...mp-phyboard-pollux-peb-av-10-etml1010g3dra.dtso | 45 ++++++++++++++++++= ++++ ...8mp-phyboard-pollux-peb-av-10-ph128800t006.dtso | 45 ++++++++++++++++++= ++++ 3 files changed, 96 insertions(+) diff --git a/arch/arm64/boot/dts/freescale/Makefile b/arch/arm64/boot/dts/f= reescale/Makefile index 9c121041128972d2239e2cc74df98b0bf7de1ac2..e4b097446440f41785dd1a0e5d3= 54796e800ee76 100644 --- a/arch/arm64/boot/dts/freescale/Makefile +++ b/arch/arm64/boot/dts/freescale/Makefile @@ -222,11 +222,17 @@ imx8mp-phyboard-pollux-etml1010g3dra-dtbs +=3D imx8mp= -phyboard-pollux-rdk.dtb \ imx8mp-phyboard-pollux-etml1010g3dra.dtbo imx8mp-phyboard-pollux-peb-av-10-dtbs +=3D imx8mp-phyboard-pollux-rdk.dtb \ imx8mp-phyboard-pollux-peb-av-10.dtbo +imx8mp-phyboard-pollux-peb-av-10-etml1010g3dra-dtbs +=3D imx8mp-phyboard-p= ollux-rdk.dtb \ + imx8mp-phyboard-pollux-peb-av-10-etml1010g3dra.dtbo +imx8mp-phyboard-pollux-peb-av-10-ph128800t006-dtbs +=3D imx8mp-phyboard-po= llux-rdk.dtb \ + imx8mp-phyboard-pollux-peb-av-10-ph128800t006.dtbo imx8mp-phyboard-pollux-ph128800t006-dtbs +=3D imx8mp-phyboard-pollux-rdk.d= tb \ imx8mp-phyboard-pollux-ph128800t006.dtbo imx8mp-phyboard-pollux-rdk-no-eth-dtbs +=3D imx8mp-phyboard-pollux-rdk.dtb= imx8mp-phycore-no-eth.dtbo dtb-$(CONFIG_ARCH_MXC) +=3D imx8mp-phyboard-pollux-etml1010g3dra.dtb dtb-$(CONFIG_ARCH_MXC) +=3D imx8mp-phyboard-pollux-peb-av-10.dtb +dtb-$(CONFIG_ARCH_MXC) +=3D imx8mp-phyboard-pollux-peb-av-10-etml1010g3dra= .dtb +dtb-$(CONFIG_ARCH_MXC) +=3D imx8mp-phyboard-pollux-peb-av-10-ph128800t006.= dtb dtb-$(CONFIG_ARCH_MXC) +=3D imx8mp-phyboard-pollux-ph128800t006.dtb dtb-$(CONFIG_ARCH_MXC) +=3D imx8mp-phyboard-pollux-rdk-no-eth.dtb dtb-$(CONFIG_ARCH_MXC) +=3D imx8mp-skov-basic.dtb diff --git a/arch/arm64/boot/dts/freescale/imx8mp-phyboard-pollux-peb-av-10= -etml1010g3dra.dtso b/arch/arm64/boot/dts/freescale/imx8mp-phyboard-pollux-= peb-av-10-etml1010g3dra.dtso new file mode 100644 index 0000000000000000000000000000000000000000..d71945430c801a0136a95d691af= 0cec64622a066 --- /dev/null +++ b/arch/arm64/boot/dts/freescale/imx8mp-phyboard-pollux-peb-av-10-etml10= 10g3dra.dtso @@ -0,0 +1,45 @@ +// SPDX-License-Identifier: (GPL-2.0+ OR MIT) +/* + * Copyright (C) 2025 PHYTEC Messtechnik GmbH + */ + +/dts-v1/; +/plugin/; + +#include +#include +#include "imx8mp-phyboard-pollux-peb-av-10.dtsi" + +&backlight_lvds0 { + brightness-levels =3D <0 8 16 32 64 128 255>; + default-brightness-level =3D <8>; + enable-gpios =3D <&gpio5 1 GPIO_ACTIVE_HIGH>; + num-interpolated-steps =3D <2>; + pwms =3D <&pwm4 0 50000 0>; + status =3D "okay"; +}; + +&lcdif2 { + status =3D "okay"; +}; + +&lvds_bridge { + assigned-clocks =3D <&clk IMX8MP_CLK_MEDIA_LDB>, <&clk IMX8MP_VIDEO_PLL1>; + assigned-clock-parents =3D <&clk IMX8MP_VIDEO_PLL1_OUT>; + /* + * The LVDS panel uses 72.4 MHz pixel clock, set IMX8MP_VIDEO_PLL1 to + * 72.4 * 7 =3D 506.8 MHz so the LDB serializer and LCDIFv3 scanout + * engine can reach accurate pixel clock of exactly 72.4 MHz. + */ + assigned-clock-rates =3D <0>, <506800000>; + status =3D "okay"; +}; + +&panel_lvds0 { + compatible =3D "edt,etml1010g3dra"; + status =3D "okay"; +}; + +&pwm4 { + status =3D "okay"; +}; diff --git a/arch/arm64/boot/dts/freescale/imx8mp-phyboard-pollux-peb-av-10= -ph128800t006.dtso b/arch/arm64/boot/dts/freescale/imx8mp-phyboard-pollux-p= eb-av-10-ph128800t006.dtso new file mode 100644 index 0000000000000000000000000000000000000000..8ec4bbbbabb5cc7f5ae05d641fb= 5d14931250daf --- /dev/null +++ b/arch/arm64/boot/dts/freescale/imx8mp-phyboard-pollux-peb-av-10-ph1288= 00t006.dtso @@ -0,0 +1,45 @@ +// SPDX-License-Identifier: (GPL-2.0+ OR MIT) +/* + * Copyright (C) 2025 PHYTEC Messtechnik GmbH + */ + +/dts-v1/; +/plugin/; + +#include +#include +#include "imx8mp-phyboard-pollux-peb-av-10.dtsi" + +&backlight_lvds0 { + brightness-levels =3D <0 8 16 32 64 128 255>; + default-brightness-level =3D <8>; + enable-gpios =3D <&gpio5 1 GPIO_ACTIVE_HIGH>; + num-interpolated-steps =3D <2>; + pwms =3D <&pwm4 0 66667 0>; + status =3D "okay"; +}; + +&lcdif2 { + status =3D "okay"; +}; + +&lvds_bridge { + assigned-clocks =3D <&clk IMX8MP_CLK_MEDIA_LDB>, <&clk IMX8MP_VIDEO_PLL1>; + assigned-clock-parents =3D <&clk IMX8MP_VIDEO_PLL1_OUT>; + /* + * The LVDS panel uses 66.5 MHz pixel clock, set IMX8MP_VIDEO_PLL1 to + * 66.5 * 7 =3D 465.5 MHz so the LDB serializer and LCDIFv3 scanout + * engine can reach accurate pixel clock of exactly 66.5 MHz. + */ + assigned-clock-rates =3D <0>, <465500000>; + status =3D "okay"; +}; + +&panel_lvds0 { + compatible =3D "powertip,ph128800t006-zhc01"; + status =3D "okay"; +}; + +&pwm4 { + status =3D "okay"; +}; --=20 2.51.0