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[34.77.53.213]) by smtp.gmail.com with ESMTPSA id 5b1f17b1804b1-46e2a996bf1sm36541855e9.1.2025.09.24.08.15.19 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Wed, 24 Sep 2025 08:15:19 -0700 (PDT) From: Tudor Ambarus Date: Wed, 24 Sep 2025 15:14:41 +0000 Subject: [PATCH v4 1/3] arm64: dts: exynos: gs101: add #clock-cells to the ACPM protocol node Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Content-Transfer-Encoding: quoted-printable Message-Id: <20250924-acpm-dvfs-dt-v4-1-3106d49e03f5@linaro.org> References: <20250924-acpm-dvfs-dt-v4-0-3106d49e03f5@linaro.org> In-Reply-To: <20250924-acpm-dvfs-dt-v4-0-3106d49e03f5@linaro.org> To: Peter Griffin , =?utf-8?q?Andr=C3=A9_Draszik?= , Rob Herring , Krzysztof Kozlowski , Conor Dooley , Alim Akhtar , Catalin Marinas , Will Deacon Cc: linux-arm-kernel@lists.infradead.org, linux-samsung-soc@vger.kernel.org, devicetree@vger.kernel.org, linux-kernel@vger.kernel.org, willmcvicker@google.com, kernel-team@android.com, Tudor Ambarus X-Mailer: b4 0.14.2 X-Developer-Signature: v=1; a=ed25519-sha256; t=1758726918; l=984; i=tudor.ambarus@linaro.org; s=20241212; h=from:subject:message-id; bh=JmsEgZMHNR2hZ1IS9otwlJdT37DqVFuKcq466eHfWkM=; b=In9O47CfMkMqpQRFT0EdPf6ZFFTRjGsFERp5FOQXNztXjs5m7eOB+4DwpP5+7wmzH4t124xRS d0YD7QdbCAJAnxjbbNk8gD0ezAWG0lxXstJGjc/g0YGXRMyewTbLF9z X-Developer-Key: i=tudor.ambarus@linaro.org; a=ed25519; pk=uQzE0NXo3dIjeowMTOPCpIiPHEz12IA/MbyzrZVh9WI= Make the ACPM node a clock provider by adding the mandatory "#clock-cells" property, which allows devices to reference its clock outputs. Signed-off-by: Tudor Ambarus Reviewed-by: Peter Griffin Tested-by: Peter Griffin # on gs101-oriole --- arch/arm64/boot/dts/exynos/google/gs101.dtsi | 1 + 1 file changed, 1 insertion(+) diff --git a/arch/arm64/boot/dts/exynos/google/gs101.dtsi b/arch/arm64/boot= /dts/exynos/google/gs101.dtsi index 31c99526470d0bb946d498f7546e70c84ed4845b..f88d45a368af7ef88e8cdc84b3a= 81a63a753832c 100644 --- a/arch/arm64/boot/dts/exynos/google/gs101.dtsi +++ b/arch/arm64/boot/dts/exynos/google/gs101.dtsi @@ -202,6 +202,7 @@ ext_200m: clock-2 { firmware { acpm_ipc: power-management { compatible =3D "google,gs101-acpm-ipc"; + #clock-cells =3D <1>; mboxes =3D <&ap2apm_mailbox>; shmem =3D <&apm_sram>; }; --=20 2.51.0.536.g15c5d4f767-goog From nobody Thu Oct 2 00:49:17 2025 Received: from mail-wr1-f42.google.com (mail-wr1-f42.google.com [209.85.221.42]) (using TLSv1.2 with cipher ECDHE-RSA-AES128-GCM-SHA256 (128/128 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id 33A1930DEC4 for ; Wed, 24 Sep 2025 15:15:22 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=none smtp.client-ip=209.85.221.42 ARC-Seal: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1758726925; cv=none; b=ljQrHg/23LdAaqJAHxhIQtYWxqLl6veU7t6uQW49q7shpUs4G5kSNdqy3sipsMsE0L3p2FNFFR4ss8pSwfuqPZSf9Dec9D7Cr+zrVvJOKflOWzEGG+vN5jAt+RepEacb6mo0iONGHWHKGXygvijk9cbA1odBBCaUN2y8KlOv/i0= ARC-Message-Signature: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1758726925; c=relaxed/simple; bh=fbP+TlGg3NLAStwFGbaJsLnhS+YJCTLqAERnvsIlpbU=; h=From:Date:Subject:MIME-Version:Content-Type:Message-Id:References: In-Reply-To:To:Cc; b=ByA79Q9wLyd6V7Hg+S/L/47U9oiFf+CoixkmetweLw2u8D1u+c1lsNb3hHfIASntmX5s4AKAiOj/pCzJsiMsuCVBSmFJHFslhXx85EbuPn3eep+OfFXMW3J3i9opoRolNqrJe7VAFMCQAa7m+a9Mhw6nDInakoYuMMbcwgwUL+k= ARC-Authentication-Results: i=1; smtp.subspace.kernel.org; dmarc=pass (p=none dis=none) header.from=linaro.org; spf=pass smtp.mailfrom=linaro.org; dkim=pass (2048-bit key) header.d=linaro.org header.i=@linaro.org header.b=IoN95KSI; arc=none smtp.client-ip=209.85.221.42 Authentication-Results: smtp.subspace.kernel.org; dmarc=pass (p=none dis=none) header.from=linaro.org Authentication-Results: smtp.subspace.kernel.org; spf=pass smtp.mailfrom=linaro.org Authentication-Results: smtp.subspace.kernel.org; dkim=pass (2048-bit key) header.d=linaro.org header.i=@linaro.org header.b="IoN95KSI" Received: by mail-wr1-f42.google.com with SMTP id ffacd0b85a97d-3ee1317b1f7so3488689f8f.2 for ; Wed, 24 Sep 2025 08:15:22 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; t=1758726921; x=1759331721; darn=vger.kernel.org; h=cc:to:in-reply-to:references:message-id:content-transfer-encoding :mime-version:subject:date:from:from:to:cc:subject:date:message-id :reply-to; bh=yH8er2WLBKFy2pvhJtg/nSPNfqLqFULuGIksUuRQwfc=; b=IoN95KSIwvcAZtzEgfb4Az9yz/3zwsa6R/01ugjV1orzswNz43zDNgPIbiPjslWYx0 P07KSGPzjFuc+ZIws9Nk2whxl+ShBZraIQDCVsCVDbSyp0S+Ht91A0emE5r27Mg7/7Xa FzoZewr0Dmp6ZoJUPuWFkjobgXjVnH+6kR2QXlpe7Fuu7zhuMLGNAEvy7+sp3jZRdOvQ A6CfVr3KWRhgPfeBOsI/k4poj3GybLlPGVrD8QLoUqM/BJ/KvvFiO+km6OQBGxtE8SQq UeN/BFYK3yDJp0ZmxJcBIGKB7cfdjO/SNFsdTn73BNEJ6D4yfWyj//Q6QDSnsruKf5Bx 7S8Q== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20230601; t=1758726921; x=1759331721; h=cc:to:in-reply-to:references:message-id:content-transfer-encoding :mime-version:subject:date:from:x-gm-message-state:from:to:cc :subject:date:message-id:reply-to; bh=yH8er2WLBKFy2pvhJtg/nSPNfqLqFULuGIksUuRQwfc=; b=kq7FbXoP0Lp+OwFKKi8ewR/UdDfiqlKqcCG7V4Fpbbh4vsFKR1eJn3R0Y+qQagMwaW 8ASRTL5S22MRAUroFx2BtlFh16ndMj5NRKX79bUIgk/zoVU7h7ReG5eRikUpkwAZp6JW 3N/Xi9iDJzmlx+cLLWP0Zngne3gaioeUC58aDz+hS9xEq9jWoL9ZMPD0whTyh0KYX1mO vbRPSV90s3I1/uZNwqVEZO/NRvwrM5ZMY4ylXCXXK0msgPGh2oZGC1C1LUfKSsQKAcSu nsn31KRdvODZe9pHTcrekDS8wW3XykradQnHW3UV8SiY8TcSWX8qgxL8KGuXT+qQv+h1 s0aA== X-Forwarded-Encrypted: i=1; AJvYcCX6A1np3ZpH/d/b6R94KYjzj3EWgd9DsBHUSlpB4vWgF/DHqEmlmUxIp6CjDG4HwVtyL/tb9oG6u5maBt4=@vger.kernel.org X-Gm-Message-State: AOJu0YwFQdV/sTXPdKrRcOOxTLvwxl5mLXebj/irdde73R/h0u+hU1/5 DwzSuTIrSRXNlTLWNxRtZRf0R2m4fkplhY54Xk3E98F5zscHT2ZcKf+GBx+rqKGy9B4= X-Gm-Gg: ASbGncvdDCvDEgty9XHXAYOkOw9c7f0hbNXSr6G05p6dl8KHrvb7CA6XQPX5NumU5AK hrOh5Id1y8BiYrtpKa1YuF9y8WmFy+i5kMUSrKcLgjSxguA3ZMs1ZylZnNRLhDwbiEi6edmh0bu icwXdsHrzEqSC0XGPbDzRBiTiJvfNf/vqnY8GfaI8lLAt+pljtFJwZNK9wQ348iUd2FbMLvBjsZ 0v13Z32Tp+hKvsrMAh3YvXh4AmRpbcttw/tPbcDuZEhoCpjW72UG5YwW6Ymc8D7x5ihjqy+9thl MPhWdjSEzK7ElytUJ5ZbbzWq+n7mJbJQFcyRd6vGURQvoboxjdrbUfXP+Fm05vVFZUERvDh+9uc WTb4XxPBmZh/0tqSAKp9ivOw+wrJDJN5sOrUgQVc6Ss3LiSAsS/ZlyCLaBoMt9HAHgoj6x7qh/b k= X-Google-Smtp-Source: AGHT+IGgDCS8ayniuFNQT5/k9DeS1jl9iWus2UZI/q9DVCjLLBthhuyhs6xf+tcMVx3nO1q2hjSHog== X-Received: by 2002:a05:6000:1884:b0:402:a740:1edd with SMTP id ffacd0b85a97d-40e4ba3a51dmr315711f8f.39.1758726921493; Wed, 24 Sep 2025 08:15:21 -0700 (PDT) Received: from ta2.c.googlers.com (213.53.77.34.bc.googleusercontent.com. [34.77.53.213]) by smtp.gmail.com with ESMTPSA id 5b1f17b1804b1-46e2a996bf1sm36541855e9.1.2025.09.24.08.15.20 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Wed, 24 Sep 2025 08:15:20 -0700 (PDT) From: Tudor Ambarus Date: Wed, 24 Sep 2025 15:14:42 +0000 Subject: [PATCH v4 2/3] arm64: dts: exynos: gs101: add CPU clocks Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Content-Transfer-Encoding: quoted-printable Message-Id: <20250924-acpm-dvfs-dt-v4-2-3106d49e03f5@linaro.org> References: <20250924-acpm-dvfs-dt-v4-0-3106d49e03f5@linaro.org> In-Reply-To: <20250924-acpm-dvfs-dt-v4-0-3106d49e03f5@linaro.org> To: Peter Griffin , =?utf-8?q?Andr=C3=A9_Draszik?= , Rob Herring , Krzysztof Kozlowski , Conor Dooley , Alim Akhtar , Catalin Marinas , Will Deacon Cc: linux-arm-kernel@lists.infradead.org, linux-samsung-soc@vger.kernel.org, devicetree@vger.kernel.org, linux-kernel@vger.kernel.org, willmcvicker@google.com, kernel-team@android.com, Tudor Ambarus X-Mailer: b4 0.14.2 X-Developer-Signature: v=1; a=ed25519-sha256; t=1758726918; l=3181; i=tudor.ambarus@linaro.org; s=20241212; h=from:subject:message-id; bh=fbP+TlGg3NLAStwFGbaJsLnhS+YJCTLqAERnvsIlpbU=; b=jyG1osPC3rtt7uF+ad2Qp5/Or0/SPA2xOcoNoupHjypQ2VNpx8eT81G/wEh2mhALZVnNSsyJy 50+W5DUMM9RDHBOJrxr2gCo10bcNTUDZHNDByUXpXYqFLmrF+p/kXCo X-Developer-Key: i=tudor.ambarus@linaro.org; a=ed25519; pk=uQzE0NXo3dIjeowMTOPCpIiPHEz12IA/MbyzrZVh9WI= Add the GS101 CPU clocks exposed through the ACPM protocol. Signed-off-by: Tudor Ambarus Reviewed-by: Peter Griffin Tested-by: Peter Griffin # on gs101-oriole --- arch/arm64/boot/dts/exynos/google/gs101.dtsi | 9 +++++++++ 1 file changed, 9 insertions(+) diff --git a/arch/arm64/boot/dts/exynos/google/gs101.dtsi b/arch/arm64/boot= /dts/exynos/google/gs101.dtsi index f88d45a368af7ef88e8cdc84b3a81a63a753832c..7326801c9ebf270496997839185= 594c3c1776577 100644 --- a/arch/arm64/boot/dts/exynos/google/gs101.dtsi +++ b/arch/arm64/boot/dts/exynos/google/gs101.dtsi @@ -7,6 +7,7 @@ */ =20 #include +#include #include #include #include @@ -72,6 +73,7 @@ cpu0: cpu@0 { device_type =3D "cpu"; compatible =3D "arm,cortex-a55"; reg =3D <0x0000>; + clocks =3D <&acpm_ipc GS101_CLK_ACPM_DVFS_CPUCL0>; enable-method =3D "psci"; cpu-idle-states =3D <&ananke_cpu_sleep>; capacity-dmips-mhz =3D <250>; @@ -82,6 +84,7 @@ cpu1: cpu@100 { device_type =3D "cpu"; compatible =3D "arm,cortex-a55"; reg =3D <0x0100>; + clocks =3D <&acpm_ipc GS101_CLK_ACPM_DVFS_CPUCL0>; enable-method =3D "psci"; cpu-idle-states =3D <&ananke_cpu_sleep>; capacity-dmips-mhz =3D <250>; @@ -92,6 +95,7 @@ cpu2: cpu@200 { device_type =3D "cpu"; compatible =3D "arm,cortex-a55"; reg =3D <0x0200>; + clocks =3D <&acpm_ipc GS101_CLK_ACPM_DVFS_CPUCL0>; enable-method =3D "psci"; cpu-idle-states =3D <&ananke_cpu_sleep>; capacity-dmips-mhz =3D <250>; @@ -102,6 +106,7 @@ cpu3: cpu@300 { device_type =3D "cpu"; compatible =3D "arm,cortex-a55"; reg =3D <0x0300>; + clocks =3D <&acpm_ipc GS101_CLK_ACPM_DVFS_CPUCL0>; enable-method =3D "psci"; cpu-idle-states =3D <&ananke_cpu_sleep>; capacity-dmips-mhz =3D <250>; @@ -112,6 +117,7 @@ cpu4: cpu@400 { device_type =3D "cpu"; compatible =3D "arm,cortex-a76"; reg =3D <0x0400>; + clocks =3D <&acpm_ipc GS101_CLK_ACPM_DVFS_CPUCL1>; enable-method =3D "psci"; cpu-idle-states =3D <&enyo_cpu_sleep>; capacity-dmips-mhz =3D <620>; @@ -122,6 +128,7 @@ cpu5: cpu@500 { device_type =3D "cpu"; compatible =3D "arm,cortex-a76"; reg =3D <0x0500>; + clocks =3D <&acpm_ipc GS101_CLK_ACPM_DVFS_CPUCL1>; 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[34.77.53.213]) by smtp.gmail.com with ESMTPSA id 5b1f17b1804b1-46e2a996bf1sm36541855e9.1.2025.09.24.08.15.21 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Wed, 24 Sep 2025 08:15:21 -0700 (PDT) From: Tudor Ambarus Date: Wed, 24 Sep 2025 15:14:43 +0000 Subject: [PATCH v4 3/3] arm64: dts: exynos: gs101: add OPPs Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Content-Transfer-Encoding: quoted-printable Message-Id: <20250924-acpm-dvfs-dt-v4-3-3106d49e03f5@linaro.org> References: <20250924-acpm-dvfs-dt-v4-0-3106d49e03f5@linaro.org> In-Reply-To: <20250924-acpm-dvfs-dt-v4-0-3106d49e03f5@linaro.org> To: Peter Griffin , =?utf-8?q?Andr=C3=A9_Draszik?= , Rob Herring , Krzysztof Kozlowski , Conor Dooley , Alim Akhtar , Catalin Marinas , Will Deacon Cc: linux-arm-kernel@lists.infradead.org, linux-samsung-soc@vger.kernel.org, devicetree@vger.kernel.org, linux-kernel@vger.kernel.org, willmcvicker@google.com, kernel-team@android.com, Tudor Ambarus X-Mailer: b4 0.14.2 X-Developer-Signature: v=1; a=ed25519-sha256; t=1758726918; l=8583; i=tudor.ambarus@linaro.org; s=20241212; h=from:subject:message-id; bh=jAhvrkZLf2CPegU55/45LRXE53AONwSoY/Qaao8O1WI=; b=flkdtx3/cXrM2/ZNkt5KRthl5fEZMWNALCXLHO8aK4hPDkQ2+flX6YbpaTloDjdwikO8FMxGD 7vVqaXwRUPhBMu4sq6t/FdM0q7xG1+C5cfIf12vl+Pl5zBoNJdex6x4 X-Developer-Key: i=tudor.ambarus@linaro.org; a=ed25519; pk=uQzE0NXo3dIjeowMTOPCpIiPHEz12IA/MbyzrZVh9WI= Add operating performance points (OPPs). Signed-off-by: Tudor Ambarus Reviewed-by: Peter Griffin Tested-by: Peter Griffin # on gs101-oriole --- arch/arm64/boot/dts/exynos/google/gs101.dtsi | 275 +++++++++++++++++++++++= ++++ 1 file changed, 275 insertions(+) diff --git a/arch/arm64/boot/dts/exynos/google/gs101.dtsi b/arch/arm64/boot= /dts/exynos/google/gs101.dtsi index 7326801c9ebf270496997839185594c3c1776577..9d0d943fb08c9ff0fcc3c844598= 93a3ba92226fd 100644 --- a/arch/arm64/boot/dts/exynos/google/gs101.dtsi +++ b/arch/arm64/boot/dts/exynos/google/gs101.dtsi @@ -78,6 +78,7 @@ cpu0: cpu@0 { cpu-idle-states =3D <&ananke_cpu_sleep>; capacity-dmips-mhz =3D <250>; dynamic-power-coefficient =3D <70>; + operating-points-v2 =3D <&cpucl0_opp_table>; }; =20 cpu1: cpu@100 { @@ -89,6 +90,7 @@ cpu1: cpu@100 { cpu-idle-states =3D <&ananke_cpu_sleep>; capacity-dmips-mhz =3D <250>; dynamic-power-coefficient =3D <70>; + operating-points-v2 =3D <&cpucl0_opp_table>; }; =20 cpu2: cpu@200 { @@ -100,6 +102,7 @@ cpu2: cpu@200 { cpu-idle-states =3D <&ananke_cpu_sleep>; capacity-dmips-mhz =3D <250>; dynamic-power-coefficient =3D <70>; + operating-points-v2 =3D <&cpucl0_opp_table>; }; =20 cpu3: cpu@300 { @@ -111,6 +114,7 @@ cpu3: cpu@300 { cpu-idle-states =3D <&ananke_cpu_sleep>; capacity-dmips-mhz =3D <250>; dynamic-power-coefficient =3D <70>; + operating-points-v2 =3D <&cpucl0_opp_table>; }; =20 cpu4: cpu@400 { @@ -122,6 +126,7 @@ cpu4: cpu@400 { cpu-idle-states =3D <&enyo_cpu_sleep>; capacity-dmips-mhz =3D <620>; dynamic-power-coefficient =3D <284>; + operating-points-v2 =3D <&cpucl1_opp_table>; }; =20 cpu5: cpu@500 { @@ -133,6 +138,7 @@ cpu5: cpu@500 { cpu-idle-states =3D <&enyo_cpu_sleep>; capacity-dmips-mhz =3D <620>; dynamic-power-coefficient =3D <284>; + operating-points-v2 =3D <&cpucl1_opp_table>; }; =20 cpu6: cpu@600 { @@ -144,6 +150,7 @@ cpu6: cpu@600 { cpu-idle-states =3D <&hera_cpu_sleep>; capacity-dmips-mhz =3D <1024>; dynamic-power-coefficient =3D <650>; + operating-points-v2 =3D <&cpucl2_opp_table>; }; =20 cpu7: cpu@700 { @@ -155,6 +162,7 @@ cpu7: cpu@700 { cpu-idle-states =3D <&hera_cpu_sleep>; capacity-dmips-mhz =3D <1024>; dynamic-power-coefficient =3D <650>; + operating-points-v2 =3D <&cpucl2_opp_table>; }; =20 idle-states { @@ -192,6 +200,273 @@ hera_cpu_sleep: cpu-hera-sleep { }; }; =20 + cpucl0_opp_table: opp-table-0 { + compatible =3D "operating-points-v2"; + opp-shared; + + opp-300000000 { + opp-hz =3D /bits/ 64 <300000000>; + opp-microvolt =3D <537500>; + clock-latency-ns =3D <500000>; + }; + + opp-574000000 { + opp-hz =3D /bits/ 64 <574000000>; + opp-microvolt =3D <600000>; + clock-latency-ns =3D <500000>; + }; + + opp-738000000 { + opp-hz =3D /bits/ 64 <738000000>; + opp-microvolt =3D <618750>; + clock-latency-ns =3D <500000>; + }; + + opp-930000000 { + opp-hz =3D /bits/ 64 <930000000>; + opp-microvolt =3D <668750>; + clock-latency-ns =3D <500000>; + }; + + opp-1098000000 { + opp-hz =3D /bits/ 64 <1098000000>; + opp-microvolt =3D <712500>; + clock-latency-ns =3D <500000>; + }; + + opp-1197000000 { + opp-hz =3D /bits/ 64 <1197000000>; + opp-microvolt =3D <731250>; + clock-latency-ns =3D <500000>; + }; + + opp-1328000000 { + opp-hz =3D /bits/ 64 <1328000000>; + opp-microvolt =3D <762500>; + clock-latency-ns =3D <500000>; + }; + + opp-1401000000 { + opp-hz =3D /bits/ 64 <1401000000>; + opp-microvolt =3D <781250>; + clock-latency-ns =3D <500000>; + }; + + opp-1598000000 { + opp-hz =3D /bits/ 64 <1598000000>; + opp-microvolt =3D <831250>; + clock-latency-ns =3D <500000>; + }; + + opp-1704000000 { + opp-hz =3D /bits/ 64 <1704000000>; + opp-microvolt =3D <862500>; + clock-latency-ns =3D <500000>; + }; + + opp-1803000000 { + opp-hz =3D /bits/ 64 <1803000000>; + opp-microvolt =3D <906250>; + clock-latency-ns =3D <500000>; + }; + }; + + cpucl1_opp_table: opp-table-1 { + compatible =3D "operating-points-v2"; + opp-shared; + + opp-400000000 { + opp-hz =3D /bits/ 64 <400000000>; + opp-microvolt =3D <506250>; + clock-latency-ns =3D <500000>; + }; + + opp-553000000 { + opp-hz =3D /bits/ 64 <553000000>; + opp-microvolt =3D <537500>; + clock-latency-ns =3D <500000>; + }; + + opp-696000000 { + opp-hz =3D /bits/ 64 <696000000>; + opp-microvolt =3D <562500>; + clock-latency-ns =3D <500000>; + }; + + opp-799000000 { + opp-hz =3D /bits/ 64 <799000000>; + opp-microvolt =3D <581250>; + clock-latency-ns =3D <500000>; + }; + + opp-910000000 { + opp-hz =3D /bits/ 64 <910000000>; + opp-microvolt =3D <606250>; + clock-latency-ns =3D <500000>; + }; + + opp-1024000000 { + opp-hz =3D /bits/ 64 <1024000000>; + opp-microvolt =3D <625000>; + clock-latency-ns =3D <500000>; + }; + + opp-1197000000 { + opp-hz =3D /bits/ 64 <1197000000>; + opp-microvolt =3D <662500>; + clock-latency-ns =3D <500000>; + }; + + opp-1328000000 { + opp-hz =3D /bits/ 64 <1328000000>; + opp-microvolt =3D <687500>; + clock-latency-ns =3D <500000>; + }; + + opp-1491000000 { + opp-hz =3D /bits/ 64 <1491000000>; + opp-microvolt =3D <731250>; + clock-latency-ns =3D <500000>; + }; + + opp-1663000000 { + opp-hz =3D /bits/ 64 <1663000000>; + opp-microvolt =3D <775000>; + clock-latency-ns =3D <500000>; + }; + + opp-1836000000 { + opp-hz =3D /bits/ 64 <1836000000>; + opp-microvolt =3D <818750>; + clock-latency-ns =3D <500000>; + }; + + opp-1999000000 { + opp-hz =3D /bits/ 64 <1999000000>; + opp-microvolt =3D <868750>; + clock-latency-ns =3D <500000>; + }; + + opp-2130000000 { + opp-hz =3D /bits/ 64 <2130000000>; + opp-microvolt =3D <918750>; + clock-latency-ns =3D <500000>; + }; + + opp-2253000000 { + opp-hz =3D /bits/ 64 <2253000000>; + opp-microvolt =3D <968750>; + clock-latency-ns =3D <500000>; + }; + }; + + cpucl2_opp_table: opp-table-2 { + compatible =3D "operating-points-v2"; + opp-shared; + + opp-500000000 { + opp-hz =3D /bits/ 64 <500000000>; + opp-microvolt =3D <500000>; + clock-latency-ns =3D <500000>; + }; + + opp-851000000 { + opp-hz =3D /bits/ 64 <851000000>; + opp-microvolt =3D <556250>; + clock-latency-ns =3D <500000>; + }; + + opp-984000000 { + opp-hz =3D /bits/ 64 <984000000>; + opp-microvolt =3D <575000>; + clock-latency-ns =3D <500000>; + }; + + opp-1106000000 { + opp-hz =3D /bits/ 64 <1106000000>; + opp-microvolt =3D <606250>; + clock-latency-ns =3D <500000>; + }; + + opp-1277000000 { + opp-hz =3D /bits/ 64 <1277000000>; + opp-microvolt =3D <631250>; + clock-latency-ns =3D <500000>; + }; + + opp-1426000000 { + opp-hz =3D /bits/ 64 <1426000000>; + opp-microvolt =3D <662500>; + clock-latency-ns =3D <500000>; + }; + + opp-1582000000 { + opp-hz =3D /bits/ 64 <1582000000>; + opp-microvolt =3D <693750>; + clock-latency-ns =3D <500000>; + }; + + opp-1745000000 { + opp-hz =3D /bits/ 64 <1745000000>; + opp-microvolt =3D <731250>; + clock-latency-ns =3D <500000>; + }; + + opp-1826000000 { + opp-hz =3D /bits/ 64 <1826000000>; + opp-microvolt =3D <750000>; + clock-latency-ns =3D <500000>; + }; + + opp-2048000000 { + opp-hz =3D /bits/ 64 <2048000000>; + opp-microvolt =3D <793750>; + clock-latency-ns =3D <500000>; + }; + + opp-2188000000 { + opp-hz =3D /bits/ 64 <2188000000>; + opp-microvolt =3D <831250>; + clock-latency-ns =3D <500000>; + }; + + opp-2252000000 { + opp-hz =3D /bits/ 64 <2252000000>; + opp-microvolt =3D <850000>; + clock-latency-ns =3D <500000>; + }; + + opp-2401000000 { + opp-hz =3D /bits/ 64 <2401000000>; + opp-microvolt =3D <887500>; + clock-latency-ns =3D <500000>; + }; + + opp-2507000000 { + opp-hz =3D /bits/ 64 <2507000000>; + opp-microvolt =3D <925000>; + clock-latency-ns =3D <500000>; + }; + + opp-2630000000 { + opp-hz =3D /bits/ 64 <2630000000>; + opp-microvolt =3D <968750>; + clock-latency-ns =3D <500000>; + }; + + opp-2704000000 { + opp-hz =3D /bits/ 64 <2704000000>; + opp-microvolt =3D <1000000>; + clock-latency-ns =3D <500000>; + }; + + opp-2802000000 { + opp-hz =3D /bits/ 64 <2802000000>; + opp-microvolt =3D <1056250>; + clock-latency-ns =3D <500000>; + }; + }; + /* ect node is required to be present by bootloader */ ect { }; --=20 2.51.0.536.g15c5d4f767-goog