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[95.249.236.54]) by smtp.googlemail.com with ESMTPSA id ffacd0b85a97d-3ee141e9cf7sm24889690f8f.12.2025.09.23.13.12.57 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Tue, 23 Sep 2025 13:12:59 -0700 (PDT) From: Christian Marangi To: Michael Turquette , Stephen Boyd , Rob Herring , Krzysztof Kozlowski , Conor Dooley , Matthias Brugger , AngeloGioacchino Del Regno , Ryder Lee , Jianjun Wang , Bjorn Helgaas , Lorenzo Pieralisi , =?UTF-8?q?Krzysztof=20Wilczy=C5=84ski?= , Manivannan Sadhasivam , Christian Marangi , linux-clk@vger.kernel.org, devicetree@vger.kernel.org, linux-kernel@vger.kernel.org, linux-arm-kernel@lists.infradead.org, linux-mediatek@lists.infradead.org, linux-pci@vger.kernel.org, upstream@airoha.com Subject: [PATCH v2 4/4] PCI: mediatek: add support for Airoha AN7583 SoC Date: Tue, 23 Sep 2025 22:12:32 +0200 Message-ID: <20250923201244.952-5-ansuelsmth@gmail.com> X-Mailer: git-send-email 2.51.0 In-Reply-To: <20250923201244.952-1-ansuelsmth@gmail.com> References: <20250923201244.952-1-ansuelsmth@gmail.com> Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Content-Type: text/plain; charset="utf-8" Add support for the second PCIe line present on Airoha AN7583 SoC. This is based on the Mediatek Gen1/2 PCIe driver and similar to Gen3 also require workaround for the reset signals. Introduce a new bool to skip having to reset signals and also introduce some additional logic to configure the PBUS registers required for Airoha SoC. Signed-off-by: Christian Marangi --- drivers/pci/controller/pcie-mediatek.c | 85 +++++++++++++++++++------- 1 file changed, 63 insertions(+), 22 deletions(-) diff --git a/drivers/pci/controller/pcie-mediatek.c b/drivers/pci/controlle= r/pcie-mediatek.c index 24cc30a2ab6c..640d1f1a6478 100644 --- a/drivers/pci/controller/pcie-mediatek.c +++ b/drivers/pci/controller/pcie-mediatek.c @@ -147,6 +147,7 @@ struct mtk_pcie_port; * @need_fix_class_id: whether this host's class ID needed to be fixed or = not * @need_fix_device_id: whether this host's device ID needed to be fixed o= r not * @no_msi: Bridge has no MSI support, and relies on an external block + * @skip_pcie_rstb: Skip calling RSTB bits on PCIe probe * @device_id: device ID which this host need to be fixed * @ops: pointer to configuration access functions * @startup: pointer to controller setting functions @@ -156,6 +157,7 @@ struct mtk_pcie_soc { bool need_fix_class_id; bool need_fix_device_id; bool no_msi; + bool skip_pcie_rstb; unsigned int device_id; struct pci_ops *ops; int (*startup)(struct mtk_pcie_port *port); @@ -679,28 +681,30 @@ static int mtk_pcie_startup_port_v2(struct mtk_pcie_p= ort *port) regmap_update_bits(pcie->cfg, PCIE_SYS_CFG_V2, val, val); } =20 - /* Assert all reset signals */ - writel(0, port->base + PCIE_RST_CTRL); - - /* - * Enable PCIe link down reset, if link status changed from link up to - * link down, this will reset MAC control registers and configuration - * space. - */ - writel(PCIE_LINKDOWN_RST_EN, port->base + PCIE_RST_CTRL); - - /* - * Described in PCIe CEM specification sections 2.2 (PERST# Signal) and - * 2.2.1 (Initial Power-Up (G3 to S0)). The deassertion of PERST# should - * be delayed 100ms (TPVPERL) for the power and clock to become stable. - */ - msleep(100); - - /* De-assert PHY, PE, PIPE, MAC and configuration reset */ - val =3D readl(port->base + PCIE_RST_CTRL); - val |=3D PCIE_PHY_RSTB | PCIE_PERSTB | PCIE_PIPE_SRSTB | - PCIE_MAC_SRSTB | PCIE_CRSTB; - writel(val, port->base + PCIE_RST_CTRL); + if (!soc->skip_pcie_rstb) { + /* Assert all reset signals */ + writel(0, port->base + PCIE_RST_CTRL); + + /* + * Enable PCIe link down reset, if link status changed from link up to + * link down, this will reset MAC control registers and configuration + * space. + */ + writel(PCIE_LINKDOWN_RST_EN, port->base + PCIE_RST_CTRL); + + /* + * Described in PCIe CEM specification sections 2.2 (PERST# Signal) and + * 2.2.1 (Initial Power-Up (G3 to S0)). The deassertion of PERST# should + * be delayed 100ms (TPVPERL) for the power and clock to become stable. + */ + msleep(100); + + /* De-assert PHY, PE, PIPE, MAC and configuration reset */ + val =3D readl(port->base + PCIE_RST_CTRL); + val |=3D PCIE_PHY_RSTB | PCIE_PERSTB | PCIE_PIPE_SRSTB | + PCIE_MAC_SRSTB | PCIE_CRSTB; + writel(val, port->base + PCIE_RST_CTRL); + } =20 /* Set up vendor ID and class code */ if (soc->need_fix_class_id) { @@ -1105,6 +1109,33 @@ static int mtk_pcie_probe(struct platform_device *pd= ev) if (err) goto put_resources; =20 + if (device_is_compatible(dev, "airoha,an7583-pcie")) { + struct resource_entry *entry; + struct regmap *pbus_regmap; + resource_size_t addr; + u32 args[2], size; + + /* + * Configure PBus base address and base address mask to allow the + * hw to detect if a given address is accessible on PCIe controller. + */ + pbus_regmap =3D syscon_regmap_lookup_by_phandle_args(dev->of_node, + "mediatek,pbus-csr", + ARRAY_SIZE(args), + args); + if (IS_ERR(pbus_regmap)) + return PTR_ERR(pbus_regmap); + + entry =3D resource_list_first_type(&host->windows, IORESOURCE_MEM); + if (!entry) + return -ENODEV; + + addr =3D entry->res->start - entry->offset; + regmap_write(pbus_regmap, args[0], lower_32_bits(addr)); + size =3D lower_32_bits(resource_size(entry->res)); + regmap_write(pbus_regmap, args[1], GENMASK(31, __fls(size))); + } + return 0; =20 put_resources: @@ -1205,6 +1236,15 @@ static const struct mtk_pcie_soc mtk_pcie_soc_mt7622= =3D { .setup_irq =3D mtk_pcie_setup_irq, }; =20 +static const struct mtk_pcie_soc mtk_pcie_soc_an7583 =3D { + .skip_pcie_rstb =3D true, + .need_fix_class_id =3D true, + .need_fix_device_id =3D false, + .ops =3D &mtk_pcie_ops_v2, + .startup =3D mtk_pcie_startup_port_v2, + .setup_irq =3D mtk_pcie_setup_irq, +}; + static const struct mtk_pcie_soc mtk_pcie_soc_mt7629 =3D { .need_fix_class_id =3D true, .need_fix_device_id =3D true, @@ -1215,6 +1255,7 @@ static const struct mtk_pcie_soc mtk_pcie_soc_mt7629 = =3D { }; =20 static const struct of_device_id mtk_pcie_ids[] =3D { + { .compatible =3D "airoha,an7583-pcie", .data =3D &mtk_pcie_soc_an7583 }, { .compatible =3D "mediatek,mt2701-pcie", .data =3D &mtk_pcie_soc_v1 }, { .compatible =3D "mediatek,mt7623-pcie", .data =3D &mtk_pcie_soc_v1 }, { .compatible =3D "mediatek,mt2712-pcie", .data =3D &mtk_pcie_soc_mt2712 = }, --=20 2.51.0