From nobody Thu Oct 2 01:57:53 2025 Received: from mail-wm1-f46.google.com (mail-wm1-f46.google.com [209.85.128.46]) (using TLSv1.2 with cipher ECDHE-RSA-AES128-GCM-SHA256 (128/128 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id 28C3F30AAC8 for ; Tue, 23 Sep 2025 20:12:55 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=none smtp.client-ip=209.85.128.46 ARC-Seal: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1758658376; cv=none; b=OPWkkSNwCT0sOfs2QSrerziB7F6qZMyHyehMSrvHWBGK6wVg6GJ9sfQL7gx2/H8FD6dW0o2DQtzS5+zuauvQKTfN/arT87rG+m2WDgQCJYsaolt7M13hkTfsjM3AwsQCxRGiOSsTI1D3YZr6EPVgTioAfWw7iw7K3ublLPV0jcI= ARC-Message-Signature: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1758658376; c=relaxed/simple; bh=pQQc50aYzZqifBZLt/GUeCSMwtVtlqq98lQJ7t3A0hk=; h=From:To:Subject:Date:Message-ID:In-Reply-To:References: MIME-Version; b=QeYa4DsMWWB0xb0cwoMkq3x6zsYR28UKqcssLP4/e5bCUcPhrzPvGXh9hfB1tndSWpA/dRvg7p3oRY97oT2CQByNCyFLvWWU+wBJBA1F7dlVNmRqOx6WU+QRBQXCLhYcvqhYYx8EI2MnBaSQ1m1216tbckJc1k1MMnzBH4k7PjE= ARC-Authentication-Results: i=1; smtp.subspace.kernel.org; dmarc=pass (p=none dis=none) header.from=gmail.com; spf=pass smtp.mailfrom=gmail.com; dkim=pass (2048-bit key) header.d=gmail.com header.i=@gmail.com header.b=GdaLm28z; arc=none smtp.client-ip=209.85.128.46 Authentication-Results: smtp.subspace.kernel.org; dmarc=pass (p=none dis=none) header.from=gmail.com Authentication-Results: smtp.subspace.kernel.org; spf=pass smtp.mailfrom=gmail.com Authentication-Results: smtp.subspace.kernel.org; dkim=pass (2048-bit key) header.d=gmail.com header.i=@gmail.com header.b="GdaLm28z" Received: by mail-wm1-f46.google.com with SMTP id 5b1f17b1804b1-45dcff2f313so37600915e9.0 for ; Tue, 23 Sep 2025 13:12:54 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=gmail.com; s=20230601; t=1758658373; x=1759263173; darn=vger.kernel.org; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:to:from:from:to:cc:subject:date:message-id :reply-to; bh=S/aSYEPITl7MXFUBK4l9sWKvsSHUrdrtUDK4IHLwFVI=; b=GdaLm28zJdmARM/vjxZu6Cy1UUqOuylADCdBvQm7kf2zMRz2kiqhqlP/29XylFicbc 88QSqo3TUiBydYebyvW6p/8/BUCTk5auL+9pzKFyEnMoEQqanJAiNDAeUJPkUj4TJy6T 6fMGQeL52htGG8cfrfnO405If6BVbeZ0M++0YM0O97DKwe6QxCf9Qz+YhHkSolXKSHrS fcbWJ3p3KOuucvQxTA9CafhIHoB5Tbfvu6VEMG2zHPXOIIhtFhXFBhnmo9it6YsDfHfx N4tWA6tRJknC7CGrBrbBVELPBF6XKf0bckQLymGBHgRX/7Y12xuUwRNQHpxBQPLrf+Pt aIaA== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20230601; t=1758658373; x=1759263173; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:to:from:x-gm-message-state:from:to:cc :subject:date:message-id:reply-to; bh=S/aSYEPITl7MXFUBK4l9sWKvsSHUrdrtUDK4IHLwFVI=; b=mOQG2rO5bhVLLQZ9xFPir9wwWV6GKH7dkMaVxhPxWxx/dGt/xnEllzCsdXOvZyvGAi fDs7JhI4ZNj0w6a5n90+HorvPvdOPj3vMleYwax3VDUwPykZcalP0WulCx+luex1bGUG aLglLVfPrpGCVaom0Izfb1r4X4eXAUPlmm35TMxcgQnD51iGMGop4vdANa8ReeuB+r/u XF/d0GkIbSj3cwowzkTcVvWTK5FutznKaq49dgmO4vMMVzdkHuBnxJwC9WcUtjTdrKgi m99jfcxsiDXwBASvqlsMeaP23cNidYcmPafnS9ee9/GB2dmR8xlUawCQTmF+VfD6wgw7 yxwQ== X-Forwarded-Encrypted: i=1; AJvYcCXtBdE910vYonle41QFbx3EeCVj6N7zEstkWNuXeLaa5heHW6gB5LnFW/9kBnHfWLUogw/AiETKAC8xhQ0=@vger.kernel.org X-Gm-Message-State: AOJu0YxtDP0sqS2bSP5pZfNwhmIq6Mzv3skfBWpFP3peLZKIIVJ+BBCD yLPZmAts7KFoCO5OADFo0gmW0OI9tYNdlI6tIQt/KSoqaDoPDRxmLymu X-Gm-Gg: ASbGnctbTIZ+hCSlrDGs/7hhoOLGnahvcvO2FOOEPAY1ZePjsaomzX6/iVetVagtMdB zoYlgpGk4t3HTk2FdKd8LnXjAjLRqFoRRuMskyqJ6Q+9rz6L9LyK0D56xvJWwQf3ZEw4RaH1yEM 0K/V3lzCNKZ886qGJpI95nX8RMvPWlpV/cZxIKkLuSUPp4s2rPDRtFoVFYQ31D5vUPKOJXvTadx jbgNmhJ2ELudo3ybw+zvPAQB308ajfsZvuObuMJjJqNiPCzQ7VHPGk0MM92gwr3CVIjPXATvxjN w7NthB7Hi80HWbSL/PoYWPO6J7t9K4UZUBPSJDZAQLkwaAn6R7zs6XuUcbim0hvtdU40AWCgiik u9y0kwIVqo6AJsSfVRWqfaRvAKk7QBnmoXKWAmSlao7w720OfU3NpgAAW5G7htislqUq45eo= X-Google-Smtp-Source: AGHT+IEEsRLoHeCjXxyp+KHw/4kToNUaWd3xzTGb2VSF+HgIp8CNjCGOmpc4a03QsHuOffoop0UVIA== X-Received: by 2002:a05:600c:4f44:b0:46d:996b:826d with SMTP id 5b1f17b1804b1-46e1daca1cemr38382195e9.34.1758658373435; Tue, 23 Sep 2025 13:12:53 -0700 (PDT) Received: from Ansuel-XPS24 (host-95-249-236-54.retail.telecomitalia.it. [95.249.236.54]) by smtp.googlemail.com with ESMTPSA id ffacd0b85a97d-3ee141e9cf7sm24889690f8f.12.2025.09.23.13.12.51 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Tue, 23 Sep 2025 13:12:53 -0700 (PDT) From: Christian Marangi To: Michael Turquette , Stephen Boyd , Rob Herring , Krzysztof Kozlowski , Conor Dooley , Matthias Brugger , AngeloGioacchino Del Regno , Ryder Lee , Jianjun Wang , Bjorn Helgaas , Lorenzo Pieralisi , =?UTF-8?q?Krzysztof=20Wilczy=C5=84ski?= , Manivannan Sadhasivam , Christian Marangi , linux-clk@vger.kernel.org, devicetree@vger.kernel.org, linux-kernel@vger.kernel.org, linux-arm-kernel@lists.infradead.org, linux-mediatek@lists.infradead.org, linux-pci@vger.kernel.org, upstream@airoha.com Subject: [PATCH v2 1/4] dt-bindings: clock: mediatek: Fix wrong compatible list for hifsys YAML Date: Tue, 23 Sep 2025 22:12:29 +0200 Message-ID: <20250923201244.952-2-ansuelsmth@gmail.com> X-Mailer: git-send-email 2.51.0 In-Reply-To: <20250923201244.952-1-ansuelsmth@gmail.com> References: <20250923201244.952-1-ansuelsmth@gmail.com> Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Content-Type: text/plain; charset="utf-8" While converting the hifsys to YAML schema, the "syscon" compatible was dropped for the mt7623 and the mt2701 compatible. Add back the compatible to mute DTBs warning on "make dtbs_check" and reflect real state of the .dtsi. Signed-off-by: Christian Marangi --- .../devicetree/bindings/clock/mediatek,mt2701-hifsys.yaml | 8 +++++--- 1 file changed, 5 insertions(+), 3 deletions(-) diff --git a/Documentation/devicetree/bindings/clock/mediatek,mt2701-hifsys= .yaml b/Documentation/devicetree/bindings/clock/mediatek,mt2701-hifsys.yaml index 9e7c725093aa..aa3345ea8283 100644 --- a/Documentation/devicetree/bindings/clock/mediatek,mt2701-hifsys.yaml +++ b/Documentation/devicetree/bindings/clock/mediatek,mt2701-hifsys.yaml @@ -16,13 +16,15 @@ maintainers: properties: compatible: oneOf: - - enum: - - mediatek,mt2701-hifsys - - mediatek,mt7622-hifsys + - items: + - const: mediatek,mt2701-hifsys + - const: syscon + - const: mediatek,mt7622-hifsys - items: - enum: - mediatek,mt7623-hifsys - const: mediatek,mt2701-hifsys + - const: syscon =20 reg: maxItems: 1 --=20 2.51.0 From nobody Thu Oct 2 01:57:53 2025 Received: from mail-wr1-f42.google.com (mail-wr1-f42.google.com [209.85.221.42]) (using TLSv1.2 with cipher ECDHE-RSA-AES128-GCM-SHA256 (128/128 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id 6883430B515 for ; Tue, 23 Sep 2025 20:12:57 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=none smtp.client-ip=209.85.221.42 ARC-Seal: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1758658380; cv=none; b=fkat4GPnSoDq0Oqp1Ywy/9AcKXiYs/PyYn286MiUOgATykbLx/CD5WxkG6V7XPqydwfgL2ckZZQeEs/odwRCY+kxD6cpF8Ws+uJataQaDhlVeNHHEFwKCyRAMvcqHtUVafgarQS9NTcJ2+LaMWSzBVKb+oBgT9XgwkAf9r9oXsc= ARC-Message-Signature: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1758658380; c=relaxed/simple; bh=rrkRAJwO9hx6jYPM9O50w/IhSWYxpkME8Xc2KPtC5mE=; h=From:To:Subject:Date:Message-ID:In-Reply-To:References: MIME-Version; b=ZihvTvkxcML60HDuJjZ7eKZzZaPUQhJaX5EKwdM8YUfV5aZ6WcMPTxMYc06CB7fPvfnqZdUTRn0lG7GUz9zwFkC6iiNti/dC6YLb3i6rcUFyRJ+dZvBG+fMUlxMPSszqYjCnTyHZ8kpok9YRPGujDrnwvESRHijRaKdUMqoCl1A= ARC-Authentication-Results: i=1; smtp.subspace.kernel.org; dmarc=pass (p=none dis=none) header.from=gmail.com; spf=pass smtp.mailfrom=gmail.com; dkim=pass (2048-bit key) header.d=gmail.com header.i=@gmail.com header.b=nVnjtMZy; arc=none smtp.client-ip=209.85.221.42 Authentication-Results: smtp.subspace.kernel.org; dmarc=pass (p=none dis=none) header.from=gmail.com Authentication-Results: smtp.subspace.kernel.org; spf=pass smtp.mailfrom=gmail.com Authentication-Results: smtp.subspace.kernel.org; dkim=pass (2048-bit key) header.d=gmail.com header.i=@gmail.com header.b="nVnjtMZy" Received: by mail-wr1-f42.google.com with SMTP id ffacd0b85a97d-3f99ac9acc4so2585365f8f.3 for ; Tue, 23 Sep 2025 13:12:57 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=gmail.com; s=20230601; t=1758658376; x=1759263176; darn=vger.kernel.org; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:to:from:from:to:cc:subject:date:message-id :reply-to; bh=cMJ3WopK8a5niskiRP0SzUJlGCXuhbpau4KCX70OMIU=; b=nVnjtMZyu3ON09kkbjIwp4BJmZiZbT1ipoD02q1XAqlRzhyEYkRGtAsJ5ouVJv13Xt dRbEtHUAklkJJvMFwuacUYqgiTTkeImjhu2C4y1q7bPmUZttH3pC/XzY+oMOzED8yr4I wyg4pCkt7V3Sqw7CkczHEDoJ1bQe328TUVScS4d8wnctbKmIns+lo5ZS8Gv3kMEY7CDv F/BfHMoTxZZre3ICmH0coAqiUVF8HUjuBwx+I7YsRrzlZ/NQ7jZ8SRco0BeOxB0PGkc5 Li7daUSw4vI6ZCS5S3wHoCU1VkTDd90z2TTAp4En75lYwga4C4tuNNQxXcHryY45Weg2 Uf2w== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20230601; t=1758658376; x=1759263176; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:to:from:x-gm-message-state:from:to:cc :subject:date:message-id:reply-to; bh=cMJ3WopK8a5niskiRP0SzUJlGCXuhbpau4KCX70OMIU=; b=XeWMZiGO/EWXK4Kpge+I35mgPy53KCMVjZqdEKNNea1hdXjcXgP6+q4ZVyujz9YKvh GJItAydXMcI+NOlDCYgHPJVi1x9Xmi10Vf5EQ7t1i/h6Gtofj40NcuvxdHHnBCXGiZaS 7jUknfrvP+bpNwl200Unbc1YGlwM5AOJUNRjIp/wDfnxIPpivZeU5OpSWnVvJMexIu9N WPXZTgCkseitY/cpWbO6pUCoLsL4zCsvj8QKTZKik/nYR/x36lzEPb34PFgpI+lcpN+B WnNUrnXTXHiRTTBCL7Yy7TOZgHnSmP46RJ6T4nxPyGWw9v1itCcvyF/HQjJGmvHiWjtZ G0Zw== X-Forwarded-Encrypted: i=1; AJvYcCX9X6zlen0P9mdFX77rzAXNzusSPcnSSiWZwS4y53gJLthDiCzgIU92cANUg2yDmDIU8PWLUmdSl1qqgMk=@vger.kernel.org X-Gm-Message-State: AOJu0YxTO2EBrReKVg8mOXGfPl/WPljbW3X9z9EdSQ6nY4+AakV/uc3C bpJ8hcRhPfctFYKZDZZyUir31EF4FxlQK71uLnkcej5C5UVMgpeajIig X-Gm-Gg: ASbGncs6GjoWjrvR1bd68hUJ1hf9Z82V/4xaLIJing/mZHHUhob17ZcbbOLrcKmenVE Hef7uSdTO4O12kvRiTvDEXnfpo6Q6dcWkpdJcI1icllv4VfJCUKJJbEFBKtQ7UMcN1Yp6ZUP3/Y t6ZLf+T3nmaokngtmQf0bbxx8hTw+zSztlC37DDqBeySV3W/kP4As20OUzqSsWqLgZJYLm5HsVe wL44Wje+g8nGY4anT4R2klKFF2pLamAAjC3+riQqnP79pvYUzOUwHQ8yIdaf9cgsGfSovL6WDzg RMQajgljcXoP6iYQyNPebUqT55M2sCBxfZRB98YRLc3nBI6ihJ7o/ZsiX+ZZoh8VK8OAyqTCoG8 BB9yBElm+yXuEZtV5OYPRxPV8J2ydTIbPxp3DuY47a8ZtBvo3jhXYIR56W9AFQUP+i6YDUHuxFg LeA7v4Lw== X-Google-Smtp-Source: AGHT+IELp6YayQqecWu0duXT9CSJC4/XXxloPvyyEWgn6vnxteQpPWWsQi05yl4EqFwKjpmaN7kLzg== X-Received: by 2002:a5d:64e8:0:b0:3fb:bb69:d91b with SMTP id ffacd0b85a97d-405c49a1e6cmr3274693f8f.2.1758658375503; Tue, 23 Sep 2025 13:12:55 -0700 (PDT) Received: from Ansuel-XPS24 (host-95-249-236-54.retail.telecomitalia.it. [95.249.236.54]) by smtp.googlemail.com with ESMTPSA id ffacd0b85a97d-3ee141e9cf7sm24889690f8f.12.2025.09.23.13.12.53 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Tue, 23 Sep 2025 13:12:55 -0700 (PDT) From: Christian Marangi To: Michael Turquette , Stephen Boyd , Rob Herring , Krzysztof Kozlowski , Conor Dooley , Matthias Brugger , AngeloGioacchino Del Regno , Ryder Lee , Jianjun Wang , Bjorn Helgaas , Lorenzo Pieralisi , =?UTF-8?q?Krzysztof=20Wilczy=C5=84ski?= , Manivannan Sadhasivam , Christian Marangi , linux-clk@vger.kernel.org, devicetree@vger.kernel.org, linux-kernel@vger.kernel.org, linux-arm-kernel@lists.infradead.org, linux-mediatek@lists.infradead.org, linux-pci@vger.kernel.org, upstream@airoha.com Subject: [PATCH v2 2/4] dt-bindings: PCI: mediatek: Convert to YAML schema Date: Tue, 23 Sep 2025 22:12:30 +0200 Message-ID: <20250923201244.952-3-ansuelsmth@gmail.com> X-Mailer: git-send-email 2.51.0 In-Reply-To: <20250923201244.952-1-ansuelsmth@gmail.com> References: <20250923201244.952-1-ansuelsmth@gmail.com> Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Content-Type: text/plain; charset="utf-8" Convert the PCI mediatek Documentation to YAML schema to enable validation of the supported GEN1/2 Mediatek PCIe controller. While converting, lots of cleanup were done from the .txt with better specifying what is supported by the various PCIe controller variant and drop of redundant info that are part of the standard PCIe Host Bridge schema. To reduce schema complexity the .txt is split in 2 YAML, one for mt7623/mt2701 and the other for every other compatible. Signed-off-by: Christian Marangi --- .../bindings/pci/mediatek-pcie-mt7623.yaml | 173 ++++++++ .../devicetree/bindings/pci/mediatek-pcie.txt | 289 ------------- .../bindings/pci/mediatek-pcie.yaml | 404 ++++++++++++++++++ 3 files changed, 577 insertions(+), 289 deletions(-) create mode 100644 Documentation/devicetree/bindings/pci/mediatek-pcie-mt7= 623.yaml delete mode 100644 Documentation/devicetree/bindings/pci/mediatek-pcie.txt create mode 100644 Documentation/devicetree/bindings/pci/mediatek-pcie.yaml diff --git a/Documentation/devicetree/bindings/pci/mediatek-pcie-mt7623.yam= l b/Documentation/devicetree/bindings/pci/mediatek-pcie-mt7623.yaml new file mode 100644 index 000000000000..2f201c84e29a --- /dev/null +++ b/Documentation/devicetree/bindings/pci/mediatek-pcie-mt7623.yaml @@ -0,0 +1,173 @@ +# SPDX-License-Identifier: (GPL-2.0 OR BSD-2-Clause) +%YAML 1.2 +--- +$id: http://devicetree.org/schemas/pci/mediatek-pcie-mt7623.yaml# +$schema: http://devicetree.org/meta-schemas/core.yaml# + +title: PCIe controller on MediaTek SoCs + +maintainers: + - Christian Marangi + +properties: + compatible: + enum: + - mediatek,mt2701-pcie + - mediatek,mt7623-pcie + + reg: + minItems: 4 + maxItems: 4 + + reg-names: + items: + - const: subsys + - const: port0 + - const: port1 + - const: port2 + + clocks: + minItems: 4 + maxItems: 4 + + clock-names: + items: + - const: free_ck + - const: sys_ck0 + - const: sys_ck1 + - const: sys_ck2 + + resets: + minItems: 3 + maxItems: 3 + + reset-names: + items: + - const: pcie-rst0 + - const: pcie-rst1 + - const: pcie-rst2 + + phys: + minItems: 3 + maxItems: 3 + + phy-names: + items: + - const: pcie-phy0 + - const: pcie-phy1 + - const: pcie-phy2 + + power-domains: + maxItems: 1 + +required: + - compatible + - reg + - reg-names + - ranges + - clocks + - clock-names + - '#interrupt-cells' + - resets + - reset-names + - phys + - phy-names + - power-domains + - pcie@0,0 + - pcie@1,0 + - pcie@2,0 + +allOf: + - $ref: /schemas/pci/pci-host-bridge.yaml# + +unevaluatedProperties: false + +examples: + # MT7623 + - | + #include + #include + #include + #include + #include + #include + + soc { + #address-cells =3D <2>; + #size-cells =3D <2>; + + hifsys: syscon@1a000000 { + compatible =3D "mediatek,mt7623-hifsys", + "mediatek,mt2701-hifsys", + "syscon"; + reg =3D <0 0x1a000000 0 0x1000>; + #clock-cells =3D <1>; + #reset-cells =3D <1>; + }; + + pcie@1a140000 { + compatible =3D "mediatek,mt7623-pcie"; + device_type =3D "pci"; + reg =3D <0 0x1a140000 0 0x1000>, /* PCIe shared registers */ + <0 0x1a142000 0 0x1000>, /* Port0 registers */ + <0 0x1a143000 0 0x1000>, /* Port1 registers */ + <0 0x1a144000 0 0x1000>; /* Port2 registers */ + reg-names =3D "subsys", "port0", "port1", "port2"; + #address-cells =3D <3>; + #size-cells =3D <2>; + #interrupt-cells =3D <1>; + interrupt-map-mask =3D <0xf800 0 0 0>; + interrupt-map =3D <0x0000 0 0 0 &sysirq GIC_SPI 193 IRQ_TYPE_L= EVEL_LOW>, + <0x0800 0 0 0 &sysirq GIC_SPI 194 IRQ_TYPE_LEV= EL_LOW>, + <0x1000 0 0 0 &sysirq GIC_SPI 195 IRQ_TYPE_LEV= EL_LOW>; + clocks =3D <&topckgen CLK_TOP_ETHIF_SEL>, + <&hifsys CLK_HIFSYS_PCIE0>, + <&hifsys CLK_HIFSYS_PCIE1>, + <&hifsys CLK_HIFSYS_PCIE2>; + clock-names =3D "free_ck", "sys_ck0", "sys_ck1", "sys_ck2"; + resets =3D <&hifsys MT2701_HIFSYS_PCIE0_RST>, + <&hifsys MT2701_HIFSYS_PCIE1_RST>, + <&hifsys MT2701_HIFSYS_PCIE2_RST>; + reset-names =3D "pcie-rst0", "pcie-rst1", "pcie-rst2"; + phys =3D <&pcie0_phy PHY_TYPE_PCIE>, <&pcie1_phy PHY_TYPE_PCIE= >, + <&pcie2_phy PHY_TYPE_PCIE>; + phy-names =3D "pcie-phy0", "pcie-phy1", "pcie-phy2"; + power-domains =3D <&scpsys MT2701_POWER_DOMAIN_HIF>; + bus-range =3D <0x00 0xff>; + ranges =3D <0x81000000 0 0x1a160000 0 0x1a160000 0 0x00010000 = /* I/O space */ + 0x83000000 0 0x60000000 0 0x60000000 0 0x10000000>; = /* memory space */ + + pcie@0,0 { + device_type =3D "pci"; + reg =3D <0x0000 0 0 0 0>; + #address-cells =3D <3>; + #size-cells =3D <2>; + #interrupt-cells =3D <1>; + interrupt-map-mask =3D <0 0 0 0>; + interrupt-map =3D <0 0 0 0 &sysirq GIC_SPI 193 IRQ_TYPE_LE= VEL_LOW>; + ranges; + }; + + pcie@1,0 { + device_type =3D "pci"; + reg =3D <0x0800 0 0 0 0>; + #address-cells =3D <3>; + #size-cells =3D <2>; + #interrupt-cells =3D <1>; + interrupt-map-mask =3D <0 0 0 0>; + interrupt-map =3D <0 0 0 0 &sysirq GIC_SPI 194 IRQ_TYPE_LE= VEL_LOW>; + ranges; + }; + + pcie@2,0 { + device_type =3D "pci"; + reg =3D <0x1000 0 0 0 0>; + #address-cells =3D <3>; + #size-cells =3D <2>; + #interrupt-cells =3D <1>; + interrupt-map-mask =3D <0 0 0 0>; + interrupt-map =3D <0 0 0 0 &sysirq GIC_SPI 195 IRQ_TYPE_LE= VEL_LOW>; + ranges; + }; + }; + }; diff --git a/Documentation/devicetree/bindings/pci/mediatek-pcie.txt b/Docu= mentation/devicetree/bindings/pci/mediatek-pcie.txt deleted file mode 100644 index 684227522267..000000000000 --- a/Documentation/devicetree/bindings/pci/mediatek-pcie.txt +++ /dev/null @@ -1,289 +0,0 @@ -MediaTek Gen2 PCIe controller - -Required properties: -- compatible: Should contain one of the following strings: - "mediatek,mt2701-pcie" - "mediatek,mt2712-pcie" - "mediatek,mt7622-pcie" - "mediatek,mt7623-pcie" - "mediatek,mt7629-pcie" - "airoha,en7523-pcie" -- device_type: Must be "pci" -- reg: Base addresses and lengths of the root ports. -- reg-names: Names of the above areas to use during resource lookup. -- #address-cells: Address representation for root ports (must be 3) -- #size-cells: Size representation for root ports (must be 2) -- clocks: Must contain an entry for each entry in clock-names. - See ../clocks/clock-bindings.txt for details. -- clock-names: - Mandatory entries: - - sys_ckN :transaction layer and data link layer clock - Required entries for MT2701/MT7623: - - free_ck :for reference clock of PCIe subsys - Required entries for MT2712/MT7622: - - ahb_ckN :AHB slave interface operating clock for CSR access and RC - initiated MMIO access - Required entries for MT7622: - - axi_ckN :application layer MMIO channel operating clock - - aux_ckN :pe2_mac_bridge and pe2_mac_core operating clock when - pcie_mac_ck/pcie_pipe_ck is turned off - - obff_ckN :OBFF functional block operating clock - - pipe_ckN :LTSSM and PHY/MAC layer operating clock - where N starting from 0 to one less than the number of root ports. -- phys: List of PHY specifiers (used by generic PHY framework). -- phy-names : Must be "pcie-phy0", "pcie-phy1", "pcie-phyN".. based on the - number of PHYs as specified in *phys* property. -- power-domains: A phandle and power domain specifier pair to the power do= main - which is responsible for collapsing and restoring power to the periphera= l. -- bus-range: Range of bus numbers associated with this controller. -- ranges: Ranges for the PCI memory and I/O regions. - -Required properties for MT7623/MT2701: -- #interrupt-cells: Size representation for interrupts (must be 1) -- interrupt-map-mask and interrupt-map: Standard PCI IRQ mapping properties - Please refer to the standard PCI bus binding document for a more detailed - explanation. -- resets: Must contain an entry for each entry in reset-names. - See ../reset/reset.txt for details. -- reset-names: Must be "pcie-rst0", "pcie-rst1", "pcie-rstN".. based on the - number of root ports. - -Required properties for MT2712/MT7622/MT7629: --interrupts: A list of interrupt outputs of the controller, must have one - entry for each PCIe port -- interrupt-names: Must include the following entries: - - "pcie_irq": The interrupt that is asserted when an MSI/INTX is received -- linux,pci-domain: PCI domain ID. Should be unique for each host controll= er - -In addition, the device tree node must have sub-nodes describing each -PCIe port interface, having the following mandatory properties: - -Required properties: -- device_type: Must be "pci" -- reg: Only the first four bytes are used to refer to the correct bus numb= er - and device number. -- #address-cells: Must be 3 -- #size-cells: Must be 2 -- #interrupt-cells: Must be 1 -- interrupt-map-mask and interrupt-map: Standard PCI IRQ mapping properties - Please refer to the standard PCI bus binding document for a more detailed - explanation. -- ranges: Sub-ranges distributed from the PCIe controller node. An empty - property is sufficient. - -Examples for MT7623: - - hifsys: syscon@1a000000 { - compatible =3D "mediatek,mt7623-hifsys", - "mediatek,mt2701-hifsys", - "syscon"; - reg =3D <0 0x1a000000 0 0x1000>; - #clock-cells =3D <1>; - #reset-cells =3D <1>; - }; - - pcie: pcie@1a140000 { - compatible =3D "mediatek,mt7623-pcie"; - device_type =3D "pci"; - reg =3D <0 0x1a140000 0 0x1000>, /* PCIe shared registers */ - <0 0x1a142000 0 0x1000>, /* Port0 registers */ - <0 0x1a143000 0 0x1000>, /* Port1 registers */ - <0 0x1a144000 0 0x1000>; /* Port2 registers */ - reg-names =3D "subsys", "port0", "port1", "port2"; - #address-cells =3D <3>; - #size-cells =3D <2>; - #interrupt-cells =3D <1>; - interrupt-map-mask =3D <0xf800 0 0 0>; - interrupt-map =3D <0x0000 0 0 0 &sysirq GIC_SPI 193 IRQ_TYPE_LEVEL_LOW>, - <0x0800 0 0 0 &sysirq GIC_SPI 194 IRQ_TYPE_LEVEL_LOW>, - <0x1000 0 0 0 &sysirq GIC_SPI 195 IRQ_TYPE_LEVEL_LOW>; - clocks =3D <&topckgen CLK_TOP_ETHIF_SEL>, - <&hifsys CLK_HIFSYS_PCIE0>, - <&hifsys CLK_HIFSYS_PCIE1>, - <&hifsys CLK_HIFSYS_PCIE2>; - clock-names =3D "free_ck", "sys_ck0", "sys_ck1", "sys_ck2"; - resets =3D <&hifsys MT2701_HIFSYS_PCIE0_RST>, - <&hifsys MT2701_HIFSYS_PCIE1_RST>, - <&hifsys MT2701_HIFSYS_PCIE2_RST>; - reset-names =3D "pcie-rst0", "pcie-rst1", "pcie-rst2"; - phys =3D <&pcie0_phy PHY_TYPE_PCIE>, <&pcie1_phy PHY_TYPE_PCIE>, - <&pcie2_phy PHY_TYPE_PCIE>; - phy-names =3D "pcie-phy0", "pcie-phy1", "pcie-phy2"; - power-domains =3D <&scpsys MT2701_POWER_DOMAIN_HIF>; - bus-range =3D <0x00 0xff>; - ranges =3D <0x81000000 0 0x1a160000 0 0x1a160000 0 0x00010000 /* I/O spa= ce */ - 0x83000000 0 0x60000000 0 0x60000000 0 0x10000000>; /* memory space */ - - pcie@0,0 { - reg =3D <0x0000 0 0 0 0>; - #address-cells =3D <3>; - #size-cells =3D <2>; - #interrupt-cells =3D <1>; - interrupt-map-mask =3D <0 0 0 0>; - interrupt-map =3D <0 0 0 0 &sysirq GIC_SPI 193 IRQ_TYPE_LEVEL_LOW>; - ranges; - }; - - pcie@1,0 { - reg =3D <0x0800 0 0 0 0>; - #address-cells =3D <3>; - #size-cells =3D <2>; - #interrupt-cells =3D <1>; - interrupt-map-mask =3D <0 0 0 0>; - interrupt-map =3D <0 0 0 0 &sysirq GIC_SPI 194 IRQ_TYPE_LEVEL_LOW>; - ranges; - }; - - pcie@2,0 { - reg =3D <0x1000 0 0 0 0>; - #address-cells =3D <3>; - #size-cells =3D <2>; - #interrupt-cells =3D <1>; - interrupt-map-mask =3D <0 0 0 0>; - interrupt-map =3D <0 0 0 0 &sysirq GIC_SPI 195 IRQ_TYPE_LEVEL_LOW>; - ranges; - }; - }; - -Examples for MT2712: - - pcie1: pcie@112ff000 { - compatible =3D "mediatek,mt2712-pcie"; - device_type =3D "pci"; - reg =3D <0 0x112ff000 0 0x1000>; - reg-names =3D "port1"; - linux,pci-domain =3D <1>; - #address-cells =3D <3>; - #size-cells =3D <2>; - interrupts =3D ; - interrupt-names =3D "pcie_irq"; - clocks =3D <&topckgen CLK_TOP_PE2_MAC_P1_SEL>, - <&pericfg CLK_PERI_PCIE1>; - clock-names =3D "sys_ck1", "ahb_ck1"; - phys =3D <&u3port1 PHY_TYPE_PCIE>; - phy-names =3D "pcie-phy1"; - bus-range =3D <0x00 0xff>; - ranges =3D <0x82000000 0 0x11400000 0x0 0x11400000 0 0x300000>; - status =3D "disabled"; - - #interrupt-cells =3D <1>; - interrupt-map-mask =3D <0 0 0 7>; - interrupt-map =3D <0 0 0 1 &pcie_intc1 0>, - <0 0 0 2 &pcie_intc1 1>, - <0 0 0 3 &pcie_intc1 2>, - <0 0 0 4 &pcie_intc1 3>; - pcie_intc1: interrupt-controller { - interrupt-controller; - #address-cells =3D <0>; - #interrupt-cells =3D <1>; - }; - }; - - pcie0: pcie@11700000 { - compatible =3D "mediatek,mt2712-pcie"; - device_type =3D "pci"; - reg =3D <0 0x11700000 0 0x1000>; - reg-names =3D "port0"; - linux,pci-domain =3D <0>; - #address-cells =3D <3>; - #size-cells =3D <2>; - interrupts =3D ; - interrupt-names =3D "pcie_irq"; - clocks =3D <&topckgen CLK_TOP_PE2_MAC_P0_SEL>, - <&pericfg CLK_PERI_PCIE0>; - clock-names =3D "sys_ck0", "ahb_ck0"; - phys =3D <&u3port0 PHY_TYPE_PCIE>; - phy-names =3D "pcie-phy0"; - bus-range =3D <0x00 0xff>; - ranges =3D <0x82000000 0 0x20000000 0x0 0x20000000 0 0x10000000>; - status =3D "disabled"; - - #interrupt-cells =3D <1>; - interrupt-map-mask =3D <0 0 0 7>; - interrupt-map =3D <0 0 0 1 &pcie_intc0 0>, - <0 0 0 2 &pcie_intc0 1>, - <0 0 0 3 &pcie_intc0 2>, - <0 0 0 4 &pcie_intc0 3>; - pcie_intc0: interrupt-controller { - interrupt-controller; - #address-cells =3D <0>; - #interrupt-cells =3D <1>; - }; - }; - -Examples for MT7622: - - pcie0: pcie@1a143000 { - compatible =3D "mediatek,mt7622-pcie"; - device_type =3D "pci"; - reg =3D <0 0x1a143000 0 0x1000>; - reg-names =3D "port0"; - linux,pci-domain =3D <0>; - #address-cells =3D <3>; - #size-cells =3D <2>; - interrupts =3D ; - interrupt-names =3D "pcie_irq"; - clocks =3D <&pciesys CLK_PCIE_P0_MAC_EN>, - <&pciesys CLK_PCIE_P0_AHB_EN>, - <&pciesys CLK_PCIE_P0_AUX_EN>, - <&pciesys CLK_PCIE_P0_AXI_EN>, - <&pciesys CLK_PCIE_P0_OBFF_EN>, - <&pciesys CLK_PCIE_P0_PIPE_EN>; - clock-names =3D "sys_ck0", "ahb_ck0", "aux_ck0", - "axi_ck0", "obff_ck0", "pipe_ck0"; - - power-domains =3D <&scpsys MT7622_POWER_DOMAIN_HIF0>; - bus-range =3D <0x00 0xff>; - ranges =3D <0x82000000 0 0x20000000 0x0 0x20000000 0 0x8000000>; - status =3D "disabled"; - - #interrupt-cells =3D <1>; - interrupt-map-mask =3D <0 0 0 7>; - interrupt-map =3D <0 0 0 1 &pcie_intc0 0>, - <0 0 0 2 &pcie_intc0 1>, - <0 0 0 3 &pcie_intc0 2>, - <0 0 0 4 &pcie_intc0 3>; - pcie_intc0: interrupt-controller { - interrupt-controller; - #address-cells =3D <0>; - #interrupt-cells =3D <1>; - }; - }; - - pcie1: pcie@1a145000 { - compatible =3D "mediatek,mt7622-pcie"; - device_type =3D "pci"; - reg =3D <0 0x1a145000 0 0x1000>; - reg-names =3D "port1"; - linux,pci-domain =3D <1>; - #address-cells =3D <3>; - #size-cells =3D <2>; - interrupts =3D ; - interrupt-names =3D "pcie_irq"; - clocks =3D <&pciesys CLK_PCIE_P1_MAC_EN>, - /* designer has connect RC1 with p0_ahb clock */ - <&pciesys CLK_PCIE_P0_AHB_EN>, - <&pciesys CLK_PCIE_P1_AUX_EN>, - <&pciesys CLK_PCIE_P1_AXI_EN>, - <&pciesys CLK_PCIE_P1_OBFF_EN>, - <&pciesys CLK_PCIE_P1_PIPE_EN>; - clock-names =3D "sys_ck1", "ahb_ck1", "aux_ck1", - "axi_ck1", "obff_ck1", "pipe_ck1"; - - power-domains =3D <&scpsys MT7622_POWER_DOMAIN_HIF0>; - bus-range =3D <0x00 0xff>; - ranges =3D <0x82000000 0 0x28000000 0x0 0x28000000 0 0x8000000>; - status =3D "disabled"; - - #interrupt-cells =3D <1>; - interrupt-map-mask =3D <0 0 0 7>; - interrupt-map =3D <0 0 0 1 &pcie_intc1 0>, - <0 0 0 2 &pcie_intc1 1>, - <0 0 0 3 &pcie_intc1 2>, - <0 0 0 4 &pcie_intc1 3>; - pcie_intc1: interrupt-controller { - interrupt-controller; - #address-cells =3D <0>; - #interrupt-cells =3D <1>; - }; - }; diff --git a/Documentation/devicetree/bindings/pci/mediatek-pcie.yaml b/Doc= umentation/devicetree/bindings/pci/mediatek-pcie.yaml new file mode 100644 index 000000000000..e3afedb77a01 --- /dev/null +++ b/Documentation/devicetree/bindings/pci/mediatek-pcie.yaml @@ -0,0 +1,404 @@ +# SPDX-License-Identifier: (GPL-2.0 OR BSD-2-Clause) +%YAML 1.2 +--- +$id: http://devicetree.org/schemas/pci/mediatek-pcie.yaml# +$schema: http://devicetree.org/meta-schemas/core.yaml# + +title: PCIe controller on MediaTek SoCs + +maintainers: + - Christian Marangi + +properties: + compatible: + oneOf: + - enum: + - mediatek,mt2712-pcie + - mediatek,mt7622-pcie + - mediatek,mt7629-pcie + - items: + - const: airoha,en7523-pcie + - const: mediatek,mt7622-pcie + + reg: + minItems: 1 + maxItems: 4 + + reg-names: + minItems: 1 + maxItems: 4 + + clocks: + minItems: 1 + maxItems: 6 + + clock-names: + minItems: 1 + maxItems: 6 + + interrupts: + maxItems: 1 + + interrupt-names: + const: pcie_irq + + resets: + minItems: 1 + maxItems: 3 + + reset-names: + minItems: 1 + maxItems: 3 + + phys: + minItems: 1 + maxItems: 3 + + phy-names: + minItems: 1 + maxItems: 3 + + power-domains: + maxItems: 1 + + '#interrupt-cells': + const: 1 + + interrupt-controller: + description: Interrupt controller node for handling legacy PCI interru= pts. + type: object + properties: + '#address-cells': + const: 0 + '#interrupt-cells': + const: 1 + interrupt-controller: true + + required: + - '#address-cells' + - '#interrupt-cells' + - interrupt-controller + + additionalProperties: false + +required: + - compatible + - reg + - reg-names + - ranges + - clocks + - clock-names + - '#interrupt-cells' + - interrupts + - interrupt-names + - interrupt-controller + +allOf: + - $ref: /schemas/pci/pci-host-bridge.yaml# + + - if: + properties: + compatible: + const: mediatek,mt2712-pcie + then: + properties: + reg: + maxItems: 1 + + reg-names: + items: + - enum: [ port0, port1 ] + + clocks: + minItems: 2 + maxItems: 2 + + clock-names: + items: + - enum: [ sys_ck0, sys_ck1 ] + - enum: [ ahb_ck0, ahb_ck1 ] + + reset: false + + reset-names: false + + phys: + maxItems: 1 + + phy-names: + items: + - enum: [ pcie-phy0, pcie-phy1 ] + + power-domains: false + + required: + - phys + - phy-names + + - if: + properties: + compatible: + const: mediatek,mt7622-pcie + then: + properties: + reg: + maxItems: 1 + + reg-names: + items: + - enum: [ port0, port1 ] + + clocks: + minItems: 6 + maxItems: 6 + + clock-names: + items: + - enum: [ sys_ck0, sys_ck1 ] + - enum: [ ahb_ck0, ahb_ck1 ] + - enum: [ aux_ck0, aux_ck1 ] + - enum: [ axi_ck0, axi_ck1 ] + - enum: [ obff_ck0, obff_ck1 ] + - enum: [ pipe_ck0, pipe_ck1 ] + + reset: false + + reset-names: false + + phys: false + + phy-names: false + + required: + - power-domains + + - if: + properties: + compatible: + const: mediatek,mt7629-pcie + then: + properties: + reg: + maxItems: 1 + + reg-names: + items: + - enum: [ port0, port1 ] + + clocks: + minItems: 6 + maxItems: 6 + + clock-names: + items: + - enum: [ sys_ck0, sys_ck1 ] + - enum: [ ahb_ck0, ahb_ck1 ] + - enum: [ aux_ck0, aux_ck1 ] + - enum: [ axi_ck0, axi_ck1 ] + - enum: [ obff_ck0, obff_ck1 ] + - enum: [ pipe_ck0, pipe_ck1 ] + + reset: false + + reset-names: false + + phys: + maxItems: 1 + + phy-names: + items: + - enum: [ pcie-phy0, pcie-phy1 ] + + required: + - power-domains + + - if: + properties: + compatible: + contains: + const: airoha,en7523-pcie + then: + properties: + reg: + maxItems: 1 + + reg-names: + items: + - enum: [ port0, port1 ] + + clocks: + maxItems: 1 + + clock-names: + items: + - enum: [ sys_ck0, sys_ck1 ] + + reset: false + + reset-names: false + + phys: false + + phy-names: false + + power-domain: false + +unevaluatedProperties: false + +examples: + # MT2712 + - | + #include + #include + #include + + soc_1 { + #address-cells =3D <2>; + #size-cells =3D <2>; + + pcie@112ff000 { + compatible =3D "mediatek,mt2712-pcie"; + device_type =3D "pci"; + reg =3D <0 0x112ff000 0 0x1000>; + reg-names =3D "port1"; + linux,pci-domain =3D <1>; + #address-cells =3D <3>; + #size-cells =3D <2>; + interrupts =3D ; + interrupt-names =3D "pcie_irq"; + clocks =3D <&topckgen>, /* CLK_TOP_PE2_MAC_P1_SEL */ + <&pericfg>; /* CLK_PERI_PCIE1 */ + clock-names =3D "sys_ck1", "ahb_ck1"; + phys =3D <&u3port1 PHY_TYPE_PCIE>; + phy-names =3D "pcie-phy1"; + bus-range =3D <0x00 0xff>; + ranges =3D <0x82000000 0 0x11400000 0x0 0x11400000 0 0x30000= 0>; + + #interrupt-cells =3D <1>; + interrupt-map-mask =3D <0 0 0 7>; + interrupt-map =3D <0 0 0 1 &pcie_intc1 0>, + <0 0 0 2 &pcie_intc1 1>, + <0 0 0 3 &pcie_intc1 2>, + <0 0 0 4 &pcie_intc1 3>; + pcie_intc1: interrupt-controller { + interrupt-controller; + #address-cells =3D <0>; + #interrupt-cells =3D <1>; + }; + }; + + pcie@11700000 { + compatible =3D "mediatek,mt2712-pcie"; + device_type =3D "pci"; + reg =3D <0 0x11700000 0 0x1000>; + reg-names =3D "port0"; + linux,pci-domain =3D <0>; + #address-cells =3D <3>; + #size-cells =3D <2>; + interrupts =3D ; + interrupt-names =3D "pcie_irq"; + clocks =3D <&topckgen>, /* CLK_TOP_PE2_MAC_P0_SEL */ + <&pericfg>; /* CLK_PERI_PCIE0 */ + clock-names =3D "sys_ck0", "ahb_ck0"; + phys =3D <&u3port0 PHY_TYPE_PCIE>; + phy-names =3D "pcie-phy0"; + bus-range =3D <0x00 0xff>; + ranges =3D <0x82000000 0 0x20000000 0x0 0x20000000 0 0x1000000= 0>; + + #interrupt-cells =3D <1>; + interrupt-map-mask =3D <0 0 0 7>; + interrupt-map =3D <0 0 0 1 &pcie_intc0 0>, + <0 0 0 2 &pcie_intc0 1>, + <0 0 0 3 &pcie_intc0 2>, + <0 0 0 4 &pcie_intc0 3>; + pcie_intc0: interrupt-controller { + interrupt-controller; + #address-cells =3D <0>; + #interrupt-cells =3D <1>; + }; + }; + }; + + # MT7622 + - | + #include + #include + #include + + soc_2 { + #address-cells =3D <2>; + #size-cells =3D <2>; + + pcie@1a143000 { + compatible =3D "mediatek,mt7622-pcie"; + device_type =3D "pci"; + reg =3D <0 0x1a143000 0 0x1000>; + reg-names =3D "port0"; + linux,pci-domain =3D <0>; + #address-cells =3D <3>; + #size-cells =3D <2>; + interrupts =3D ; + interrupt-names =3D "pcie_irq"; + clocks =3D <&pciesys>, /* CLK_PCIE_P0_MAC_EN */ + <&pciesys>, /* CLK_PCIE_P0_AHB_EN */ + <&pciesys>, /* CLK_PCIE_P0_AUX_EN */ + <&pciesys>, /* CLK_PCIE_P0_AXI_EN */ + <&pciesys>, /* CLK_PCIE_P0_OBFF_EN */ + <&pciesys>; /* CLK_PCIE_P0_PIPE_EN */ + clock-names =3D "sys_ck0", "ahb_ck0", "aux_ck0", + "axi_ck0", "obff_ck0", "pipe_ck0"; + + power-domains =3D <&scpsys MT7622_POWER_DOMAIN_HIF0>; + bus-range =3D <0x00 0xff>; + ranges =3D <0x82000000 0 0x20000000 0x0 0x20000000 0 0x80000= 00>; + + #interrupt-cells =3D <1>; + interrupt-map-mask =3D <0 0 0 7>; + interrupt-map =3D <0 0 0 1 &pcie_intc0_1 0>, + <0 0 0 2 &pcie_intc0_1 1>, + <0 0 0 3 &pcie_intc0_1 2>, + <0 0 0 4 &pcie_intc0_1 3>; + pcie_intc0_1: interrupt-controller { + interrupt-controller; + #address-cells =3D <0>; + #interrupt-cells =3D <1>; + }; + }; + + pcie@1a145000 { + compatible =3D "mediatek,mt7622-pcie"; + device_type =3D "pci"; + reg =3D <0 0x1a145000 0 0x1000>; + reg-names =3D "port1"; + linux,pci-domain =3D <1>; + #address-cells =3D <3>; + #size-cells =3D <2>; + interrupts =3D ; + interrupt-names =3D "pcie_irq"; + clocks =3D <&pciesys>, /* CLK_PCIE_P1_MAC_EN */ + /* designer has connect RC1 with p0_ahb clock */ + <&pciesys>, /* CLK_PCIE_P0_AHB_EN */ + <&pciesys>, /* CLK_PCIE_P1_AUX_EN */ + <&pciesys>, /* CLK_PCIE_P1_AXI_EN */ + <&pciesys>, /* CLK_PCIE_P1_OBFF_EN */ + <&pciesys>; /* CLK_PCIE_P1_PIPE_EN */ + clock-names =3D "sys_ck1", "ahb_ck1", "aux_ck1", + "axi_ck1", "obff_ck1", "pipe_ck1"; + + power-domains =3D <&scpsys MT7622_POWER_DOMAIN_HIF0>; + bus-range =3D <0x00 0xff>; + ranges =3D <0x82000000 0 0x28000000 0x0 0x28000000 0 0x80000= 00>; + + #interrupt-cells =3D <1>; + interrupt-map-mask =3D <0 0 0 7>; + interrupt-map =3D <0 0 0 1 &pcie_intc1_1 0>, + <0 0 0 2 &pcie_intc1_1 1>, + <0 0 0 3 &pcie_intc1_1 2>, + <0 0 0 4 &pcie_intc1_1 3>; + pcie_intc1_1: interrupt-controller { + interrupt-controller; + #address-cells =3D <0>; + #interrupt-cells =3D <1>; + }; + }; + }; --=20 2.51.0 From nobody Thu Oct 2 01:57:53 2025 Received: from mail-wr1-f49.google.com (mail-wr1-f49.google.com [209.85.221.49]) (using TLSv1.2 with cipher ECDHE-RSA-AES128-GCM-SHA256 (128/128 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id 3BA8930BF66 for ; Tue, 23 Sep 2025 20:12:59 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=none smtp.client-ip=209.85.221.49 ARC-Seal: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1758658381; cv=none; b=HYsYaggwX/5DEjBcMsC4L6UVYAsYY3S/A9uLMoY4tUL+8XBgzZkhqOxY9nLg7+0C2KzgG12bVQpDYvJc2a3PuMdHj6Xklzf5iM+vmeMrkwKGdWWFY6EQZOxnW1C7cagECmh5ESTKf07F1CzAM4M2LFY5jx7JsmqboJip2IiphAg= ARC-Message-Signature: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1758658381; c=relaxed/simple; bh=wI2EgBAstfuh0Lwsj21CyJ/ou9l4B9diH54Sb1sikXo=; h=From:To:Subject:Date:Message-ID:In-Reply-To:References: MIME-Version; b=t8N3T0WUA5ELm4K69SC4Ntwpm8F6FQlOWec2MtifFCRYCuHOi+rzxG3OO/4wMIruAXI+Kl8dRUhcGPDsN/2RiU/QkFvKKIZfI26tCyOPA3PNDqfieZz+5XwMRuIETgEreqPYnfTmtubBrGz4ciqQiGexiTzTzvJYdU8Xauykhcs= ARC-Authentication-Results: i=1; smtp.subspace.kernel.org; dmarc=pass (p=none dis=none) header.from=gmail.com; spf=pass smtp.mailfrom=gmail.com; dkim=pass (2048-bit key) header.d=gmail.com header.i=@gmail.com header.b=I4aWfbJM; arc=none smtp.client-ip=209.85.221.49 Authentication-Results: smtp.subspace.kernel.org; dmarc=pass (p=none dis=none) header.from=gmail.com Authentication-Results: smtp.subspace.kernel.org; spf=pass smtp.mailfrom=gmail.com Authentication-Results: smtp.subspace.kernel.org; dkim=pass (2048-bit key) header.d=gmail.com header.i=@gmail.com header.b="I4aWfbJM" Received: by mail-wr1-f49.google.com with SMTP id ffacd0b85a97d-3ee1381b835so3965787f8f.1 for ; Tue, 23 Sep 2025 13:12:59 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=gmail.com; s=20230601; t=1758658378; x=1759263178; darn=vger.kernel.org; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:to:from:from:to:cc:subject:date:message-id :reply-to; bh=ojrSKhmG/fxO+GWCa4ng/6S+zCuiK4Lwk2+N5nW6KeM=; b=I4aWfbJMLxNGvHYHVIkYpnqu8mEh3cI/hAX5eyDZ5wTUjKLvHB2bDVv50CDshakNMb cjBSIVdgxBZPpzbunAzbLyksezuF01h96yPYuvUduP/NNJjegpVODYKeVlDjJmaY7W50 9ChaMWE06wd628Utf/mDKIcqgQKkvPzgI1foL4SxuJ28vJAemWHwFgxSc00w+4KQxJ4i nxMjBg4FnqBj7ZUdLxXe0ogc1nnDgfNg03CNKTJ1EutTpezyKV05ihMxvPpMJqvLD6d9 gcpgv/UX634iwwBWlda64efvWwP0ogOrTvpYzwtj6B6ccM7fvFImyr63n+JSba4Wh4D8 cnCQ== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20230601; t=1758658378; x=1759263178; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:to:from:x-gm-message-state:from:to:cc :subject:date:message-id:reply-to; bh=ojrSKhmG/fxO+GWCa4ng/6S+zCuiK4Lwk2+N5nW6KeM=; b=qFc3MKD7el2q+/Qku9PTYv5SEwgL1SYiuqsMEAAqoUZr0ytsgGbtjfpPn6PL0VwmoI QrNLO09HniOj0za704x0Wgndm/7FhIDtu1IXLz0X9XjbwkyH70rlDcd/In5SEQ2J11C1 n5tSHwedtiGf/93Oy0RDjrVw0OTwZqeyTrEcRPm3SUYAeHzI3TDhSFXETDZGYrqd8nXu N/UJaeWpTRr3z27H6pOhJIL3m+UPS8DgJ4udQ52Nhu1LHB+euDaoQMkwF2f+vu2uYEVI L5NSVf5eJcltj2t4PhMxgSJNWV4YYpY6qam38GNJ7RoFjoq1vRdzlyE7HtlKmXyH0s1A Vy6w== X-Forwarded-Encrypted: i=1; AJvYcCV2w5JCNXMKv0JWBAkkM0JUoTWydhpwTvPiv2BLawRB1Xscp0Byo4FEjc4LaKSpjzJd4gFgQ/pMEQoOUXg=@vger.kernel.org X-Gm-Message-State: AOJu0YzCOSib9oLBb+v2phldk6BsUCc3I4x8jbvmSguDvfLdmr4jVaq4 3UKQUYFTL1oBAgPqggFHPg/lZ/lgAlzGkZDGb3KpZlqNYt6KpMKQYZ5D X-Gm-Gg: ASbGnctIBj+TAjTPWW7u9tQNm+IVGnAdo1HcyYPRwLVRvW9GG8fd1vdKRpIufzSOdZj pvCgV6DbiF8W87BmzzgODKgClYs7LIEPtex/AVM1Hrl+xQLQdDGJ/TWovhOahHanz6s5+PERSj3 k/AgzgwxWophyraYGbjr40AQORHf4E21VfuKW+/gwxa1gqLCGJ0wN8XmFv8kk8WaWBO93oaDmMx PDoUAnlsW8FIoeZm54Rx/lGfJr53MvRYimuYRm2se3Dm2ssThZj/zaUYTnKNXEXXSEOON0IFVGN k4yLbmU/tKG7LobaX/a2rrP+7mmd4r2k/M5LxxyYOsJoLwuHqyHVjmmcKw5KHhzQxT4Xb05Tyr4 8G3vTGWenvjEsbfAV9VQvZVMni+vlMJgV33vc18orBATtlOHKCVy5XtKVlB5CkxzODWgq+nY= X-Google-Smtp-Source: AGHT+IGqK47tNLWDzv+QVmr3Noen4JYHJzHX9XOvwSn6hx1DoeLXgBT/x9MNl6d/T3WqvGo45eUn9g== X-Received: by 2002:a05:6000:4024:b0:3d5:d5ea:38d5 with SMTP id ffacd0b85a97d-405c5eb6416mr3557423f8f.25.1758658377507; Tue, 23 Sep 2025 13:12:57 -0700 (PDT) Received: from Ansuel-XPS24 (host-95-249-236-54.retail.telecomitalia.it. [95.249.236.54]) by smtp.googlemail.com with ESMTPSA id ffacd0b85a97d-3ee141e9cf7sm24889690f8f.12.2025.09.23.13.12.55 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Tue, 23 Sep 2025 13:12:57 -0700 (PDT) From: Christian Marangi To: Michael Turquette , Stephen Boyd , Rob Herring , Krzysztof Kozlowski , Conor Dooley , Matthias Brugger , AngeloGioacchino Del Regno , Ryder Lee , Jianjun Wang , Bjorn Helgaas , Lorenzo Pieralisi , =?UTF-8?q?Krzysztof=20Wilczy=C5=84ski?= , Manivannan Sadhasivam , Christian Marangi , linux-clk@vger.kernel.org, devicetree@vger.kernel.org, linux-kernel@vger.kernel.org, linux-arm-kernel@lists.infradead.org, linux-mediatek@lists.infradead.org, linux-pci@vger.kernel.org, upstream@airoha.com Subject: [PATCH v2 3/4] dt-bindings: PCI: mediatek: Add support for Airoha AN7583 Date: Tue, 23 Sep 2025 22:12:31 +0200 Message-ID: <20250923201244.952-4-ansuelsmth@gmail.com> X-Mailer: git-send-email 2.51.0 In-Reply-To: <20250923201244.952-1-ansuelsmth@gmail.com> References: <20250923201244.952-1-ansuelsmth@gmail.com> Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Content-Type: text/plain; charset="utf-8" Introduce Airoha AN7583 SoC compatible in mediatek PCIe controller binding. Similar to GEN3, the Airoha AN7583 GEN2 PCIe controller require the PBUS csr property to permit the correct functionality of the PCIe controller. Signed-off-by: Christian Marangi --- .../bindings/pci/mediatek-pcie.yaml | 110 ++++++++++++++++++ 1 file changed, 110 insertions(+) diff --git a/Documentation/devicetree/bindings/pci/mediatek-pcie.yaml b/Doc= umentation/devicetree/bindings/pci/mediatek-pcie.yaml index e3afedb77a01..46000049a6c5 100644 --- a/Documentation/devicetree/bindings/pci/mediatek-pcie.yaml +++ b/Documentation/devicetree/bindings/pci/mediatek-pcie.yaml @@ -13,6 +13,7 @@ properties: compatible: oneOf: - enum: + - airoha,an7583-pcie - mediatek,mt2712-pcie - mediatek,mt7622-pcie - mediatek,mt7629-pcie @@ -61,6 +62,17 @@ properties: power-domains: maxItems: 1 =20 + mediatek,pbus-csr: + $ref: /schemas/types.yaml#/definitions/phandle-array + items: + - items: + - description: phandle to pbus-csr syscon + - description: offset of pbus-csr base address register + - description: offset of pbus-csr base address mask register + description: + Phandle with two arguments to the syscon node used to detect if + a given address is accessible on PCIe controller. + '#interrupt-cells': const: 1 =20 @@ -96,6 +108,45 @@ required: allOf: - $ref: /schemas/pci/pci-host-bridge.yaml# =20 + - if: + properties: + compatible: + const: airoha,an7583-pcie + then: + properties: + reg: + maxItems: 1 + + reg-names: + const: port1 + + clocks: + maxItems: 1 + + clock-names: + const: sys_ck1 + + reset: + maxItems: 1 + + reset-names: + const: pcie-rst1 + + phys: + maxItems: 1 + + phy-names: + const: pcie-phy1 + + power-domain: false + + required: + - resets + - reset-names + - phys + - phy-names + - mediatek,pbus-csr + - if: properties: compatible: @@ -131,6 +182,8 @@ allOf: =20 power-domains: false =20 + mediatek,pbus-csr: false + required: - phys - phy-names @@ -169,6 +222,8 @@ allOf: =20 phy-names: false =20 + mediatek,pbus-csr: false + required: - power-domains =20 @@ -209,6 +264,8 @@ allOf: items: - enum: [ pcie-phy0, pcie-phy1 ] =20 + mediatek,pbus-csr: false + required: - power-domains =20 @@ -243,6 +300,8 @@ allOf: =20 power-domain: false =20 + mediatek,pbus-csr: false + unevaluatedProperties: false =20 examples: @@ -402,3 +461,54 @@ examples: }; }; }; + + # AN7583 + - | + #include + #include + #include + + soc_3 { + #address-cells =3D <2>; + #size-cells =3D <2>; + + pcie@1fa92000 { + compatible =3D "airoha,an7583-pcie"; + device_type =3D "pci"; + linux,pci-domain =3D <1>; + #address-cells =3D <3>; + #size-cells =3D <2>; + + reg =3D <0x0 0x1fa92000 0x0 0x1670>; + reg-names =3D "port1"; + + clocks =3D <&scuclk EN7523_CLK_PCIE>; + clock-names =3D "sys_ck1"; + + phys =3D <&pciephy>; + phy-names =3D "pcie-phy1"; + + ranges =3D <0x02000000 0 0x24000000 0x0 0x24000000 0 0x4000000= >; + + resets =3D <&scuclk>; /* AN7583_PCIE1_RST */ + reset-names =3D "pcie-rst1"; + + mediatek,pbus-csr =3D <&pbus_csr 0x8 0xc>; + + interrupts =3D ; + interrupt-names =3D "pcie_irq"; + bus-range =3D <0x00 0xff>; + #interrupt-cells =3D <1>; + interrupt-map-mask =3D <0 0 0 7>; + interrupt-map =3D <0 0 0 1 &pcie_intc1 0>, + <0 0 0 2 &pcie_intc1 1>, + <0 0 0 3 &pcie_intc1 2>, + <0 0 0 4 &pcie_intc1 3>; + + pcie_intc1_4: interrupt-controller { + interrupt-controller; + #address-cells =3D <0>; + #interrupt-cells =3D <1>; + }; + }; + }; --=20 2.51.0 From nobody Thu Oct 2 01:57:53 2025 Received: from mail-wr1-f43.google.com (mail-wr1-f43.google.com [209.85.221.43]) (using TLSv1.2 with cipher ECDHE-RSA-AES128-GCM-SHA256 (128/128 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id 5FB9830C36F for ; Tue, 23 Sep 2025 20:13:01 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=none smtp.client-ip=209.85.221.43 ARC-Seal: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1758658385; cv=none; b=ltQokGhwoEi+hzL6zsHepp4hK65Zf/G6/mc6bElH7eRK/qmGC1IRP5OrMjKwnH5wgtnV32ZcqZOzPd3vVlo6kwwi7litdDEa0O12FbVHxh8Zti1ENu7KVIdc7tHy1liQVXXlM8VaO07ZT1y3WcE/rCtPVzFyPhwxugV46CG5ATE= ARC-Message-Signature: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1758658385; c=relaxed/simple; bh=gQpZKL9PYN00DxqOhZ2zLTrFv9ZJsPxReul3Hvo1omc=; h=From:To:Subject:Date:Message-ID:In-Reply-To:References: MIME-Version; b=caPfgu6TawrG72b/YAimVPsHaYwaetn+6j39UpJkYzLxe5qf8EXR5DVxwhaRkK3wE7ZADaJvfMXOIRZnWTfghvg+tnut+Gzolhnao4qrVtNx/Rc19aOOf9XpwyWzqOxfcyg8zRhRqDCYLQjzdFF568sQopNf/hgayNNSFJhLWDA= ARC-Authentication-Results: i=1; smtp.subspace.kernel.org; dmarc=pass (p=none dis=none) header.from=gmail.com; spf=pass smtp.mailfrom=gmail.com; dkim=pass (2048-bit key) header.d=gmail.com header.i=@gmail.com header.b=k78OxRq0; arc=none smtp.client-ip=209.85.221.43 Authentication-Results: smtp.subspace.kernel.org; dmarc=pass (p=none dis=none) header.from=gmail.com Authentication-Results: smtp.subspace.kernel.org; spf=pass smtp.mailfrom=gmail.com Authentication-Results: smtp.subspace.kernel.org; dkim=pass (2048-bit key) header.d=gmail.com header.i=@gmail.com header.b="k78OxRq0" Received: by mail-wr1-f43.google.com with SMTP id ffacd0b85a97d-3ee12807d97so5249129f8f.0 for ; Tue, 23 Sep 2025 13:13:01 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=gmail.com; s=20230601; t=1758658380; x=1759263180; darn=vger.kernel.org; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:to:from:from:to:cc:subject:date:message-id :reply-to; bh=aly97HE4DbfA98BoW1r98QzzxmSOsTSspnaWMcDHFeI=; b=k78OxRq0jDjdH/jSVoQ42tnSX4MziM/58G72QrK0KirNaygnUtcjxwaxFTP/bVEeHh V+hY5F8ghWi63phHNSGNo7fD0h4ynudLvkLnFTWbX80O07+c5QaGGoNke2Bw3cxVUPIh 7qY+BVY8bd7wDncwtpd3JthZzFF6cKuCfaaIfjt7RL1r+M4s7mG5eBKQ/gUoN4KAmuBt xIOccVcifUXrDATGNVbJFl/OIc1kdVxALyVsfW//Yuf/YDhPpNBoGomOgC5m/DxiHz2u DkiSVUn++xV2q48Q685kX8Asv1h7pcDXDM4O2Q/9/go9hJhRzTa1ZaH6JQrRuBvn/ckY c71g== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20230601; t=1758658380; x=1759263180; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:to:from:x-gm-message-state:from:to:cc :subject:date:message-id:reply-to; bh=aly97HE4DbfA98BoW1r98QzzxmSOsTSspnaWMcDHFeI=; b=DcX1P9A2rC83QH3JUc095He/kJ/3mDKsg2vX2TcLvLihQ5b7SOn2Aj7v7yTgr+QQ31 8aA42ceuDgWgfMff1ItoCEoEkgpSzMZmJuMTuaTzzs+74QukxWg7K93cq7MxM2Gi9O6N tF/GsPCQareEjFEHjZgl5SNDF3GaFXllcm499oFzzD57WcFUR6lz3Buvz6Fld7jf4WTu 8MljeuJWbk6kqkHfkOC5n3D9j9g1LOJEj2Ke62lCLdqMDdjgKgi2MVE1Shh0Hk8sG10F DbhgIZVq/KbSMZip2w0rNSslHQkhYIWz1mTv+FVEx38N24a4XaynY4p2v7BPL4XYlYvr nq8w== X-Forwarded-Encrypted: i=1; AJvYcCWZaKE7/5T8lneI/f0FlNc1x4cJyyaAV/ogSBqUOYl9BabrxxRh+XoVRqRJNLEkL/i+dq4KbP85PSMx6wA=@vger.kernel.org X-Gm-Message-State: AOJu0Yx8GhH4A+BRnTRdFhkTu1UauSAFyHxNtqsfg9Nge4DCseILG5UW nFSeqcEajl/lFLiXx2rcY6SeQfmu9vGCYFfOlZEdJGRBIm+K11+ZDIU0 X-Gm-Gg: ASbGnctyk8X/c+VzKWMljaQdBiKGNSistZd8C3tQuJJT2XRfwhCOSEjL/fn1H5K/mtI H6TrlLrCYoO+pAVcmQYMRPRPp+ss1aHLZrHS3gLmkOr82Aak5cPi4WL+CZKoJOYDeYDEu4nQ4Y6 ncCDPyhxzX+LHHH5OeWBclbH8xjeMVWcHegL6qkNRFb+8bvx7GmmCUiQGUNeZKx1wg3UVe58HLe 5C/lRh1iS2Rqaj+KUS20QqVT8v0d38T5rhcMSXWAk/dztmYWAmgudkR5o/GkYd8V6eSM2WOray6 JKGphdIxGK5xXnmWn1qCD+2mYIbXyLV02ErkDLZDft+TAWJcRtsc9u8QsFpQKXB3M/al+oAY3x8 I+/tNgrdWlldcCooGECjnewb0HisSRFqWrZO7a0Ti1qXqwaqnRihG0ZClanWuy07xvypoKec= X-Google-Smtp-Source: AGHT+IFbHn8VL6NabBiNOJDmra87r8MK+4nqnknbe3Uap+qkSdJFvH4B0H/cqDTPX4N5G1MGJJWP8Q== X-Received: by 2002:a5d:5889:0:b0:3ec:d78d:8fde with SMTP id ffacd0b85a97d-405cb7bbd49mr3615361f8f.44.1758658379499; Tue, 23 Sep 2025 13:12:59 -0700 (PDT) Received: from Ansuel-XPS24 (host-95-249-236-54.retail.telecomitalia.it. [95.249.236.54]) by smtp.googlemail.com with ESMTPSA id ffacd0b85a97d-3ee141e9cf7sm24889690f8f.12.2025.09.23.13.12.57 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Tue, 23 Sep 2025 13:12:59 -0700 (PDT) From: Christian Marangi To: Michael Turquette , Stephen Boyd , Rob Herring , Krzysztof Kozlowski , Conor Dooley , Matthias Brugger , AngeloGioacchino Del Regno , Ryder Lee , Jianjun Wang , Bjorn Helgaas , Lorenzo Pieralisi , =?UTF-8?q?Krzysztof=20Wilczy=C5=84ski?= , Manivannan Sadhasivam , Christian Marangi , linux-clk@vger.kernel.org, devicetree@vger.kernel.org, linux-kernel@vger.kernel.org, linux-arm-kernel@lists.infradead.org, linux-mediatek@lists.infradead.org, linux-pci@vger.kernel.org, upstream@airoha.com Subject: [PATCH v2 4/4] PCI: mediatek: add support for Airoha AN7583 SoC Date: Tue, 23 Sep 2025 22:12:32 +0200 Message-ID: <20250923201244.952-5-ansuelsmth@gmail.com> X-Mailer: git-send-email 2.51.0 In-Reply-To: <20250923201244.952-1-ansuelsmth@gmail.com> References: <20250923201244.952-1-ansuelsmth@gmail.com> Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Content-Type: text/plain; charset="utf-8" Add support for the second PCIe line present on Airoha AN7583 SoC. This is based on the Mediatek Gen1/2 PCIe driver and similar to Gen3 also require workaround for the reset signals. Introduce a new bool to skip having to reset signals and also introduce some additional logic to configure the PBUS registers required for Airoha SoC. Signed-off-by: Christian Marangi --- drivers/pci/controller/pcie-mediatek.c | 85 +++++++++++++++++++------- 1 file changed, 63 insertions(+), 22 deletions(-) diff --git a/drivers/pci/controller/pcie-mediatek.c b/drivers/pci/controlle= r/pcie-mediatek.c index 24cc30a2ab6c..640d1f1a6478 100644 --- a/drivers/pci/controller/pcie-mediatek.c +++ b/drivers/pci/controller/pcie-mediatek.c @@ -147,6 +147,7 @@ struct mtk_pcie_port; * @need_fix_class_id: whether this host's class ID needed to be fixed or = not * @need_fix_device_id: whether this host's device ID needed to be fixed o= r not * @no_msi: Bridge has no MSI support, and relies on an external block + * @skip_pcie_rstb: Skip calling RSTB bits on PCIe probe * @device_id: device ID which this host need to be fixed * @ops: pointer to configuration access functions * @startup: pointer to controller setting functions @@ -156,6 +157,7 @@ struct mtk_pcie_soc { bool need_fix_class_id; bool need_fix_device_id; bool no_msi; + bool skip_pcie_rstb; unsigned int device_id; struct pci_ops *ops; int (*startup)(struct mtk_pcie_port *port); @@ -679,28 +681,30 @@ static int mtk_pcie_startup_port_v2(struct mtk_pcie_p= ort *port) regmap_update_bits(pcie->cfg, PCIE_SYS_CFG_V2, val, val); } =20 - /* Assert all reset signals */ - writel(0, port->base + PCIE_RST_CTRL); - - /* - * Enable PCIe link down reset, if link status changed from link up to - * link down, this will reset MAC control registers and configuration - * space. - */ - writel(PCIE_LINKDOWN_RST_EN, port->base + PCIE_RST_CTRL); - - /* - * Described in PCIe CEM specification sections 2.2 (PERST# Signal) and - * 2.2.1 (Initial Power-Up (G3 to S0)). The deassertion of PERST# should - * be delayed 100ms (TPVPERL) for the power and clock to become stable. - */ - msleep(100); - - /* De-assert PHY, PE, PIPE, MAC and configuration reset */ - val =3D readl(port->base + PCIE_RST_CTRL); - val |=3D PCIE_PHY_RSTB | PCIE_PERSTB | PCIE_PIPE_SRSTB | - PCIE_MAC_SRSTB | PCIE_CRSTB; - writel(val, port->base + PCIE_RST_CTRL); + if (!soc->skip_pcie_rstb) { + /* Assert all reset signals */ + writel(0, port->base + PCIE_RST_CTRL); + + /* + * Enable PCIe link down reset, if link status changed from link up to + * link down, this will reset MAC control registers and configuration + * space. + */ + writel(PCIE_LINKDOWN_RST_EN, port->base + PCIE_RST_CTRL); + + /* + * Described in PCIe CEM specification sections 2.2 (PERST# Signal) and + * 2.2.1 (Initial Power-Up (G3 to S0)). The deassertion of PERST# should + * be delayed 100ms (TPVPERL) for the power and clock to become stable. + */ + msleep(100); + + /* De-assert PHY, PE, PIPE, MAC and configuration reset */ + val =3D readl(port->base + PCIE_RST_CTRL); + val |=3D PCIE_PHY_RSTB | PCIE_PERSTB | PCIE_PIPE_SRSTB | + PCIE_MAC_SRSTB | PCIE_CRSTB; + writel(val, port->base + PCIE_RST_CTRL); + } =20 /* Set up vendor ID and class code */ if (soc->need_fix_class_id) { @@ -1105,6 +1109,33 @@ static int mtk_pcie_probe(struct platform_device *pd= ev) if (err) goto put_resources; =20 + if (device_is_compatible(dev, "airoha,an7583-pcie")) { + struct resource_entry *entry; + struct regmap *pbus_regmap; + resource_size_t addr; + u32 args[2], size; + + /* + * Configure PBus base address and base address mask to allow the + * hw to detect if a given address is accessible on PCIe controller. + */ + pbus_regmap =3D syscon_regmap_lookup_by_phandle_args(dev->of_node, + "mediatek,pbus-csr", + ARRAY_SIZE(args), + args); + if (IS_ERR(pbus_regmap)) + return PTR_ERR(pbus_regmap); + + entry =3D resource_list_first_type(&host->windows, IORESOURCE_MEM); + if (!entry) + return -ENODEV; + + addr =3D entry->res->start - entry->offset; + regmap_write(pbus_regmap, args[0], lower_32_bits(addr)); + size =3D lower_32_bits(resource_size(entry->res)); + regmap_write(pbus_regmap, args[1], GENMASK(31, __fls(size))); + } + return 0; =20 put_resources: @@ -1205,6 +1236,15 @@ static const struct mtk_pcie_soc mtk_pcie_soc_mt7622= =3D { .setup_irq =3D mtk_pcie_setup_irq, }; =20 +static const struct mtk_pcie_soc mtk_pcie_soc_an7583 =3D { + .skip_pcie_rstb =3D true, + .need_fix_class_id =3D true, + .need_fix_device_id =3D false, + .ops =3D &mtk_pcie_ops_v2, + .startup =3D mtk_pcie_startup_port_v2, + .setup_irq =3D mtk_pcie_setup_irq, +}; + static const struct mtk_pcie_soc mtk_pcie_soc_mt7629 =3D { .need_fix_class_id =3D true, .need_fix_device_id =3D true, @@ -1215,6 +1255,7 @@ static const struct mtk_pcie_soc mtk_pcie_soc_mt7629 = =3D { }; =20 static const struct of_device_id mtk_pcie_ids[] =3D { + { .compatible =3D "airoha,an7583-pcie", .data =3D &mtk_pcie_soc_an7583 }, { .compatible =3D "mediatek,mt2701-pcie", .data =3D &mtk_pcie_soc_v1 }, { .compatible =3D "mediatek,mt7623-pcie", .data =3D &mtk_pcie_soc_v1 }, { .compatible =3D "mediatek,mt2712-pcie", .data =3D &mtk_pcie_soc_mt2712 = }, --=20 2.51.0