From nobody Thu Oct 2 03:36:20 2025 Received: from relmlie6.idc.renesas.com (relmlor2.renesas.com [210.160.252.172]) by smtp.subspace.kernel.org (Postfix) with ESMTP id 5098B2356C7; Tue, 23 Sep 2025 16:06:05 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=none smtp.client-ip=210.160.252.172 ARC-Seal: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1758643568; cv=none; b=BTqh+dQbnXzoZ4dHooSx46VsJuF8W8cRlJf6rso2EmltFLxZHxnJHbTrijfOB3UrHEnMBmGTFuzeWSRcFHGuXSNZ3HC9Lx/10da6F6AQDSIaTtSLcx6EEaFLQ7ppCaZjRFLUUooaXz6/PCoLZXzO8ZoQAz8YEdauvoKtujKmg4k= ARC-Message-Signature: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1758643568; c=relaxed/simple; bh=WkkC0kT5N1Q9IYtxl+k06yYtAGzKSUAMrKpNLaxFa6s=; h=From:To:Cc:Subject:Date:Message-ID:In-Reply-To:References: MIME-Version; b=CsXwuGxuPDlcktKspPedbcXQuWuzp3FEb9laHC51rCPajBUqXfmLPG0OOkbOw72DwuRIYKjSpCX/wvyAsTHtiKsBOX1Ho3daJITbbvK0l3hhfWN0SpRvC+K7HUzjGIO1ynRzOtUqV4e21OtwIJVMPutq0btWQFy2Kz0NyhylHGo= ARC-Authentication-Results: i=1; smtp.subspace.kernel.org; dmarc=pass (p=none dis=none) header.from=renesas.com; spf=pass smtp.mailfrom=renesas.com; arc=none smtp.client-ip=210.160.252.172 Authentication-Results: smtp.subspace.kernel.org; dmarc=pass (p=none dis=none) header.from=renesas.com Authentication-Results: smtp.subspace.kernel.org; spf=pass smtp.mailfrom=renesas.com X-CSE-ConnectionGUID: gyGMm+LbS6a0rEVG2hINUg== X-CSE-MsgGUID: bs7SgK8uRsmkXt1mLdYZdA== Received: from unknown (HELO relmlir5.idc.renesas.com) ([10.200.68.151]) by relmlie6.idc.renesas.com with ESMTP; 24 Sep 2025 01:06:05 +0900 Received: from demon-pc.localdomain (unknown [10.226.93.64]) by relmlir5.idc.renesas.com (Postfix) with ESMTP id E6D064008A2F; Wed, 24 Sep 2025 01:05:59 +0900 (JST) From: Cosmin Tanislav To: Cc: Cosmin Tanislav , Jonathan Cameron , David Lechner , =?UTF-8?q?Nuno=20S=C3=A1?= , Andy Shevchenko , Rob Herring , Krzysztof Kozlowski , Conor Dooley , Geert Uytterhoeven , Magnus Damm , Michael Turquette , Stephen Boyd , Lad Prabhakar , linux-iio@vger.kernel.org, linux-renesas-soc@vger.kernel.org, devicetree@vger.kernel.org, linux-kernel@vger.kernel.org, linux-clk@vger.kernel.org Subject: [PATCH 1/7] clk: renesas: r9a09g077: Add ADC modules clock Date: Tue, 23 Sep 2025 19:05:15 +0300 Message-ID: <20250923160524.1096720-2-cosmin-gabriel.tanislav.xa@renesas.com> X-Mailer: git-send-email 2.51.0 In-Reply-To: <20250923160524.1096720-1-cosmin-gabriel.tanislav.xa@renesas.com> References: <20250923160524.1096720-1-cosmin-gabriel.tanislav.xa@renesas.com> Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Content-Type: text/plain; charset="utf-8" Renesas RZ/T2H (R9A09G077) and RZ/N2H (R9A09G087) SoCs have three 12bit ADC peripherals, each with its own peripheral clock. For conversion, they use the PCLKL clock. Add their clocks to the list of module clocks. Signed-off-by: Cosmin Tanislav Reviewed-by: Geert Uytterhoeven --- drivers/clk/renesas/r9a09g077-cpg.c | 3 +++ 1 file changed, 3 insertions(+) diff --git a/drivers/clk/renesas/r9a09g077-cpg.c b/drivers/clk/renesas/r9a0= 9g077-cpg.c index 3aaa154102d5..5dca5c44043e 100644 --- a/drivers/clk/renesas/r9a09g077-cpg.c +++ b/drivers/clk/renesas/r9a09g077-cpg.c @@ -192,6 +192,9 @@ static const struct mssr_mod_clk r9a09g077_mod_clks[] _= _initconst =3D { DEF_MOD("sci4fck", 12, CLK_SCI4ASYNC), DEF_MOD("iic0", 100, R9A09G077_CLK_PCLKL), DEF_MOD("iic1", 101, R9A09G077_CLK_PCLKL), + DEF_MOD("adc0", 206, R9A09G077_CLK_PCLKH), + DEF_MOD("adc1", 207, R9A09G077_CLK_PCLKH), + DEF_MOD("adc2", 225, R9A09G077_CLK_PCLKM), DEF_MOD("gmac0", 400, R9A09G077_CLK_PCLKM), DEF_MOD("ethsw", 401, R9A09G077_CLK_PCLKM), DEF_MOD("ethss", 403, R9A09G077_CLK_PCLKM), --=20 2.51.0