From nobody Thu Oct 2 02:16:39 2025 Received: from relmlie6.idc.renesas.com (relmlor2.renesas.com [210.160.252.172]) by smtp.subspace.kernel.org (Postfix) with ESMTP id 5098B2356C7; Tue, 23 Sep 2025 16:06:05 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=none smtp.client-ip=210.160.252.172 ARC-Seal: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1758643568; cv=none; b=BTqh+dQbnXzoZ4dHooSx46VsJuF8W8cRlJf6rso2EmltFLxZHxnJHbTrijfOB3UrHEnMBmGTFuzeWSRcFHGuXSNZ3HC9Lx/10da6F6AQDSIaTtSLcx6EEaFLQ7ppCaZjRFLUUooaXz6/PCoLZXzO8ZoQAz8YEdauvoKtujKmg4k= ARC-Message-Signature: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1758643568; c=relaxed/simple; bh=WkkC0kT5N1Q9IYtxl+k06yYtAGzKSUAMrKpNLaxFa6s=; h=From:To:Cc:Subject:Date:Message-ID:In-Reply-To:References: MIME-Version; b=CsXwuGxuPDlcktKspPedbcXQuWuzp3FEb9laHC51rCPajBUqXfmLPG0OOkbOw72DwuRIYKjSpCX/wvyAsTHtiKsBOX1Ho3daJITbbvK0l3hhfWN0SpRvC+K7HUzjGIO1ynRzOtUqV4e21OtwIJVMPutq0btWQFy2Kz0NyhylHGo= ARC-Authentication-Results: i=1; smtp.subspace.kernel.org; dmarc=pass (p=none dis=none) header.from=renesas.com; spf=pass smtp.mailfrom=renesas.com; arc=none smtp.client-ip=210.160.252.172 Authentication-Results: smtp.subspace.kernel.org; dmarc=pass (p=none dis=none) header.from=renesas.com Authentication-Results: smtp.subspace.kernel.org; spf=pass smtp.mailfrom=renesas.com X-CSE-ConnectionGUID: gyGMm+LbS6a0rEVG2hINUg== X-CSE-MsgGUID: bs7SgK8uRsmkXt1mLdYZdA== Received: from unknown (HELO relmlir5.idc.renesas.com) ([10.200.68.151]) by relmlie6.idc.renesas.com with ESMTP; 24 Sep 2025 01:06:05 +0900 Received: from demon-pc.localdomain (unknown [10.226.93.64]) by relmlir5.idc.renesas.com (Postfix) with ESMTP id E6D064008A2F; Wed, 24 Sep 2025 01:05:59 +0900 (JST) From: Cosmin Tanislav To: Cc: Cosmin Tanislav , Jonathan Cameron , David Lechner , =?UTF-8?q?Nuno=20S=C3=A1?= , Andy Shevchenko , Rob Herring , Krzysztof Kozlowski , Conor Dooley , Geert Uytterhoeven , Magnus Damm , Michael Turquette , Stephen Boyd , Lad Prabhakar , linux-iio@vger.kernel.org, linux-renesas-soc@vger.kernel.org, devicetree@vger.kernel.org, linux-kernel@vger.kernel.org, linux-clk@vger.kernel.org Subject: [PATCH 1/7] clk: renesas: r9a09g077: Add ADC modules clock Date: Tue, 23 Sep 2025 19:05:15 +0300 Message-ID: <20250923160524.1096720-2-cosmin-gabriel.tanislav.xa@renesas.com> X-Mailer: git-send-email 2.51.0 In-Reply-To: <20250923160524.1096720-1-cosmin-gabriel.tanislav.xa@renesas.com> References: <20250923160524.1096720-1-cosmin-gabriel.tanislav.xa@renesas.com> Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Content-Type: text/plain; charset="utf-8" Renesas RZ/T2H (R9A09G077) and RZ/N2H (R9A09G087) SoCs have three 12bit ADC peripherals, each with its own peripheral clock. For conversion, they use the PCLKL clock. Add their clocks to the list of module clocks. Signed-off-by: Cosmin Tanislav Reviewed-by: Geert Uytterhoeven --- drivers/clk/renesas/r9a09g077-cpg.c | 3 +++ 1 file changed, 3 insertions(+) diff --git a/drivers/clk/renesas/r9a09g077-cpg.c b/drivers/clk/renesas/r9a0= 9g077-cpg.c index 3aaa154102d5..5dca5c44043e 100644 --- a/drivers/clk/renesas/r9a09g077-cpg.c +++ b/drivers/clk/renesas/r9a09g077-cpg.c @@ -192,6 +192,9 @@ static const struct mssr_mod_clk r9a09g077_mod_clks[] _= _initconst =3D { DEF_MOD("sci4fck", 12, CLK_SCI4ASYNC), DEF_MOD("iic0", 100, R9A09G077_CLK_PCLKL), DEF_MOD("iic1", 101, R9A09G077_CLK_PCLKL), + DEF_MOD("adc0", 206, R9A09G077_CLK_PCLKH), + DEF_MOD("adc1", 207, R9A09G077_CLK_PCLKH), + DEF_MOD("adc2", 225, R9A09G077_CLK_PCLKM), DEF_MOD("gmac0", 400, R9A09G077_CLK_PCLKM), DEF_MOD("ethsw", 401, R9A09G077_CLK_PCLKM), DEF_MOD("ethss", 403, R9A09G077_CLK_PCLKM), --=20 2.51.0 From nobody Thu Oct 2 02:16:39 2025 Received: from relmlie5.idc.renesas.com (relmlor1.renesas.com [210.160.252.171]) by smtp.subspace.kernel.org (Postfix) with ESMTP id C3FC1266B56; Tue, 23 Sep 2025 16:06:12 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=none smtp.client-ip=210.160.252.171 ARC-Seal: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1758643575; cv=none; b=RDkdubwHJCa39gocILAYBreUHxa2IIgYvG/nubpRcrytidA3e0cvK6R0KkS5ICtJ3VSFy5uMWDZpxElW0UR7dZOfPqim5YCzbllge93J68QhodJgTVd6wEpCqP6/XDaG/EqLlNpIgBVhdGIqRiNRNDdT/vMa9cq4rNfASbMuaQo= ARC-Message-Signature: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1758643575; c=relaxed/simple; bh=BJJpFKc3eWPnUQN05pacgwN7SfjzcTDEsetqVeomAtg=; h=From:To:Cc:Subject:Date:Message-ID:In-Reply-To:References: MIME-Version; b=fog+v030n9tTz+wmL5rHxZRfktWeRuIVNdd18qrasDQA0s1g0nGqhs3iLSn77JX+Xsjni5fA0jHkbpg/nj9rruaWock9/fRp4WBkxGMCK8cSkguqMVjpLkpByvvZ+VuKg9zLAiE50PxnqYf9DPCncZ8L4LSvV+X+G/iZQ6c03Jo= ARC-Authentication-Results: i=1; smtp.subspace.kernel.org; dmarc=pass (p=none dis=none) header.from=renesas.com; spf=pass smtp.mailfrom=renesas.com; arc=none smtp.client-ip=210.160.252.171 Authentication-Results: smtp.subspace.kernel.org; dmarc=pass (p=none dis=none) header.from=renesas.com Authentication-Results: smtp.subspace.kernel.org; spf=pass smtp.mailfrom=renesas.com X-CSE-ConnectionGUID: OU6AneBWR+aivyAowQmlbw== X-CSE-MsgGUID: yLMfyZXzQ2KSfB8WP/fzjg== Received: from unknown (HELO relmlir5.idc.renesas.com) ([10.200.68.151]) by relmlie5.idc.renesas.com with ESMTP; 24 Sep 2025 01:06:12 +0900 Received: from demon-pc.localdomain (unknown [10.226.93.64]) by relmlir5.idc.renesas.com (Postfix) with ESMTP id 91CAF4008A2F; Wed, 24 Sep 2025 01:06:06 +0900 (JST) From: Cosmin Tanislav To: Cc: Cosmin Tanislav , Jonathan Cameron , David Lechner , =?UTF-8?q?Nuno=20S=C3=A1?= , Andy Shevchenko , Rob Herring , Krzysztof Kozlowski , Conor Dooley , Geert Uytterhoeven , Magnus Damm , Michael Turquette , Stephen Boyd , Lad Prabhakar , linux-iio@vger.kernel.org, linux-renesas-soc@vger.kernel.org, devicetree@vger.kernel.org, linux-kernel@vger.kernel.org, linux-clk@vger.kernel.org Subject: [PATCH 2/7] dt-bindings: iio: adc: document RZ/T2H and RZ/N2H ADC Date: Tue, 23 Sep 2025 19:05:16 +0300 Message-ID: <20250923160524.1096720-3-cosmin-gabriel.tanislav.xa@renesas.com> X-Mailer: git-send-email 2.51.0 In-Reply-To: <20250923160524.1096720-1-cosmin-gabriel.tanislav.xa@renesas.com> References: <20250923160524.1096720-1-cosmin-gabriel.tanislav.xa@renesas.com> Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Content-Type: text/plain; charset="utf-8" Document the A/D 12-Bit successive approximation converters found in the Renesas RZ/T2H (R9A09G077) and RZ/N2H (R9A09G087) SoCs. RZ/T2H has two ADCs with 4 channels and one with 6. RZ/N2H has two ADCs with 4 channels and one with 15. Signed-off-by: Cosmin Tanislav --- .../iio/adc/renesas,r9a09g077-adc.yaml | 170 ++++++++++++++++++ MAINTAINERS | 7 + 2 files changed, 177 insertions(+) create mode 100644 Documentation/devicetree/bindings/iio/adc/renesas,r9a09= g077-adc.yaml diff --git a/Documentation/devicetree/bindings/iio/adc/renesas,r9a09g077-ad= c.yaml b/Documentation/devicetree/bindings/iio/adc/renesas,r9a09g077-adc.ya= ml new file mode 100644 index 000000000000..840108cd317e --- /dev/null +++ b/Documentation/devicetree/bindings/iio/adc/renesas,r9a09g077-adc.yaml @@ -0,0 +1,170 @@ +# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause) +%YAML 1.2 +--- +$id: http://devicetree.org/schemas/iio/adc/renesas,r9a09g077-adc.yaml# +$schema: http://devicetree.org/meta-schemas/core.yaml# + +title: Renesas RZ/T2H / RZ/N2H ADC12 + +maintainers: + - Cosmin Tanislav + +description: | + A/D Converter block is a successive approximation analog-to-digital conv= erter + with a 12-bit accuracy. Up to 15 analog input channels can be selected. + Conversions can be performed in single or continuous mode. Result of the= ADC + is stored in a 16-bit data register corresponding to each channel. + +properties: + compatible: + enum: + - renesas,r9a09g077-adc # RZ/T2H + - renesas,r9a09g087-adc # RZ/N2H + + reg: + maxItems: 1 + + interrupts: + items: + - description: A/D scan end interrupt + - description: A/D scan end interrupt for Group B + - description: A/D scan end interrupt for Group C + - description: Window A compare match + - description: Window B compare match + - description: Compare match + - description: Compare mismatch + + interrupt-names: + items: + - const: adi + - const: gbadi + - const: gcadi + - const: cmpai + - const: cmpbi + - const: wcmpm + - const: wcmpum + + clocks: + items: + - description: converter clock + - description: peripheral clock + + clock-names: + items: + - const: adclk + - const: pclk + + power-domains: + maxItems: 1 + + renesas,max-channels: + $ref: /schemas/types.yaml#/definitions/uint32 + description: | + Maximum number of channels supported by the ADC. + RZ/T2H has two ADCs with 4 channels and one with 6 channels. + RZ/N2H has two ADCs with 4 channels and one with 15 channels. + + '#address-cells': + const: 1 + + '#size-cells': + const: 0 + + "#io-channel-cells": + const: 1 + +required: + - compatible + - reg + - interrupts + - clocks + - clock-names + - power-domains + - renesas,max-channels + +patternProperties: + "^channel@[0-9a-e]$": + $ref: adc.yaml + type: object + description: The external channels which are connected to the ADC. + + properties: + reg: + description: The channel number. + maximum: 14 + + required: + - reg + + additionalProperties: false + +allOf: + - if: + properties: + compatible: + contains: + const: renesas,r9a09g077-adc + then: + properties: + renesas,max-channels: + enum: [4, 6] + + patternProperties: + "^channel@[6-9a-e]$": false + "^channel@[0-5]$": + properties: + reg: + maximum: 5 + + - if: + properties: + compatible: + contains: + enum: + - renesas,r9a09g087-adc + then: + properties: + renesas,max-channels: + enum: [4, 15] + +additionalProperties: false + +examples: + - | + #include + #include + + adc@80008000 { + compatible =3D "renesas,r9a09g077-adc"; + reg =3D <0x80008000 0x400>; + interrupts =3D , + , + , + , + , + , + ; + interrupt-names =3D "adi", "gbadi", "gcadi", + "cmpai", "cmpbi", "wcmpm", "wcmpum"; + clocks =3D <&cpg CPG_CORE R9A09G077_CLK_PCLKL>, + <&cpg CPG_MOD 225>; + clock-names =3D "adclk", "pclk"; + power-domains =3D <&cpg>; + #address-cells =3D <1>; + #size-cells =3D <0>; + #io-channel-cells =3D <1>; + renesas,max-channels =3D <6>; + + channel@0 { + reg =3D <0x0>; + }; + channel@1 { + reg =3D <0x1>; + }; + channel@2 { + reg =3D <0x2>; + }; + channel@3 { + reg =3D <0x3>; + }; + }; diff --git a/MAINTAINERS b/MAINTAINERS index 9f4b48801879..07e0d37cf468 100644 --- a/MAINTAINERS +++ b/MAINTAINERS @@ -21822,6 +21822,13 @@ S: Supported F: Documentation/devicetree/bindings/timer/renesas,rz-mtu3.yaml F: drivers/counter/rz-mtu3-cnt.c =20 +RENESAS RZ/T2H / RZ/N2H A/D DRIVER +M: Cosmin Tanislav +L: linux-iio@vger.kernel.org +L: linux-renesas-soc@vger.kernel.org +S: Supported +F: Documentation/devicetree/bindings/iio/adc/renesas,r9a09g077-adc.yaml + RENESAS RTCA-3 RTC DRIVER M: Claudiu Beznea L: linux-rtc@vger.kernel.org --=20 2.51.0 From nobody Thu Oct 2 02:16:39 2025 Received: from relmlie5.idc.renesas.com (relmlor1.renesas.com [210.160.252.171]) by smtp.subspace.kernel.org (Postfix) with ESMTP id CC9891CAA92; Tue, 23 Sep 2025 16:06:18 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=none smtp.client-ip=210.160.252.171 ARC-Seal: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1758643581; cv=none; b=gGqnDgBIVh08DH9C4OcfSveVeA1VtkTXmvlFFQpn3hZONPV5urDKp2obWbFaj0ERbhzw6WiY9TisWSzppxs/o3vmvwZqsYLq+XUcs9pmEc3jPo85Iy2fZxk0ZqkBHeei+poJmORfw3SLKSIZ9Cs8qUX7oU5g+bryF5l8rd+zymE= ARC-Message-Signature: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1758643581; c=relaxed/simple; bh=GHLGTILQlTv8YD3GAt+6w8bpMvd0SKNS6A3xo7wTiaw=; h=From:To:Cc:Subject:Date:Message-ID:In-Reply-To:References: MIME-Version:Content-Type; b=Y/tNu22YbFVNQEXwszfiCNVPenGxJ2MBOURogBKm8roerdEuMZTyonwEboHY1/PvxzgWJfLj6FiHEUpsmzT3CwgiB9VdkTmCVipXjl/tKyM2NFmagytZ2TGOLkmZNaYoOFpCkOzSCXYrPQVHf1HFdhPs2BQ8BpHhZhVZhrh/YAQ= ARC-Authentication-Results: i=1; smtp.subspace.kernel.org; dmarc=pass (p=none dis=none) header.from=renesas.com; spf=pass smtp.mailfrom=renesas.com; arc=none smtp.client-ip=210.160.252.171 Authentication-Results: smtp.subspace.kernel.org; dmarc=pass (p=none dis=none) header.from=renesas.com Authentication-Results: smtp.subspace.kernel.org; spf=pass smtp.mailfrom=renesas.com X-CSE-ConnectionGUID: OW6lnDmzQoiAEfcfak5bHQ== X-CSE-MsgGUID: jvz/5zRNQDaQj0Pql0ZjgQ== Received: from unknown (HELO relmlir5.idc.renesas.com) ([10.200.68.151]) by relmlie5.idc.renesas.com with ESMTP; 24 Sep 2025 01:06:18 +0900 Received: from demon-pc.localdomain (unknown [10.226.93.64]) by relmlir5.idc.renesas.com (Postfix) with ESMTP id 358114008A2F; Wed, 24 Sep 2025 01:06:12 +0900 (JST) From: Cosmin Tanislav To: Cc: Cosmin Tanislav , Jonathan Cameron , David Lechner , =?UTF-8?q?Nuno=20S=C3=A1?= , Andy Shevchenko , Rob Herring , Krzysztof Kozlowski , Conor Dooley , Geert Uytterhoeven , Magnus Damm , Michael Turquette , Stephen Boyd , Lad Prabhakar , linux-iio@vger.kernel.org, linux-renesas-soc@vger.kernel.org, devicetree@vger.kernel.org, linux-kernel@vger.kernel.org, linux-clk@vger.kernel.org Subject: [PATCH 3/7] iio: adc: add RZ/T2H / RZ/N2H ADC driver Date: Tue, 23 Sep 2025 19:05:17 +0300 Message-ID: <20250923160524.1096720-4-cosmin-gabriel.tanislav.xa@renesas.com> X-Mailer: git-send-email 2.51.0 In-Reply-To: <20250923160524.1096720-1-cosmin-gabriel.tanislav.xa@renesas.com> References: <20250923160524.1096720-1-cosmin-gabriel.tanislav.xa@renesas.com> Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Content-Transfer-Encoding: quoted-printable Add support for the A/D 12-Bit successive approximation converters found in the Renesas RZ/T2H (R9A09G077) and RZ/N2H (R9A09G087) SoCs. RZ/T2H has two ADCs with 4 channels and one with 6. RZ/N2H has two ADCs with 4 channels and one with 15. Conversions can be performed in single or continuous mode. Result of the conversion is stored in a 16-bit data register corresponding to each channel. The conversions can be started by a software trigger, a synchronous trigger (from MTU or from ELC) or an asynchronous external trigger (from ADTRGn# pin). Only single mode with software trigger is supported for now. Signed-off-by: Cosmin Tanislav --- MAINTAINERS | 1 + drivers/iio/adc/Kconfig | 10 ++ drivers/iio/adc/Makefile | 1 + drivers/iio/adc/rzt2h_adc.c | 328 ++++++++++++++++++++++++++++++++++++ 4 files changed, 340 insertions(+) create mode 100644 drivers/iio/adc/rzt2h_adc.c diff --git a/MAINTAINERS b/MAINTAINERS index 07e0d37cf468..d550399dc390 100644 --- a/MAINTAINERS +++ b/MAINTAINERS @@ -21828,6 +21828,7 @@ L: linux-iio@vger.kernel.org L: linux-renesas-soc@vger.kernel.org S: Supported F: Documentation/devicetree/bindings/iio/adc/renesas,r9a09g077-adc.yaml +F: drivers/iio/adc/rzt2h_adc.c =20 RENESAS RTCA-3 RTC DRIVER M: Claudiu Beznea diff --git a/drivers/iio/adc/Kconfig b/drivers/iio/adc/Kconfig index 58a14e6833f6..cab5eeba48fe 100644 --- a/drivers/iio/adc/Kconfig +++ b/drivers/iio/adc/Kconfig @@ -1403,6 +1403,16 @@ config RZG2L_ADC To compile this driver as a module, choose M here: the module will be called rzg2l_adc. =20 +config RZT2H_ADC + tristate "Renesas RZ/T2H / RZ/N2H ADC driver" + select IIO_ADC_HELPER + help + Say yes here to build support for the ADC found in Renesas + RZ/T2H / RZ/N2H SoCs. + + To compile this driver as a module, choose M here: the + module will be called rzt2h_adc. + config SC27XX_ADC tristate "Spreadtrum SC27xx series PMICs ADC" depends on MFD_SC27XX_PMIC || COMPILE_TEST diff --git a/drivers/iio/adc/Makefile b/drivers/iio/adc/Makefile index d008f78dc010..ed647a734c51 100644 --- a/drivers/iio/adc/Makefile +++ b/drivers/iio/adc/Makefile @@ -123,6 +123,7 @@ obj-$(CONFIG_ROHM_BD79112) +=3D rohm-bd79112.o obj-$(CONFIG_ROHM_BD79124) +=3D rohm-bd79124.o obj-$(CONFIG_ROCKCHIP_SARADC) +=3D rockchip_saradc.o obj-$(CONFIG_RZG2L_ADC) +=3D rzg2l_adc.o +obj-$(CONFIG_RZT2H_ADC) +=3D rzt2h_adc.o obj-$(CONFIG_SC27XX_ADC) +=3D sc27xx_adc.o obj-$(CONFIG_SD_ADC_MODULATOR) +=3D sd_adc_modulator.o obj-$(CONFIG_SOPHGO_CV1800B_ADC) +=3D sophgo-cv1800b-adc.o diff --git a/drivers/iio/adc/rzt2h_adc.c b/drivers/iio/adc/rzt2h_adc.c new file mode 100644 index 000000000000..d855a79b3d96 --- /dev/null +++ b/drivers/iio/adc/rzt2h_adc.c @@ -0,0 +1,328 @@ +// SPDX-License-Identifier: GPL-2.0 + +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include + +#define RZT2H_NAME "rzt2h-adc" + +#define RZT2H_ADCSR_REG 0x00 +#define RZT2H_ADCSR_ADIE_MASK BIT(12) +#define RZT2H_ADCSR_ADCS_MASK GENMASK(14, 13) +#define RZT2H_ADCSR_ADCS_SINGLE 0b00 +#define RZT2H_ADCSR_ADST_MASK BIT(15) + +#define RZT2H_ADANSA0_REG 0x04 +#define RZT2H_ADANSA0_CH_MASK(x) BIT(x) + +#define RZT2H_ADDR_REG(x) (0x20 + 0x2 * (x)) + +#define RZT2H_ADCALCTL_REG 0x1f0 +#define RZT2H_ADCALCTL_CAL_MASK BIT(0) +#define RZT2H_ADCALCTL_CAL_RDY_MASK BIT(1) +#define RZT2H_ADCALCTL_CAL_ERR_MASK BIT(2) + +#define RZT2H_ADC_MAX_CHANNELS 16 +#define RZT2H_ADC_VREF_MV 1800 +#define RZT2H_ADC_RESOLUTION 12 + +struct rzt2h_adc { + void __iomem *base; + struct device *dev; + + struct completion completion; + /* lock to protect against multiple access to the device */ + struct mutex lock; + + const struct iio_chan_spec *channels; + unsigned int num_channels; + + u16 data[RZT2H_ADC_MAX_CHANNELS]; +}; + +static void rzt2h_adc_start_stop(struct rzt2h_adc *adc, bool start, + unsigned int conversion_type) +{ + u16 mask; + u16 reg; + + reg =3D readw(adc->base + RZT2H_ADCSR_REG); + + if (start) { + /* Set conversion type */ + reg &=3D ~RZT2H_ADCSR_ADCS_MASK; + reg |=3D FIELD_PREP(RZT2H_ADCSR_ADCS_MASK, conversion_type); + } + + /* Toggle end of conversion interrupt and start bit. */ + mask =3D RZT2H_ADCSR_ADIE_MASK | RZT2H_ADCSR_ADST_MASK; + if (start) + reg |=3D mask; + else + reg &=3D ~mask; + + writew(reg, adc->base + RZT2H_ADCSR_REG); +} + +static void rzt2h_adc_start(struct rzt2h_adc *adc, unsigned int conversion= _type) +{ + rzt2h_adc_start_stop(adc, true, conversion_type); +} + +static void rzt2h_adc_stop(struct rzt2h_adc *adc) +{ + rzt2h_adc_start_stop(adc, false, 0); +} + +static int rzt2h_adc_read_single(struct rzt2h_adc *adc, unsigned int ch, i= nt *val) +{ + int ret; + + ret =3D pm_runtime_resume_and_get(adc->dev); + if (ret) + return ret; + + guard(mutex)(&adc->lock); + + reinit_completion(&adc->completion); + + /* Enable a single channel */ + writew(RZT2H_ADANSA0_CH_MASK(ch), adc->base + RZT2H_ADANSA0_REG); + + rzt2h_adc_start(adc, RZT2H_ADCSR_ADCS_SINGLE); + + /* + * Datasheet Page 2770, Table 41.1: + * 0.32us per channel when sample-and-hold circuits are not in use. + */ + ret =3D wait_for_completion_timeout(&adc->completion, usecs_to_jiffies(1)= ); + if (!ret) { + ret =3D -ETIMEDOUT; + goto disable; + } + + *val =3D adc->data[ch]; + ret =3D IIO_VAL_INT; + +disable: + rzt2h_adc_stop(adc); + + pm_runtime_put_autosuspend(adc->dev); + + return ret; +} + +static void rzt2h_adc_set_cal(struct rzt2h_adc *adc, bool cal) +{ + u16 val; + + val =3D readw(adc->base + RZT2H_ADCALCTL_REG); + if (cal) + val |=3D RZT2H_ADCALCTL_CAL_MASK; + else + val &=3D ~RZT2H_ADCALCTL_CAL_MASK; + + writew(val, adc->base + RZT2H_ADCALCTL_REG); +} + +static int rzt2h_adc_calibrate(struct rzt2h_adc *adc) +{ + u16 val; + int ret; + + rzt2h_adc_set_cal(adc, true); + + ret =3D read_poll_timeout(readw, val, val & RZT2H_ADCALCTL_CAL_RDY_MASK, + 200, 1000, true, adc->base + RZT2H_ADCALCTL_REG); + if (ret) { + dev_err(adc->dev, "Calibration timed out: %d\n", ret); + return ret; + } + + if (val & RZT2H_ADCALCTL_CAL_ERR_MASK) { + dev_err(adc->dev, "Calibration failed\n"); + return -EINVAL; + } + + rzt2h_adc_set_cal(adc, false); + + return 0; +} + +static int rzt2h_adc_read_raw(struct iio_dev *indio_dev, + struct iio_chan_spec const *chan, + int *val, int *val2, long mask) +{ + struct rzt2h_adc *adc =3D iio_priv(indio_dev); + + switch (mask) { + case IIO_CHAN_INFO_RAW: + return rzt2h_adc_read_single(adc, chan->channel, val); + case IIO_CHAN_INFO_SCALE: + *val =3D RZT2H_ADC_VREF_MV; + *val2 =3D RZT2H_ADC_RESOLUTION; + return IIO_VAL_FRACTIONAL_LOG2; + default: + return -EINVAL; + } +} + +static const struct iio_info rzt2h_adc_iio_info =3D { + .read_raw =3D rzt2h_adc_read_raw, +}; + +static irqreturn_t rzt2h_adc_isr(int irq, void *private) +{ + struct rzt2h_adc *adc =3D private; + unsigned long enabled_channels; + unsigned int ch; + + enabled_channels =3D readw(adc->base + RZT2H_ADANSA0_REG); + if (!enabled_channels) + return IRQ_NONE; + + for_each_set_bit(ch, &enabled_channels, adc->num_channels) + adc->data[ch] =3D readw(adc->base + RZT2H_ADDR_REG(ch)); + + complete(&adc->completion); + + return IRQ_HANDLED; +} + +static const struct iio_chan_spec rzt2h_adc_chan_template =3D { + .indexed =3D 1, + .info_mask_separate =3D BIT(IIO_CHAN_INFO_RAW) | + BIT(IIO_CHAN_INFO_SCALE), + .type =3D IIO_VOLTAGE, +}; + +static int rzt2h_adc_parse_properties(struct rzt2h_adc *adc) +{ + struct iio_chan_spec *chan_array; + u32 max_channels; + int ret; + + ret =3D device_property_read_u32(adc->dev, "renesas,max-channels", + &max_channels); + if (ret) + return dev_err_probe(adc->dev, ret, + "Failed to find max-channels property"); + + ret =3D devm_iio_adc_device_alloc_chaninfo_se(adc->dev, + &rzt2h_adc_chan_template, + max_channels - 1, + &chan_array); + if (ret < 0) + return dev_err_probe(adc->dev, ret, "Failed to read channel info"); + + adc->num_channels =3D ret; + adc->channels =3D chan_array; + + return 0; +} + +static int rzt2h_adc_probe(struct platform_device *pdev) +{ + struct device *dev =3D &pdev->dev; + struct iio_dev *indio_dev; + struct rzt2h_adc *adc; + int ret; + int irq; + + indio_dev =3D devm_iio_device_alloc(dev, sizeof(*adc)); + if (!indio_dev) + return -ENOMEM; + + adc =3D iio_priv(indio_dev); + adc->dev =3D dev; + init_completion(&adc->completion); + + ret =3D devm_mutex_init(dev, &adc->lock); + if (ret) + return ret; + + platform_set_drvdata(pdev, indio_dev); + + ret =3D rzt2h_adc_parse_properties(adc); + if (ret) + return ret; + + adc->base =3D devm_platform_ioremap_resource(pdev, 0); + if (IS_ERR(adc->base)) + return PTR_ERR(adc->base); + + pm_runtime_set_autosuspend_delay(dev, 300); + pm_runtime_use_autosuspend(dev); + ret =3D devm_pm_runtime_enable(dev); + if (ret) + return ret; + + irq =3D platform_get_irq_byname(pdev, "adi"); + if (irq < 0) + return irq; + + ret =3D devm_request_irq(dev, irq, rzt2h_adc_isr, 0, dev_name(dev), adc); + if (ret) + return ret; + + indio_dev->name =3D RZT2H_NAME; + indio_dev->info =3D &rzt2h_adc_iio_info; + indio_dev->modes =3D INDIO_DIRECT_MODE; + indio_dev->channels =3D adc->channels; + indio_dev->num_channels =3D adc->num_channels; + + return devm_iio_device_register(dev, indio_dev); +} + +static const struct of_device_id rzt2h_adc_match[] =3D { + { .compatible =3D "renesas,r9a09g077-adc" }, + { .compatible =3D "renesas,r9a09g087-adc" }, + { } +}; +MODULE_DEVICE_TABLE(of, rzt2h_adc_match); + +static int rzt2h_adc_pm_runtime_resume(struct device *dev) +{ + struct iio_dev *indio_dev =3D dev_get_drvdata(dev); + struct rzt2h_adc *adc =3D iio_priv(indio_dev); + + /* + * Datasheet Page 2810, Section 41.5.6: + * After release from the module-stop state, wait for at least + * 0.5 =C2=B5s before starting A/D conversion. + */ + fsleep(1); + + return rzt2h_adc_calibrate(adc); +} + +static const struct dev_pm_ops rzt2h_adc_pm_ops =3D { + RUNTIME_PM_OPS(NULL, rzt2h_adc_pm_runtime_resume, NULL) +}; + +static struct platform_driver rzt2h_adc_driver =3D { + .probe =3D rzt2h_adc_probe, + .driver =3D { + .name =3D RZT2H_NAME, + .of_match_table =3D rzt2h_adc_match, + .pm =3D pm_ptr(&rzt2h_adc_pm_ops), + }, +}; + +module_platform_driver(rzt2h_adc_driver); + +MODULE_AUTHOR("Cosmin Tanislav "); +MODULE_DESCRIPTION("Renesas RZ/T2H / RZ/N2H ADC driver"); +MODULE_LICENSE("GPL"); +MODULE_IMPORT_NS("IIO_DRIVER"); --=20 2.51.0 From nobody Thu Oct 2 02:16:39 2025 Received: from relmlie5.idc.renesas.com (relmlor1.renesas.com [210.160.252.171]) by smtp.subspace.kernel.org (Postfix) with ESMTP id 7A3EB2E763A; Tue, 23 Sep 2025 16:06:25 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=none smtp.client-ip=210.160.252.171 ARC-Seal: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1758643587; cv=none; b=CNMxf0WkWut/mC5YSBX50Y3q3hrT0w88qIhKbK7aH32DVJl/WOh3EftAeuH5tKD4ePTCEmBMB//BeQgLBrgo37hUsrfYiFyIg7o6WPT3nFPSS8mgQG65KBYbPNPqtsyHf5CvVhKlLwouBfBE9DIMz2ihcA/T0biv6vTS42G9D/I= ARC-Message-Signature: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1758643587; c=relaxed/simple; bh=6gOaHYuIwEr92Shv5PBAYHfT69KDlnHVSNib1pOfPRI=; h=From:To:Cc:Subject:Date:Message-ID:In-Reply-To:References: MIME-Version; b=B2+woGW4Q+jqhtw6vPvY4p4xIB1zQuR9pRcJcm9t0XUg/yDfFlICH0MgJWwl1DzZ2zx1OqiSKtVlSwORkcME+MJC/M8VaMxdCf1REQSsbPY5CTWpo5p1kaByQAr6C11OsFdDlIkzcrKHq2LbI5DGJ6gEVHqD7vi9s2QNhaA7eHc= ARC-Authentication-Results: i=1; smtp.subspace.kernel.org; dmarc=pass (p=none dis=none) header.from=renesas.com; spf=pass smtp.mailfrom=renesas.com; arc=none smtp.client-ip=210.160.252.171 Authentication-Results: smtp.subspace.kernel.org; dmarc=pass (p=none dis=none) header.from=renesas.com Authentication-Results: smtp.subspace.kernel.org; spf=pass smtp.mailfrom=renesas.com X-CSE-ConnectionGUID: s7zQlce8Sl+AgqQJ+CreIg== X-CSE-MsgGUID: 4j2xTM65Q6ufwNEOTvWa/g== Received: from unknown (HELO relmlir5.idc.renesas.com) ([10.200.68.151]) by relmlie5.idc.renesas.com with ESMTP; 24 Sep 2025 01:06:25 +0900 Received: from demon-pc.localdomain (unknown [10.226.93.64]) by relmlir5.idc.renesas.com (Postfix) with ESMTP id D55144008A2F; Wed, 24 Sep 2025 01:06:19 +0900 (JST) From: Cosmin Tanislav To: Cc: Cosmin Tanislav , Jonathan Cameron , David Lechner , =?UTF-8?q?Nuno=20S=C3=A1?= , Andy Shevchenko , Rob Herring , Krzysztof Kozlowski , Conor Dooley , Geert Uytterhoeven , Magnus Damm , Michael Turquette , Stephen Boyd , Lad Prabhakar , linux-iio@vger.kernel.org, linux-renesas-soc@vger.kernel.org, devicetree@vger.kernel.org, linux-kernel@vger.kernel.org, linux-clk@vger.kernel.org Subject: [PATCH 4/7] arm64: dts: renesas: r9a09g077: Add ADCs support Date: Tue, 23 Sep 2025 19:05:18 +0300 Message-ID: <20250923160524.1096720-5-cosmin-gabriel.tanislav.xa@renesas.com> X-Mailer: git-send-email 2.51.0 In-Reply-To: <20250923160524.1096720-1-cosmin-gabriel.tanislav.xa@renesas.com> References: <20250923160524.1096720-1-cosmin-gabriel.tanislav.xa@renesas.com> Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Content-Type: text/plain; charset="utf-8" Renesas RZ/T2H (R9A09G077) includes three 12-Bit successive approximation A/D converters, two 4-channel ADCs, and one 6-channel ADC. Add support for all of them. Signed-off-by: Cosmin Tanislav --- arch/arm64/boot/dts/renesas/r9a09g077.dtsi | 69 ++++++++++++++++++++++ 1 file changed, 69 insertions(+) diff --git a/arch/arm64/boot/dts/renesas/r9a09g077.dtsi b/arch/arm64/boot/d= ts/renesas/r9a09g077.dtsi index 37a696d8ec6d..bfb317d7066c 100644 --- a/arch/arm64/boot/dts/renesas/r9a09g077.dtsi +++ b/arch/arm64/boot/dts/renesas/r9a09g077.dtsi @@ -666,6 +666,75 @@ gic: interrupt-controller@83000000 { interrupts =3D ; }; =20 + adc0: adc@90014000 { + compatible =3D "renesas,r9a09g077-adc"; + reg =3D <0 0x90014000 0 0x400>; + interrupts =3D , + , + , + , + , + , + ; + interrupt-names =3D "adi", "gbadi", "gcadi", + "cmpai", "cmpbi", "wcmpm", "wcmpum"; + clocks =3D <&cpg CPG_CORE R9A09G077_CLK_PCLKL>, + <&cpg CPG_MOD 206>; + clock-names =3D "adclk", "pclk"; + power-domains =3D <&cpg>; + #address-cells =3D <1>; + #size-cells =3D <0>; + #io-channel-cells =3D <1>; + renesas,max-channels =3D <4>; + status =3D "disabled"; + }; + + adc1: adc@90014400 { + compatible =3D "renesas,r9a09g077-adc"; + reg =3D <0 0x90014400 0 0x400>; + interrupts =3D , + , + , + , + , + , + ; + interrupt-names =3D "adi", "gbadi", "gcadi", + "cmpai", "cmpbi", "wcmpm", "wcmpum"; + clocks =3D <&cpg CPG_CORE R9A09G077_CLK_PCLKL>, + <&cpg CPG_MOD 207>; + clock-names =3D "adclk", "pclk"; + power-domains =3D <&cpg>; + #address-cells =3D <1>; + #size-cells =3D <0>; + #io-channel-cells =3D <1>; + renesas,max-channels =3D <4>; + status =3D "disabled"; + }; + + adc2: adc@80008000 { + compatible =3D "renesas,r9a09g077-adc"; + reg =3D <0 0x80008000 0 0x400>; + interrupts =3D , + , + , + , + , + , + ; + interrupt-names =3D "adi", "gbadi", "gcadi", + "cmpai", "cmpbi", "wcmpm", "wcmpum"; + clocks =3D <&cpg CPG_CORE R9A09G077_CLK_PCLKL>, + <&cpg CPG_MOD 225>; + clock-names =3D "adclk", "pclk"; + power-domains =3D <&cpg>; + #address-cells =3D <1>; + #size-cells =3D <0>; + #io-channel-cells =3D <1>; + renesas,max-channels =3D <6>; + status =3D "disabled"; + }; + ohci: usb@92040000 { compatible =3D "generic-ohci"; reg =3D <0 0x92040000 0 0x100>; --=20 2.51.0 From nobody Thu Oct 2 02:16:39 2025 Received: from relmlie6.idc.renesas.com (relmlor2.renesas.com [210.160.252.172]) by smtp.subspace.kernel.org (Postfix) with ESMTP id 88F73255F31; Tue, 23 Sep 2025 16:06:32 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=none smtp.client-ip=210.160.252.172 ARC-Seal: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1758643594; cv=none; b=hyAZNI8CNbXC69u8bfO7mYWZPvdGNFSTguvjpw7IeK3uix6f17CFFhtA1Jhr7XBW7c83bwIN72FZvg2OpeK9S0W6AhrVbhqBcAK1/Tx6iAEVKWLp6QgAeKyhuG8LqAXHYSEqtUYQZumrbCpGan/3W+NGTcCn2izwraOk+Xd45zE= ARC-Message-Signature: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1758643594; c=relaxed/simple; bh=x1yOWnf7BlpJEG8EWYAT2jSSVwYz8D6FZmHjS8CE+Gg=; h=From:To:Cc:Subject:Date:Message-ID:In-Reply-To:References: MIME-Version; b=jCNpQd5kvMiSiXaasaolmSbtgdEZz47sy03UfC+4cbnDggQqFcnPPVL8mlmkbn3mq5hIkzeE2aTNc5zRrDMHeI/jqbIqPQ2YXe/Kn4qZaZosuqTcWgznGI0+ZBW7r0+/AIQWy04RXR7nneuUVBuegKcgzXYbLdjDYGL10/mK0k4= ARC-Authentication-Results: i=1; smtp.subspace.kernel.org; dmarc=pass (p=none dis=none) header.from=renesas.com; spf=pass smtp.mailfrom=renesas.com; arc=none smtp.client-ip=210.160.252.172 Authentication-Results: smtp.subspace.kernel.org; dmarc=pass (p=none dis=none) header.from=renesas.com Authentication-Results: smtp.subspace.kernel.org; spf=pass smtp.mailfrom=renesas.com X-CSE-ConnectionGUID: g+WV/4OcS0mIeK8LcGHjUg== X-CSE-MsgGUID: 9N/xtJKaSUy+b3nLRtg+bQ== Received: from unknown (HELO relmlir5.idc.renesas.com) ([10.200.68.151]) by relmlie6.idc.renesas.com with ESMTP; 24 Sep 2025 01:06:31 +0900 Received: from demon-pc.localdomain (unknown [10.226.93.64]) by relmlir5.idc.renesas.com (Postfix) with ESMTP id 745BA400C752; Wed, 24 Sep 2025 01:06:26 +0900 (JST) From: Cosmin Tanislav To: Cc: Cosmin Tanislav , Jonathan Cameron , David Lechner , =?UTF-8?q?Nuno=20S=C3=A1?= , Andy Shevchenko , Rob Herring , Krzysztof Kozlowski , Conor Dooley , Geert Uytterhoeven , Magnus Damm , Michael Turquette , Stephen Boyd , Lad Prabhakar , linux-iio@vger.kernel.org, linux-renesas-soc@vger.kernel.org, devicetree@vger.kernel.org, linux-kernel@vger.kernel.org, linux-clk@vger.kernel.org Subject: [PATCH 5/7] arm64: dts: renesas: r9a09g087: Add ADCs support Date: Tue, 23 Sep 2025 19:05:19 +0300 Message-ID: <20250923160524.1096720-6-cosmin-gabriel.tanislav.xa@renesas.com> X-Mailer: git-send-email 2.51.0 In-Reply-To: <20250923160524.1096720-1-cosmin-gabriel.tanislav.xa@renesas.com> References: <20250923160524.1096720-1-cosmin-gabriel.tanislav.xa@renesas.com> Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Content-Type: text/plain; charset="utf-8" Renesas RZ/T2H (R9A09G087) includes three 12-Bit successive approximation A/D converters, two 4-channel ADCs, and one 15-channel ADC. Add support for all of them. Signed-off-by: Cosmin Tanislav --- arch/arm64/boot/dts/renesas/r9a09g087.dtsi | 69 ++++++++++++++++++++++ 1 file changed, 69 insertions(+) diff --git a/arch/arm64/boot/dts/renesas/r9a09g087.dtsi b/arch/arm64/boot/d= ts/renesas/r9a09g087.dtsi index 88669868f0ee..faca2fd47257 100644 --- a/arch/arm64/boot/dts/renesas/r9a09g087.dtsi +++ b/arch/arm64/boot/dts/renesas/r9a09g087.dtsi @@ -666,6 +666,75 @@ gic: interrupt-controller@83000000 { interrupts =3D ; }; =20 + adc0: adc@90014000 { + compatible =3D "renesas,r9a09g087-adc"; + reg =3D <0 0x90014000 0 0x400>; + interrupts =3D , + , + , + , + , + , + ; + interrupt-names =3D "adi", "gbadi", "gcadi", + "cmpai", "cmpbi", "wcmpm", "wcmpum"; + clocks =3D <&cpg CPG_CORE R9A09G087_CLK_PCLKL>, + <&cpg CPG_MOD 206>; + clock-names =3D "adclk", "pclk"; + power-domains =3D <&cpg>; + #address-cells =3D <1>; + #size-cells =3D <0>; + #io-channel-cells =3D <1>; + renesas,max-channels =3D <4>; + status =3D "disabled"; + }; + + adc1: adc@90014400 { + compatible =3D "renesas,r9a09g087-adc"; + reg =3D <0 0x90014400 0 0x400>; + interrupts =3D , + , + , + , + , + , + ; + interrupt-names =3D "adi", "gbadi", "gcadi", + "cmpai", "cmpbi", "wcmpm", "wcmpum"; + clocks =3D <&cpg CPG_CORE R9A09G087_CLK_PCLKL>, + <&cpg CPG_MOD 207>; + clock-names =3D "adclk", "pclk"; + power-domains =3D <&cpg>; + #address-cells =3D <1>; + #size-cells =3D <0>; + #io-channel-cells =3D <1>; + renesas,max-channels =3D <4>; + status =3D "disabled"; + }; + + adc2: adc@80008000 { + compatible =3D "renesas,r9a09g087-adc"; + reg =3D <0 0x80008000 0 0x400>; + interrupts =3D , + , + , + , + , + , + ; + interrupt-names =3D "adi", "gbadi", "gcadi", + "cmpai", "cmpbi", "wcmpm", "wcmpum"; + clocks =3D <&cpg CPG_CORE R9A09G087_CLK_PCLKL>, + <&cpg CPG_MOD 225>; + clock-names =3D "adclk", "pclk"; + power-domains =3D <&cpg>; + #address-cells =3D <1>; + #size-cells =3D <0>; + #io-channel-cells =3D <1>; + renesas,max-channels =3D <15>; + status =3D "disabled"; + }; + ohci: usb@92040000 { compatible =3D "generic-ohci"; reg =3D <0 0x92040000 0 0x100>; --=20 2.51.0 From nobody Thu Oct 2 02:16:39 2025 Received: from relmlie6.idc.renesas.com (relmlor2.renesas.com [210.160.252.172]) by smtp.subspace.kernel.org (Postfix) with ESMTP id A8A6F255F31; Tue, 23 Sep 2025 16:06:38 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=none smtp.client-ip=210.160.252.172 ARC-Seal: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1758643600; cv=none; b=GJqZsRb8TyZUijE3J3jhpz5KTPeF6PnvPOXsa7MVtgZGwd8Q7CGcuzSzNa3+LH73FRu6QTIKH+DOpCR9JQp/3t22FrLSpYQa2nL2pdQEIBVCkHJ3Q9VgHul8EB4Irkk+1lJ6DZZsQFOtrkEBaJ/Z+2Ft+H9MJqV/20HKjhe+cFM= ARC-Message-Signature: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1758643600; c=relaxed/simple; bh=XQ3XKuMVVnlhB58MduVr+0rxBWpHh/TwGzeY/ypNSww=; h=From:To:Cc:Subject:Date:Message-ID:In-Reply-To:References: MIME-Version; b=HFKwc46TUInG3aqesWbWPfrdoVGMoPK9TBLvMF1nuqxu0U1ObM1lL1AflAo7YPIkbr8+w9VV12sat+X4L3/Nq3KnlXWKOkO7N7cEwpQRki5BnlX1MKRDTF5t2HbtgLCOTAMx0Vq9DVb39Z7++FFFpW8oruckU8kToarMznADafk= ARC-Authentication-Results: i=1; smtp.subspace.kernel.org; dmarc=pass (p=none dis=none) header.from=renesas.com; spf=pass smtp.mailfrom=renesas.com; arc=none smtp.client-ip=210.160.252.172 Authentication-Results: smtp.subspace.kernel.org; dmarc=pass (p=none dis=none) header.from=renesas.com Authentication-Results: smtp.subspace.kernel.org; spf=pass smtp.mailfrom=renesas.com X-CSE-ConnectionGUID: N4UvnteMQ+S8MeSLsrrAvA== X-CSE-MsgGUID: UJ/s2eGKTxSiRuTyRZA/9g== Received: from unknown (HELO relmlir5.idc.renesas.com) ([10.200.68.151]) by relmlie6.idc.renesas.com with ESMTP; 24 Sep 2025 01:06:38 +0900 Received: from demon-pc.localdomain (unknown [10.226.93.64]) by relmlir5.idc.renesas.com (Postfix) with ESMTP id 049D94008A2F; Wed, 24 Sep 2025 01:06:32 +0900 (JST) From: Cosmin Tanislav To: Cc: Cosmin Tanislav , Jonathan Cameron , David Lechner , =?UTF-8?q?Nuno=20S=C3=A1?= , Andy Shevchenko , Rob Herring , Krzysztof Kozlowski , Conor Dooley , Geert Uytterhoeven , Magnus Damm , Michael Turquette , Stephen Boyd , Lad Prabhakar , linux-iio@vger.kernel.org, linux-renesas-soc@vger.kernel.org, devicetree@vger.kernel.org, linux-kernel@vger.kernel.org, linux-clk@vger.kernel.org Subject: [PATCH 6/7] arm64: dts: renesas: rzt2h/rzn2h-evk: enable ADCs Date: Tue, 23 Sep 2025 19:05:20 +0300 Message-ID: <20250923160524.1096720-7-cosmin-gabriel.tanislav.xa@renesas.com> X-Mailer: git-send-email 2.51.0 In-Reply-To: <20250923160524.1096720-1-cosmin-gabriel.tanislav.xa@renesas.com> References: <20250923160524.1096720-1-cosmin-gabriel.tanislav.xa@renesas.com> Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Content-Type: text/plain; charset="utf-8" The ADCs on RZ/T2H and RZ/N2H are exposed on the evaluation kit boards. Enable them. Signed-off-by: Cosmin Tanislav --- .../dts/renesas/r9a09g077m44-rzt2h-evk.dts | 28 +++++++ .../dts/renesas/r9a09g087m44-rzn2h-evk.dts | 64 +++++++++++++++ .../dts/renesas/rzt2h-n2h-evk-common.dtsi | 79 +++++++++++++++++++ 3 files changed, 171 insertions(+) diff --git a/arch/arm64/boot/dts/renesas/r9a09g077m44-rzt2h-evk.dts b/arch/= arm64/boot/dts/renesas/r9a09g077m44-rzt2h-evk.dts index 9170c563208a..e94b84393bd9 100644 --- a/arch/arm64/boot/dts/renesas/r9a09g077m44-rzt2h-evk.dts +++ b/arch/arm64/boot/dts/renesas/r9a09g077m44-rzt2h-evk.dts @@ -252,3 +252,31 @@ usb_pins: usb-pins { ; /* OVRCUR */ }; }; + +&adc2 { + status =3D "okay"; + + channel@0 { + reg =3D <0x0>; + }; + + channel@1 { + reg =3D <0x1>; + }; + + channel@2 { + reg =3D <0x2>; + }; + + channel@3 { + reg =3D <0x3>; + }; + + channel@4 { + reg =3D <0x4>; + }; + + channel@5 { + reg =3D <0x5>; + }; +}; diff --git a/arch/arm64/boot/dts/renesas/r9a09g087m44-rzn2h-evk.dts b/arch/= arm64/boot/dts/renesas/r9a09g087m44-rzn2h-evk.dts index 279f2510044b..d27da157c6d6 100644 --- a/arch/arm64/boot/dts/renesas/r9a09g087m44-rzn2h-evk.dts +++ b/arch/arm64/boot/dts/renesas/r9a09g087m44-rzn2h-evk.dts @@ -305,3 +305,67 @@ usb_pins: usb-pins { ; /* OVRCUR */ }; }; + +&adc2 { + status =3D "okay"; + + channel@0 { + reg =3D <0x0>; + }; + + channel@1 { + reg =3D <0x1>; + }; + + channel@2 { + reg =3D <0x2>; + }; + + channel@3 { + reg =3D <0x3>; + }; + + channel@4 { + reg =3D <0x4>; + }; + + channel@5 { + reg =3D <0x5>; + }; + + channel@6 { + reg =3D <0x6>; + }; + + channel@7 { + reg =3D <0x7>; + }; + + channel@8 { + reg =3D <0x8>; + }; + + channel@9 { + reg =3D <0x9>; + }; + + channel@a { + reg =3D <0xa>; + }; + + channel@b { + reg =3D <0xb>; + }; + + channel@c { + reg =3D <0xc>; + }; + + channel@d { + reg =3D <0xd>; + }; + + channel@e { + reg =3D <0xe>; + }; +}; diff --git a/arch/arm64/boot/dts/renesas/rzt2h-n2h-evk-common.dtsi b/arch/a= rm64/boot/dts/renesas/rzt2h-n2h-evk-common.dtsi index 9ca26725a3e9..a7123a9ec684 100644 --- a/arch/arm64/boot/dts/renesas/rzt2h-n2h-evk-common.dtsi +++ b/arch/arm64/boot/dts/renesas/rzt2h-n2h-evk-common.dtsi @@ -338,3 +338,82 @@ &wdt2 { status =3D "okay"; timeout-sec =3D <60>; }; + +/* + * ADC0 AN000 can be connected to a potentiometer on the board or + * exposed on ADC header. + * + * T2H: + * SW17[1] =3D ON, SW17[2] =3D OFF - Potentiometer + * SW17[1] =3D OFF, SW17[2] =3D ON - CN41 header + * N2H: + * DSW6[1] =3D OFF, DSW6[2] =3D ON - Potentiometer + * DSW6[1] =3D ON, DSW6[2] =3D OFF - CN3 header + */ +&adc0 { + status =3D "okay"; + + channel@0 { + reg =3D <0x0>; + }; + + channel@1 { + reg =3D <0x1>; + }; + + channel@2 { + reg =3D <0x2>; + }; + + channel@3 { + reg =3D <0x3>; + }; +}; + +/* + * ADC1 AN100 can be exposed on ADC header or on mikroBUS connector. + * + * T2H: + * SW18[1] =3D ON, SW18[2] =3D OFF - CN42 header + * SW18[1] =3D OFF, SW18[2] =3D ON - mikroBUS + * N2H: + * DSW6[3] =3D ON, DSW6[4] =3D OFF - CN4 header + * DSW6[3] =3D OFF, DSW6[4] =3D ON - mikroBUS + * + * ADC1 AN101 can be exposed on ADC header or on Grove2 connector. + * + * T2H: + * SW18[3] =3D ON, SW18[4] =3D OFF - CN42 header + * SW18[3] =3D OFF, SW18[4] =3D ON - Grove2 + * N2H: + * DSW6[5] =3D ON, DSW6[6] =3D OFF - CN4 header + * DSW6[5] =3D OFF, DSW6[6] =3D ON - Grove2 + * + * ADC1 AN102 can be exposed on ADC header or on Grove2 connector. + * + * T2H: + * SW18[5] =3D ON, SW18[6] =3D OFF - CN42 header + * SW18[5] =3D OFF, SW18[6] =3D ON - Grove2 + * N2H: + * DSW6[7] =3D ON, DSW6[8] =3D OFF - CN4 header + * DSW6[7] =3D OFF, DSW6[8] =3D ON - Grove2 + */ +&adc1 { + status =3D "okay"; + + channel@0 { + reg =3D <0x0>; + }; + + channel@1 { + reg =3D <0x1>; + }; + + channel@2 { + reg =3D <0x2>; + }; + + channel@3 { + reg =3D <0x3>; + }; +}; --=20 2.51.0 From nobody Thu Oct 2 02:16:39 2025 Received: from relmlie5.idc.renesas.com (relmlor1.renesas.com [210.160.252.171]) by smtp.subspace.kernel.org (Postfix) with ESMTP id 440D42E3B0E; Tue, 23 Sep 2025 16:06:45 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=none smtp.client-ip=210.160.252.171 ARC-Seal: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1758643608; cv=none; b=RfQbXgqD3Ae3IOhqayXYoiwEfhtWgqQZzuJnl/9+LFHiQc6WwBDK7qWyWJfyu7RV5DJMxHW32L0M8cNskvlCFfG/cucLwH/dd+uyuoJhXJt18SCs0ZnZ3bt3d5PNQkt1onjF7gkVhPgfZV+bMLtcCJWux8mCNkQkb0h39e1Hk3o= ARC-Message-Signature: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1758643608; c=relaxed/simple; bh=tnTqUW1CCfg20bZn8bGpLx7RaTcWjSs1bsmxkTRlM+Q=; h=From:To:Cc:Subject:Date:Message-ID:In-Reply-To:References: MIME-Version; b=EAPbJsC2FkA4l6KsiO7ccCb8HDeDh2MLz7LtP654nRMp0631xYxYLn/GqsWeZ7lh6ob3kkDvhFXkie2yY1TyFd5GQ52tpeme0qBM0CwSuDUxu0huPqWE9sbRGiEuywdEJIMaclbEEsJOIzf9QZQv/6QLYJIbU336GMWnt5rh2A0= ARC-Authentication-Results: i=1; smtp.subspace.kernel.org; dmarc=pass (p=none dis=none) header.from=renesas.com; spf=pass smtp.mailfrom=renesas.com; arc=none smtp.client-ip=210.160.252.171 Authentication-Results: smtp.subspace.kernel.org; dmarc=pass (p=none dis=none) header.from=renesas.com Authentication-Results: smtp.subspace.kernel.org; spf=pass smtp.mailfrom=renesas.com X-CSE-ConnectionGUID: vx0ukpZOTGWznyPbR2tKtw== X-CSE-MsgGUID: wAMhTSygQ4OlpfDSYicdzQ== Received: from unknown (HELO relmlir5.idc.renesas.com) ([10.200.68.151]) by relmlie5.idc.renesas.com with ESMTP; 24 Sep 2025 01:06:44 +0900 Received: from demon-pc.localdomain (unknown [10.226.93.64]) by relmlir5.idc.renesas.com (Postfix) with ESMTP id 6D1ED4008A2F; Wed, 24 Sep 2025 01:06:39 +0900 (JST) From: Cosmin Tanislav To: Cc: Cosmin Tanislav , Jonathan Cameron , David Lechner , =?UTF-8?q?Nuno=20S=C3=A1?= , Andy Shevchenko , Rob Herring , Krzysztof Kozlowski , Conor Dooley , Geert Uytterhoeven , Magnus Damm , Michael Turquette , Stephen Boyd , Lad Prabhakar , linux-iio@vger.kernel.org, linux-renesas-soc@vger.kernel.org, devicetree@vger.kernel.org, linux-kernel@vger.kernel.org, linux-clk@vger.kernel.org Subject: [PATCH 7/7] arm64: defconfig: enable RZ/T2H / RZ/N2H ADC driver Date: Tue, 23 Sep 2025 19:05:21 +0300 Message-ID: <20250923160524.1096720-8-cosmin-gabriel.tanislav.xa@renesas.com> X-Mailer: git-send-email 2.51.0 In-Reply-To: <20250923160524.1096720-1-cosmin-gabriel.tanislav.xa@renesas.com> References: <20250923160524.1096720-1-cosmin-gabriel.tanislav.xa@renesas.com> Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Content-Type: text/plain; charset="utf-8" Renesas RZ/T2H (R9A09G077) and RZ/N2H (R9A09G087) SoCs include three 12-Bit successive approximation A/D converters. RZ/T2H has two ADCs with 4 channels and one with 6. RZ/N2H has two ADCs with 4 channels and one with 15. Enable the driver for them. Signed-off-by: Cosmin Tanislav --- arch/arm64/configs/defconfig | 1 + 1 file changed, 1 insertion(+) diff --git a/arch/arm64/configs/defconfig b/arch/arm64/configs/defconfig index 8fd1bf869942..3a1326652d47 100644 --- a/arch/arm64/configs/defconfig +++ b/arch/arm64/configs/defconfig @@ -1581,6 +1581,7 @@ CONFIG_QCOM_SPMI_VADC=3Dm CONFIG_QCOM_SPMI_ADC5=3Dm CONFIG_ROCKCHIP_SARADC=3Dm CONFIG_RZG2L_ADC=3Dm +CONFIG_RZT2H_ADC=3Dm CONFIG_SOPHGO_CV1800B_ADC=3Dm CONFIG_TI_ADS1015=3Dm CONFIG_TI_AM335X_ADC=3Dm --=20 2.51.0