From nobody Thu Oct 2 03:34:05 2025 Received: from mail-wm1-f47.google.com (mail-wm1-f47.google.com [209.85.128.47]) (using TLSv1.2 with cipher ECDHE-RSA-AES128-GCM-SHA256 (128/128 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id CA11C23A984 for ; Tue, 23 Sep 2025 14:45:32 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=none smtp.client-ip=209.85.128.47 ARC-Seal: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1758638735; cv=none; b=ms1cJqfY/g7aawbkzBF9Exa6Z2+M/ZfLtn2FLhZQDTruFBqNSKLZRASo2fQY4mmwTjGqHzAlCeM6p9QAcp0LEsS8AaU6RY9bJHpqZGZLnHNDo11MMCcxRFCJmJAM5BdZgndkcX5VF0JqxjJ43+Vw5EzpSRZQe4NMX1j/jACsNoI= ARC-Message-Signature: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1758638735; c=relaxed/simple; bh=OjsLrF0BpyixmbNmZqRDeZM8/Q9vuOqtCut1I2w6tGk=; h=From:To:Cc:Subject:Date:Message-ID:In-Reply-To:References: MIME-Version; b=ajwSVTA6E71nOl7EMEdvURFd46MJxMXznVo4CvcCaE9FLhBv8hFmfiQa0HofkHyDpZv3k/1c9WrS9FF+wiNO1Fzi1n+oCb3sKzkA3XeO/Zszg1S3yVQY7jYr7McfnvJ/z7v5gUTNebc8NIateWJsKDO77oHgY2/38w7SXFfXLdw= ARC-Authentication-Results: i=1; smtp.subspace.kernel.org; dmarc=pass (p=none dis=none) header.from=gmail.com; spf=pass smtp.mailfrom=gmail.com; dkim=pass (2048-bit key) header.d=gmail.com header.i=@gmail.com header.b=ij+NF/sf; arc=none smtp.client-ip=209.85.128.47 Authentication-Results: smtp.subspace.kernel.org; dmarc=pass (p=none dis=none) header.from=gmail.com Authentication-Results: smtp.subspace.kernel.org; spf=pass smtp.mailfrom=gmail.com Authentication-Results: smtp.subspace.kernel.org; dkim=pass (2048-bit key) header.d=gmail.com header.i=@gmail.com header.b="ij+NF/sf" Received: by mail-wm1-f47.google.com with SMTP id 5b1f17b1804b1-46e1e318f58so7930415e9.2 for ; Tue, 23 Sep 2025 07:45:32 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=gmail.com; s=20230601; t=1758638731; x=1759243531; darn=vger.kernel.org; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:from:to:cc:subject:date :message-id:reply-to; bh=lPc1khGgtKoM3FlGkfqU+I3xy6hkWBPtPzJJrRqEf2k=; b=ij+NF/sfiWk+1ENFruXrQ4KJ+jnBN03VRNgTXIMFy/ZU631B99ithKyI4JJxy4SZIS XpVYQzQwzle/VEceSbLb8br9OdVh+7boYfCgapNaLysQLcUJkk29g3S6cZo1ZdhAoYoT yaSnG4BxqLNHoIKgjaP05sYrfQRE3Y9/oWJCjcwriZSzldtZe7k1PIUjQxIhG+RK/opW QrVBBAih3nSgVUCFalIvsTQebfOfao6h0EwBM0tyPjLue9k6TLuf9v8b+aT4uKzcrCgS vHXcGk+t5uaOkbyBQlpDhA6HoxYUWFLe7IplM6uZV/fFmjhxkAqrDI4OWWkUJwDxJEAz 5wwg== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20230601; t=1758638731; x=1759243531; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:x-gm-message-state:from:to:cc :subject:date:message-id:reply-to; bh=lPc1khGgtKoM3FlGkfqU+I3xy6hkWBPtPzJJrRqEf2k=; b=qqk0MVwjEDgMEA5cc9G77+vxfBsV03+Uwf3LkG0I1abUTVj3pW0NLoXDmOcd55Ogbn duayOpF9/L6kTuS8DA6ey1Echyq0v810+vZXmlgOHRz/nCqAmCjFrOjO2TELV7DFR29Z 0jvVsS6x8o3ugQKe8v8fwd5ehgmHELXDQxaLcQ4amW1DUHOtfXsuM0TS5zpGwGQpCZS1 H29Zpmp6+cd2tkFbbKu9Pj08fnY0up3L9Q6BJb8iRTV0LQzSsSMQK4QBmEmm8TgN7E81 z176bsJxgXGcJ2kLRAuHhK7DznIlcbneAE5Db2pTiDWVI+JwMQ4w+UEu7wPTzv/Lo6me YQPg== X-Forwarded-Encrypted: i=1; AJvYcCXF/Y9Tf1G7GptX+x4wPhxqB4+oKaBfnAJ+MhBfdyH8m3Q/PjcOY50ytLet/OXcWkXu+eDRAd5JpmDTSNo=@vger.kernel.org X-Gm-Message-State: AOJu0Ywekvx5agHeaYaPKWmieMaq7QVkM4dEBMM4a6XlLkJ5JJZlLGyu ueMAVK0PcvcveYRJYlDEMrGoa21li0iix5B1MiEsO9fo79S8q4OtiqML X-Gm-Gg: ASbGncuYYJ2MnMryxD9SBOViQQYoXnGtIH1B6fK9AnDsvq5/pF9IVNXyu68LbXSMX41 c5NuyEks/TumH/e+g/mslzL96DjIlRYhXskLUxD8uQGXm113UF5BSlXr98MxF9/G6rfPvk1MFXt /Xlqc04qqO4D/GG1QWCyXxc9E34j4QMFcxXph7iQCKKBG8BfDVHqvSo/R0HjcZcVkeCLSjYh+d7 MJPAg/5OGBMxbxgNEp9GOTVdA+zSTGorNXkU3R7Zyzf1TvvQDRxb2oPWU9N4qdlEmyZ60FTaLnS Ovvc98rhESFq7ZX2zPhv54P+0HEudBAzI9YH7dp3P7gPcKbwnprm/BEaBBtkTWX8RHCidA15Lgs 7DUKgvAaycWmxnykimzN9NcgLOi4uvhXnByL7YMZn6iW9BaBu3BR0R4s1TJSQTCkup1jwhsu4dN wfow== X-Google-Smtp-Source: AGHT+IHw/moOQQdjQkyrnN2ABVgFGjJsARhjpZqCkhFnEqOLp4++U1HM/kmTdYY+jb+YZL8vgz1o9g== X-Received: by 2002:a05:600c:8b0d:b0:46e:2330:e959 with SMTP id 5b1f17b1804b1-46e2330ea71mr14864405e9.37.1758638730981; Tue, 23 Sep 2025 07:45:30 -0700 (PDT) Received: from biju.lan (host86-139-30-37.range86-139.btcentralplus.com. [86.139.30.37]) by smtp.gmail.com with ESMTPSA id 5b1f17b1804b1-464f0aac3fdsm238940435e9.1.2025.09.23.07.45.30 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Tue, 23 Sep 2025 07:45:30 -0700 (PDT) From: Biju X-Google-Original-From: Biju To: =?UTF-8?q?Uwe=20Kleine-K=C3=B6nig?= , Philipp Zabel Cc: Biju Das , linux-pwm@vger.kernel.org, linux-kernel@vger.kernel.org, Geert Uytterhoeven , Prabhakar Mahadev Lad , Biju Das , linux-renesas-soc@vger.kernel.org Subject: [PATCH v3 6/8] pwm: rzg2l-gpt: Add suspend/resume support Date: Tue, 23 Sep 2025 15:45:10 +0100 Message-ID: <20250923144524.191892-7-biju.das.jz@bp.renesas.com> X-Mailer: git-send-email 2.43.0 In-Reply-To: <20250923144524.191892-1-biju.das.jz@bp.renesas.com> References: <20250923144524.191892-1-biju.das.jz@bp.renesas.com> Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Content-Type: text/plain; charset="utf-8" From: Biju Das On RZ/G3E using PSCI, s2ram powers down the SoC. Add suspend/resume callbacks for save/restore GPT context. Signed-off-by: Biju Das --- v3: * New patch. --- drivers/pwm/pwm-rzg2l-gpt.c | 118 +++++++++++++++++++++++++++++++----- 1 file changed, 102 insertions(+), 16 deletions(-) diff --git a/drivers/pwm/pwm-rzg2l-gpt.c b/drivers/pwm/pwm-rzg2l-gpt.c index 087bc3c0778c..abf8dae52b91 100644 --- a/drivers/pwm/pwm-rzg2l-gpt.c +++ b/drivers/pwm/pwm-rzg2l-gpt.c @@ -101,14 +101,26 @@ struct rzg2l_gpt_info { u8 prescale_pow_of_two_mult_factor; }; =20 +struct rzg2l_gpt_cache { + u32 gtpr; + u32 gtccr[2]; + u32 gtcr; + u32 gtior; +}; + struct rzg2l_gpt_chip { void __iomem *mmio; struct mutex lock; /* lock to protect shared channel resources */ const struct rzg2l_gpt_info *info; + struct clk *clk; + struct clk *bus_clk; + struct reset_control *rst; + struct reset_control *rst_s; unsigned long rate_khz; u32 period_ticks[RZG2L_MAX_HW_CHANNELS]; u32 channel_request_count[RZG2L_MAX_HW_CHANNELS]; u32 channel_enable_count[RZG2L_MAX_HW_CHANNELS]; + struct rzg2l_gpt_cache hw_cache[RZG2L_MAX_HW_CHANNELS]; }; =20 /* This represents a hardware configuration for one channel */ @@ -465,10 +477,8 @@ static int rzg2l_gpt_probe(struct platform_device *pde= v) { struct rzg2l_gpt_chip *rzg2l_gpt; struct device *dev =3D &pdev->dev; - struct reset_control *rstc; struct pwm_chip *chip; unsigned long rate; - struct clk *clk; int ret; =20 chip =3D devm_pwmchip_alloc(dev, RZG2L_MAX_PWM_CHANNELS, sizeof(*rzg2l_gp= t)); @@ -482,27 +492,29 @@ static int rzg2l_gpt_probe(struct platform_device *pd= ev) =20 rzg2l_gpt->info =3D of_device_get_match_data(dev); =20 - rstc =3D devm_reset_control_get_exclusive_deasserted(dev, NULL); - if (IS_ERR(rstc)) - return dev_err_probe(dev, PTR_ERR(rstc), "Cannot deassert reset control\= n"); + rzg2l_gpt->rst =3D devm_reset_control_get_exclusive_deasserted(dev, NULL); + if (IS_ERR(rzg2l_gpt->rst)) + return dev_err_probe(dev, PTR_ERR(rzg2l_gpt->rst), + "Cannot deassert reset control\n"); =20 - rstc =3D devm_reset_control_get_optional_exclusive_deasserted(dev, "rst_s= "); - if (IS_ERR(rstc)) - return dev_err_probe(dev, PTR_ERR(rstc), "Cannot deassert rst_s reset\n"= ); + rzg2l_gpt->rst_s =3D devm_reset_control_get_optional_exclusive_deasserted= (dev, "rst_s"); + if (IS_ERR(rzg2l_gpt->rst_s)) + return dev_err_probe(dev, PTR_ERR(rzg2l_gpt->rst_s), + "Cannot deassert rst_s reset\n"); =20 - clk =3D devm_clk_get_optional_enabled(dev, "bus"); - if (IS_ERR(clk)) - return dev_err_probe(dev, PTR_ERR(clk), "Cannot get bus clock\n"); + rzg2l_gpt->bus_clk =3D devm_clk_get_optional_enabled(dev, "bus"); + if (IS_ERR(rzg2l_gpt->bus_clk)) + return dev_err_probe(dev, PTR_ERR(rzg2l_gpt->bus_clk), "Cannot get bus c= lock\n"); =20 - clk =3D devm_clk_get_enabled(dev, NULL); - if (IS_ERR(clk)) - return dev_err_probe(dev, PTR_ERR(clk), "Cannot get clock\n"); + rzg2l_gpt->clk =3D devm_clk_get_enabled(dev, NULL); + if (IS_ERR(rzg2l_gpt->clk)) + return dev_err_probe(dev, PTR_ERR(rzg2l_gpt->clk), "Cannot get clock\n"); =20 - ret =3D devm_clk_rate_exclusive_get(dev, clk); + ret =3D devm_clk_rate_exclusive_get(dev, rzg2l_gpt->clk); if (ret) return ret; =20 - rate =3D clk_get_rate(clk); + rate =3D clk_get_rate(rzg2l_gpt->clk); if (!rate) return dev_err_probe(dev, -EINVAL, "The gpt clk rate is 0"); =20 @@ -529,9 +541,80 @@ static int rzg2l_gpt_probe(struct platform_device *pde= v) if (ret) return dev_err_probe(dev, ret, "Failed to add PWM chip\n"); =20 + platform_set_drvdata(pdev, chip); + return 0; } =20 +static int rzg2l_gpt_suspend(struct device *dev) +{ + struct pwm_chip *chip =3D dev_get_drvdata(dev); + struct rzg2l_gpt_chip *rzg2l_gpt =3D to_rzg2l_gpt_chip(chip); + unsigned int i; + + for (i =3D 0; i < RZG2L_MAX_HW_CHANNELS; i++) { + if (!rzg2l_gpt->channel_enable_count[i]) + continue; + + rzg2l_gpt->hw_cache[i].gtpr =3D rzg2l_gpt_read(rzg2l_gpt, RZG2L_GTPR(i)); + rzg2l_gpt->hw_cache[i].gtccr[0] =3D rzg2l_gpt_read(rzg2l_gpt, RZG2L_GTCC= R(i, 0)); + rzg2l_gpt->hw_cache[i].gtccr[1] =3D rzg2l_gpt_read(rzg2l_gpt, RZG2L_GTCC= R(i, 1)); + rzg2l_gpt->hw_cache[i].gtcr =3D rzg2l_gpt_read(rzg2l_gpt, RZG2L_GTCR(i)); + rzg2l_gpt->hw_cache[i].gtior =3D rzg2l_gpt_read(rzg2l_gpt, RZG2L_GTIOR(i= )); + } + + clk_disable_unprepare(rzg2l_gpt->clk); + clk_disable_unprepare(rzg2l_gpt->bus_clk); + reset_control_assert(rzg2l_gpt->rst_s); + reset_control_assert(rzg2l_gpt->rst); + + return 0; +} + +static int rzg2l_gpt_resume(struct device *dev) +{ + struct pwm_chip *chip =3D dev_get_drvdata(dev); + struct rzg2l_gpt_chip *rzg2l_gpt =3D to_rzg2l_gpt_chip(chip); + unsigned int i; + int ret; + + ret =3D reset_control_deassert(rzg2l_gpt->rst); + if (ret) + return ret; + + ret =3D reset_control_deassert(rzg2l_gpt->rst_s); + if (ret) + goto fail_reset; + + ret =3D clk_prepare_enable(rzg2l_gpt->bus_clk); + if (ret) + goto fail_reset_all; + + ret =3D clk_prepare_enable(rzg2l_gpt->clk); + if (ret) + goto fail_bus_clk; + + for (i =3D 0; i < RZG2L_MAX_HW_CHANNELS; i++) { + if (!rzg2l_gpt->channel_enable_count[i]) + continue; + + rzg2l_gpt_write(rzg2l_gpt, RZG2L_GTPR(i), rzg2l_gpt->hw_cache[i].gtpr); + rzg2l_gpt_write(rzg2l_gpt, RZG2L_GTCCR(i, 0), rzg2l_gpt->hw_cache[i].gtc= cr[0]); + rzg2l_gpt_write(rzg2l_gpt, RZG2L_GTCCR(i, 1), rzg2l_gpt->hw_cache[i].gtc= cr[1]); + rzg2l_gpt_write(rzg2l_gpt, RZG2L_GTCR(i), rzg2l_gpt->hw_cache[i].gtcr); + rzg2l_gpt_write(rzg2l_gpt, RZG2L_GTIOR(i), rzg2l_gpt->hw_cache[i].gtior); + } + + return 0; +fail_bus_clk: + clk_disable_unprepare(rzg2l_gpt->bus_clk); +fail_reset_all: + reset_control_assert(rzg2l_gpt->rst_s); +fail_reset: + reset_control_assert(rzg2l_gpt->rst); + return ret; +} + static const struct rzg2l_gpt_info rzg3e_data =3D { .calculate_prescale =3D rzg3e_gpt_calculate_prescale, .gtcr_tpcs_mask =3D GENMASK(26, 23), @@ -551,10 +634,13 @@ static const struct of_device_id rzg2l_gpt_of_table[]= =3D { }; MODULE_DEVICE_TABLE(of, rzg2l_gpt_of_table); =20 +static DEFINE_SIMPLE_DEV_PM_OPS(rzg2l_gpt_pm_ops, rzg2l_gpt_suspend, rzg2l= _gpt_resume); + static struct platform_driver rzg2l_gpt_driver =3D { .driver =3D { .name =3D "pwm-rzg2l-gpt", .of_match_table =3D rzg2l_gpt_of_table, + .pm =3D pm_sleep_ptr(&rzg2l_gpt_pm_ops), }, .probe =3D rzg2l_gpt_probe, }; --=20 2.43.0