From nobody Thu Oct 2 02:15:13 2025 Received: from mail-wm1-f52.google.com (mail-wm1-f52.google.com [209.85.128.52]) (using TLSv1.2 with cipher ECDHE-RSA-AES128-GCM-SHA256 (128/128 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id CBCC323A98E for ; Tue, 23 Sep 2025 14:45:29 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=none smtp.client-ip=209.85.128.52 ARC-Seal: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1758638732; cv=none; b=NHiSsOsoDLtfk50/p6xbDe8G2Fz+Izpe7sJYdBFw27rGzW2/wQJiRfVPyvc9EcsVw989wFr9ja6ElOuxcJBoiExHCPM1UqTxkisUwWpH4f45DnZw3QxHwmGsMgvk6AJPkE2g5I2u856qwEZmT6T4wWtMrVGvXYevsFKpsCMwcco= ARC-Message-Signature: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1758638732; c=relaxed/simple; bh=v/6yP43Xas8IL2SDwh5MqBaXKzliC0aaemzEd5pY6i8=; h=From:To:Cc:Subject:Date:Message-ID:In-Reply-To:References: MIME-Version; b=bnBfwNEfd+Yg81oNnfFc8ZLP9CKN7jSqW/fltn8sHcy8WxxZ4oNAey7SwyThGY4o45+2er3TUA45hYtNj5lvy2NFwpqMFQTlcTcaV/F5jFtfIKC2y11IQimJ2HCw0ulAglK9hDMU2tCKZuC16lrhV/IEV4tGY38doHoeNkApq3Q= ARC-Authentication-Results: i=1; smtp.subspace.kernel.org; dmarc=pass (p=none dis=none) header.from=gmail.com; spf=pass smtp.mailfrom=gmail.com; dkim=pass (2048-bit key) header.d=gmail.com header.i=@gmail.com header.b=OB85I1+j; arc=none smtp.client-ip=209.85.128.52 Authentication-Results: smtp.subspace.kernel.org; dmarc=pass (p=none dis=none) header.from=gmail.com Authentication-Results: smtp.subspace.kernel.org; spf=pass smtp.mailfrom=gmail.com Authentication-Results: smtp.subspace.kernel.org; dkim=pass (2048-bit key) header.d=gmail.com header.i=@gmail.com header.b="OB85I1+j" Received: by mail-wm1-f52.google.com with SMTP id 5b1f17b1804b1-46b303f755aso28478655e9.1 for ; Tue, 23 Sep 2025 07:45:29 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=gmail.com; s=20230601; t=1758638728; x=1759243528; darn=vger.kernel.org; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:from:to:cc:subject:date :message-id:reply-to; bh=7hWknpiUnT9ncdcJYksHsytZcbFmlaZdO2Pms9xtMZQ=; b=OB85I1+ji4vjyb+s8CmATtkF+FseZjwU1pri18ws6xcn4Ppcu5gLemhXK0VwISNU5R ujbQPQFHRLMN0f4pIAtWpu8fclGhlW+o+Oqfr7vRo9WLDNnRjpQdvnucdBON8VhV0pvq Saz7Na/6gORltaeBsQuYLt2QImlV11us4MuWQD7FNzDbX5H7OTXWf/McQMJKHZ8hFkyT VZmvoXr0Jv1dS+hKVXHPN4LjQUorCxfmeJIj5R4cVenurmJSkAi3poo8bQ9wqBnNCBvr 0p78RXUhJJIqKHYk4mlZELF7GXULpFgAdS6vrYduEwxO26TDRKRN4vL2Hu3ylBsn+eKk 1lHA== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20230601; t=1758638728; x=1759243528; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:x-gm-message-state:from:to:cc :subject:date:message-id:reply-to; bh=7hWknpiUnT9ncdcJYksHsytZcbFmlaZdO2Pms9xtMZQ=; b=cC7I17lvsNx93vxh+dxYdeq9mCG1hIVlESXvgf/pJC1GpBeSCZ/ZxY9YmJlk5nfMUq dfuhMHSt20EN2ZZvyk+fs6p9zug8/0uTN5xDn+NB1R0n9sNdNtv+FMzUOhj8WTOHmBHE B4885pMVvtwdud3Bl1Fg6B/fJDxe3sw85PAI+jOvlaINwtCMvMK+EG2ZrdABuRAQro1g hatVxrAqU/vk23VE8ppQYtexm0WO4h6LUuDHIikoDrXDDZBjUcRtxERzMaK9PlkMx/pB pRs9AWVtbzg8UtmI1WWQ4UVBGdmxWMq33wEiKolbS3I4y71UI41aDASuNxxA8oXyFjkR G1Ug== X-Forwarded-Encrypted: i=1; AJvYcCVdMpFcKSXzKjOTi9MFuU9dAjxPRnUftcDR2J0R/GD3EbRma/a5qxyPbK/GYpcjJ7EMydPbhOj+XXVrkR4=@vger.kernel.org X-Gm-Message-State: AOJu0Yyh58BEFrdOrxSjiBy3upxSXmB7688AuDE8Wd4P83jfPD/hC43l IMNI2UWMCzpOoa9M6bRl/BPvaD1sW5vrS7oaQsAfw8MS1iSQizeWpMYd X-Gm-Gg: ASbGncsr5lc/lJ8/Ay3///FVKM/ruM0ZEYdZ2s8cNpEdclFa2vGAuIK9v++HQmAlXzM vyxeivu7IeE6cGiaK6mZI5ZmlQEDFP/u34o9j/GWF1Wqv8PyiqHFtQ0OAVAe2bsZdTUQWvbgtJR Kz1CgX4kksrSwBgNnKkrvTEFMj5ll+f4taHLpy6YQPPGvtnbSaAJAU8TgFB+xK6HY4BFeuQ8jJx LWSN8fJhAf/KOxVLMkimm3wjRWmoncIBzFwskRMeaQNgQ+j04LD1qqydr2nnpK3aUIvbNwXNW/L /R/TN0Cxj2qHJkKwZzYs+9hqXDDIZwcfFlcsxsSd5TGxDbr6IHobPipnnR/ehJkHiBS2k42if9z wYs4R3w+Kk3vzf53qm0cu3s4Bnb2vTgtfEGQzaveG3Q26YLp3rLOUc2CBQgOiCOgyaOOhEb9jZQ sSiA== X-Google-Smtp-Source: AGHT+IEfEIkKW4I9tGlw8bA5Jwg+sH3rB4c1YHW3qG0pAgSBH5W2hvRjK+Ule13vT0cVygKWhd9FoQ== X-Received: by 2002:a05:600c:4595:b0:45f:2bc1:22d0 with SMTP id 5b1f17b1804b1-46e1dac9c58mr29386395e9.33.1758638727687; Tue, 23 Sep 2025 07:45:27 -0700 (PDT) Received: from biju.lan (host86-139-30-37.range86-139.btcentralplus.com. [86.139.30.37]) by smtp.gmail.com with ESMTPSA id 5b1f17b1804b1-464f0aac3fdsm238940435e9.1.2025.09.23.07.45.27 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Tue, 23 Sep 2025 07:45:27 -0700 (PDT) From: Biju X-Google-Original-From: Biju To: =?UTF-8?q?Uwe=20Kleine-K=C3=B6nig?= , Rob Herring , Krzysztof Kozlowski , Conor Dooley , Geert Uytterhoeven , Magnus Damm Cc: Biju Das , linux-pwm@vger.kernel.org, devicetree@vger.kernel.org, linux-kernel@vger.kernel.org, linux-renesas-soc@vger.kernel.org, Prabhakar Mahadev Lad , Biju Das Subject: [PATCH v3 1/8] dt-bindings: pwm: Document RZ/G3E GPT support Date: Tue, 23 Sep 2025 15:45:05 +0100 Message-ID: <20250923144524.191892-2-biju.das.jz@bp.renesas.com> X-Mailer: git-send-email 2.43.0 In-Reply-To: <20250923144524.191892-1-biju.das.jz@bp.renesas.com> References: <20250923144524.191892-1-biju.das.jz@bp.renesas.com> Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Content-Type: text/plain; charset="utf-8" From: Biju Das Document support for the GPT found on the Renesas RZ/G3E (R9A09G047) SoC. The GPT is a 32-bit timer with 16 hardware channels (GPT0: 8 channel and GPT1: 8channels). The hardware supports simultaneous control of all channels. PWM waveforms can be generated by controlling the up-counter, downcounter, or up- and down-counter. Signed-off-by: Biju Das Reviewed-by: Rob Herring (Arm) --- v2->v3: * Added Rb tag from Rob. v1->v2: * Created separate document for RZ/G3E GPT. * Updated commit header and description. --- .../bindings/pwm/renesas,rzg3e-gpt.yaml | 323 ++++++++++++++++++ 1 file changed, 323 insertions(+) create mode 100644 Documentation/devicetree/bindings/pwm/renesas,rzg3e-gpt= .yaml diff --git a/Documentation/devicetree/bindings/pwm/renesas,rzg3e-gpt.yaml b= /Documentation/devicetree/bindings/pwm/renesas,rzg3e-gpt.yaml new file mode 100644 index 000000000000..cb4ffab5f47f --- /dev/null +++ b/Documentation/devicetree/bindings/pwm/renesas,rzg3e-gpt.yaml @@ -0,0 +1,323 @@ +# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause) +%YAML 1.2 +--- +$id: http://devicetree.org/schemas/pwm/renesas,rzg3e-gpt.yaml# +$schema: http://devicetree.org/meta-schemas/core.yaml# + +title: Renesas RZ/G3E General PWM Timer (GPT) + +maintainers: + - Biju Das + +description: | + RZ/G3E General PWM Timer (GPT) composed of 16 channels with 32-bit + timer. It supports the following functions + * 32 bits x 16 channels. + * Up-counting or down-counting (saw waves) or up/down-counting + (triangle waves) for each counter. + * Clock sources independently selectable for each channel. + * Four I/O pins per channel. + * Two output compare/input capture registers per channel. + * For the two output compare/input capture registers of each channel, + four registers are provided as buffer registers and are capable of + operating as comparison registers when buffering is not in use. + * In output compare operation, buffer switching can be at crests or + troughs, enabling the generation of laterally asymmetric PWM waveforms. + * Registers for setting up frame cycles in each channel (with capability + for generating interrupts at overflow or underflow) + * Generation of dead times in PWM operation. + * Synchronous starting, stopping and clearing counters for arbitrary + channels. + * Count start, count stop, count clear, up-count, down-count, or input + capture operation in response to a maximum of 8 ELC events. + * Count start, count stop, count clear, up-count, down-count, or input + capture operation in response to the status of two input pins. + * Starting, clearing, stopping and up/down counters in response to a + maximum of four external triggers. + * Output pin disable function by detected short-circuits between output + pins. + * A/D converter start triggers can be generated. + * Compare match A to F event and overflow/underflow event can be output + to the ELC. + * Enables the noise filter for input capture. + * Logical operation between the channel output. + +properties: + compatible: + items: + - const: renesas,r9a09g047-gpt # RZ/G3E + + reg: + maxItems: 1 + + '#pwm-cells': + const: 3 + + interrupts: + items: + - description: Input capture/compare match of the GTCCRA for channel= GPT{0,1}.0 + - description: Input capture/compare match of the GTCCRB for channel= GPT{0,1}.0 + - description: Compare match with the GTCCRC for channel GPT{0,1}.0 + - description: Compare match with the GTCCRD for channel GPT{0,1}.0 + - description: Compare match with the GTCCRE for channel GPT{0,1}.0 + - description: Compare match with the GTCCRF for channel GPT{0,1}.0 + - description: A and B both high interrupt for channel GPT{0,1}.0 + - description: A and B both low interrupt for channel GPT{0,1}.0 + - description: Input capture/compare match of the GTCCRA for channel= GPT{0,1}.1 + - description: Input capture/compare match of the GTCCRB for channel= GPT{0,1}.1 + - description: Compare match with the GTCCRC for channel GPT{0,1}.1 + - description: Compare match with the GTCCRD for channel GPT{0,1}.1 + - description: Compare match with the GTCCRE for channel GPT{0,1}.1 + - description: Compare match with the GTCCRF for channel GPT{0,1}.1 + - description: A and B both high interrupt for channel GPT{0,1}.1 + - description: A and B both low interrupt for channel GPT{0,1}.1 + - description: Input capture/compare match of the GTCCRA for channel= GPT{0,1}.2 + - description: Input capture/compare match of the GTCCRB for channel= GPT{0,1}.2 + - description: Compare match with the GTCCRC for channel GPT{0,1}.2 + - description: Compare match with the GTCCRD for channel GPT{0,1}.2 + - description: Compare match with the GTCCRE for channel GPT{0,1}.2 + - description: Compare match with the GTCCRF for channel GPT{0,1}.2 + - description: A and B both high interrupt for channel GPT{0,1}.2 + - description: A and B both low interrupt for channel GPT{0,1}.2 + - description: Input capture/compare match of the GTCCRA for channel= GPT{0,1}.3 + - description: Input capture/compare match of the GTCCRB for channel= GPT{0,1}.3 + - description: Compare match with the GTCCRC for channel GPT{0,1}.3 + - description: Compare match with the GTCCRD for channel GPT{0,1}.3 + - description: Compare match with the GTCCRE for channel GPT{0,1}.3 + - description: Compare match with the GTCCRF for channel GPT{0,1}.3 + - description: A and B both high interrupt for channel GPT{0,1}.3 + - description: A and B both low interrupt for channel GPT{0,1}.3 + - description: Input capture/compare match of the GTCCRA for channel= GPT{0,1}.4 + - description: Input capture/compare match of the GTCCRB for channel= GPT{0,1}.4 + - description: Compare match with the GTCCRC for channel GPT{0,1}.4 + - description: Compare match with the GTCCRD for channel GPT{0,1}.4 + - description: Compare match with the GTCCRE for channel GPT{0,1}.4 + - description: Compare match with the GTCCRF for channel GPT{0,1}.4 + - description: A and B both high interrupt for channel GPT{0,1}.4 + - description: A and B both low interrupt for channel GPT{0,1}.4 + - description: Input capture/compare match of the GTCCRA for channel= GPT{0,1}.5 + - description: Input capture/compare match of the GTCCRB for channel= GPT{0,1}.5 + - description: Compare match with the GTCCRC for channel GPT{0,1}.5 + - description: Compare match with the GTCCRD for channel GPT{0,1}.5 + - description: Compare match with the GTCCRE for channel GPT{0,1}.5 + - description: Compare match with the GTCCRF for channel GPT{0,1}.5 + - description: A and B both high interrupt for channel GPT{0,1}.5 + - description: A and B both low interrupt for channel GPT{0,1}.5 + - description: Input capture/compare match of the GTCCRA for channel= GPT{0,1}.6 + - description: Input capture/compare match of the GTCCRB for channel= GPT{0,1}.6 + - description: Compare match with the GTCCRC for channel GPT{0,1}.6 + - description: Compare match with the GTCCRD for channel GPT{0,1}.6 + - description: Compare match with the GTCCRE for channel GPT{0,1}.6 + - description: Compare match with the GTCCRF for channel GPT{0,1}.6 + - description: A and B both high interrupt for channel GPT{0,1}.6 + - description: A and B both low interrupt for channel GPT{0,1}.6 + - description: Input capture/compare match of the GTCCRA for channel= GPT{0,1}.7 + - description: Input capture/compare match of the GTCCRB for channel= GPT{0,1}.7 + - description: Compare match with the GTCCRC for channel GPT{0,1}.7 + - description: Compare match with the GTCCRD for channel GPT{0,1}.7 + - description: Compare match with the GTCCRE for channel GPT{0,1}.7 + - description: Compare match with the GTCCRF for channel GPT{0,1}.7 + - description: A and B both high interrupt for channel GPT{0,1}.7 + - description: A and B both low interrupt for channel GPT{0,1}.7 + + interrupt-names: + items: + - const: gtcia0 + - const: gtcib0 + - const: gtcic0 + - const: gtcid0 + - const: gtcie0 + - const: gtcif0 + - const: gtcih0 + - const: gtcil0 + - const: gtcia1 + - const: gtcib1 + - const: gtcic1 + - const: gtcid1 + - const: gtcie1 + - const: gtcif1 + - const: gtcih1 + - const: gtcil1 + - const: gtcia2 + - const: gtcib2 + - const: gtcic2 + - const: gtcid2 + - const: gtcie2 + - const: gtcif2 + - const: gtcih2 + - const: gtcil2 + - const: gtcia3 + - const: gtcib3 + - const: gtcic3 + - const: gtcid3 + - const: gtcie3 + - const: gtcif3 + - const: gtcih3 + - const: gtcil3 + - const: gtcia4 + - const: gtcib4 + - const: gtcic4 + - const: gtcid4 + - const: gtcie4 + - const: gtcif4 + - const: gtcih4 + - const: gtcil4 + - const: gtcia5 + - const: gtcib5 + - const: gtcic5 + - const: gtcid5 + - const: gtcie5 + - const: gtcif5 + - const: gtcih5 + - const: gtcil5 + - const: gtcia6 + - const: gtcib6 + - const: gtcic6 + - const: gtcid6 + - const: gtcie6 + - const: gtcif6 + - const: gtcih6 + - const: gtcil6 + - const: gtcia7 + - const: gtcib7 + - const: gtcic7 + - const: gtcid7 + - const: gtcie7 + - const: gtcif7 + - const: gtcih7 + - const: gtcil7 + + clocks: + items: + - description: Core clock (PCLKD) + - description: Bus clock (PCLKA) + + clock-names: + items: + - const: core + - const: bus + + power-domains: + maxItems: 1 + + resets: + items: + - description: Reset for bus clock (PCLKA/PCLKD) + - description: Reset for core clock (PCLKD) + + reset-names: + items: + - const: rst_p + - const: rst_s + +required: + - compatible + - reg + - interrupts + - interrupt-names + - clocks + - clock-names + - power-domains + - resets + - reset-names + +allOf: + - $ref: pwm.yaml# + +additionalProperties: false + +examples: + - | + #include + #include + + pwm@13010000 { + compatible =3D "renesas,r9a09g047-gpt"; + reg =3D <0x13010000 0x10000>; + interrupts =3D , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + ; + interrupt-names =3D "gtcia0", "gtcib0", "gtcic0", "gtcid0", + "gtcie0", "gtcif0", "gtcih0", "gtcil0", + "gtcia1", "gtcib1", "gtcic1", "gtcid1", + "gtcie1", "gtcif1", "gtcih1", "gtcil1", + "gtcia2", "gtcib2", "gtcic2", "gtcid2", + "gtcie2", "gtcif2", "gtcih2", "gtcil2", + "gtcia3", "gtcib3", "gtcic3", "gtcid3", + "gtcie3", "gtcif3", "gtcih3", "gtcil3", + "gtcia4", "gtcib4", "gtcic4", "gtcid4", + "gtcie4", "gtcif4", "gtcih4", "gtcil4", + "gtcia5", "gtcib5", "gtcic5", "gtcid5", + "gtcie5", "gtcif5", "gtcih5", "gtcil5", + "gtcia6", "gtcib6", "gtcic6", "gtcid6", + "gtcie6", "gtcif6", "gtcih6", "gtcil6", + "gtcia7", "gtcib7", "gtcic7", "gtcid7", + "gtcie7", "gtcif7", "gtcih7", "gtcil7"; + clocks =3D <&cpg CPG_MOD 0x31>, <&cpg CPG_MOD 0x31>; + clock-names =3D "core", "bus"; + power-domains =3D <&cpg>; + resets =3D <&cpg 0x59>, <&cpg 0x5a>; + reset-names =3D "rst_p", "rst_s"; + #pwm-cells =3D <3>; + }; --=20 2.43.0 From nobody Thu Oct 2 02:15:13 2025 Received: from mail-wm1-f42.google.com (mail-wm1-f42.google.com [209.85.128.42]) (using TLSv1.2 with cipher ECDHE-RSA-AES128-GCM-SHA256 (128/128 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id 4105323D7DE for ; Tue, 23 Sep 2025 14:45:30 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=none smtp.client-ip=209.85.128.42 ARC-Seal: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1758638732; cv=none; b=ULBKohAdiheHD7Tq8mAv918BY6Oe3djQIlyCP0PLvRt+awaJKdu+h6qErFfHA8HHM2YUuZsG6hSni08glorRFx6j1CPDeLB+mWMcXL43bzSI9Bm4qWT/MVJFQub+KCo2jrH8AfYzvoDHL8YTOrkIIq0xMLUOuB1xYl9mmF3dFgg= ARC-Message-Signature: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1758638732; c=relaxed/simple; bh=gHfJe2wkX0a4J0T2iaI/ZrXum2g8dABmTaj/MRvdciw=; h=From:To:Cc:Subject:Date:Message-ID:In-Reply-To:References: MIME-Version; b=mRb9Iq0cMZ7mkWKQrIMULDdLhsmKcx6zF7NJ/JiQeHzrft3IaDMRmPmAlCVKvLdzGWH2QaikrTrsUHrVQ8ARWiNzDxqMeYcX+e0Es66OFNpPHMkVx6ieKXgSMLZPfz51PHlk4KtgM3vXXIM5E+KLs1hN5DCnVkjq83q+qxi3Zv8= ARC-Authentication-Results: i=1; smtp.subspace.kernel.org; dmarc=pass (p=none dis=none) header.from=gmail.com; spf=pass smtp.mailfrom=gmail.com; dkim=pass (2048-bit key) header.d=gmail.com header.i=@gmail.com header.b=bGBhYd0w; arc=none smtp.client-ip=209.85.128.42 Authentication-Results: smtp.subspace.kernel.org; dmarc=pass (p=none dis=none) header.from=gmail.com Authentication-Results: smtp.subspace.kernel.org; spf=pass smtp.mailfrom=gmail.com Authentication-Results: smtp.subspace.kernel.org; dkim=pass (2048-bit key) header.d=gmail.com header.i=@gmail.com header.b="bGBhYd0w" Received: by mail-wm1-f42.google.com with SMTP id 5b1f17b1804b1-45dd5e24d16so54900565e9.3 for ; Tue, 23 Sep 2025 07:45:29 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=gmail.com; s=20230601; t=1758638728; x=1759243528; darn=vger.kernel.org; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:from:to:cc:subject:date :message-id:reply-to; bh=By9iTZQYVaW98aaM8/fCSAHAyxcTKcPpA3ibSeZs1YE=; b=bGBhYd0w++KpcxU7aVvecVbsR5MQIPpvzfsnOQmGahz/yh6ivnTHGt904m3D0OViQA JauHkmL+4FhKrV2OAgIGVLuXaGFDN5bmVWRTgWquXlIQrUTEqtmDqnLFX2w+bk+YGzd/ an5XtmHGtTCM5NyWRJYe9ftUmkBYNXmvBHX06tdd1SIElpvh3YverTe9gMyUW1tufHpX hBIP0mQbTybk0fhQuYPYwvgUyQoYmRL+Fpfd0SlRfvUnTtl8pLvIqB3TJQGEeYAdEtjf 2+B1NG7T2tBl0LNUa2HSlPM752Fw70fsSE4Bq7naPZPf8UrOSD8GVBm1s9rKHlLMvzwA 66mA== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20230601; t=1758638728; x=1759243528; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:x-gm-message-state:from:to:cc :subject:date:message-id:reply-to; bh=By9iTZQYVaW98aaM8/fCSAHAyxcTKcPpA3ibSeZs1YE=; b=tOar6anReLC/ymtEykDnTZ8wNjKPf964VlAs7Ot6B1yM8ZVXvgn/QgFwsTdEQHigt6 2rhMnBHPMdx2fP70arIV5s63owqQcsSWa2kJrYhAaM4EfSTN7vfNpBfxh6+7SNTZPqIt HZAYscC5fJy/i8+9CqE+o34MHCgj+a0qBi3CQr98xBnhpZ0vp0gaJIXfLzsIoF7LfdUv O3soqDpzccrxreymAK4RuR8vQLdAhaIGrqcbnSEkD4gte52XBa8phgNVUnBKZw7VY1Aw yp7LIAIKM3tEYA94wA84NOvbCMD59H/j6cgJ7vmTN8YGKa3phgUQ3tCrJR819545xlip brVw== X-Forwarded-Encrypted: i=1; AJvYcCVlSTOLfi3QsXWMkqb9pQVsvkhUN16orReyiKG6laegauApzkPnZCCInOQNU8raNshMejhbQSch5A/5Kl4=@vger.kernel.org X-Gm-Message-State: AOJu0Yys+OoQZn+yd7qllYwVuYYHs5uiLY5lVWRSF7ljuPcNXMcQROaz 680Pv55QUKcnAyFCCENSyVHQHnIH9zb+1i8o3PvGYWie8T1j9g1dDNJ+ X-Gm-Gg: ASbGnctPomFZHEABVCx3HS9XZeeRpWqFw/U6ZvRB6aaReHeOEYdDFoP1vzdZJoAt90M W1zER6mKHvzbCof9bnFHeOjyH/jQH5nwnEjBujEQTR0QwOOhIcHJEu29qTWTGbySiId+NWHdB3Q NFlSlRIfFDm+l9DDfzuiHzmvSRhijlLisI+2PEymGe8f/huo5uU2+cCcRh6xTQc+lU3oTqNXebz 1iE3iegAtnfl4Bqg29uU1s0DnmfxLge9FLw3UH+jQEaoiDz9xrJvwEjrPZsEKCoAVMrhkYpwCEV jfi5YjiO62Cs3Zo8Bb3gUd2QtQKhsUL/ZtfdFSUHOI8mGtzXRyKOyzV7jDQjGhKMTJna1a/62Ay o/MrUwVObSomaDp4xk4Ktky5PIwIMeEbwEPkIDZ/v/KWSmWKxhiRxJLxCImb2xTVtghw5f+aMPz ppJQ== X-Google-Smtp-Source: AGHT+IGeaLZNcziJFwxEnB+ujLHDeNr3b8C5SkLS7nPKFj5AlRt42fsuSfQ2qfOOoel3vyehbrlVsA== X-Received: by 2002:a05:600c:c171:b0:46e:1abc:1811 with SMTP id 5b1f17b1804b1-46e1dadca3cmr28239555e9.27.1758638728217; Tue, 23 Sep 2025 07:45:28 -0700 (PDT) Received: from biju.lan (host86-139-30-37.range86-139.btcentralplus.com. [86.139.30.37]) by smtp.gmail.com with ESMTPSA id 5b1f17b1804b1-464f0aac3fdsm238940435e9.1.2025.09.23.07.45.27 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Tue, 23 Sep 2025 07:45:27 -0700 (PDT) From: Biju X-Google-Original-From: Biju To: =?UTF-8?q?Uwe=20Kleine-K=C3=B6nig?= , Geert Uytterhoeven , Magnus Damm Cc: Biju Das , linux-pwm@vger.kernel.org, linux-kernel@vger.kernel.org, linux-renesas-soc@vger.kernel.org, Prabhakar Mahadev Lad , Biju Das , Tommaso Merciai Subject: [PATCH v3 2/8] pwm: rzg2l-gpt: Add info variable to struct rzg2l_gpt_chip Date: Tue, 23 Sep 2025 15:45:06 +0100 Message-ID: <20250923144524.191892-3-biju.das.jz@bp.renesas.com> X-Mailer: git-send-email 2.43.0 In-Reply-To: <20250923144524.191892-1-biju.das.jz@bp.renesas.com> References: <20250923144524.191892-1-biju.das.jz@bp.renesas.com> Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Content-Type: text/plain; charset="utf-8" From: Biju Das RZ/G3E GPT IP is similar to the one found on RZ/G2L GPT, but there are some differences. The field width of prescalar on RZ/G3E is 4 whereas on RZ/G2L it is 3. Add rzg2l_gpt_info variable to handle this differences. The FIELD_PREP and FIELD_GET macro is giving compilation issue as the parameters are not build time constants. So added Non-constant mask variant of FIELD_GET() and FIELD_PREP(). Reviewed-by: Tommaso Merciai Signed-off-by: Biju Das --- v2->v3: * No change. v1->v2: * Collected tag. --- drivers/pwm/pwm-rzg2l-gpt.c | 33 ++++++++++++++++++++++++++++----- 1 file changed, 28 insertions(+), 5 deletions(-) diff --git a/drivers/pwm/pwm-rzg2l-gpt.c b/drivers/pwm/pwm-rzg2l-gpt.c index 392bd129574b..1d09fb01c72f 100644 --- a/drivers/pwm/pwm-rzg2l-gpt.c +++ b/drivers/pwm/pwm-rzg2l-gpt.c @@ -33,6 +33,19 @@ #include #include =20 +/* Non-constant mask variant of FIELD_GET() and FIELD_PREP() */ +#define field_get(_mask, _reg) \ +({\ + typeof(_mask) (mask) =3D (_mask); \ + (((_reg) & (mask)) >> (ffs(mask) - 1)); \ +}) + +#define field_prep(_mask, _val) \ +({\ + typeof(_mask) (mask) =3D (_mask); \ + (((_val) << (ffs(mask) - 1)) & (mask)); \ +}) + #define RZG2L_GET_CH(hwpwm) ((hwpwm) / 2) #define RZG2L_GET_CH_OFFS(ch) (0x100 * (ch)) =20 @@ -46,7 +59,6 @@ =20 #define RZG2L_GTCR_CST BIT(0) #define RZG2L_GTCR_MD GENMASK(18, 16) -#define RZG2L_GTCR_TPCS GENMASK(26, 24) =20 #define RZG2L_GTCR_MD_SAW_WAVE_PWM_MODE FIELD_PREP(RZG2L_GTCR_MD, 0) =20 @@ -77,9 +89,14 @@ #define RZG2L_MAX_SCALE_FACTOR 1024 #define RZG2L_MAX_TICKS ((u64)U32_MAX * RZG2L_MAX_SCALE_FACTOR) =20 +struct rzg2l_gpt_info { + u32 gtcr_tpcs_mask; +}; + struct rzg2l_gpt_chip { void __iomem *mmio; struct mutex lock; /* lock to protect shared channel resources */ + const struct rzg2l_gpt_info *info; unsigned long rate_khz; u32 period_ticks[RZG2L_MAX_HW_CHANNELS]; u32 channel_request_count[RZG2L_MAX_HW_CHANNELS]; @@ -324,7 +341,7 @@ static int rzg2l_gpt_read_waveform(struct pwm_chip *chi= p, =20 guard(mutex)(&rzg2l_gpt->lock); if (rzg2l_gpt_is_ch_enabled(rzg2l_gpt, pwm->hwpwm, >cr)) { - wfhw->prescale =3D FIELD_GET(RZG2L_GTCR_TPCS, gtcr); + wfhw->prescale =3D field_get(rzg2l_gpt->info->gtcr_tpcs_mask, gtcr); wfhw->gtpr =3D rzg2l_gpt_read(rzg2l_gpt, RZG2L_GTPR(ch)); wfhw->gtccr =3D rzg2l_gpt_read(rzg2l_gpt, RZG2L_GTCCR(ch, sub_ch)); if (wfhw->gtccr > wfhw->gtpr) @@ -364,8 +381,8 @@ static int rzg2l_gpt_write_waveform(struct pwm_chip *ch= ip, rzg2l_gpt_write(rzg2l_gpt, RZG2L_GTUDDTYC(ch), RZG2L_GTUDDTYC_UP_COUNTIN= G); =20 /* Select count clock */ - rzg2l_gpt_modify(rzg2l_gpt, RZG2L_GTCR(ch), RZG2L_GTCR_TPCS, - FIELD_PREP(RZG2L_GTCR_TPCS, wfhw->prescale)); + rzg2l_gpt_modify(rzg2l_gpt, RZG2L_GTCR(ch), rzg2l_gpt->info->gtcr_tpcs_m= ask, + field_prep(rzg2l_gpt->info->gtcr_tpcs_mask, wfhw->prescale)); =20 /* Set period */ rzg2l_gpt_write(rzg2l_gpt, RZG2L_GTPR(ch), wfhw->gtpr); @@ -430,6 +447,8 @@ static int rzg2l_gpt_probe(struct platform_device *pdev) if (IS_ERR(rzg2l_gpt->mmio)) return PTR_ERR(rzg2l_gpt->mmio); =20 + rzg2l_gpt->info =3D of_device_get_match_data(dev); + rstc =3D devm_reset_control_get_exclusive_deasserted(dev, NULL); if (IS_ERR(rstc)) return dev_err_probe(dev, PTR_ERR(rstc), "Cannot deassert reset control\= n"); @@ -472,8 +491,12 @@ static int rzg2l_gpt_probe(struct platform_device *pde= v) return 0; } =20 +static const struct rzg2l_gpt_info rzg2l_data =3D { + .gtcr_tpcs_mask =3D GENMASK(26, 24), +}; + static const struct of_device_id rzg2l_gpt_of_table[] =3D { - { .compatible =3D "renesas,rzg2l-gpt", }, + { .compatible =3D "renesas,rzg2l-gpt", .data =3D &rzg2l_data }, { /* Sentinel */ } }; MODULE_DEVICE_TABLE(of, rzg2l_gpt_of_table); --=20 2.43.0 From nobody Thu Oct 2 02:15:13 2025 Received: from mail-wm1-f45.google.com (mail-wm1-f45.google.com [209.85.128.45]) (using TLSv1.2 with cipher ECDHE-RSA-AES128-GCM-SHA256 (128/128 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id 4684B1E8332 for ; Tue, 23 Sep 2025 14:45:31 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=none smtp.client-ip=209.85.128.45 ARC-Seal: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1758638734; cv=none; b=TflogKhg9wDq7vKEbOHWeZOwhKa/AHds0wE3SWzus16YGnM5eRsDAkdLHB7LKlO1xYpkiOYyZmz8ZCccFOy7HZMinh7B5hiF5Rtzdc1f7HeqN9BNjr0dt3NNCA0b7kt/vulgYq9/kuzynSQ6Gu5ruLPr5Ow3EuxsiKfU7aqeyUA= ARC-Message-Signature: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1758638734; c=relaxed/simple; bh=PzTUGS3rsi6YZUQn0pGItTVR2WZEHdiGxiZsu870EA4=; h=From:To:Cc:Subject:Date:Message-ID:In-Reply-To:References: MIME-Version; b=UqIZoX52iax0xuvjaQhYCns3yFqntWhAZGj0ij9vxdUGeowYY/SOKx4I0qqm/ybFqhaYPXxcItwdJRjS8ooEMg8dT/r66LEzHfEd/eIheLS2UJvP0I0DREklF1AB6P/EGdeZpsQemdMGZu9c3yVp8y/zbEaa4arB44xAayWeBlc= ARC-Authentication-Results: i=1; smtp.subspace.kernel.org; dmarc=pass (p=none dis=none) header.from=gmail.com; spf=pass smtp.mailfrom=gmail.com; dkim=pass (2048-bit key) header.d=gmail.com header.i=@gmail.com header.b=AwUF5Wkz; arc=none smtp.client-ip=209.85.128.45 Authentication-Results: smtp.subspace.kernel.org; dmarc=pass (p=none dis=none) header.from=gmail.com Authentication-Results: smtp.subspace.kernel.org; spf=pass smtp.mailfrom=gmail.com Authentication-Results: smtp.subspace.kernel.org; dkim=pass (2048-bit key) header.d=gmail.com header.i=@gmail.com header.b="AwUF5Wkz" Received: by mail-wm1-f45.google.com with SMTP id 5b1f17b1804b1-46e1cc6299cso9761895e9.1 for ; Tue, 23 Sep 2025 07:45:30 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=gmail.com; s=20230601; t=1758638729; x=1759243529; darn=vger.kernel.org; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:from:to:cc:subject:date :message-id:reply-to; bh=4anwDx9v8HakV13d09macXf0BjQ85fB9OQZaHSABwj8=; b=AwUF5Wkz6XghTj5KI+h0SCDJbB7WQCUfkUyJIV2XSLgXo/Iu+z/20jfOF6r0zXqsx0 nl3W1gIXM2QJoJucqRyUplTBxVieVhDQIGv+yCgMoiDePMGustSd9+wK12ORx4jqNe/4 DDdszVstt3D38054YvKcBhkdCH/RA+EbXhMJoOuANTg6hJs0VAAmm02SV2PRVqkNltEJ UOm2jZN3hpq1QtSYYXJrBOHwTRPMOWIVFfWsH6bfpqjTmodsjPSJx8WKM/jhsV7MnYFS 2nB8Oyr5kXySerFfYLk9o9nSuUiSHDTH6xnOB4Z2hIlfURX/EaVZNTcVKr23pHIFlbda vSHg== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20230601; t=1758638729; x=1759243529; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:x-gm-message-state:from:to:cc :subject:date:message-id:reply-to; bh=4anwDx9v8HakV13d09macXf0BjQ85fB9OQZaHSABwj8=; b=Aiab3KW+tqkvQjq88Tp/onQPJnlQ/GZK58uEzK1CtJIpXB0I1hnNmSqhH7TmaVclNt CbYXaRcZGjAcJ+OGd+M12EXQjiV/LUOGUICwFDZveQDt5ULaQj+OVvcBftLm3aQD3hbj VQsld3MJOKi7Ay7sB1J5lWcoR921S0t2jMjPfzx9eJw4giBLT31x5s0bo4mrZvdI72oX nHatQpy3ss6FySr9jVOssSz1otqerlyW7ITeiohTkgWIyCbzBVzKenAxbizsbaRJkcZF 8iSH3r3rQqGM5dJuHJrlgVjtI5wQhERdBIvj3jQ/Be4Fm+8dkmPh1smokkvmh0crOEky oEKw== X-Forwarded-Encrypted: i=1; AJvYcCWiQLfeYJ01t5yY/DKfLAlJUZiJKFVoaFMiaIhOd496HvVhVQiVMgGUPQCJDGOTVD7UlVWLjFKgLKJJl1M=@vger.kernel.org X-Gm-Message-State: AOJu0YxgrkSzrxkVJMdXosAqoOGJmh1WpnCHt1JK3qX5k7ewd0DLMjHU PU+pzZ0vHwNux7J6Tv9NbaSGRZQ/m6KzZlNv2r6FdB2g4QLiGfAcVwUV X-Gm-Gg: ASbGnctkpYoKEWUU6YY2YzxZTHfG34xHigBTZUrV2G+9XcjAzthesyYYEtppND4nfEK cgC+x4ZZwjYH6uBQ43tdEod0DeHSF6EbRWETUzjhHWhfOy6sRB3EjTUcL/tzIN4ZI/P8snCQGk/ Lz1M40CI1/fN3avVe/qs3uycxj5EonaizrCRuVoHZSg9PVLm7zrOUGjAjHZWX0xKqGgsboQ1tt+ rzeG6bum4YO4Aqmku751Rl7/3s8ycNs6qSsCTtj9Q2kuIYk4n+AY/iEGRKbZiW6gmTpmr6Lnd4f 21SvbCvQ2nS4w1ojaTY/Nr0v/eRQQNW0HEFDvzSoDyW5sY9dujub1ZScBQaYSUv0z9TQoEXRcBr /KpUf+VxVq8TGZ0Un91ZOGg8CfHgkMce7yvEdFW9QXUP86RQLvGWQp0av2Cl4CPIQHbxNxbch+E pQlg== X-Google-Smtp-Source: AGHT+IEoPP6mKCiiA6RwSLS+InzvMGsDizgIiADIxBNHLgXuqyF6vVEwKBgbDeUyQkGB/UlkMhrHkg== X-Received: by 2002:a05:600c:3152:b0:45b:7a93:f108 with SMTP id 5b1f17b1804b1-46e1d994a15mr31555955e9.3.1758638729239; Tue, 23 Sep 2025 07:45:29 -0700 (PDT) Received: from biju.lan (host86-139-30-37.range86-139.btcentralplus.com. [86.139.30.37]) by smtp.gmail.com with ESMTPSA id 5b1f17b1804b1-464f0aac3fdsm238940435e9.1.2025.09.23.07.45.28 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Tue, 23 Sep 2025 07:45:28 -0700 (PDT) From: Biju X-Google-Original-From: Biju To: =?UTF-8?q?Uwe=20Kleine-K=C3=B6nig?= , Geert Uytterhoeven , Magnus Damm Cc: Biju Das , linux-pwm@vger.kernel.org, linux-kernel@vger.kernel.org, linux-renesas-soc@vger.kernel.org, Prabhakar Mahadev Lad , Biju Das , Tommaso Merciai Subject: [PATCH v3 3/8] pwm: rzg2l-gpt: Add prescale_pow_of_two_mult_factor variable to struct rzg2l_gpt_info Date: Tue, 23 Sep 2025 15:45:07 +0100 Message-ID: <20250923144524.191892-4-biju.das.jz@bp.renesas.com> X-Mailer: git-send-email 2.43.0 In-Reply-To: <20250923144524.191892-1-biju.das.jz@bp.renesas.com> References: <20250923144524.191892-1-biju.das.jz@bp.renesas.com> Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Content-Type: text/plain; charset="utf-8" From: Biju Das RZ/G3E GPT IP has prescale factor power of 2 where as that of RZ/G2L is 4. Add prescale_pow_of_two_mult_factor variable to struct rzg2l_gpt_info for handling this difference. Reviewed-by: Tommaso Merciai Signed-off-by: Biju Das --- v2->v3: * No change. v1->v2: * Collected tag. --- drivers/pwm/pwm-rzg2l-gpt.c | 17 ++++++++++++----- 1 file changed, 12 insertions(+), 5 deletions(-) diff --git a/drivers/pwm/pwm-rzg2l-gpt.c b/drivers/pwm/pwm-rzg2l-gpt.c index 1d09fb01c72f..d1baac37c771 100644 --- a/drivers/pwm/pwm-rzg2l-gpt.c +++ b/drivers/pwm/pwm-rzg2l-gpt.c @@ -91,6 +91,7 @@ =20 struct rzg2l_gpt_info { u32 gtcr_tpcs_mask; + u8 prescale_pow_of_two_mult_factor; }; =20 struct rzg2l_gpt_chip { @@ -229,6 +230,7 @@ static void rzg2l_gpt_disable(struct rzg2l_gpt_chip *rz= g2l_gpt, static u64 rzg2l_gpt_calculate_period_or_duty(struct rzg2l_gpt_chip *rzg2l= _gpt, u32 val, u8 prescale) { + const struct rzg2l_gpt_info *info =3D rzg2l_gpt->info; u64 tmp; =20 /* @@ -238,15 +240,18 @@ static u64 rzg2l_gpt_calculate_period_or_duty(struct = rzg2l_gpt_chip *rzg2l_gpt, * < 2^32 * 2^10 * 2^20 * =3D 2^62 */ - tmp =3D (u64)val << (2 * prescale); + tmp =3D (u64)val << (info->prescale_pow_of_two_mult_factor * prescale); tmp *=3D USEC_PER_SEC; =20 return DIV64_U64_ROUND_UP(tmp, rzg2l_gpt->rate_khz); } =20 -static u32 rzg2l_gpt_calculate_pv_or_dc(u64 period_or_duty_cycle, u8 presc= ale) +static u32 rzg2l_gpt_calculate_pv_or_dc(const struct rzg2l_gpt_info *info, + u64 period_or_duty_cycle, u8 prescale) { - return min_t(u64, DIV_ROUND_DOWN_ULL(period_or_duty_cycle, 1 << (2 * pres= cale)), + return min_t(u64, + DIV_ROUND_DOWN_ULL(period_or_duty_cycle, + 1 << (info->prescale_pow_of_two_mult_factor * prescale)), U32_MAX); } =20 @@ -257,6 +262,7 @@ static int rzg2l_gpt_round_waveform_tohw(struct pwm_chi= p *chip, =20 { struct rzg2l_gpt_chip *rzg2l_gpt =3D to_rzg2l_gpt_chip(chip); + const struct rzg2l_gpt_info *info =3D rzg2l_gpt->info; struct rzg2l_gpt_waveform *wfhw =3D _wfhw; bool is_small_second_period =3D false; u8 ch =3D RZG2L_GET_CH(pwm->hwpwm); @@ -291,7 +297,7 @@ static int rzg2l_gpt_round_waveform_tohw(struct pwm_chi= p *chip, } =20 wfhw->prescale =3D rzg2l_gpt_calculate_prescale(rzg2l_gpt, period_ticks); - pv =3D rzg2l_gpt_calculate_pv_or_dc(period_ticks, wfhw->prescale); + pv =3D rzg2l_gpt_calculate_pv_or_dc(info, period_ticks, wfhw->prescale); wfhw->gtpr =3D pv; if (is_small_second_period) return 1; @@ -299,7 +305,7 @@ static int rzg2l_gpt_round_waveform_tohw(struct pwm_chi= p *chip, duty_ticks =3D mul_u64_u64_div_u64(wf->duty_length_ns, rzg2l_gpt->rate_kh= z, USEC_PER_SEC); if (duty_ticks > period_ticks) duty_ticks =3D period_ticks; - dc =3D rzg2l_gpt_calculate_pv_or_dc(duty_ticks, wfhw->prescale); + dc =3D rzg2l_gpt_calculate_pv_or_dc(info, duty_ticks, wfhw->prescale); wfhw->gtccr =3D dc; =20 /* @@ -493,6 +499,7 @@ static int rzg2l_gpt_probe(struct platform_device *pdev) =20 static const struct rzg2l_gpt_info rzg2l_data =3D { .gtcr_tpcs_mask =3D GENMASK(26, 24), + .prescale_pow_of_two_mult_factor =3D 2, }; =20 static const struct of_device_id rzg2l_gpt_of_table[] =3D { --=20 2.43.0 From nobody Thu Oct 2 02:15:13 2025 Received: from mail-wm1-f43.google.com (mail-wm1-f43.google.com [209.85.128.43]) (using TLSv1.2 with cipher ECDHE-RSA-AES128-GCM-SHA256 (128/128 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id BC1341917E3 for ; Tue, 23 Sep 2025 14:45:31 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=none smtp.client-ip=209.85.128.43 ARC-Seal: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1758638733; cv=none; b=dD6Rb94uLITHFeDWF9hB/k5XMMPe64L3qkGC3ltQbJw0nh/HNGf/nKd7Jl4nr6ZND8qO/aFtP/qy5bI0m5sIGtCQbmMJxS7/6AUPHG4Saf32NQwlBDri79Bu6V2twZkM8sbKRI2lewiKnYELMONfNJ+PQQ+tIgvKrCT0gT4PlCI= ARC-Message-Signature: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1758638733; c=relaxed/simple; bh=BhWuoBkwSqw7NsnaFxyyeGWfpXdoxScAEzI75wSxdoo=; h=From:To:Cc:Subject:Date:Message-ID:In-Reply-To:References: MIME-Version; b=ePInMVCs7kH0oxQlOz4tUlN7uOeq9jvYtJx8ivoeWUdHl83Cbf0R5L5ZAflF6FrHA9a4K8fxu7tqBwLYANT2ZhIQ+hA7h8hygSmA0kGvZbYkmj5caErUjrL1oEgz0WDXdR8E08os3fP60C69mN5Z6j74OT09gskh4uanaO+woRc= ARC-Authentication-Results: i=1; smtp.subspace.kernel.org; dmarc=pass (p=none dis=none) header.from=gmail.com; spf=pass smtp.mailfrom=gmail.com; dkim=pass (2048-bit key) header.d=gmail.com header.i=@gmail.com header.b=FEQT7DYo; arc=none smtp.client-ip=209.85.128.43 Authentication-Results: smtp.subspace.kernel.org; dmarc=pass (p=none dis=none) header.from=gmail.com Authentication-Results: smtp.subspace.kernel.org; spf=pass smtp.mailfrom=gmail.com Authentication-Results: smtp.subspace.kernel.org; dkim=pass (2048-bit key) header.d=gmail.com header.i=@gmail.com header.b="FEQT7DYo" Received: by mail-wm1-f43.google.com with SMTP id 5b1f17b1804b1-46d25f99d5aso16200325e9.0 for ; Tue, 23 Sep 2025 07:45:31 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=gmail.com; s=20230601; t=1758638730; x=1759243530; darn=vger.kernel.org; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:from:to:cc:subject:date :message-id:reply-to; bh=nZ1YIkKOG5ZcKxrbiXISvB8CTGBUs6wL4teYcebD1Q4=; b=FEQT7DYo2hX02tuLV5h9xVUq8L8/PTrNHeHKOao3zglT9cFp7OdON9cerOzn74Tz4L wMkKfzBxmkYGrSF8ZJniLluh2Eex33Tol/Qp1uHHO43oGX2/B+owFsyC/5znuntrSQFI Mg1PfoFHNWs+xuWXTNpfxs+s0jqydcU73fR2xxjM8bCwaUc2ouWuSR1YpT/CeA8/Yy5L OACGw0kTxn56QbLAA1WhwiK37IIpapXHz75I2jbfndtRksxvu3LdqKxsSqpLDZoybfJ9 KMA2Vd3YBpfsVIa8VCrHDt2RSkriAEIcl4BGIOUG7J7E9/y+bWrbhmD0Ih6x9vxVBCsA MwMg== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20230601; t=1758638730; x=1759243530; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:x-gm-message-state:from:to:cc :subject:date:message-id:reply-to; bh=nZ1YIkKOG5ZcKxrbiXISvB8CTGBUs6wL4teYcebD1Q4=; b=I5wZIVayT0wAUG7iAkEVf9/JM56nZVLz9+GwJxTiptRxujrsFgEDL2wPQG6pg7QFNl y6HYBepaGA6yJUSoHjPRSqZx0cy/ViZzre3wBQvm1aszL3o7NbFwR1bwOQ8DwuJqBjdj EEuYR1z6W6P11U4QmHvO2oOjJlxLW0UWlC3lZIMxfxn5FZZ0tCWOJFHzFYt1Pt305Ir9 ydyorPnB/0dKO6Eq3E7CX8yvXy3dHaSL/sPXErinYnkTbyNUPX0SklztNbb6UuIphA6s xAyVZgdiO4TPVVnoq+vUNpJBPd6blcoG+WcNOVKxZa1tmAcLlRBWWugFKEZgSIE6R5Q9 MaLg== X-Forwarded-Encrypted: i=1; AJvYcCW9/LkKDNvEt8+iCfCAC7XkXgSg/EfG15EvjHZri9hcmBbvqSh4QW2ulFdhII6CXy0NwO8HQNpOF/UXDKc=@vger.kernel.org X-Gm-Message-State: AOJu0YyfcBEa2Zo4qX70uwYR1e2BeK+bRJw01Ip2aJcuZfrF5o+KMLSZ LWVFt33LSMkJ7ibtruYAYcKav9jemZN23F/0BA96X3+7BZLrBi3RJ5i5 X-Gm-Gg: ASbGncvrtac/T1GSsjDxhkRiJ6rN4EtsXvkuh5/CtFtyHtxuylSbj8qHAJc5bwnyyrU 1/19idXdxBZdvf9vQ9/hgvW/5LWdCzg0Zq33nmbucLxQOi0K31xSV21XGPxC/gtzahUNos6+sv7 2/l5PgAaEQX7jPrS/2SWLw7cAfVf4teIWIzMqau7ACltklFQbagEvg9PoYId5vd1y1q2N3JMSOV FLdPEBP2XZoh78Oj792m4DeNcPIVE6Y+x5XuWOQmbcbKV+pvaQdqT0CqDq6k8Pu+yYL/9umIokP 8DjXcKmDoIk55fUSaW5LYdyxOnIVrHjC0alnyJWIa446ur0urV46ihny+jsK3hoXnZBNejM50Ij ES4LUF2y3HSdSUAZ3121HRi3S7PsZBR5dcw2rkQmiIbFXBbysoE3mZCfzAOqHdmlbGI+/ze1JSW j3Lw== X-Google-Smtp-Source: AGHT+IGulPwH5fOVINKa0rDW3oB4wGGljY9HIdmcQhZBQGeWIV8NPJpIlAmFtXu7jcdUNxVdFZrEVQ== X-Received: by 2002:a05:6000:2203:b0:3ee:11d1:2a1e with SMTP id ffacd0b85a97d-405cb2f1435mr2813593f8f.10.1758638729848; Tue, 23 Sep 2025 07:45:29 -0700 (PDT) Received: from biju.lan (host86-139-30-37.range86-139.btcentralplus.com. [86.139.30.37]) by smtp.gmail.com with ESMTPSA id 5b1f17b1804b1-464f0aac3fdsm238940435e9.1.2025.09.23.07.45.29 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Tue, 23 Sep 2025 07:45:29 -0700 (PDT) From: Biju X-Google-Original-From: Biju To: =?UTF-8?q?Uwe=20Kleine-K=C3=B6nig?= , Geert Uytterhoeven , Magnus Damm Cc: Biju Das , linux-pwm@vger.kernel.org, linux-kernel@vger.kernel.org, linux-renesas-soc@vger.kernel.org, Prabhakar Mahadev Lad , Biju Das , Tommaso Merciai Subject: [PATCH v3 4/8] pwm: rzg2l-gpt: Add calculate_prescale() callback to struct rzg2l_gpt_info Date: Tue, 23 Sep 2025 15:45:08 +0100 Message-ID: <20250923144524.191892-5-biju.das.jz@bp.renesas.com> X-Mailer: git-send-email 2.43.0 In-Reply-To: <20250923144524.191892-1-biju.das.jz@bp.renesas.com> References: <20250923144524.191892-1-biju.das.jz@bp.renesas.com> Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Content-Type: text/plain; charset="utf-8" From: Biju Das RZ/G2L GPT the prescale factors are continuous power of 4 whereas on RZ/G3E it is power of 2 but discontinuous. Add calculate_prescale() callback to struct rzg2l_gpt_info for handling this difference. Reviewed-by: Tommaso Merciai Signed-off-by: Biju Das --- v2->v3: * No change. v1->v2: * Collected tag. --- drivers/pwm/pwm-rzg2l-gpt.c | 7 ++++--- 1 file changed, 4 insertions(+), 3 deletions(-) diff --git a/drivers/pwm/pwm-rzg2l-gpt.c b/drivers/pwm/pwm-rzg2l-gpt.c index d1baac37c771..0af3aaf1917a 100644 --- a/drivers/pwm/pwm-rzg2l-gpt.c +++ b/drivers/pwm/pwm-rzg2l-gpt.c @@ -90,6 +90,7 @@ #define RZG2L_MAX_TICKS ((u64)U32_MAX * RZG2L_MAX_SCALE_FACTOR) =20 struct rzg2l_gpt_info { + u8 (*calculate_prescale)(u64 period); u32 gtcr_tpcs_mask; u8 prescale_pow_of_two_mult_factor; }; @@ -138,8 +139,7 @@ static void rzg2l_gpt_modify(struct rzg2l_gpt_chip *rzg= 2l_gpt, u32 reg, u32 clr, (rzg2l_gpt_read(rzg2l_gpt, reg) & ~clr) | set); } =20 -static u8 rzg2l_gpt_calculate_prescale(struct rzg2l_gpt_chip *rzg2l_gpt, - u64 period_ticks) +static u8 rzg2l_gpt_calculate_prescale(u64 period_ticks) { u32 prescaled_period_ticks; u8 prescale; @@ -296,7 +296,7 @@ static int rzg2l_gpt_round_waveform_tohw(struct pwm_chi= p *chip, period_ticks =3D rzg2l_gpt->period_ticks[ch]; } =20 - wfhw->prescale =3D rzg2l_gpt_calculate_prescale(rzg2l_gpt, period_ticks); + wfhw->prescale =3D info->calculate_prescale(period_ticks); pv =3D rzg2l_gpt_calculate_pv_or_dc(info, period_ticks, wfhw->prescale); wfhw->gtpr =3D pv; if (is_small_second_period) @@ -498,6 +498,7 @@ static int rzg2l_gpt_probe(struct platform_device *pdev) } =20 static const struct rzg2l_gpt_info rzg2l_data =3D { + .calculate_prescale =3D rzg2l_gpt_calculate_prescale, .gtcr_tpcs_mask =3D GENMASK(26, 24), .prescale_pow_of_two_mult_factor =3D 2, }; --=20 2.43.0 From nobody Thu Oct 2 02:15:13 2025 Received: from mail-wm1-f42.google.com (mail-wm1-f42.google.com [209.85.128.42]) (using TLSv1.2 with cipher ECDHE-RSA-AES128-GCM-SHA256 (128/128 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id 5DC62253944 for ; Tue, 23 Sep 2025 14:45:32 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=none smtp.client-ip=209.85.128.42 ARC-Seal: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1758638734; cv=none; b=AWD9Ys1WGZgici/CB2UjYMux8kX/sCN0CLfYabowr0nbEMFWD+XpFQ6hwSU+KTihlhPZ335DtKcYIPzgUni85+Y4IUswhF3XCjCKros/k098SS33Q2KnTjDlpb55HF39mV+8JSScJml8qb6r7PxbmaBEbc0A3RjjAhxwgvkyL2Y= ARC-Message-Signature: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1758638734; c=relaxed/simple; bh=9KLJ4BwtbpJm/9b4WxuSUtjekeadp6ZfsZa6/vsycek=; h=From:To:Cc:Subject:Date:Message-ID:In-Reply-To:References: MIME-Version; b=kDmjeERsl6rY5CAs63R9sE5Izk3C9ZJy+sCw81Mdvxs+NRjaUpqT79RQt/MovSzVzo6E6Z0HEmn2EAqDqFOvGKhAHzfKFRTnq5D1jRlnoPrH0VOar/Ixo30s+oCfIjP4zzhUaEXsESDypXkhF0YziaDDo/BY+f9m26Y3jVPIv0o= ARC-Authentication-Results: i=1; smtp.subspace.kernel.org; dmarc=pass (p=none dis=none) header.from=gmail.com; spf=pass smtp.mailfrom=gmail.com; dkim=pass (2048-bit key) header.d=gmail.com header.i=@gmail.com header.b=UOrjEdl9; arc=none smtp.client-ip=209.85.128.42 Authentication-Results: smtp.subspace.kernel.org; dmarc=pass (p=none dis=none) header.from=gmail.com Authentication-Results: smtp.subspace.kernel.org; spf=pass smtp.mailfrom=gmail.com Authentication-Results: smtp.subspace.kernel.org; dkim=pass (2048-bit key) header.d=gmail.com header.i=@gmail.com header.b="UOrjEdl9" Received: by mail-wm1-f42.google.com with SMTP id 5b1f17b1804b1-45dd505a1dfso40578645e9.2 for ; Tue, 23 Sep 2025 07:45:32 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=gmail.com; s=20230601; t=1758638730; x=1759243530; darn=vger.kernel.org; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:from:to:cc:subject:date :message-id:reply-to; bh=iJzzrWzUCil64+RXOrKpLt8hJS1/JsUfq3sdCZB4Iv8=; b=UOrjEdl9MFT2vIinolk9C2fNfVlEjjKV7oPzOEaofVrCEaCssC5nkdzit14konTK1j GXTskkJ37uFUwkwNW0bVB8cBrUCmhE+qy8b3DJkOmhXNLigCAn7hjbRruXsFwuwwxUSV ehNAIwWuOvc25j2RZdlp3drm30XaT6+e8i2QKOwCP53pDauF/xxPm0iGSvvC7YgbdpzV vYNLYiaCzL/YBJ+P4an8Uewxc+okqdwo3fwCuYWwQDkz6GZXl0HxcrlARp1LyfStu9qE MAat8SNwfBGy2+dRafzJ560Rorhxi9lH843QTDRjFz3vf6bWyRpQCw7mWLSdgTZuhRW4 duKQ== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20230601; t=1758638730; x=1759243530; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:x-gm-message-state:from:to:cc :subject:date:message-id:reply-to; bh=iJzzrWzUCil64+RXOrKpLt8hJS1/JsUfq3sdCZB4Iv8=; b=JR1CwQV6BKlxEBj08LdKxSmwt4404OMcNBf5ANfmFO3uS2C1cfjUuPkMtbhrWblT/G q/3ajerrX5HADpw3kv05GBP2oqd2kRGlwv08ulXKRcxdhr5ZlFO5OGNG+xpW3fH/Yhn+ QEoepH80HDUt2tetQmDSUGutJLniTGJnOVRTMhcbBGkWCQssBOsmVOCXbDuMxmMohY93 5uGIM4qoG4upeSG7drw5hErC6B5tuqT2NrFVQXrvIOnX1c03vRCj8S9Jvqu96eqstAs6 HeB26Nh9H4CWNzF+8R7ZlSXLfpzDIoFPZ/0KeTC45ZIooBb4MG5OS1MsVJP5CmJ1PNPx Pj6w== X-Forwarded-Encrypted: i=1; AJvYcCVUhJl8Ws1pTgAvQgYJiES82ti1NcfQ/6I5l1y7PZyj/sCZL3wG7+ZkmUGFTT+W99BkM6ziJxsXGEpWyTo=@vger.kernel.org X-Gm-Message-State: AOJu0YywhQXrE6v3ydMpzSwJYLjltPzZVVwEil1isIY3sl+us3B3Gz9S LCOcxbjGZOvX8kL5MTDCHc/sMSkKGuCcH2RZcvyU4C4KKcwHR3fsfCFN X-Gm-Gg: ASbGncvUhBgmtnhfppICIQ360vp60aCMBDdPPur7S6EjWfMZY0C55aqKWRPC3uY/JaA 748+yblbs+cSBvcu5bVM2oIu4wH/JosWXc1oC7vPW9kxn39hi5Td3MDaUXgvfFw0RKuVDiAoSgY /YpX6m2lCHcx9FIz8q4KBIIYZiltoPEbW4uWSpH7ecQRIZr5R/i0FAahdXAYl1vUdnSMKLiYOsR lB7MLDRkoF/IJXdYUAtT1xG9P7XoI6kvAfXLU8yPcDFPWHoPMhJ+r341RbBN7OpZ2uDkD7JpVV5 CRk2i4QvQASmFLtficleRJNWXul8bC3uCFwe4iBCci+aa1KjP4NxLUpCnflWVTcVArH6FtPX56M ZEeW57tVVvOtNFyr2w7cXftLfYN5qMB4ezk2XYXuwW2QIBx9N9szX3Z842ojwAcpWazjkFgyQ5V 7d5A== X-Google-Smtp-Source: AGHT+IF8SaV47gPXwoIWR6PYZsGf9RNwLPvhOV3otS7XPoc5em+Mo1XsY9TmdJAjeAKHts9TAgBzRw== X-Received: by 2002:a05:600c:154e:b0:45f:29e4:92fc with SMTP id 5b1f17b1804b1-46e1daacd4emr26901375e9.20.1758638730444; Tue, 23 Sep 2025 07:45:30 -0700 (PDT) Received: from biju.lan (host86-139-30-37.range86-139.btcentralplus.com. [86.139.30.37]) by smtp.gmail.com with ESMTPSA id 5b1f17b1804b1-464f0aac3fdsm238940435e9.1.2025.09.23.07.45.29 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Tue, 23 Sep 2025 07:45:30 -0700 (PDT) From: Biju X-Google-Original-From: Biju To: =?UTF-8?q?Uwe=20Kleine-K=C3=B6nig?= , Geert Uytterhoeven , Magnus Damm Cc: Biju Das , linux-pwm@vger.kernel.org, linux-kernel@vger.kernel.org, linux-renesas-soc@vger.kernel.org, Prabhakar Mahadev Lad , Biju Das , Tommaso Merciai Subject: [PATCH v3 5/8] pwm: rzg2l-gpt: Add RZ/G3E support Date: Tue, 23 Sep 2025 15:45:09 +0100 Message-ID: <20250923144524.191892-6-biju.das.jz@bp.renesas.com> X-Mailer: git-send-email 2.43.0 In-Reply-To: <20250923144524.191892-1-biju.das.jz@bp.renesas.com> References: <20250923144524.191892-1-biju.das.jz@bp.renesas.com> Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Content-Type: text/plain; charset="utf-8" From: Biju Das Add RZ/G3E GPT support. It has multiple clocks and resets compared to RZ/G2L. Also prescale field width and factor for calculating prescale are different. Reviewed-by: Tommaso Merciai Signed-off-by: Biju Das --- v2->v3: * No change. v1->v2: * Added link to hardware manual * Updated limitation section * Collected tag=20 --- drivers/pwm/pwm-rzg2l-gpt.c | 46 +++++++++++++++++++++++++++++++++++-- 1 file changed, 44 insertions(+), 2 deletions(-) diff --git a/drivers/pwm/pwm-rzg2l-gpt.c b/drivers/pwm/pwm-rzg2l-gpt.c index 0af3aaf1917a..087bc3c0778c 100644 --- a/drivers/pwm/pwm-rzg2l-gpt.c +++ b/drivers/pwm/pwm-rzg2l-gpt.c @@ -6,15 +6,21 @@ * * Hardware manual for this IP can be found here * https://www.renesas.com/eu/en/document/mah/rzg2l-group-rzg2lc-group-use= rs-manual-hardware-0?language=3Den + * https://www.renesas.com/en/document/mah/rzg3e-group-users-manual-hardwa= re * * Limitations: * - Counter must be stopped before modifying Mode and Prescaler. * - When PWM is disabled, the output is driven to inactive. * - While the hardware supports both polarities, the driver (for now) * only handles normal polarity. - * - General PWM Timer (GPT) has 8 HW channels for PWM operations and - * each HW channel have 2 IOs. + * - For RZ/G2L, the General PWM Timer (GPT) has 8 HW channels for PWM + operations and each HW channel have 2 IOs (GTIOCn{A, B}). * - Each IO is modelled as an independent PWM channel. + * - For RZ/G3E, the General PWM Timer (GPT) has 16 HW channels for PWM + operations (GPT0: 8 channels, GPT1: 8 Channels) and each HW channel + have 4 IOs (GTIOCn{A,AN,B,BN}). The 2 extra IOs GTIOCnAN and GTIOCnBN + in RZ/G3E are anti-phase signals of GTIOCnA and GTIOCnB. The + anti-phase signals of RZ/G3E are not modelled as PWM channel. * - When both channels are used, disabling the channel on one stops the * other. * - When both channels are used, the period of both IOs in the HW channel @@ -153,6 +159,27 @@ static u8 rzg2l_gpt_calculate_prescale(u64 period_tick= s) return prescale; } =20 +static u8 rzg3e_gpt_calculate_prescale(u64 period_ticks) +{ + u32 prescaled_period_ticks; + u8 prescale; + + prescaled_period_ticks =3D period_ticks >> 32; + if (prescaled_period_ticks >=3D 64 && prescaled_period_ticks < 256) { + prescale =3D 6; + } else if (prescaled_period_ticks >=3D 256 && prescaled_period_ticks < 10= 24) { + prescale =3D 8; + } else if (prescaled_period_ticks >=3D 1024) { + prescale =3D 10; + } else { + prescale =3D fls(prescaled_period_ticks); + if (prescale > 1) + prescale -=3D 1; + } + + return prescale; +} + static int rzg2l_gpt_request(struct pwm_chip *chip, struct pwm_device *pwm) { struct rzg2l_gpt_chip *rzg2l_gpt =3D to_rzg2l_gpt_chip(chip); @@ -459,6 +486,14 @@ static int rzg2l_gpt_probe(struct platform_device *pde= v) if (IS_ERR(rstc)) return dev_err_probe(dev, PTR_ERR(rstc), "Cannot deassert reset control\= n"); =20 + rstc =3D devm_reset_control_get_optional_exclusive_deasserted(dev, "rst_s= "); + if (IS_ERR(rstc)) + return dev_err_probe(dev, PTR_ERR(rstc), "Cannot deassert rst_s reset\n"= ); + + clk =3D devm_clk_get_optional_enabled(dev, "bus"); + if (IS_ERR(clk)) + return dev_err_probe(dev, PTR_ERR(clk), "Cannot get bus clock\n"); + clk =3D devm_clk_get_enabled(dev, NULL); if (IS_ERR(clk)) return dev_err_probe(dev, PTR_ERR(clk), "Cannot get clock\n"); @@ -497,6 +532,12 @@ static int rzg2l_gpt_probe(struct platform_device *pde= v) return 0; } =20 +static const struct rzg2l_gpt_info rzg3e_data =3D { + .calculate_prescale =3D rzg3e_gpt_calculate_prescale, + .gtcr_tpcs_mask =3D GENMASK(26, 23), + .prescale_pow_of_two_mult_factor =3D 1, +}; + static const struct rzg2l_gpt_info rzg2l_data =3D { .calculate_prescale =3D rzg2l_gpt_calculate_prescale, .gtcr_tpcs_mask =3D GENMASK(26, 24), @@ -504,6 +545,7 @@ static const struct rzg2l_gpt_info rzg2l_data =3D { }; =20 static const struct of_device_id rzg2l_gpt_of_table[] =3D { + { .compatible =3D "renesas,r9a09g047-gpt", .data =3D &rzg3e_data }, { .compatible =3D "renesas,rzg2l-gpt", .data =3D &rzg2l_data }, { /* Sentinel */ } }; --=20 2.43.0 From nobody Thu Oct 2 02:15:13 2025 Received: from mail-wm1-f47.google.com (mail-wm1-f47.google.com [209.85.128.47]) (using TLSv1.2 with cipher ECDHE-RSA-AES128-GCM-SHA256 (128/128 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id CA11C23A984 for ; Tue, 23 Sep 2025 14:45:32 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=none smtp.client-ip=209.85.128.47 ARC-Seal: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1758638735; cv=none; b=ms1cJqfY/g7aawbkzBF9Exa6Z2+M/ZfLtn2FLhZQDTruFBqNSKLZRASo2fQY4mmwTjGqHzAlCeM6p9QAcp0LEsS8AaU6RY9bJHpqZGZLnHNDo11MMCcxRFCJmJAM5BdZgndkcX5VF0JqxjJ43+Vw5EzpSRZQe4NMX1j/jACsNoI= ARC-Message-Signature: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1758638735; c=relaxed/simple; bh=OjsLrF0BpyixmbNmZqRDeZM8/Q9vuOqtCut1I2w6tGk=; h=From:To:Cc:Subject:Date:Message-ID:In-Reply-To:References: MIME-Version; b=ajwSVTA6E71nOl7EMEdvURFd46MJxMXznVo4CvcCaE9FLhBv8hFmfiQa0HofkHyDpZv3k/1c9WrS9FF+wiNO1Fzi1n+oCb3sKzkA3XeO/Zszg1S3yVQY7jYr7McfnvJ/z7v5gUTNebc8NIateWJsKDO77oHgY2/38w7SXFfXLdw= ARC-Authentication-Results: i=1; smtp.subspace.kernel.org; dmarc=pass (p=none dis=none) header.from=gmail.com; spf=pass smtp.mailfrom=gmail.com; dkim=pass (2048-bit key) header.d=gmail.com header.i=@gmail.com header.b=ij+NF/sf; arc=none smtp.client-ip=209.85.128.47 Authentication-Results: smtp.subspace.kernel.org; dmarc=pass (p=none dis=none) header.from=gmail.com Authentication-Results: smtp.subspace.kernel.org; spf=pass smtp.mailfrom=gmail.com Authentication-Results: smtp.subspace.kernel.org; dkim=pass (2048-bit key) header.d=gmail.com header.i=@gmail.com header.b="ij+NF/sf" Received: by mail-wm1-f47.google.com with SMTP id 5b1f17b1804b1-46e1e318f58so7930415e9.2 for ; Tue, 23 Sep 2025 07:45:32 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=gmail.com; s=20230601; t=1758638731; x=1759243531; darn=vger.kernel.org; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:from:to:cc:subject:date :message-id:reply-to; bh=lPc1khGgtKoM3FlGkfqU+I3xy6hkWBPtPzJJrRqEf2k=; b=ij+NF/sfiWk+1ENFruXrQ4KJ+jnBN03VRNgTXIMFy/ZU631B99ithKyI4JJxy4SZIS XpVYQzQwzle/VEceSbLb8br9OdVh+7boYfCgapNaLysQLcUJkk29g3S6cZo1ZdhAoYoT yaSnG4BxqLNHoIKgjaP05sYrfQRE3Y9/oWJCjcwriZSzldtZe7k1PIUjQxIhG+RK/opW QrVBBAih3nSgVUCFalIvsTQebfOfao6h0EwBM0tyPjLue9k6TLuf9v8b+aT4uKzcrCgS vHXcGk+t5uaOkbyBQlpDhA6HoxYUWFLe7IplM6uZV/fFmjhxkAqrDI4OWWkUJwDxJEAz 5wwg== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20230601; t=1758638731; x=1759243531; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:x-gm-message-state:from:to:cc :subject:date:message-id:reply-to; bh=lPc1khGgtKoM3FlGkfqU+I3xy6hkWBPtPzJJrRqEf2k=; b=qqk0MVwjEDgMEA5cc9G77+vxfBsV03+Uwf3LkG0I1abUTVj3pW0NLoXDmOcd55Ogbn duayOpF9/L6kTuS8DA6ey1Echyq0v810+vZXmlgOHRz/nCqAmCjFrOjO2TELV7DFR29Z 0jvVsS6x8o3ugQKe8v8fwd5ehgmHELXDQxaLcQ4amW1DUHOtfXsuM0TS5zpGwGQpCZS1 H29Zpmp6+cd2tkFbbKu9Pj08fnY0up3L9Q6BJb8iRTV0LQzSsSMQK4QBmEmm8TgN7E81 z176bsJxgXGcJ2kLRAuHhK7DznIlcbneAE5Db2pTiDWVI+JwMQ4w+UEu7wPTzv/Lo6me YQPg== X-Forwarded-Encrypted: i=1; AJvYcCXF/Y9Tf1G7GptX+x4wPhxqB4+oKaBfnAJ+MhBfdyH8m3Q/PjcOY50ytLet/OXcWkXu+eDRAd5JpmDTSNo=@vger.kernel.org X-Gm-Message-State: AOJu0Ywekvx5agHeaYaPKWmieMaq7QVkM4dEBMM4a6XlLkJ5JJZlLGyu ueMAVK0PcvcveYRJYlDEMrGoa21li0iix5B1MiEsO9fo79S8q4OtiqML X-Gm-Gg: ASbGncuYYJ2MnMryxD9SBOViQQYoXnGtIH1B6fK9AnDsvq5/pF9IVNXyu68LbXSMX41 c5NuyEks/TumH/e+g/mslzL96DjIlRYhXskLUxD8uQGXm113UF5BSlXr98MxF9/G6rfPvk1MFXt /Xlqc04qqO4D/GG1QWCyXxc9E34j4QMFcxXph7iQCKKBG8BfDVHqvSo/R0HjcZcVkeCLSjYh+d7 MJPAg/5OGBMxbxgNEp9GOTVdA+zSTGorNXkU3R7Zyzf1TvvQDRxb2oPWU9N4qdlEmyZ60FTaLnS Ovvc98rhESFq7ZX2zPhv54P+0HEudBAzI9YH7dp3P7gPcKbwnprm/BEaBBtkTWX8RHCidA15Lgs 7DUKgvAaycWmxnykimzN9NcgLOi4uvhXnByL7YMZn6iW9BaBu3BR0R4s1TJSQTCkup1jwhsu4dN wfow== X-Google-Smtp-Source: AGHT+IHw/moOQQdjQkyrnN2ABVgFGjJsARhjpZqCkhFnEqOLp4++U1HM/kmTdYY+jb+YZL8vgz1o9g== X-Received: by 2002:a05:600c:8b0d:b0:46e:2330:e959 with SMTP id 5b1f17b1804b1-46e2330ea71mr14864405e9.37.1758638730981; Tue, 23 Sep 2025 07:45:30 -0700 (PDT) Received: from biju.lan (host86-139-30-37.range86-139.btcentralplus.com. [86.139.30.37]) by smtp.gmail.com with ESMTPSA id 5b1f17b1804b1-464f0aac3fdsm238940435e9.1.2025.09.23.07.45.30 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Tue, 23 Sep 2025 07:45:30 -0700 (PDT) From: Biju X-Google-Original-From: Biju To: =?UTF-8?q?Uwe=20Kleine-K=C3=B6nig?= , Philipp Zabel Cc: Biju Das , linux-pwm@vger.kernel.org, linux-kernel@vger.kernel.org, Geert Uytterhoeven , Prabhakar Mahadev Lad , Biju Das , linux-renesas-soc@vger.kernel.org Subject: [PATCH v3 6/8] pwm: rzg2l-gpt: Add suspend/resume support Date: Tue, 23 Sep 2025 15:45:10 +0100 Message-ID: <20250923144524.191892-7-biju.das.jz@bp.renesas.com> X-Mailer: git-send-email 2.43.0 In-Reply-To: <20250923144524.191892-1-biju.das.jz@bp.renesas.com> References: <20250923144524.191892-1-biju.das.jz@bp.renesas.com> Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Content-Type: text/plain; charset="utf-8" From: Biju Das On RZ/G3E using PSCI, s2ram powers down the SoC. Add suspend/resume callbacks for save/restore GPT context. Signed-off-by: Biju Das --- v3: * New patch. --- drivers/pwm/pwm-rzg2l-gpt.c | 118 +++++++++++++++++++++++++++++++----- 1 file changed, 102 insertions(+), 16 deletions(-) diff --git a/drivers/pwm/pwm-rzg2l-gpt.c b/drivers/pwm/pwm-rzg2l-gpt.c index 087bc3c0778c..abf8dae52b91 100644 --- a/drivers/pwm/pwm-rzg2l-gpt.c +++ b/drivers/pwm/pwm-rzg2l-gpt.c @@ -101,14 +101,26 @@ struct rzg2l_gpt_info { u8 prescale_pow_of_two_mult_factor; }; =20 +struct rzg2l_gpt_cache { + u32 gtpr; + u32 gtccr[2]; + u32 gtcr; + u32 gtior; +}; + struct rzg2l_gpt_chip { void __iomem *mmio; struct mutex lock; /* lock to protect shared channel resources */ const struct rzg2l_gpt_info *info; + struct clk *clk; + struct clk *bus_clk; + struct reset_control *rst; + struct reset_control *rst_s; unsigned long rate_khz; u32 period_ticks[RZG2L_MAX_HW_CHANNELS]; u32 channel_request_count[RZG2L_MAX_HW_CHANNELS]; u32 channel_enable_count[RZG2L_MAX_HW_CHANNELS]; + struct rzg2l_gpt_cache hw_cache[RZG2L_MAX_HW_CHANNELS]; }; =20 /* This represents a hardware configuration for one channel */ @@ -465,10 +477,8 @@ static int rzg2l_gpt_probe(struct platform_device *pde= v) { struct rzg2l_gpt_chip *rzg2l_gpt; struct device *dev =3D &pdev->dev; - struct reset_control *rstc; struct pwm_chip *chip; unsigned long rate; - struct clk *clk; int ret; =20 chip =3D devm_pwmchip_alloc(dev, RZG2L_MAX_PWM_CHANNELS, sizeof(*rzg2l_gp= t)); @@ -482,27 +492,29 @@ static int rzg2l_gpt_probe(struct platform_device *pd= ev) =20 rzg2l_gpt->info =3D of_device_get_match_data(dev); =20 - rstc =3D devm_reset_control_get_exclusive_deasserted(dev, NULL); - if (IS_ERR(rstc)) - return dev_err_probe(dev, PTR_ERR(rstc), "Cannot deassert reset control\= n"); + rzg2l_gpt->rst =3D devm_reset_control_get_exclusive_deasserted(dev, NULL); + if (IS_ERR(rzg2l_gpt->rst)) + return dev_err_probe(dev, PTR_ERR(rzg2l_gpt->rst), + "Cannot deassert reset control\n"); =20 - rstc =3D devm_reset_control_get_optional_exclusive_deasserted(dev, "rst_s= "); - if (IS_ERR(rstc)) - return dev_err_probe(dev, PTR_ERR(rstc), "Cannot deassert rst_s reset\n"= ); + rzg2l_gpt->rst_s =3D devm_reset_control_get_optional_exclusive_deasserted= (dev, "rst_s"); + if (IS_ERR(rzg2l_gpt->rst_s)) + return dev_err_probe(dev, PTR_ERR(rzg2l_gpt->rst_s), + "Cannot deassert rst_s reset\n"); =20 - clk =3D devm_clk_get_optional_enabled(dev, "bus"); - if (IS_ERR(clk)) - return dev_err_probe(dev, PTR_ERR(clk), "Cannot get bus clock\n"); + rzg2l_gpt->bus_clk =3D devm_clk_get_optional_enabled(dev, "bus"); + if (IS_ERR(rzg2l_gpt->bus_clk)) + return dev_err_probe(dev, PTR_ERR(rzg2l_gpt->bus_clk), "Cannot get bus c= lock\n"); =20 - clk =3D devm_clk_get_enabled(dev, NULL); - if (IS_ERR(clk)) - return dev_err_probe(dev, PTR_ERR(clk), "Cannot get clock\n"); + rzg2l_gpt->clk =3D devm_clk_get_enabled(dev, NULL); + if (IS_ERR(rzg2l_gpt->clk)) + return dev_err_probe(dev, PTR_ERR(rzg2l_gpt->clk), "Cannot get clock\n"); =20 - ret =3D devm_clk_rate_exclusive_get(dev, clk); + ret =3D devm_clk_rate_exclusive_get(dev, rzg2l_gpt->clk); if (ret) return ret; =20 - rate =3D clk_get_rate(clk); + rate =3D clk_get_rate(rzg2l_gpt->clk); if (!rate) return dev_err_probe(dev, -EINVAL, "The gpt clk rate is 0"); =20 @@ -529,9 +541,80 @@ static int rzg2l_gpt_probe(struct platform_device *pde= v) if (ret) return dev_err_probe(dev, ret, "Failed to add PWM chip\n"); =20 + platform_set_drvdata(pdev, chip); + return 0; } =20 +static int rzg2l_gpt_suspend(struct device *dev) +{ + struct pwm_chip *chip =3D dev_get_drvdata(dev); + struct rzg2l_gpt_chip *rzg2l_gpt =3D to_rzg2l_gpt_chip(chip); + unsigned int i; + + for (i =3D 0; i < RZG2L_MAX_HW_CHANNELS; i++) { + if (!rzg2l_gpt->channel_enable_count[i]) + continue; + + rzg2l_gpt->hw_cache[i].gtpr =3D rzg2l_gpt_read(rzg2l_gpt, RZG2L_GTPR(i)); + rzg2l_gpt->hw_cache[i].gtccr[0] =3D rzg2l_gpt_read(rzg2l_gpt, RZG2L_GTCC= R(i, 0)); + rzg2l_gpt->hw_cache[i].gtccr[1] =3D rzg2l_gpt_read(rzg2l_gpt, RZG2L_GTCC= R(i, 1)); + rzg2l_gpt->hw_cache[i].gtcr =3D rzg2l_gpt_read(rzg2l_gpt, RZG2L_GTCR(i)); + rzg2l_gpt->hw_cache[i].gtior =3D rzg2l_gpt_read(rzg2l_gpt, RZG2L_GTIOR(i= )); + } + + clk_disable_unprepare(rzg2l_gpt->clk); + clk_disable_unprepare(rzg2l_gpt->bus_clk); + reset_control_assert(rzg2l_gpt->rst_s); + reset_control_assert(rzg2l_gpt->rst); + + return 0; +} + +static int rzg2l_gpt_resume(struct device *dev) +{ + struct pwm_chip *chip =3D dev_get_drvdata(dev); + struct rzg2l_gpt_chip *rzg2l_gpt =3D to_rzg2l_gpt_chip(chip); + unsigned int i; + int ret; + + ret =3D reset_control_deassert(rzg2l_gpt->rst); + if (ret) + return ret; + + ret =3D reset_control_deassert(rzg2l_gpt->rst_s); + if (ret) + goto fail_reset; + + ret =3D clk_prepare_enable(rzg2l_gpt->bus_clk); + if (ret) + goto fail_reset_all; + + ret =3D clk_prepare_enable(rzg2l_gpt->clk); + if (ret) + goto fail_bus_clk; + + for (i =3D 0; i < RZG2L_MAX_HW_CHANNELS; i++) { + if (!rzg2l_gpt->channel_enable_count[i]) + continue; + + rzg2l_gpt_write(rzg2l_gpt, RZG2L_GTPR(i), rzg2l_gpt->hw_cache[i].gtpr); + rzg2l_gpt_write(rzg2l_gpt, RZG2L_GTCCR(i, 0), rzg2l_gpt->hw_cache[i].gtc= cr[0]); + rzg2l_gpt_write(rzg2l_gpt, RZG2L_GTCCR(i, 1), rzg2l_gpt->hw_cache[i].gtc= cr[1]); + rzg2l_gpt_write(rzg2l_gpt, RZG2L_GTCR(i), rzg2l_gpt->hw_cache[i].gtcr); + rzg2l_gpt_write(rzg2l_gpt, RZG2L_GTIOR(i), rzg2l_gpt->hw_cache[i].gtior); + } + + return 0; +fail_bus_clk: + clk_disable_unprepare(rzg2l_gpt->bus_clk); +fail_reset_all: + reset_control_assert(rzg2l_gpt->rst_s); +fail_reset: + reset_control_assert(rzg2l_gpt->rst); + return ret; +} + static const struct rzg2l_gpt_info rzg3e_data =3D { .calculate_prescale =3D rzg3e_gpt_calculate_prescale, .gtcr_tpcs_mask =3D GENMASK(26, 23), @@ -551,10 +634,13 @@ static const struct of_device_id rzg2l_gpt_of_table[]= =3D { }; MODULE_DEVICE_TABLE(of, rzg2l_gpt_of_table); =20 +static DEFINE_SIMPLE_DEV_PM_OPS(rzg2l_gpt_pm_ops, rzg2l_gpt_suspend, rzg2l= _gpt_resume); + static struct platform_driver rzg2l_gpt_driver =3D { .driver =3D { .name =3D "pwm-rzg2l-gpt", .of_match_table =3D rzg2l_gpt_of_table, + .pm =3D pm_sleep_ptr(&rzg2l_gpt_pm_ops), }, .probe =3D rzg2l_gpt_probe, }; --=20 2.43.0 From nobody Thu Oct 2 02:15:13 2025 Received: from mail-wr1-f45.google.com (mail-wr1-f45.google.com [209.85.221.45]) (using TLSv1.2 with cipher ECDHE-RSA-AES128-GCM-SHA256 (128/128 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id ACD5A257AC6 for ; Tue, 23 Sep 2025 14:45:33 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=none smtp.client-ip=209.85.221.45 ARC-Seal: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1758638737; cv=none; b=aQkewxBihwE+ODr4Ii2PWcAIxWSaUCTeuxI/0clwM25ULlFNYf3JrvvWMrqtsgX+Qhoie91ez114YfDdJ3LB3lsFDFIgR2PA9hB4uqbqcwSocd5werpUc4+7pPGidc6A3RNgrTBhUCIwPoX0VzyQFmGUoBYUDuqN5MDhPqH7JUw= ARC-Message-Signature: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1758638737; c=relaxed/simple; bh=PC08gB/w+egRp5QGS5q1tZdtfmPuAMJz7z2nsCmwUpE=; h=From:To:Cc:Subject:Date:Message-ID:In-Reply-To:References: MIME-Version; b=IdboaPE89JJC5L9JHE5QizSROIfBSbAdmaF2GFU1HjzBqHasb8ciWxJ1KxqAVoOzl4G7qgbQTSpDhNeG1/swI5Rpxcd3C+wcrMX7wFbqezuGfaSZNPBulsI3hvLDRwCydevRDv2dBiKtmqwgLfxx6erOAROd7r1/V3/ozMdGo6g= ARC-Authentication-Results: i=1; smtp.subspace.kernel.org; dmarc=pass (p=none dis=none) header.from=gmail.com; spf=pass smtp.mailfrom=gmail.com; dkim=pass (2048-bit key) header.d=gmail.com header.i=@gmail.com header.b=W3oiPW/a; arc=none smtp.client-ip=209.85.221.45 Authentication-Results: smtp.subspace.kernel.org; dmarc=pass (p=none dis=none) header.from=gmail.com Authentication-Results: smtp.subspace.kernel.org; spf=pass smtp.mailfrom=gmail.com Authentication-Results: smtp.subspace.kernel.org; dkim=pass (2048-bit key) header.d=gmail.com header.i=@gmail.com header.b="W3oiPW/a" Received: by mail-wr1-f45.google.com with SMTP id ffacd0b85a97d-3ee155e0c08so3620814f8f.2 for ; Tue, 23 Sep 2025 07:45:33 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=gmail.com; s=20230601; t=1758638732; x=1759243532; darn=vger.kernel.org; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:from:to:cc:subject:date :message-id:reply-to; bh=G80ItpmxJpnUoRL/kfIZ5sW+AOj0ITPN400GcF79LCE=; b=W3oiPW/aNZXRC58A1Awz7/eORgFUQuDw0pu0ykMOp6TK0ItOs0+bB3wBIFLbxw2kTv YovNxUXvltX1ca7PEC7D2P+cYWrLv/QALAWbTCw4wL4av4yQdPnV6qSKf2X4CrzPNr9l 8Ez7kF3IYIneb3JL/hUiyITr5j7Q7oLxCplZVPVFtTIs6xiYJw79PJY4XvoVz0m6+iZp cTwl6bjcNL4YIzxN5GJXcjqoVw/DY+R+fzAXblBb8eM1GZLS+i0ZNwyiDDo7yKJ0RVOX suDDDcD2LDG/gyK73Fzg3K84a9CQV8x4HtYK/Aqz3pBzbHYCkqQk7uYMdKZJ9oVGXHK9 IVhw== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20230601; t=1758638732; x=1759243532; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:x-gm-message-state:from:to:cc :subject:date:message-id:reply-to; bh=G80ItpmxJpnUoRL/kfIZ5sW+AOj0ITPN400GcF79LCE=; b=jEiY1YZm7D0BUMThSfuS91jui7AxfCW8YRHyUOpj0UuFjb0zE/84Bp3DbvWR9WIeMq 7QopYaVfNuwXinZo4k/4O2v+T0DQgquwOSA4ShzQzqK2qE3njz2WS9e1n4Ab7VOLiRHw Qqcvghy8LpJ8eOyFIWJT61WMlsr3rerrmxHL8OfKcf7QX2wsW9d71xhz5AFrlg19H+vF YsuauD4naibCu5EsadTsxfOzCHNtBqsa9FpemMv9ANHRuS4n05yspDWT8CWtdNEPIf4W +/Mij4dlNFAlcDgC1kaPuulrYSyKxdW5/dK9H00U8m3e8LblssFmazBnLUg5sCyXpfxS 98Tw== X-Forwarded-Encrypted: i=1; AJvYcCVCvKRe/HdfaZ9w/8Yqm1NI1hTPviCeSII8UqKogthBsv9oHGa7uTPD6YACx5RzsSs7XDzc6om6oMZNcuI=@vger.kernel.org X-Gm-Message-State: AOJu0YzmCvs+AOdyYLc0etk5Zy1GuOetdiQbEDUccp4pYJascDf+RNKu eMEl14GppLzWvCxrJHdQeVoUjflkQgs7aXbqJKwVAqbR8z07dILQSm4P X-Gm-Gg: ASbGncttHHIhfrlpit9clrpQHwocp8IIC8N+E0Mq3M/eV7UD06g1nie5hyxLy3JyPZJ 0MSualoBTM7+WgryQ8nwdxAm4WrX9HZ7b9cV6qb3o/dvnj+wM9ikXE1t8LE9Q49kZ827MbLE12r 5sVBwv2USXx5OI2zaY2snjCfqw28YV88czNRbxGhmhFbWxMwwZECZGLjJhd57OX1PFkqymsYzNt Idor98jUDXYLAWONjh4H4lu6SMYO+YvQ134c8xkxRNYlPxfuodAeLBbLO2+btgJZ59wmxUTD+hL r1C1Zl2sWzFNt/eZr7cRXl0jD2wlq26FhhhGPvNScaLcuOihacalVvTwIH9aXUe54NOsqSvI/0D z9afIdSnIvWNhrLH3z7ZyVsGhLL5uxMN5GdLcxGdDxL197gJNl6h7w4TyAcwkr1sF/1yGeZccCY XuXQ== X-Google-Smtp-Source: AGHT+IGYJqg3g59q+kGLJJp06XQ1vqNuniExnf+RSDw2EEI792G/PGnzGmPNDfsYQ83ycJ6V10rFpA== X-Received: by 2002:a05:6000:2907:b0:3f4:a9f5:c10e with SMTP id ffacd0b85a97d-405c9352242mr2984554f8f.36.1758638731818; Tue, 23 Sep 2025 07:45:31 -0700 (PDT) Received: from biju.lan (host86-139-30-37.range86-139.btcentralplus.com. [86.139.30.37]) by smtp.gmail.com with ESMTPSA id 5b1f17b1804b1-464f0aac3fdsm238940435e9.1.2025.09.23.07.45.31 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Tue, 23 Sep 2025 07:45:31 -0700 (PDT) From: Biju X-Google-Original-From: Biju To: Geert Uytterhoeven , Magnus Damm , Rob Herring , Krzysztof Kozlowski , Conor Dooley Cc: Biju Das , linux-renesas-soc@vger.kernel.org, devicetree@vger.kernel.org, linux-kernel@vger.kernel.org, Prabhakar Mahadev Lad , Biju Das Subject: [PATCH v3 7/8] arm64: dts: renesas: r9a09g047: Add GPT nodes Date: Tue, 23 Sep 2025 15:45:11 +0100 Message-ID: <20250923144524.191892-8-biju.das.jz@bp.renesas.com> X-Mailer: git-send-email 2.43.0 In-Reply-To: <20250923144524.191892-1-biju.das.jz@bp.renesas.com> References: <20250923144524.191892-1-biju.das.jz@bp.renesas.com> Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Content-Type: text/plain; charset="utf-8" From: Biju Das The RZ/G3E SoC has 2 GPT's. Add GPT nodes to RZ/G3E ("R9A09G047") SoC DTSI. Signed-off-by: Biju Das --- v2->v3: * No change. v1->v2: * No change. --- arch/arm64/boot/dts/renesas/r9a09g047.dtsi | 184 +++++++++++++++++++++ 1 file changed, 184 insertions(+) diff --git a/arch/arm64/boot/dts/renesas/r9a09g047.dtsi b/arch/arm64/boot/d= ts/renesas/r9a09g047.dtsi index 47d843c79021..73331874b57c 100644 --- a/arch/arm64/boot/dts/renesas/r9a09g047.dtsi +++ b/arch/arm64/boot/dts/renesas/r9a09g047.dtsi @@ -587,6 +587,190 @@ channel5 { }; }; =20 + gpt0: pwm@13010000 { + compatible =3D "renesas,r9a09g047-gpt"; + reg =3D <0 0x13010000 0 0x10000>; + #pwm-cells =3D <3>; + interrupts =3D , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + ; + interrupt-names =3D "gtcia0", "gtcib0", "gtcic0", "gtcid0", + "gtcie0", "gtcif0", "gtcih0", "gtcil0", + "gtcia1", "gtcib1", "gtcic1", "gtcid1", + "gtcie1", "gtcif1", "gtcih1", "gtcil1", + "gtcia2", "gtcib2", "gtcic2", "gtcid2", + "gtcie2", "gtcif2", "gtcih2", "gtcil2", + "gtcia3", "gtcib3", "gtcic3", "gtcid3", + "gtcie3", "gtcif3", "gtcih3", "gtcil3", + "gtcia4", "gtcib4", "gtcic4", "gtcid4", + "gtcie4", "gtcif4", "gtcih4", "gtcil4", + "gtcia5", "gtcib5", "gtcic5", "gtcid5", + "gtcie5", "gtcif5", "gtcih5", "gtcil5", + "gtcia6", "gtcib6", "gtcic6", "gtcid6", + "gtcie6", "gtcif6", "gtcih6", "gtcil6", + "gtcia7", "gtcib7", "gtcic7", "gtcid7", + "gtcie7", "gtcif7", "gtcih7", "gtcil7"; + clocks =3D <&cpg CPG_MOD 0x31>, <&cpg CPG_MOD 0x31>; + clock-names =3D "core", "bus"; + resets =3D <&cpg 0x59>, <&cpg 0x5a>; + reset-names =3D "rst_p", "rst_s"; + power-domains =3D <&cpg>; + status =3D "disabled"; + }; + + gpt1: pwm@13020000 { + compatible =3D "renesas,r9a09g047-gpt"; + reg =3D <0 0x13020000 0 0x10000>; + #pwm-cells =3D <3>; + interrupts =3D , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + ; + interrupt-names =3D "gtcia0", "gtcib0", "gtcic0", "gtcid0", + "gtcie0", "gtcif0", "gtcih0", "gtcil0", + "gtcia1", "gtcib1", "gtcic1", "gtcid1", + "gtcie1", "gtcif1", "gtcih1", "gtcil1", + "gtcia2", "gtcib2", "gtcic2", "gtcid2", + "gtcie2", "gtcif2", "gtcih2", "gtcil2", + "gtcia3", "gtcib3", "gtcic3", "gtcid3", + "gtcie3", "gtcif3", "gtcih3", "gtcil3", + "gtcia4", "gtcib4", "gtcic4", "gtcid4", + "gtcie4", "gtcif4", "gtcih4", "gtcil4", + "gtcia5", "gtcib5", "gtcic5", "gtcid5", + "gtcie5", "gtcif5", "gtcih5", "gtcil5", + "gtcia6", "gtcib6", "gtcic6", "gtcid6", + "gtcie6", "gtcif6", "gtcih6", "gtcil6", + "gtcia7", "gtcib7", "gtcic7", "gtcid7", + "gtcie7", "gtcif7", "gtcih7", "gtcil7"; + clocks =3D <&cpg CPG_MOD 0x32>, <&cpg CPG_MOD 0x32>; + clock-names =3D "core", "bus"; + resets =3D <&cpg 0x5b>, <&cpg 0x5c>; + reset-names =3D "rst_p", "rst_s"; + power-domains =3D <&cpg>; + status =3D "disabled"; + }; + wdt1: watchdog@14400000 { compatible =3D "renesas,r9a09g047-wdt", "renesas,r9a09g057-wdt"; reg =3D <0 0x14400000 0 0x400>; --=20 2.43.0 From nobody Thu Oct 2 02:15:13 2025 Received: from mail-wr1-f54.google.com (mail-wr1-f54.google.com [209.85.221.54]) (using TLSv1.2 with cipher ECDHE-RSA-AES128-GCM-SHA256 (128/128 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id EB7D22475CF for ; Tue, 23 Sep 2025 14:45:34 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=none smtp.client-ip=209.85.221.54 ARC-Seal: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1758638737; cv=none; b=QQvajm02+fATjDrdM948e0kekhZPD2bL3Klwx7Hzr4qayKTxzC59lOGu0ZaXLotjRG1X4GuR0SkORkR0iWgWX//CVlhVUd0uP58a1B6N9c3bborEbvMjX4fsJvdHrZB96CX8i3wZtUeuHJyMXKexso6zQn4F7fYFuaQrcH2WrIo= ARC-Message-Signature: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1758638737; c=relaxed/simple; bh=FG2G0j9yMRpJsyLnTSTOBI0IBmgFvNkuE6tgk8O+uWE=; h=From:To:Cc:Subject:Date:Message-ID:In-Reply-To:References: MIME-Version; b=j7eJrUqVT1lR26X6xWHOCmRDnM+ynRgTl0DF6WVOqajCVkpCAqHS2UZjAaXYz+Wut3NDT/mnyLo0s7Xzjj/RJheWFlasIKhAHmE6xJG05YQFd0SJHsF8LdfKDVlvdGdhyfhRqnr35I/osXGaECZO+pq8edyiGWFsh26ZFsRJsuA= ARC-Authentication-Results: i=1; smtp.subspace.kernel.org; dmarc=pass (p=none dis=none) header.from=gmail.com; spf=pass smtp.mailfrom=gmail.com; dkim=pass (2048-bit key) header.d=gmail.com header.i=@gmail.com header.b=BGCVa6X7; arc=none smtp.client-ip=209.85.221.54 Authentication-Results: smtp.subspace.kernel.org; dmarc=pass (p=none dis=none) header.from=gmail.com Authentication-Results: smtp.subspace.kernel.org; spf=pass smtp.mailfrom=gmail.com Authentication-Results: smtp.subspace.kernel.org; dkim=pass (2048-bit key) header.d=gmail.com header.i=@gmail.com header.b="BGCVa6X7" Received: by mail-wr1-f54.google.com with SMTP id ffacd0b85a97d-3f1153f4254so1918720f8f.1 for ; Tue, 23 Sep 2025 07:45:34 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=gmail.com; s=20230601; t=1758638733; x=1759243533; darn=vger.kernel.org; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:from:to:cc:subject:date :message-id:reply-to; bh=0aOwKfNY2vdwS6wqcAavDYBOG0gp/iK+khNJ/Lz+BCQ=; b=BGCVa6X7qYc5ZVPjdJ3B/ZlE+Y5CFL6hP4EGD26AO7z8Sjv+ag326z+/eSb15GjuxJ T88/FVxlveVrpL/ZFzi08J6byiqFTLDOziaxX/9Bo095kHLTw9M9/WVtq4kNyseVHujh e435GzOc9P7vGsVK3GPyycfnUBoBpkr/EwByuHgwuSCwvjC5iUmL1N0r3XK4y3EXIGcd h76+pnM3nGpFv4t0izaKmIbg2OMTjJ3LPfafQJl9eID+AJzwQKVMQT2dyj4XE5xkU/Gi n1y4LoZ4fQ1xsSKeWDbX+YmPAN7mUZ0MvgaoLepsfz0seXKdPvgQigDvgfAnyXcnUbzt Snxg== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20230601; t=1758638733; x=1759243533; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:x-gm-message-state:from:to:cc :subject:date:message-id:reply-to; bh=0aOwKfNY2vdwS6wqcAavDYBOG0gp/iK+khNJ/Lz+BCQ=; b=khS2lnIqfm9kgKo5V3TmjrJ3zIpMvBC8qgQRqZgyhJcF02fw16qqucYKBC3y2jEMCd ZlcjOxP4HgFStL2OzTO67+rot7o3UGyyCTDh8TLjNuZDy+Nt+HfTBUHzRvsNvkrqccf4 NaNLdGdNl4s3QCJ/KLSY83diHTMzEDkpYan19z5TNufeUwowfRnOixxeTIm8KQhFHKnK y5nsjnYpSLQXMxO2FliE3JfspHqylpaEIP1wywOjp72/WgChGwOZFqLmzjskAhtuC5Lh EcMEWZcHKePf4geKoBAnv/9XIx+T0gDK6FFIwCGw+Q8cFDghqZhv7l23XKqC47EZMewF exjw== X-Forwarded-Encrypted: i=1; AJvYcCWJPLQfs12QSpN7IRjt15VCzGvttDhDFUPMC0/ldRr3/k2qZeIwaNsUNeKLNvBBJemHiOi1UPOil8u4u+U=@vger.kernel.org X-Gm-Message-State: AOJu0YyhhCL4aryGcS4ElWZjmSTawNhC93HUdJMenTjtYU74ZwKOzGGN L4gR44QJ3VNayyrYqJhUYT+D/SgIHwUVpOqUdfakcnnyKqtmRh0QEbiW X-Gm-Gg: ASbGncuzJSkj6T+c0InFg+DCGbjNa4tr33geTdJdF1D9Ef+2KqWA9YNOZcOh8+cwENc EnEMGhirKrzIeBIqwVioVkyVoE8B7zOz9biILBctyjJew7rmrgfBy756ah5CuH0cbn9M+9i40w9 PNJ3VWmeSPKUb2ZK3WRAfTu6f+HYU90UGp6rMuuOqI/XLIJ6rIiN9UDR32k74JYu4i3v87VlV5Y hReK9unc5dnxObqpQ8wWFVyzdtkvOJnmKUm1g0eG9m/L9+mY22NHWVnsWs49iWMTpFqQFMnWm1p pJjzjza/cKIfaJF+djslVx42/UoZpD1P3q27v/B65W4se4+0LaV4zJL6vRo4ziyCJ/S9rrU7xyf jdzZQ438JSC84GOMllQMeYleYs4adlxZcAkiqJO38eHCd8RWVcX0O0kt5is2splj3/vgFjKUX2P jujA== X-Google-Smtp-Source: AGHT+IHY05P7YPOHKEC6gk74dg40jQ6ah53p1VKJbL2X1DkEDEeClFCRPiP0QIJXrv+8WCuJmAyFYQ== X-Received: by 2002:a05:6000:1ace:b0:3eb:f3de:1a87 with SMTP id ffacd0b85a97d-405cc70fa43mr3239608f8f.56.1758638732654; Tue, 23 Sep 2025 07:45:32 -0700 (PDT) Received: from biju.lan (host86-139-30-37.range86-139.btcentralplus.com. [86.139.30.37]) by smtp.gmail.com with ESMTPSA id 5b1f17b1804b1-464f0aac3fdsm238940435e9.1.2025.09.23.07.45.31 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Tue, 23 Sep 2025 07:45:32 -0700 (PDT) From: Biju X-Google-Original-From: Biju To: Geert Uytterhoeven , Magnus Damm , Rob Herring , Krzysztof Kozlowski , Conor Dooley Cc: Biju Das , linux-renesas-soc@vger.kernel.org, devicetree@vger.kernel.org, linux-kernel@vger.kernel.org, Prabhakar Mahadev Lad , Biju Das , Tommaso Merciai Subject: [PATCH v3 8/8] arm64: dts: renesas: r9a09g047e57-smarc: Enable GPT on carrier board Date: Tue, 23 Sep 2025 15:45:12 +0100 Message-ID: <20250923144524.191892-9-biju.das.jz@bp.renesas.com> X-Mailer: git-send-email 2.43.0 In-Reply-To: <20250923144524.191892-1-biju.das.jz@bp.renesas.com> References: <20250923144524.191892-1-biju.das.jz@bp.renesas.com> Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Content-Type: text/plain; charset="utf-8" From: Biju Das The GTIOC4{A,B} IOs are available on the carrier board's PMOD1_6A connector. Enable the GPT on the carrier board by adding the GPT pinmux and node on the carrier board dtsi file. Reviewed-by: Tommaso Merciai Signed-off-by: Biju Das --- v2->v3: * No change. v1->v2: * Collected tags. --- arch/arm64/boot/dts/renesas/r9a09g047e57-smarc.dts | 13 +++++++++++++ 1 file changed, 13 insertions(+) diff --git a/arch/arm64/boot/dts/renesas/r9a09g047e57-smarc.dts b/arch/arm6= 4/boot/dts/renesas/r9a09g047e57-smarc.dts index 08e814c03fa8..86df67e9230d 100644 --- a/arch/arm64/boot/dts/renesas/r9a09g047e57-smarc.dts +++ b/arch/arm64/boot/dts/renesas/r9a09g047e57-smarc.dts @@ -84,6 +84,14 @@ &can_transceiver1 { }; #endif =20 +#if (!SW_LCD_EN) && (!SW_GPIO8_CAN0_STB) +&gpt0 { + pinctrl-0 =3D <&gpt0_pins>; + pinctrl-names =3D "default"; + status =3D "okay"; +}; +#endif + &i2c0 { pinctrl-0 =3D <&i2c0_pins>; pinctrl-names =3D "default"; @@ -125,6 +133,11 @@ can4_pins: can4 { }; }; =20 + gpt0_pins: gpt0 { + pinmux =3D , /* GTIOC4A */ + ; /* GTIOC4B */ + }; + i2c0_pins: i2c0 { pinmux =3D , /* SCL0 */ ; /* SDA0 */ --=20 2.43.0