From nobody Thu Oct 2 04:45:14 2025 Received: from smtp.kernel.org (aws-us-west-2-korg-mail-1.web.codeaurora.org [10.30.226.201]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id 8CF5525A357; Tue, 23 Sep 2025 14:02:53 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=none smtp.client-ip=10.30.226.201 ARC-Seal: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1758636173; cv=none; b=JyNIMoEm+jU0go1iwKkZjsZ537rfCpQyUBchXTrhoDHzG419RYCyqnBiMPBvG9s9O8mKXT5qtZFLWplpDnMt3ns+BbkbfAGeLTED9N+BM/Z2RUsrhZt0rhzSZ/s+1yR2H9xqGhC5yiBOl3uM3h6+DAZk3wEb8ssgjrRCNFiRYMg= ARC-Message-Signature: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1758636173; c=relaxed/simple; bh=Qg34C9exkp2NB8HBKF6gQRoaPUtMAb5daqSaeZ5VcOE=; h=From:To:Cc:Subject:Date:Message-ID:In-Reply-To:References: MIME-Version; b=s6r3vhW6ZbBw0Kk+CDuTSXIWSVMjCxT6Kgl64pqUVqug3K7LpPV7zzFDM67gUN/QyinONtSqEOIj9955opwH+CXgXcqJXo3RQWqxKWThSb2iJ3j9vl3Io/oLPiTAOqQgrfc1NKqPPXk9HehswBKySDPl9V2Hg+U6M6ZMU5qI7J8= ARC-Authentication-Results: i=1; smtp.subspace.kernel.org; dkim=pass (2048-bit key) header.d=kernel.org header.i=@kernel.org header.b=rUp0aMdO; arc=none smtp.client-ip=10.30.226.201 Authentication-Results: smtp.subspace.kernel.org; dkim=pass (2048-bit key) header.d=kernel.org header.i=@kernel.org header.b="rUp0aMdO" Received: by smtp.kernel.org (Postfix) with ESMTPSA id BDB2DC19423; Tue, 23 Sep 2025 14:02:52 +0000 (UTC) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=kernel.org; s=k20201202; t=1758636172; bh=Qg34C9exkp2NB8HBKF6gQRoaPUtMAb5daqSaeZ5VcOE=; h=From:To:Cc:Subject:Date:In-Reply-To:References:From; b=rUp0aMdO5ZtjRnqrzLLuX8BbdqZ+4uxgtW6rUXzh7F5DBC2rNEc23n8NM7BBRfEPY 3gpkUuh4eD2ptjdd26nk7U/r/5JuikR3D6gHHeQ3RamrOLtQlJfwSN44tWkPzM/2D1 mNhNCrVt8zPLR/qaoPBhd+JZ25zPjqamL1qaH7b+YrFi4nc10BgnrE3vneIAvvU/El kGrAoWZDbv9H5NOe08sexZnoWw1cgC1A/Uv5JbqoK0y4TI9YziSUlaC9zfC3L5oYUZ po3V4AgAaq9+aDwy+0V84jRVo3snDhnVpJi1Hv6Wi4gG2QOAARoxY+JAFrqfgOKQb2 vj2j8SxtbHXZQ== Received: by wens.tw (Postfix, from userid 1000) id 50B67606B2; Tue, 23 Sep 2025 22:02:48 +0800 (CST) From: Chen-Yu Tsai To: Andrew Lunn , "David S. Miller" , Eric Dumazet , Jakub Kicinski , Paolo Abeni , Rob Herring , Krzysztof Kozlowski , Conor Dooley , Chen-Yu Tsai , Jernej Skrabec , Samuel Holland Cc: netdev@vger.kernel.org, devicetree@vger.kernel.org, linux-arm-kernel@lists.infradead.org, linux-sunxi@lists.linux.dev, linux-kernel@vger.kernel.org, Andre Przywara , Jernej Skrabec , Andrew Lunn Subject: [PATCH net-next v7 6/6] arm64: dts: allwinner: t527: orangepi-4a: Enable Ethernet port Date: Tue, 23 Sep 2025 22:02:46 +0800 Message-ID: <20250923140247.2622602-7-wens@kernel.org> X-Mailer: git-send-email 2.47.3 In-Reply-To: <20250923140247.2622602-1-wens@kernel.org> References: <20250923140247.2622602-1-wens@kernel.org> Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Content-Type: text/plain; charset="utf-8" From: Chen-Yu Tsai On the Orangepi 4A board, the second Ethernet controller, aka the GMAC200, is connected to an external Motorcomm YT8531 PHY. The PHY uses an external 25MHz crystal, has the SoC's PI15 pin connected to its reset pin, and the PI16 pin for its interrupt pin. Enable it. Acked-by: Jernej Skrabec Reviewed-by: Andrew Lunn Signed-off-by: Chen-Yu Tsai --- Changes since v1: - Switch to generic (tx|rx)-internal-delay-ps properties --- .../dts/allwinner/sun55i-t527-orangepi-4a.dts | 23 +++++++++++++++++++ 1 file changed, 23 insertions(+) diff --git a/arch/arm64/boot/dts/allwinner/sun55i-t527-orangepi-4a.dts b/ar= ch/arm64/boot/dts/allwinner/sun55i-t527-orangepi-4a.dts index 39a4e194712a..9e6b21cf293e 100644 --- a/arch/arm64/boot/dts/allwinner/sun55i-t527-orangepi-4a.dts +++ b/arch/arm64/boot/dts/allwinner/sun55i-t527-orangepi-4a.dts @@ -15,6 +15,7 @@ / { compatible =3D "xunlong,orangepi-4a", "allwinner,sun55i-t527"; =20 aliases { + ethernet0 =3D &gmac1; serial0 =3D &uart0; }; =20 @@ -102,11 +103,33 @@ &ehci1 { status =3D "okay"; }; =20 +&gmac1 { + phy-mode =3D "rgmii-id"; + phy-handle =3D <&ext_rgmii_phy>; + phy-supply =3D <®_cldo4>; + + tx-internal-delay-ps =3D <0>; + rx-internal-delay-ps =3D <300>; + + status =3D "okay"; +}; + &gpu { mali-supply =3D <®_dcdc2>; status =3D "okay"; }; =20 +&mdio1 { + ext_rgmii_phy: ethernet-phy@1 { + compatible =3D "ethernet-phy-ieee802.3-c22"; + reg =3D <1>; + interrupts-extended =3D <&pio 8 16 IRQ_TYPE_LEVEL_LOW>; /* PI16 */ + reset-gpios =3D <&pio 8 15 GPIO_ACTIVE_LOW>; /* PI15 */ + reset-assert-us =3D <10000>; + reset-deassert-us =3D <150000>; + }; +}; + &mmc0 { vmmc-supply =3D <®_cldo3>; cd-gpios =3D <&pio 5 6 (GPIO_ACTIVE_LOW | GPIO_PULL_UP)>; /* PF6 */ --=20 2.47.3