From nobody Thu Oct 2 04:45:13 2025 Received: from smtp.kernel.org (aws-us-west-2-korg-mail-1.web.codeaurora.org [10.30.226.201]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id 374D0257842; Tue, 23 Sep 2025 14:02:52 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=none smtp.client-ip=10.30.226.201 ARC-Seal: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1758636173; cv=none; b=cettYbwdzv07tD2/cxAQOA++AozKLTq7UUAU+h3J5yLm9xOAF76kMxPw80rSd11iFM+rrHx54Ft7yRiNliZkqqIYgMWqGPbulD/aQATWjLNkN70uDYamDCCCOYZF7cOybYQMb+hTtqGQP0B80aC8H272ZxdqANpKYvG4N37w6zk= ARC-Message-Signature: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1758636173; c=relaxed/simple; bh=LaxIY3ciZrjZcZx8L7T/CqcZbDAJyhjiMK8HyefyTF0=; h=From:To:Cc:Subject:Date:Message-ID:In-Reply-To:References: MIME-Version; b=fq3jyIWgSKBmoLbb8P2oSlRa+lC1vj6nOrqrBqQdWoIEIu67iM/xlWms1dRPpeq8iAncjK/zxI+A1vrsekLdax6j8WS1B+unfuyXwQZKZL5MWhxQo4HogXIwr3Y/ds/LgXeUc6BbzHiPfDiY1ZxL50ruivNZSfJVqSz/igVI/KQ= ARC-Authentication-Results: i=1; smtp.subspace.kernel.org; dkim=pass (2048-bit key) header.d=kernel.org header.i=@kernel.org header.b=m09qMalz; arc=none smtp.client-ip=10.30.226.201 Authentication-Results: smtp.subspace.kernel.org; dkim=pass (2048-bit key) header.d=kernel.org header.i=@kernel.org header.b="m09qMalz" Received: by smtp.kernel.org (Postfix) with ESMTPSA id 85B7CC4CEF5; Tue, 23 Sep 2025 14:02:52 +0000 (UTC) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=kernel.org; s=k20201202; t=1758636172; bh=LaxIY3ciZrjZcZx8L7T/CqcZbDAJyhjiMK8HyefyTF0=; h=From:To:Cc:Subject:Date:In-Reply-To:References:From; b=m09qMalzdD2Zj7aMf1Af09yE2jRKQGYEElE5T1T2tm7fH4TXFayKpTAwsW3SvF4XA VUl3Bnmi8e4QnLtL15n56Kg6pnyoLp26Tiw8TuwmEk1aOdpAVnh8COitXJuI94XYRy cfnhHKuFCZXi3OkBLzzTJ4eXlS1Fbyl8BkCey70jVddTJnggEmR1DZ86Qkek3Qkgc7 ++t2zI8r0VPKwL2DAV8mDcrPa/qMIjINQgAMxsivLamdQxLVbaBDTML1dGaW5bUvAy Q5aY56thK0wFcCCJclQbVCd4FqOfsWNAIZ3glvSwKQ5sdqouNXjXWJyGtjubk4zYnf egMBoCfyNFhVQ== Received: by wens.tw (Postfix, from userid 1000) id 44002606B1; Tue, 23 Sep 2025 22:02:48 +0800 (CST) From: Chen-Yu Tsai To: Andrew Lunn , "David S. Miller" , Eric Dumazet , Jakub Kicinski , Paolo Abeni , Rob Herring , Krzysztof Kozlowski , Conor Dooley , Chen-Yu Tsai , Jernej Skrabec , Samuel Holland Cc: netdev@vger.kernel.org, devicetree@vger.kernel.org, linux-arm-kernel@lists.infradead.org, linux-sunxi@lists.linux.dev, linux-kernel@vger.kernel.org, Andre Przywara , Jernej Skrabec , Andrew Lunn Subject: [PATCH net-next v7 5/6] arm64: dts: allwinner: t527: avaota-a1: enable second Ethernet port Date: Tue, 23 Sep 2025 22:02:45 +0800 Message-ID: <20250923140247.2622602-6-wens@kernel.org> X-Mailer: git-send-email 2.47.3 In-Reply-To: <20250923140247.2622602-1-wens@kernel.org> References: <20250923140247.2622602-1-wens@kernel.org> Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Content-Type: text/plain; charset="utf-8" From: Chen-Yu Tsai On the Avaota A1 board, the second Ethernet controller, aka the GMAC200, is connected to a second external RTL8211F-CG PHY. The PHY uses an external 25MHz crystal, and has the SoC's PJ16 pin connected to its reset pin. Enable the second Ethernet port. Also fix up the label for the existing external PHY connected to the first Ethernet port. Acked-by: Jernej Skrabec Reviewed-by: Andrew Lunn Signed-off-by: Chen-Yu Tsai --- Changes since v1: - Switch to generic (tx|rx)-internal-delay-ps properties --- .../dts/allwinner/sun55i-t527-avaota-a1.dts | 26 +++++++++++++++++-- 1 file changed, 24 insertions(+), 2 deletions(-) diff --git a/arch/arm64/boot/dts/allwinner/sun55i-t527-avaota-a1.dts b/arch= /arm64/boot/dts/allwinner/sun55i-t527-avaota-a1.dts index 1b054fa8ef74..054d0357c139 100644 --- a/arch/arm64/boot/dts/allwinner/sun55i-t527-avaota-a1.dts +++ b/arch/arm64/boot/dts/allwinner/sun55i-t527-avaota-a1.dts @@ -13,6 +13,7 @@ / { =20 aliases { ethernet0 =3D &gmac0; + ethernet1 =3D &gmac1; serial0 =3D &uart0; }; =20 @@ -73,7 +74,7 @@ &ehci1 { =20 &gmac0 { phy-mode =3D "rgmii-id"; - phy-handle =3D <&ext_rgmii_phy>; + phy-handle =3D <&ext_rgmii0_phy>; phy-supply =3D <®_dcdc4>; =20 allwinner,tx-delay-ps =3D <100>; @@ -82,13 +83,24 @@ &gmac0 { status =3D "okay"; }; =20 +&gmac1 { + phy-mode =3D "rgmii-id"; + phy-handle =3D <&ext_rgmii1_phy>; + phy-supply =3D <®_dcdc4>; + + tx-internal-delay-ps =3D <100>; + rx-internal-delay-ps =3D <100>; + + status =3D "okay"; +}; + &gpu { mali-supply =3D <®_dcdc2>; status =3D "okay"; }; =20 &mdio0 { - ext_rgmii_phy: ethernet-phy@1 { + ext_rgmii0_phy: ethernet-phy@1 { compatible =3D "ethernet-phy-ieee802.3-c22"; reg =3D <1>; reset-gpios =3D <&pio 7 8 GPIO_ACTIVE_LOW>; /* PH8 */ @@ -97,6 +109,16 @@ ext_rgmii_phy: ethernet-phy@1 { }; }; =20 +&mdio1 { + ext_rgmii1_phy: ethernet-phy@1 { + compatible =3D "ethernet-phy-ieee802.3-c22"; + reg =3D <1>; + reset-gpios =3D <&pio 9 16 GPIO_ACTIVE_LOW>; /* PJ16 */ + reset-assert-us =3D <10000>; + reset-deassert-us =3D <150000>; + }; +}; + &mmc0 { vmmc-supply =3D <®_cldo3>; cd-gpios =3D <&pio 5 6 (GPIO_ACTIVE_LOW | GPIO_PULL_UP)>; /* PF6 */ --=20 2.47.3