From nobody Thu Oct 2 04:45:14 2025 Received: from smtp.kernel.org (aws-us-west-2-korg-mail-1.web.codeaurora.org [10.30.226.201]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id D4C102C18A; Tue, 23 Sep 2025 14:02:50 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=none smtp.client-ip=10.30.226.201 ARC-Seal: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1758636170; cv=none; b=gGG0ni/XT2lLEP8UdRpURVR9yln+uyKvv7ja7kkZeuS71HJr9dk5EQvSloN8s+TQNub8QGNgyHS/jUdutsiIudv+OMu+QNRWBOwwjn/Xalg4u2OBEO3QmgNjSIa7lbUQwk3+u/N14gF792OxqmPG4DEZLQ/dVUV93WMstz4Xv2I= ARC-Message-Signature: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1758636170; c=relaxed/simple; bh=rx7cTQhbHRFL+3YWoqnP53MCOR0zwAA48Z7BXBg9pb8=; h=From:To:Cc:Subject:Date:Message-ID:In-Reply-To:References: MIME-Version; b=WYw06d1LQvsBXCNYf0dMt75mWkhdjooiMHaijScQtaK898mqEZwc+s+Sajb0YjzCOJ1unJNygTgOAa7/xzmkcYG42yV9IIIR5xPuGOp5/oXW897lB4ReR4q4tIC+IatZS8TQqERqUJ2f9bZLGifZM1g5CGnCE1NHefi1GaJRcpw= ARC-Authentication-Results: i=1; smtp.subspace.kernel.org; dkim=pass (2048-bit key) header.d=kernel.org header.i=@kernel.org header.b=Cjh9lXJi; arc=none smtp.client-ip=10.30.226.201 Authentication-Results: smtp.subspace.kernel.org; dkim=pass (2048-bit key) header.d=kernel.org header.i=@kernel.org header.b="Cjh9lXJi" Received: by smtp.kernel.org (Postfix) with ESMTPSA id 5DD4DC4AF09; Tue, 23 Sep 2025 14:02:50 +0000 (UTC) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=kernel.org; s=k20201202; t=1758636170; bh=rx7cTQhbHRFL+3YWoqnP53MCOR0zwAA48Z7BXBg9pb8=; h=From:To:Cc:Subject:Date:In-Reply-To:References:From; b=Cjh9lXJinGubymHzTR8iqkFWHo4/T+IVyPeOOJTqk5xNF0ysF0BFzz5ZP6X33I6iU kjmFzhh9y0LP49AaQBa2TRdJrcu3gjyAsZLWMCCvuAlxdiJjlKbo4oqteslU5Jbv87 6iGmWxUmXiG6Rd4NU56EbrhPsOmiffgbU/AKhn8iaxfGJhaa7CbFNqci2nUutt0DZP sAP7ZkImbREwAF5fu1W8oQB1juq9445HPePL88N+R+4Yu2hABq0Gl+460ssA+0wrX1 AYxVt63e7BKzqhLdN1sQ88s5SfUQkW01kkqBI1DBdLagBdwfrAo2eeRqIRVNZbwbsb j0XG6YcGPjcbQ== Received: by wens.tw (Postfix, from userid 1000) id 35554606A9; Tue, 23 Sep 2025 22:02:48 +0800 (CST) From: Chen-Yu Tsai To: Andrew Lunn , "David S. Miller" , Eric Dumazet , Jakub Kicinski , Paolo Abeni , Rob Herring , Krzysztof Kozlowski , Conor Dooley , Chen-Yu Tsai , Jernej Skrabec , Samuel Holland Cc: netdev@vger.kernel.org, devicetree@vger.kernel.org, linux-arm-kernel@lists.infradead.org, linux-sunxi@lists.linux.dev, linux-kernel@vger.kernel.org, Andre Przywara , Jernej Skrabec , Andrew Lunn Subject: [PATCH net-next v7 4/6] arm64: dts: allwinner: a527: cubie-a5e: Enable second Ethernet port Date: Tue, 23 Sep 2025 22:02:44 +0800 Message-ID: <20250923140247.2622602-5-wens@kernel.org> X-Mailer: git-send-email 2.47.3 In-Reply-To: <20250923140247.2622602-1-wens@kernel.org> References: <20250923140247.2622602-1-wens@kernel.org> Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Content-Type: text/plain; charset="utf-8" From: Chen-Yu Tsai On the Radxa Cubie A5E board, the second Ethernet controller, aka the GMAC200, is connected to a second external Maxio MAE0621A PHY. The PHY uses an external 25MHz crystal, and has the SoC's PJ16 pin connected to its reset pin. Enable the second Ethernet port. Also fix up the label for the existing external PHY connected to the first Ethernet port. An enable delay for the PHY supply regulator is added to make sure the PHY's internal regulators are fully powered and the PHY is operational. Acked-by: Jernej Skrabec Reviewed-by: Andrew Lunn Signed-off-by: Chen-Yu Tsai --- Changes since v1: - Switch to generic (tx|rx)-internal-delay-ps properties - Add PHY regulator delay --- .../dts/allwinner/sun55i-a527-cubie-a5e.dts | 28 +++++++++++++++++-- 1 file changed, 26 insertions(+), 2 deletions(-) diff --git a/arch/arm64/boot/dts/allwinner/sun55i-a527-cubie-a5e.dts b/arch= /arm64/boot/dts/allwinner/sun55i-a527-cubie-a5e.dts index f82a8d121697..bfdf1728cd14 100644 --- a/arch/arm64/boot/dts/allwinner/sun55i-a527-cubie-a5e.dts +++ b/arch/arm64/boot/dts/allwinner/sun55i-a527-cubie-a5e.dts @@ -14,6 +14,7 @@ / { =20 aliases { ethernet0 =3D &gmac0; + ethernet1 =3D &gmac1; serial0 =3D &uart0; }; =20 @@ -75,7 +76,7 @@ &ehci1 { =20 &gmac0 { phy-mode =3D "rgmii-id"; - phy-handle =3D <&ext_rgmii_phy>; + phy-handle =3D <&ext_rgmii0_phy>; phy-supply =3D <®_cldo3>; =20 allwinner,tx-delay-ps =3D <300>; @@ -84,13 +85,24 @@ &gmac0 { status =3D "okay"; }; =20 +&gmac1 { + phy-mode =3D "rgmii-id"; + phy-handle =3D <&ext_rgmii1_phy>; + phy-supply =3D <®_cldo4>; + + tx-internal-delay-ps =3D <300>; + rx-internal-delay-ps =3D <400>; + + status =3D "okay"; +}; + &gpu { mali-supply =3D <®_dcdc2>; status =3D "okay"; }; =20 &mdio0 { - ext_rgmii_phy: ethernet-phy@1 { + ext_rgmii0_phy: ethernet-phy@1 { compatible =3D "ethernet-phy-ieee802.3-c22"; reg =3D <1>; reset-gpios =3D <&pio 7 8 GPIO_ACTIVE_LOW>; /* PH8 */ @@ -99,6 +111,16 @@ ext_rgmii_phy: ethernet-phy@1 { }; }; =20 +&mdio1 { + ext_rgmii1_phy: ethernet-phy@1 { + compatible =3D "ethernet-phy-ieee802.3-c22"; + reg =3D <1>; + reset-gpios =3D <&pio 9 16 GPIO_ACTIVE_LOW>; /* PJ16 */ + reset-assert-us =3D <10000>; + reset-deassert-us =3D <150000>; + }; +}; + &mmc0 { vmmc-supply =3D <®_cldo3>; cd-gpios =3D <&pio 5 6 (GPIO_ACTIVE_LOW | GPIO_PULL_UP)>; /* PF6 */ @@ -250,6 +272,8 @@ reg_cldo4: cldo4 { regulator-min-microvolt =3D <3300000>; regulator-max-microvolt =3D <3300000>; regulator-name =3D "vcc-pj-phy"; + /* enough time for the PHY to fully power on */ + regulator-enable-ramp-delay =3D <150000>; }; =20 reg_cpusldo: cpusldo { --=20 2.47.3