From nobody Thu Oct 2 04:45:14 2025 Received: from smtp.kernel.org (aws-us-west-2-korg-mail-1.web.codeaurora.org [10.30.226.201]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id D4CC71B9831; Tue, 23 Sep 2025 14:02:50 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=none smtp.client-ip=10.30.226.201 ARC-Seal: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1758636170; cv=none; b=UvMX1KKtUki41GzlWcvNMggZgWifEhB7m7O0kc2zE4GiWUEsh245N/Vw705QLiUulezYLX67pzz22bt/5gNg1u0JYWrUqaImS+M0/2fh2hX/xIBMSKcUxZx8Alt7hSawu4P9sZ3t814rsEkzgaItO0OGlcu8OQYNaAqX3aFpoeQ= ARC-Message-Signature: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1758636170; c=relaxed/simple; bh=HhxH6oHHh9exPTDIHT0zcp6L2eUxeGZB5IX0TTPVCb0=; h=From:To:Cc:Subject:Date:Message-ID:In-Reply-To:References: MIME-Version; b=DoiTdi57GZSfw8lmtRGGfioQRfa7zq8cYQb9/atTWlqtDPW/djYCuHfpXWobdQQrOcobCR9MmBwtr4bRKSZUdHP7f/Gd587e57S4q34vAq09b867z75szntK3TYTqYBSIcNTwIdSrkgK5PS3WL4q8AlKXl24fJsE6Z2Qs85HjBA= ARC-Authentication-Results: i=1; smtp.subspace.kernel.org; dkim=pass (2048-bit key) header.d=kernel.org header.i=@kernel.org header.b=DjmhlK9i; arc=none smtp.client-ip=10.30.226.201 Authentication-Results: smtp.subspace.kernel.org; dkim=pass (2048-bit key) header.d=kernel.org header.i=@kernel.org header.b="DjmhlK9i" Received: by smtp.kernel.org (Postfix) with ESMTPSA id 5806CC4CEF5; Tue, 23 Sep 2025 14:02:50 +0000 (UTC) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=kernel.org; s=k20201202; t=1758636170; bh=HhxH6oHHh9exPTDIHT0zcp6L2eUxeGZB5IX0TTPVCb0=; h=From:To:Cc:Subject:Date:In-Reply-To:References:From; b=DjmhlK9ird7Yl4lwcw/cDjrGkrVJfbgcF+fsCiTJdSmQDNBs1m0SPWxQ1SKpOSXmX 4jLB1NsTWhjPz3w8SlYYz3+cbqmrh/RJjcyiF4n3YrJH9FjhJWM3bhSOO8ex+fNBDl SEMsmtchvs6HVqYRm28Ae0zRGt9ThuPiq0N9yZ9kiot2TEvEyZD4NF4rQyrukodvxL m8m6CH6bl2gu/KQ2rRH+pWVMxTwc+ybgtvIh5j/+tAHTn/S0bQ8OpCQdXJdrXZx7rZ watOxq6Ga0Qdm8psAZTccu5ZU0dSgeCvoQUi+b+LASe4S18j9hPuxX5C2InSeOuPgE iIAlB3in8vneQ== Received: by wens.tw (Postfix, from userid 1000) id 21BAE5FEEE; Tue, 23 Sep 2025 22:02:48 +0800 (CST) From: Chen-Yu Tsai To: Andrew Lunn , "David S. Miller" , Eric Dumazet , Jakub Kicinski , Paolo Abeni , Rob Herring , Krzysztof Kozlowski , Conor Dooley , Chen-Yu Tsai , Jernej Skrabec , Samuel Holland Cc: netdev@vger.kernel.org, devicetree@vger.kernel.org, linux-arm-kernel@lists.infradead.org, linux-sunxi@lists.linux.dev, linux-kernel@vger.kernel.org, Andre Przywara , Jernej Skrabec Subject: [PATCH net-next v7 3/6] arm64: dts: allwinner: a523: Add GMAC200 ethernet controller Date: Tue, 23 Sep 2025 22:02:43 +0800 Message-ID: <20250923140247.2622602-4-wens@kernel.org> X-Mailer: git-send-email 2.47.3 In-Reply-To: <20250923140247.2622602-1-wens@kernel.org> References: <20250923140247.2622602-1-wens@kernel.org> Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Content-Type: text/plain; charset="utf-8" From: Chen-Yu Tsai The A523 SoC family has a second ethernet controller, called the GMAC200. It is not exposed on all the SoCs in the family. Add a device node for it. All the hardware specific settings are from the vendor BSP. Acked-by: Jernej Skrabec Signed-off-by: Chen-Yu Tsai --- Changes since v1: - Fixed typo in tx-queues-config --- .../arm64/boot/dts/allwinner/sun55i-a523.dtsi | 55 +++++++++++++++++++ 1 file changed, 55 insertions(+) diff --git a/arch/arm64/boot/dts/allwinner/sun55i-a523.dtsi b/arch/arm64/bo= ot/dts/allwinner/sun55i-a523.dtsi index 7b36c47a3a13..a9e051a8bea3 100644 --- a/arch/arm64/boot/dts/allwinner/sun55i-a523.dtsi +++ b/arch/arm64/boot/dts/allwinner/sun55i-a523.dtsi @@ -182,6 +182,16 @@ rgmii0_pins: rgmii0-pins { bias-disable; }; =20 + rgmii1_pins: rgmii1-pins { + pins =3D "PJ0", "PJ1", "PJ2", "PJ3", "PJ4", + "PJ5", "PJ6", "PJ7", "PJ8", "PJ9", + "PJ11", "PJ12", "PJ13", "PJ14", "PJ15"; + allwinner,pinmux =3D <5>; + function =3D "gmac1"; + drive-strength =3D <40>; + bias-disable; + }; + uart0_pb_pins: uart0-pb-pins { pins =3D "PB9", "PB10"; allwinner,pinmux =3D <2>; @@ -603,6 +613,51 @@ mdio0: mdio { }; }; =20 + gmac1: ethernet@4510000 { + compatible =3D "allwinner,sun55i-a523-gmac200", + "snps,dwmac-4.20a"; + reg =3D <0x04510000 0x10000>; + clocks =3D <&ccu CLK_BUS_EMAC1>, <&ccu CLK_MBUS_EMAC1>; + clock-names =3D "stmmaceth", "mbus"; + resets =3D <&ccu RST_BUS_EMAC1>; + reset-names =3D "stmmaceth"; + interrupts =3D ; + interrupt-names =3D "macirq"; + pinctrl-names =3D "default"; + pinctrl-0 =3D <&rgmii1_pins>; + power-domains =3D <&pck600 PD_VO1>; + syscon =3D <&syscon>; + snps,fixed-burst; + snps,axi-config =3D <&gmac1_stmmac_axi_setup>; + snps,mtl-rx-config =3D <&gmac1_mtl_rx_setup>; + snps,mtl-tx-config =3D <&gmac1_mtl_tx_setup>; + status =3D "disabled"; + + mdio1: mdio { + compatible =3D "snps,dwmac-mdio"; + #address-cells =3D <1>; + #size-cells =3D <0>; + }; + + gmac1_mtl_rx_setup: rx-queues-config { + snps,rx-queues-to-use =3D <1>; + + queue0 {}; + }; + + gmac1_stmmac_axi_setup: stmmac-axi-config { + snps,wr_osr_lmt =3D <0xf>; + snps,rd_osr_lmt =3D <0xf>; + snps,blen =3D <256 128 64 32 16 8 4>; + }; + + gmac1_mtl_tx_setup: tx-queues-config { + snps,tx-queues-to-use =3D <1>; + + queue0 {}; + }; + }; + ppu: power-controller@7001400 { compatible =3D "allwinner,sun55i-a523-ppu"; reg =3D <0x07001400 0x400>; --=20 2.47.3