From nobody Thu Oct 2 03:27:36 2025 Received: from smtp.kernel.org (aws-us-west-2-korg-mail-1.web.codeaurora.org [10.30.226.201]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id D4C527262A; Tue, 23 Sep 2025 14:02:50 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=none smtp.client-ip=10.30.226.201 ARC-Seal: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1758636170; cv=none; b=EnxKuG5d4m0zFGUplwNVlX3viJ7fijrxMnAOkIqBrm2VgcwleM5HPwmDIkd+Ux6lgX2LVQiT5rFQwrGx3kY2hwU55Ci1x0+HKbHc3/uqy9rdcdM4n1BVV2hgrneLjpkx7AdlhuYcfedlifzDpwclg39g5JVpCptaT0dHitWIa8Q= ARC-Message-Signature: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1758636170; c=relaxed/simple; bh=wrUtZau2xE9D9sDwd69vvzmkh80bc7wxgr8Af/htrPw=; h=From:To:Cc:Subject:Date:Message-ID:In-Reply-To:References: MIME-Version; b=SKwECGRiPyZUk8HKZp2T93bwy9BkxgA7GU3f9OkdNp9+7ChSQGK36R0/s5A7xB3v03v3X3dpoQ9glMe0Qkyh7aHrDxVqHIryno1l7YNeb9LV51k9VJu8d+ynUCvzTzVOFJJ8/JIwHgvduPX1KFRAE4eRrmLtsnVsE1CKyJ53AsE= ARC-Authentication-Results: i=1; smtp.subspace.kernel.org; dkim=pass (2048-bit key) header.d=kernel.org header.i=@kernel.org header.b=l0qpxgzU; arc=none smtp.client-ip=10.30.226.201 Authentication-Results: smtp.subspace.kernel.org; dkim=pass (2048-bit key) header.d=kernel.org header.i=@kernel.org header.b="l0qpxgzU" Received: by smtp.kernel.org (Postfix) with ESMTPSA id 5BD93C113CF; Tue, 23 Sep 2025 14:02:50 +0000 (UTC) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=kernel.org; s=k20201202; t=1758636170; bh=wrUtZau2xE9D9sDwd69vvzmkh80bc7wxgr8Af/htrPw=; h=From:To:Cc:Subject:Date:In-Reply-To:References:From; b=l0qpxgzU7E7jgLvFbSUyDZ3j9/oG3S9e1uOlOW829kLUMaxv8LTONJaxlsQWnN1fS XwG+pknoFrnbT+Tj0hV19neT2ayb9NfSZdmXkCpcWN1luqAmUT8xdQvPDbrk6b9Vhm 13cipichwsFuaWO4n1EVFFMIbrbsGbkz5F17CJznpc9nqCnwo+SYJLqbRWQQmw7kn8 KmNmTNWSd28xHQisHMWBLJpq2lfmQmGNTrlKhkD0wnv+SYN4BycfG2CZraj/HGZyrS zipKywsfyIzmiGkrMkRq11syUCzR9uC1wdLzenzZ7OYPeGDXlo4KowHjy8WOMG9u4e kO2W6ZsMBasOg== Received: by wens.tw (Postfix, from userid 1000) id 0BC9C5FC15; Tue, 23 Sep 2025 22:02:48 +0800 (CST) From: Chen-Yu Tsai To: Andrew Lunn , "David S. Miller" , Eric Dumazet , Jakub Kicinski , Paolo Abeni , Rob Herring , Krzysztof Kozlowski , Conor Dooley , Chen-Yu Tsai , Jernej Skrabec , Samuel Holland Cc: netdev@vger.kernel.org, devicetree@vger.kernel.org, linux-arm-kernel@lists.infradead.org, linux-sunxi@lists.linux.dev, linux-kernel@vger.kernel.org, Andre Przywara , Conor Dooley Subject: [PATCH net-next v7 1/6] dt-bindings: net: sun8i-emac: Add A523 GMAC200 compatible Date: Tue, 23 Sep 2025 22:02:41 +0800 Message-ID: <20250923140247.2622602-2-wens@kernel.org> X-Mailer: git-send-email 2.47.3 In-Reply-To: <20250923140247.2622602-1-wens@kernel.org> References: <20250923140247.2622602-1-wens@kernel.org> Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Content-Type: text/plain; charset="utf-8" From: Chen-Yu Tsai The Allwinner A523 SoC family has a second Ethernet controller, called the GMAC200 in the BSP and T527 datasheet, and referred to as GMAC1 for numbering. This controller, according to BSP sources, is fully compatible with a slightly newer version of the Synopsys DWMAC core. The glue layer around the controller is the same as found around older DWMAC cores on Allwinner SoCs. The only slight difference is that since this is the second controller on the SoC, the register for the clock delay controls is at a different offset. Last, the integration includes a dedicated clock gate for the memory bus and the whole thing is put in a separately controllable power domain. Add a compatible string entry for it, and work in the requirements for a second clock and a power domain. Reviewed-by: Rob Herring (Arm) Acked-by: Conor Dooley Signed-off-by: Chen-Yu Tsai --- Changes since v6: - Collected tags Changes since v4: - Move clock-names list to main schema (Rob) Changes since v2: - Added "select" to avoid matching against all dwmac entries Changes since v1: - Switch to generic (tx|rx)-internal-delay-ps properties --- .../net/allwinner,sun8i-a83t-emac.yaml | 95 ++++++++++++++++++- 1 file changed, 93 insertions(+), 2 deletions(-) diff --git a/Documentation/devicetree/bindings/net/allwinner,sun8i-a83t-ema= c.yaml b/Documentation/devicetree/bindings/net/allwinner,sun8i-a83t-emac.ya= ml index 2ac709a4c472..fc62fb2a68ac 100644 --- a/Documentation/devicetree/bindings/net/allwinner,sun8i-a83t-emac.yaml +++ b/Documentation/devicetree/bindings/net/allwinner,sun8i-a83t-emac.yaml @@ -10,6 +10,21 @@ maintainers: - Chen-Yu Tsai - Maxime Ripard =20 +# We need a select here so we don't match all nodes with 'snps,dwmac' +select: + properties: + compatible: + contains: + enum: + - allwinner,sun8i-a83t-emac + - allwinner,sun8i-h3-emac + - allwinner,sun8i-r40-gmac + - allwinner,sun8i-v3s-emac + - allwinner,sun50i-a64-emac + - allwinner,sun55i-a523-gmac200 + required: + - compatible + properties: compatible: oneOf: @@ -26,6 +41,9 @@ properties: - allwinner,sun50i-h616-emac0 - allwinner,sun55i-a523-gmac0 - const: allwinner,sun50i-a64-emac + - items: + - const: allwinner,sun55i-a523-gmac200 + - const: snps,dwmac-4.20a =20 reg: maxItems: 1 @@ -37,14 +55,21 @@ properties: const: macirq =20 clocks: - maxItems: 1 + minItems: 1 + maxItems: 2 =20 clock-names: - const: stmmaceth + minItems: 1 + items: + - const: stmmaceth + - const: mbus =20 phy-supply: description: PHY regulator =20 + power-domains: + maxItems: 1 + syscon: $ref: /schemas/types.yaml#/definitions/phandle description: @@ -191,6 +216,42 @@ allOf: - mdio-parent-bus - mdio@1 =20 + - if: + properties: + compatible: + contains: + const: allwinner,sun55i-a523-gmac200 + then: + properties: + clocks: + minItems: 2 + clock-names: + minItems: 2 + tx-internal-delay-ps: + default: 0 + minimum: 0 + maximum: 700 + multipleOf: 100 + description: + External RGMII PHY TX clock delay chain value in ps. + rx-internal-delay-ps: + default: 0 + minimum: 0 + maximum: 3100 + multipleOf: 100 + description: + External RGMII PHY TX clock delay chain value in ps. + required: + - power-domains + else: + properties: + clocks: + maxItems: 1 + clock-names: + maxItems: 1 + power-domains: false + + unevaluatedProperties: false =20 examples: @@ -323,4 +384,34 @@ examples: }; }; =20 + - | + ethernet@4510000 { + compatible =3D "allwinner,sun55i-a523-gmac200", + "snps,dwmac-4.20a"; + reg =3D <0x04510000 0x10000>; + clocks =3D <&ccu 117>, <&ccu 79>; + clock-names =3D "stmmaceth", "mbus"; + resets =3D <&ccu 43>; + reset-names =3D "stmmaceth"; + interrupts =3D <0 47 4>; + interrupt-names =3D "macirq"; + pinctrl-names =3D "default"; + pinctrl-0 =3D <&rgmii1_pins>; + power-domains =3D <&pck600 4>; + syscon =3D <&syscon>; + phy-handle =3D <&ext_rgmii_phy_1>; + phy-mode =3D "rgmii-id"; + snps,fixed-burst; + snps,axi-config =3D <&gmac1_stmmac_axi_setup>; + + mdio { + compatible =3D "snps,dwmac-mdio"; + #address-cells =3D <1>; + #size-cells =3D <0>; + + ext_rgmii_phy_1: ethernet-phy@1 { + reg =3D <1>; + }; + }; + }; ... --=20 2.47.3 From nobody Thu Oct 2 03:27:36 2025 Received: from smtp.kernel.org (aws-us-west-2-korg-mail-1.web.codeaurora.org [10.30.226.201]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id 309A322259F; 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dkim=pass (2048-bit key) header.d=kernel.org header.i=@kernel.org header.b="o1S/Hv1x" Received: by smtp.kernel.org (Postfix) with ESMTPSA id 6CF50C116C6; Tue, 23 Sep 2025 14:02:50 +0000 (UTC) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=kernel.org; s=k20201202; t=1758636170; bh=SkL6UBVzYGksJa9vg1F2/54SqGDMb6/MuMtQg2Dw1jM=; h=From:To:Cc:Subject:Date:In-Reply-To:References:From; b=o1S/Hv1x5ZjXvwWhz8GcVdYWfyAkp/ARJlnftbTgIIOF57ChqI879smQCDyiiW+pR z8tl4fSbvyosOT7J4Uy8fpvdKWuUBBoC8hh1hJ6akbvPFnqPiXHhws1/64D8p6FXlB O0YH2Uy6rQN7XebkykQdmG+XUhFrIlGM0dBvLXYWgZHLixqpYjlVV1PNcJ9dgO4DP2 j85WWyhdGhSADau6hUP7MjgHcZ1W1A/ODDCvso3oif7aenqNCgvTUxkgPx0qnS6x9K h8uq0o/fo6wtp77TNwEJB1DLSBIPa6q7d3ghMXQdnWcEz6mFr0JWPPpa9/5pkO2MLf UTduNP1R2W97Q== Received: by wens.tw (Postfix, from userid 1000) id 173A45FDDE; Tue, 23 Sep 2025 22:02:48 +0800 (CST) From: Chen-Yu Tsai To: Andrew Lunn , "David S. Miller" , Eric Dumazet , Jakub Kicinski , Paolo Abeni , Rob Herring , Krzysztof Kozlowski , Conor Dooley , Chen-Yu Tsai , Jernej Skrabec , Samuel Holland Cc: netdev@vger.kernel.org, devicetree@vger.kernel.org, linux-arm-kernel@lists.infradead.org, linux-sunxi@lists.linux.dev, linux-kernel@vger.kernel.org, Andre Przywara Subject: [PATCH net-next v7 2/6] net: stmmac: Add support for Allwinner A523 GMAC200 Date: Tue, 23 Sep 2025 22:02:42 +0800 Message-ID: <20250923140247.2622602-3-wens@kernel.org> X-Mailer: git-send-email 2.47.3 In-Reply-To: <20250923140247.2622602-1-wens@kernel.org> References: <20250923140247.2622602-1-wens@kernel.org> Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Content-Type: text/plain; charset="utf-8" From: Chen-Yu Tsai The Allwinner A523 SoC family has a second Ethernet controller, called the GMAC200 in the BSP and T527 datasheet, and referred to as GMAC1 for numbering. This controller, according to BSP sources, is fully compatible with a slightly newer version of the Synopsys DWMAC core. The glue layer around the controller is the same as found around older DWMAC cores on Allwinner SoCs. The only slight difference is that since this is the second controller on the SoC, the register for the clock delay controls is at a different offset. Last, the integration includes a dedicated clock gate for the memory bus and the whole thing is put in a separately controllable power domain. Add a new driver for this hardware supporting the integration layer. Signed-off-by: Chen-Yu Tsai Reviewed-by: Jernej Skrabec --- Changes since v5: - Use plat->phy_interface instead of plat->mac_interface (Russell) Changes since v3: - Fixed printf format specifier warning Changes since v2 (all suggested by Russell King): - Include "ps" unit in "... must be multiple of ..." error message - Use FIELD_FIT to check if delay value is in range and FIELD_MAX to get the maximum value - Reword error message for delay value exceeding maximum - Drop MASK_TO_VAL Changes since v1: - Switch to generic (tx|rx)-internal-delay-ps properties - Change dev_err() + return to dev_err_probe() - Check return value from syscon regmap write - Change driver name to match file name --- drivers/net/ethernet/stmicro/stmmac/Kconfig | 12 ++ drivers/net/ethernet/stmicro/stmmac/Makefile | 1 + .../ethernet/stmicro/stmmac/dwmac-sun55i.c | 159 ++++++++++++++++++ 3 files changed, 172 insertions(+) create mode 100644 drivers/net/ethernet/stmicro/stmmac/dwmac-sun55i.c diff --git a/drivers/net/ethernet/stmicro/stmmac/Kconfig b/drivers/net/ethe= rnet/stmicro/stmmac/Kconfig index 91d9a14362bf..9507131875b2 100644 --- a/drivers/net/ethernet/stmicro/stmmac/Kconfig +++ b/drivers/net/ethernet/stmicro/stmmac/Kconfig @@ -265,6 +265,18 @@ config DWMAC_SUN8I stmmac device driver. This driver is used for H3/A83T/A64 EMAC ethernet controller. =20 +config DWMAC_SUN55I + tristate "Allwinner sun55i GMAC200 support" + default ARCH_SUNXI + depends on OF && (ARCH_SUNXI || COMPILE_TEST) + select MDIO_BUS_MUX + help + Support for Allwinner A523/T527 GMAC200 ethernet controllers. + + This selects Allwinner SoC glue layer support for the + stmmac device driver. This driver is used for A523/T527 + GMAC200 ethernet controller. + config DWMAC_THEAD tristate "T-HEAD dwmac support" depends on OF && (ARCH_THEAD || COMPILE_TEST) diff --git a/drivers/net/ethernet/stmicro/stmmac/Makefile b/drivers/net/eth= ernet/stmicro/stmmac/Makefile index b591d93f8503..51e068e26ce4 100644 --- a/drivers/net/ethernet/stmicro/stmmac/Makefile +++ b/drivers/net/ethernet/stmicro/stmmac/Makefile @@ -31,6 +31,7 @@ obj-$(CONFIG_DWMAC_STI) +=3D dwmac-sti.o obj-$(CONFIG_DWMAC_STM32) +=3D dwmac-stm32.o obj-$(CONFIG_DWMAC_SUNXI) +=3D dwmac-sunxi.o obj-$(CONFIG_DWMAC_SUN8I) +=3D dwmac-sun8i.o +obj-$(CONFIG_DWMAC_SUN55I) +=3D dwmac-sun55i.o obj-$(CONFIG_DWMAC_THEAD) +=3D dwmac-thead.o obj-$(CONFIG_DWMAC_DWC_QOS_ETH) +=3D dwmac-dwc-qos-eth.o obj-$(CONFIG_DWMAC_INTEL_PLAT) +=3D dwmac-intel-plat.o diff --git a/drivers/net/ethernet/stmicro/stmmac/dwmac-sun55i.c b/drivers/n= et/ethernet/stmicro/stmmac/dwmac-sun55i.c new file mode 100644 index 000000000000..862df173d963 --- /dev/null +++ b/drivers/net/ethernet/stmicro/stmmac/dwmac-sun55i.c @@ -0,0 +1,159 @@ +// SPDX-License-Identifier: GPL-2.0-only +/* + * dwmac-sun55i.c - Allwinner sun55i GMAC200 specific glue layer + * + * Copyright (C) 2025 Chen-Yu Tsai + * + * syscon parts taken from dwmac-sun8i.c, which is + * + * Copyright (C) 2017 Corentin Labbe + */ + +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include + +#include "stmmac.h" +#include "stmmac_platform.h" + +#define SYSCON_REG 0x34 + +/* RMII specific bits */ +#define SYSCON_RMII_EN BIT(13) /* 1: enable RMII (overrides EPIT) */ +/* Generic system control EMAC_CLK bits */ +#define SYSCON_ETXDC_MASK GENMASK(12, 10) +#define SYSCON_ERXDC_MASK GENMASK(9, 5) +/* EMAC PHY Interface Type */ +#define SYSCON_EPIT BIT(2) /* 1: RGMII, 0: MII */ +#define SYSCON_ETCS_MASK GENMASK(1, 0) +#define SYSCON_ETCS_MII 0x0 +#define SYSCON_ETCS_EXT_GMII 0x1 +#define SYSCON_ETCS_INT_GMII 0x2 + +static int sun55i_gmac200_set_syscon(struct device *dev, + struct plat_stmmacenet_data *plat) +{ + struct device_node *node =3D dev->of_node; + struct regmap *regmap; + u32 val, reg =3D 0; + int ret; + + regmap =3D syscon_regmap_lookup_by_phandle(node, "syscon"); + if (IS_ERR(regmap)) + return dev_err_probe(dev, PTR_ERR(regmap), "Unable to map syscon\n"); + + if (!of_property_read_u32(node, "tx-internal-delay-ps", &val)) { + if (val % 100) + return dev_err_probe(dev, -EINVAL, + "tx-delay must be a multiple of 100ps\n"); + val /=3D 100; + dev_dbg(dev, "set tx-delay to %x\n", val); + if (!FIELD_FIT(SYSCON_ETXDC_MASK, val)) + return dev_err_probe(dev, -EINVAL, + "TX clock delay exceeds maximum (%u00ps > %lu00ps)\n", + val, FIELD_MAX(SYSCON_ETXDC_MASK)); + + reg |=3D FIELD_PREP(SYSCON_ETXDC_MASK, val); + } + + if (!of_property_read_u32(node, "rx-internal-delay-ps", &val)) { + if (val % 100) + return dev_err_probe(dev, -EINVAL, + "rx-delay must be a multiple of 100ps\n"); + val /=3D 100; + dev_dbg(dev, "set rx-delay to %x\n", val); + if (!FIELD_FIT(SYSCON_ERXDC_MASK, val)) + return dev_err_probe(dev, -EINVAL, + "RX clock delay exceeds maximum (%u00ps > %lu00ps)\n", + val, FIELD_MAX(SYSCON_ERXDC_MASK)); + + reg |=3D FIELD_PREP(SYSCON_ERXDC_MASK, val); + } + + switch (plat->phy_interface) { + case PHY_INTERFACE_MODE_MII: + /* default */ + break; + case PHY_INTERFACE_MODE_RGMII: + case PHY_INTERFACE_MODE_RGMII_ID: + case PHY_INTERFACE_MODE_RGMII_RXID: + case PHY_INTERFACE_MODE_RGMII_TXID: + reg |=3D SYSCON_EPIT | SYSCON_ETCS_INT_GMII; + break; + case PHY_INTERFACE_MODE_RMII: + reg |=3D SYSCON_RMII_EN; + break; + default: + return dev_err_probe(dev, -EINVAL, "Unsupported interface mode: %s", + phy_modes(plat->phy_interface)); + } + + ret =3D regmap_write(regmap, SYSCON_REG, reg); + if (ret < 0) + return dev_err_probe(dev, ret, "Failed to write to syscon\n"); + + return 0; +} + +static int sun55i_gmac200_probe(struct platform_device *pdev) +{ + struct plat_stmmacenet_data *plat_dat; + struct stmmac_resources stmmac_res; + struct device *dev =3D &pdev->dev; + struct clk *clk; + int ret; + + ret =3D stmmac_get_platform_resources(pdev, &stmmac_res); + if (ret) + return ret; + + plat_dat =3D devm_stmmac_probe_config_dt(pdev, stmmac_res.mac); + if (IS_ERR(plat_dat)) + return PTR_ERR(plat_dat); + + /* BSP disables it */ + plat_dat->flags |=3D STMMAC_FLAG_SPH_DISABLE; + plat_dat->host_dma_width =3D 32; + + ret =3D sun55i_gmac200_set_syscon(dev, plat_dat); + if (ret) + return ret; + + clk =3D devm_clk_get_enabled(dev, "mbus"); + if (IS_ERR(clk)) + return dev_err_probe(dev, PTR_ERR(clk), + "Failed to get or enable MBUS clock\n"); + + ret =3D devm_regulator_get_enable_optional(dev, "phy"); + if (ret) + return dev_err_probe(dev, ret, "Failed to get or enable PHY supply\n"); + + return devm_stmmac_pltfr_probe(pdev, plat_dat, &stmmac_res); +} + +static const struct of_device_id sun55i_gmac200_match[] =3D { + { .compatible =3D "allwinner,sun55i-a523-gmac200" }, + { } +}; +MODULE_DEVICE_TABLE(of, sun55i_gmac200_match); + +static struct platform_driver sun55i_gmac200_driver =3D { + .probe =3D sun55i_gmac200_probe, + .driver =3D { + .name =3D "dwmac-sun55i", + .pm =3D &stmmac_pltfr_pm_ops, + .of_match_table =3D sun55i_gmac200_match, + }, +}; +module_platform_driver(sun55i_gmac200_driver); + +MODULE_AUTHOR("Chen-Yu Tsai "); +MODULE_DESCRIPTION("Allwinner sun55i GMAC200 specific glue layer"); +MODULE_LICENSE("GPL"); --=20 2.47.3 From nobody Thu Oct 2 03:27:36 2025 Received: from smtp.kernel.org (aws-us-west-2-korg-mail-1.web.codeaurora.org [10.30.226.201]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id D4CC71B9831; Tue, 23 Sep 2025 14:02:50 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=none smtp.client-ip=10.30.226.201 ARC-Seal: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1758636170; cv=none; b=UvMX1KKtUki41GzlWcvNMggZgWifEhB7m7O0kc2zE4GiWUEsh245N/Vw705QLiUulezYLX67pzz22bt/5gNg1u0JYWrUqaImS+M0/2fh2hX/xIBMSKcUxZx8Alt7hSawu4P9sZ3t814rsEkzgaItO0OGlcu8OQYNaAqX3aFpoeQ= ARC-Message-Signature: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1758636170; c=relaxed/simple; bh=HhxH6oHHh9exPTDIHT0zcp6L2eUxeGZB5IX0TTPVCb0=; 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Tue, 23 Sep 2025 22:02:48 +0800 (CST) From: Chen-Yu Tsai To: Andrew Lunn , "David S. Miller" , Eric Dumazet , Jakub Kicinski , Paolo Abeni , Rob Herring , Krzysztof Kozlowski , Conor Dooley , Chen-Yu Tsai , Jernej Skrabec , Samuel Holland Cc: netdev@vger.kernel.org, devicetree@vger.kernel.org, linux-arm-kernel@lists.infradead.org, linux-sunxi@lists.linux.dev, linux-kernel@vger.kernel.org, Andre Przywara , Jernej Skrabec Subject: [PATCH net-next v7 3/6] arm64: dts: allwinner: a523: Add GMAC200 ethernet controller Date: Tue, 23 Sep 2025 22:02:43 +0800 Message-ID: <20250923140247.2622602-4-wens@kernel.org> X-Mailer: git-send-email 2.47.3 In-Reply-To: <20250923140247.2622602-1-wens@kernel.org> References: <20250923140247.2622602-1-wens@kernel.org> Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Content-Type: text/plain; charset="utf-8" From: Chen-Yu Tsai The A523 SoC family has a second ethernet controller, called the GMAC200. It is not exposed on all the SoCs in the family. Add a device node for it. All the hardware specific settings are from the vendor BSP. Acked-by: Jernej Skrabec Signed-off-by: Chen-Yu Tsai --- Changes since v1: - Fixed typo in tx-queues-config --- .../arm64/boot/dts/allwinner/sun55i-a523.dtsi | 55 +++++++++++++++++++ 1 file changed, 55 insertions(+) diff --git a/arch/arm64/boot/dts/allwinner/sun55i-a523.dtsi b/arch/arm64/bo= ot/dts/allwinner/sun55i-a523.dtsi index 7b36c47a3a13..a9e051a8bea3 100644 --- a/arch/arm64/boot/dts/allwinner/sun55i-a523.dtsi +++ b/arch/arm64/boot/dts/allwinner/sun55i-a523.dtsi @@ -182,6 +182,16 @@ rgmii0_pins: rgmii0-pins { bias-disable; }; =20 + rgmii1_pins: rgmii1-pins { + pins =3D "PJ0", "PJ1", "PJ2", "PJ3", "PJ4", + "PJ5", "PJ6", "PJ7", "PJ8", "PJ9", + "PJ11", "PJ12", "PJ13", "PJ14", "PJ15"; + allwinner,pinmux =3D <5>; + function =3D "gmac1"; + drive-strength =3D <40>; + bias-disable; + }; + uart0_pb_pins: uart0-pb-pins { pins =3D "PB9", "PB10"; allwinner,pinmux =3D <2>; @@ -603,6 +613,51 @@ mdio0: mdio { }; }; =20 + gmac1: ethernet@4510000 { + compatible =3D "allwinner,sun55i-a523-gmac200", + "snps,dwmac-4.20a"; + reg =3D <0x04510000 0x10000>; + clocks =3D <&ccu CLK_BUS_EMAC1>, <&ccu CLK_MBUS_EMAC1>; + clock-names =3D "stmmaceth", "mbus"; + resets =3D <&ccu RST_BUS_EMAC1>; + reset-names =3D "stmmaceth"; + interrupts =3D ; + interrupt-names =3D "macirq"; + pinctrl-names =3D "default"; + pinctrl-0 =3D <&rgmii1_pins>; + power-domains =3D <&pck600 PD_VO1>; + syscon =3D <&syscon>; + snps,fixed-burst; + snps,axi-config =3D <&gmac1_stmmac_axi_setup>; + snps,mtl-rx-config =3D <&gmac1_mtl_rx_setup>; + snps,mtl-tx-config =3D <&gmac1_mtl_tx_setup>; + status =3D "disabled"; + + mdio1: mdio { + compatible =3D "snps,dwmac-mdio"; + #address-cells =3D <1>; + #size-cells =3D <0>; + }; + + gmac1_mtl_rx_setup: rx-queues-config { + snps,rx-queues-to-use =3D <1>; + + queue0 {}; + }; + + gmac1_stmmac_axi_setup: stmmac-axi-config { + snps,wr_osr_lmt =3D <0xf>; + snps,rd_osr_lmt =3D <0xf>; + snps,blen =3D <256 128 64 32 16 8 4>; + }; + + gmac1_mtl_tx_setup: tx-queues-config { + snps,tx-queues-to-use =3D <1>; + + queue0 {}; + }; + }; + ppu: power-controller@7001400 { compatible =3D "allwinner,sun55i-a523-ppu"; reg =3D <0x07001400 0x400>; --=20 2.47.3 From nobody Thu Oct 2 03:27:36 2025 Received: from smtp.kernel.org (aws-us-west-2-korg-mail-1.web.codeaurora.org [10.30.226.201]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id D4C102C18A; Tue, 23 Sep 2025 14:02:50 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=none smtp.client-ip=10.30.226.201 ARC-Seal: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1758636170; cv=none; b=gGG0ni/XT2lLEP8UdRpURVR9yln+uyKvv7ja7kkZeuS71HJr9dk5EQvSloN8s+TQNub8QGNgyHS/jUdutsiIudv+OMu+QNRWBOwwjn/Xalg4u2OBEO3QmgNjSIa7lbUQwk3+u/N14gF792OxqmPG4DEZLQ/dVUV93WMstz4Xv2I= ARC-Message-Signature: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1758636170; c=relaxed/simple; bh=rx7cTQhbHRFL+3YWoqnP53MCOR0zwAA48Z7BXBg9pb8=; h=From:To:Cc:Subject:Date:Message-ID:In-Reply-To:References: MIME-Version; b=WYw06d1LQvsBXCNYf0dMt75mWkhdjooiMHaijScQtaK898mqEZwc+s+Sajb0YjzCOJ1unJNygTgOAa7/xzmkcYG42yV9IIIR5xPuGOp5/oXW897lB4ReR4q4tIC+IatZS8TQqERqUJ2f9bZLGifZM1g5CGnCE1NHefi1GaJRcpw= ARC-Authentication-Results: i=1; smtp.subspace.kernel.org; dkim=pass (2048-bit key) header.d=kernel.org header.i=@kernel.org header.b=Cjh9lXJi; arc=none smtp.client-ip=10.30.226.201 Authentication-Results: smtp.subspace.kernel.org; dkim=pass (2048-bit key) header.d=kernel.org header.i=@kernel.org header.b="Cjh9lXJi" Received: by smtp.kernel.org (Postfix) with ESMTPSA id 5DD4DC4AF09; Tue, 23 Sep 2025 14:02:50 +0000 (UTC) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=kernel.org; s=k20201202; t=1758636170; bh=rx7cTQhbHRFL+3YWoqnP53MCOR0zwAA48Z7BXBg9pb8=; h=From:To:Cc:Subject:Date:In-Reply-To:References:From; b=Cjh9lXJinGubymHzTR8iqkFWHo4/T+IVyPeOOJTqk5xNF0ysF0BFzz5ZP6X33I6iU kjmFzhh9y0LP49AaQBa2TRdJrcu3gjyAsZLWMCCvuAlxdiJjlKbo4oqteslU5Jbv87 6iGmWxUmXiG6Rd4NU56EbrhPsOmiffgbU/AKhn8iaxfGJhaa7CbFNqci2nUutt0DZP sAP7ZkImbREwAF5fu1W8oQB1juq9445HPePL88N+R+4Yu2hABq0Gl+460ssA+0wrX1 AYxVt63e7BKzqhLdN1sQ88s5SfUQkW01kkqBI1DBdLagBdwfrAo2eeRqIRVNZbwbsb j0XG6YcGPjcbQ== Received: by wens.tw (Postfix, from userid 1000) id 35554606A9; Tue, 23 Sep 2025 22:02:48 +0800 (CST) From: Chen-Yu Tsai To: Andrew Lunn , "David S. Miller" , Eric Dumazet , Jakub Kicinski , Paolo Abeni , Rob Herring , Krzysztof Kozlowski , Conor Dooley , Chen-Yu Tsai , Jernej Skrabec , Samuel Holland Cc: netdev@vger.kernel.org, devicetree@vger.kernel.org, linux-arm-kernel@lists.infradead.org, linux-sunxi@lists.linux.dev, linux-kernel@vger.kernel.org, Andre Przywara , Jernej Skrabec , Andrew Lunn Subject: [PATCH net-next v7 4/6] arm64: dts: allwinner: a527: cubie-a5e: Enable second Ethernet port Date: Tue, 23 Sep 2025 22:02:44 +0800 Message-ID: <20250923140247.2622602-5-wens@kernel.org> X-Mailer: git-send-email 2.47.3 In-Reply-To: <20250923140247.2622602-1-wens@kernel.org> References: <20250923140247.2622602-1-wens@kernel.org> Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Content-Type: text/plain; charset="utf-8" From: Chen-Yu Tsai On the Radxa Cubie A5E board, the second Ethernet controller, aka the GMAC200, is connected to a second external Maxio MAE0621A PHY. The PHY uses an external 25MHz crystal, and has the SoC's PJ16 pin connected to its reset pin. Enable the second Ethernet port. Also fix up the label for the existing external PHY connected to the first Ethernet port. An enable delay for the PHY supply regulator is added to make sure the PHY's internal regulators are fully powered and the PHY is operational. Acked-by: Jernej Skrabec Reviewed-by: Andrew Lunn Signed-off-by: Chen-Yu Tsai --- Changes since v1: - Switch to generic (tx|rx)-internal-delay-ps properties - Add PHY regulator delay --- .../dts/allwinner/sun55i-a527-cubie-a5e.dts | 28 +++++++++++++++++-- 1 file changed, 26 insertions(+), 2 deletions(-) diff --git a/arch/arm64/boot/dts/allwinner/sun55i-a527-cubie-a5e.dts b/arch= /arm64/boot/dts/allwinner/sun55i-a527-cubie-a5e.dts index f82a8d121697..bfdf1728cd14 100644 --- a/arch/arm64/boot/dts/allwinner/sun55i-a527-cubie-a5e.dts +++ b/arch/arm64/boot/dts/allwinner/sun55i-a527-cubie-a5e.dts @@ -14,6 +14,7 @@ / { =20 aliases { ethernet0 =3D &gmac0; + ethernet1 =3D &gmac1; serial0 =3D &uart0; }; =20 @@ -75,7 +76,7 @@ &ehci1 { =20 &gmac0 { phy-mode =3D "rgmii-id"; - phy-handle =3D <&ext_rgmii_phy>; + phy-handle =3D <&ext_rgmii0_phy>; phy-supply =3D <®_cldo3>; =20 allwinner,tx-delay-ps =3D <300>; @@ -84,13 +85,24 @@ &gmac0 { status =3D "okay"; }; =20 +&gmac1 { + phy-mode =3D "rgmii-id"; + phy-handle =3D <&ext_rgmii1_phy>; + phy-supply =3D <®_cldo4>; + + tx-internal-delay-ps =3D <300>; + rx-internal-delay-ps =3D <400>; + + status =3D "okay"; +}; + &gpu { mali-supply =3D <®_dcdc2>; status =3D "okay"; }; =20 &mdio0 { - ext_rgmii_phy: ethernet-phy@1 { + ext_rgmii0_phy: ethernet-phy@1 { compatible =3D "ethernet-phy-ieee802.3-c22"; reg =3D <1>; reset-gpios =3D <&pio 7 8 GPIO_ACTIVE_LOW>; /* PH8 */ @@ -99,6 +111,16 @@ ext_rgmii_phy: ethernet-phy@1 { }; }; =20 +&mdio1 { + ext_rgmii1_phy: ethernet-phy@1 { + compatible =3D "ethernet-phy-ieee802.3-c22"; + reg =3D <1>; + reset-gpios =3D <&pio 9 16 GPIO_ACTIVE_LOW>; /* PJ16 */ + reset-assert-us =3D <10000>; + reset-deassert-us =3D <150000>; + }; +}; + &mmc0 { vmmc-supply =3D <®_cldo3>; cd-gpios =3D <&pio 5 6 (GPIO_ACTIVE_LOW | GPIO_PULL_UP)>; /* PF6 */ @@ -250,6 +272,8 @@ reg_cldo4: cldo4 { regulator-min-microvolt =3D <3300000>; regulator-max-microvolt =3D <3300000>; regulator-name =3D "vcc-pj-phy"; + /* enough time for the PHY to fully power on */ + regulator-enable-ramp-delay =3D <150000>; }; =20 reg_cpusldo: cpusldo { --=20 2.47.3 From nobody Thu Oct 2 03:27:36 2025 Received: from smtp.kernel.org (aws-us-west-2-korg-mail-1.web.codeaurora.org [10.30.226.201]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id 374D0257842; Tue, 23 Sep 2025 14:02:52 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=none smtp.client-ip=10.30.226.201 ARC-Seal: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1758636173; cv=none; b=cettYbwdzv07tD2/cxAQOA++AozKLTq7UUAU+h3J5yLm9xOAF76kMxPw80rSd11iFM+rrHx54Ft7yRiNliZkqqIYgMWqGPbulD/aQATWjLNkN70uDYamDCCCOYZF7cOybYQMb+hTtqGQP0B80aC8H272ZxdqANpKYvG4N37w6zk= ARC-Message-Signature: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1758636173; c=relaxed/simple; bh=LaxIY3ciZrjZcZx8L7T/CqcZbDAJyhjiMK8HyefyTF0=; h=From:To:Cc:Subject:Date:Message-ID:In-Reply-To:References: MIME-Version; b=fq3jyIWgSKBmoLbb8P2oSlRa+lC1vj6nOrqrBqQdWoIEIu67iM/xlWms1dRPpeq8iAncjK/zxI+A1vrsekLdax6j8WS1B+unfuyXwQZKZL5MWhxQo4HogXIwr3Y/ds/LgXeUc6BbzHiPfDiY1ZxL50ruivNZSfJVqSz/igVI/KQ= ARC-Authentication-Results: i=1; smtp.subspace.kernel.org; dkim=pass (2048-bit key) header.d=kernel.org header.i=@kernel.org header.b=m09qMalz; arc=none smtp.client-ip=10.30.226.201 Authentication-Results: smtp.subspace.kernel.org; dkim=pass (2048-bit key) header.d=kernel.org header.i=@kernel.org header.b="m09qMalz" Received: by smtp.kernel.org (Postfix) with ESMTPSA id 85B7CC4CEF5; Tue, 23 Sep 2025 14:02:52 +0000 (UTC) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=kernel.org; s=k20201202; t=1758636172; bh=LaxIY3ciZrjZcZx8L7T/CqcZbDAJyhjiMK8HyefyTF0=; h=From:To:Cc:Subject:Date:In-Reply-To:References:From; b=m09qMalzdD2Zj7aMf1Af09yE2jRKQGYEElE5T1T2tm7fH4TXFayKpTAwsW3SvF4XA VUl3Bnmi8e4QnLtL15n56Kg6pnyoLp26Tiw8TuwmEk1aOdpAVnh8COitXJuI94XYRy cfnhHKuFCZXi3OkBLzzTJ4eXlS1Fbyl8BkCey70jVddTJnggEmR1DZ86Qkek3Qkgc7 ++t2zI8r0VPKwL2DAV8mDcrPa/qMIjINQgAMxsivLamdQxLVbaBDTML1dGaW5bUvAy Q5aY56thK0wFcCCJclQbVCd4FqOfsWNAIZ3glvSwKQ5sdqouNXjXWJyGtjubk4zYnf egMBoCfyNFhVQ== Received: by wens.tw (Postfix, from userid 1000) id 44002606B1; Tue, 23 Sep 2025 22:02:48 +0800 (CST) From: Chen-Yu Tsai To: Andrew Lunn , "David S. Miller" , Eric Dumazet , Jakub Kicinski , Paolo Abeni , Rob Herring , Krzysztof Kozlowski , Conor Dooley , Chen-Yu Tsai , Jernej Skrabec , Samuel Holland Cc: netdev@vger.kernel.org, devicetree@vger.kernel.org, linux-arm-kernel@lists.infradead.org, linux-sunxi@lists.linux.dev, linux-kernel@vger.kernel.org, Andre Przywara , Jernej Skrabec , Andrew Lunn Subject: [PATCH net-next v7 5/6] arm64: dts: allwinner: t527: avaota-a1: enable second Ethernet port Date: Tue, 23 Sep 2025 22:02:45 +0800 Message-ID: <20250923140247.2622602-6-wens@kernel.org> X-Mailer: git-send-email 2.47.3 In-Reply-To: <20250923140247.2622602-1-wens@kernel.org> References: <20250923140247.2622602-1-wens@kernel.org> Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Content-Type: text/plain; charset="utf-8" From: Chen-Yu Tsai On the Avaota A1 board, the second Ethernet controller, aka the GMAC200, is connected to a second external RTL8211F-CG PHY. The PHY uses an external 25MHz crystal, and has the SoC's PJ16 pin connected to its reset pin. Enable the second Ethernet port. Also fix up the label for the existing external PHY connected to the first Ethernet port. Acked-by: Jernej Skrabec Reviewed-by: Andrew Lunn Signed-off-by: Chen-Yu Tsai --- Changes since v1: - Switch to generic (tx|rx)-internal-delay-ps properties --- .../dts/allwinner/sun55i-t527-avaota-a1.dts | 26 +++++++++++++++++-- 1 file changed, 24 insertions(+), 2 deletions(-) diff --git a/arch/arm64/boot/dts/allwinner/sun55i-t527-avaota-a1.dts b/arch= /arm64/boot/dts/allwinner/sun55i-t527-avaota-a1.dts index 1b054fa8ef74..054d0357c139 100644 --- a/arch/arm64/boot/dts/allwinner/sun55i-t527-avaota-a1.dts +++ b/arch/arm64/boot/dts/allwinner/sun55i-t527-avaota-a1.dts @@ -13,6 +13,7 @@ / { =20 aliases { ethernet0 =3D &gmac0; + ethernet1 =3D &gmac1; serial0 =3D &uart0; }; =20 @@ -73,7 +74,7 @@ &ehci1 { =20 &gmac0 { phy-mode =3D "rgmii-id"; - phy-handle =3D <&ext_rgmii_phy>; + phy-handle =3D <&ext_rgmii0_phy>; phy-supply =3D <®_dcdc4>; =20 allwinner,tx-delay-ps =3D <100>; @@ -82,13 +83,24 @@ &gmac0 { status =3D "okay"; }; =20 +&gmac1 { + phy-mode =3D "rgmii-id"; + phy-handle =3D <&ext_rgmii1_phy>; + phy-supply =3D <®_dcdc4>; + + tx-internal-delay-ps =3D <100>; + rx-internal-delay-ps =3D <100>; + + status =3D "okay"; +}; + &gpu { mali-supply =3D <®_dcdc2>; status =3D "okay"; }; =20 &mdio0 { - ext_rgmii_phy: ethernet-phy@1 { + ext_rgmii0_phy: ethernet-phy@1 { compatible =3D "ethernet-phy-ieee802.3-c22"; reg =3D <1>; reset-gpios =3D <&pio 7 8 GPIO_ACTIVE_LOW>; /* PH8 */ @@ -97,6 +109,16 @@ ext_rgmii_phy: ethernet-phy@1 { }; }; =20 +&mdio1 { + ext_rgmii1_phy: ethernet-phy@1 { + compatible =3D "ethernet-phy-ieee802.3-c22"; + reg =3D <1>; + reset-gpios =3D <&pio 9 16 GPIO_ACTIVE_LOW>; /* PJ16 */ + reset-assert-us =3D <10000>; + reset-deassert-us =3D <150000>; + }; +}; + &mmc0 { vmmc-supply =3D <®_cldo3>; cd-gpios =3D <&pio 5 6 (GPIO_ACTIVE_LOW | GPIO_PULL_UP)>; /* PF6 */ --=20 2.47.3 From nobody Thu Oct 2 03:27:36 2025 Received: from smtp.kernel.org (aws-us-west-2-korg-mail-1.web.codeaurora.org [10.30.226.201]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id 8CF5525A357; Tue, 23 Sep 2025 14:02:53 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=none smtp.client-ip=10.30.226.201 ARC-Seal: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1758636173; cv=none; b=JyNIMoEm+jU0go1iwKkZjsZ537rfCpQyUBchXTrhoDHzG419RYCyqnBiMPBvG9s9O8mKXT5qtZFLWplpDnMt3ns+BbkbfAGeLTED9N+BM/Z2RUsrhZt0rhzSZ/s+1yR2H9xqGhC5yiBOl3uM3h6+DAZk3wEb8ssgjrRCNFiRYMg= ARC-Message-Signature: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1758636173; c=relaxed/simple; bh=Qg34C9exkp2NB8HBKF6gQRoaPUtMAb5daqSaeZ5VcOE=; h=From:To:Cc:Subject:Date:Message-ID:In-Reply-To:References: MIME-Version; b=s6r3vhW6ZbBw0Kk+CDuTSXIWSVMjCxT6Kgl64pqUVqug3K7LpPV7zzFDM67gUN/QyinONtSqEOIj9955opwH+CXgXcqJXo3RQWqxKWThSb2iJ3j9vl3Io/oLPiTAOqQgrfc1NKqPPXk9HehswBKySDPl9V2Hg+U6M6ZMU5qI7J8= ARC-Authentication-Results: i=1; smtp.subspace.kernel.org; dkim=pass (2048-bit key) header.d=kernel.org header.i=@kernel.org header.b=rUp0aMdO; arc=none smtp.client-ip=10.30.226.201 Authentication-Results: smtp.subspace.kernel.org; dkim=pass (2048-bit key) header.d=kernel.org header.i=@kernel.org header.b="rUp0aMdO" Received: by smtp.kernel.org (Postfix) with ESMTPSA id BDB2DC19423; Tue, 23 Sep 2025 14:02:52 +0000 (UTC) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=kernel.org; s=k20201202; t=1758636172; bh=Qg34C9exkp2NB8HBKF6gQRoaPUtMAb5daqSaeZ5VcOE=; h=From:To:Cc:Subject:Date:In-Reply-To:References:From; b=rUp0aMdO5ZtjRnqrzLLuX8BbdqZ+4uxgtW6rUXzh7F5DBC2rNEc23n8NM7BBRfEPY 3gpkUuh4eD2ptjdd26nk7U/r/5JuikR3D6gHHeQ3RamrOLtQlJfwSN44tWkPzM/2D1 mNhNCrVt8zPLR/qaoPBhd+JZ25zPjqamL1qaH7b+YrFi4nc10BgnrE3vneIAvvU/El kGrAoWZDbv9H5NOe08sexZnoWw1cgC1A/Uv5JbqoK0y4TI9YziSUlaC9zfC3L5oYUZ po3V4AgAaq9+aDwy+0V84jRVo3snDhnVpJi1Hv6Wi4gG2QOAARoxY+JAFrqfgOKQb2 vj2j8SxtbHXZQ== Received: by wens.tw (Postfix, from userid 1000) id 50B67606B2; Tue, 23 Sep 2025 22:02:48 +0800 (CST) From: Chen-Yu Tsai To: Andrew Lunn , "David S. Miller" , Eric Dumazet , Jakub Kicinski , Paolo Abeni , Rob Herring , Krzysztof Kozlowski , Conor Dooley , Chen-Yu Tsai , Jernej Skrabec , Samuel Holland Cc: netdev@vger.kernel.org, devicetree@vger.kernel.org, linux-arm-kernel@lists.infradead.org, linux-sunxi@lists.linux.dev, linux-kernel@vger.kernel.org, Andre Przywara , Jernej Skrabec , Andrew Lunn Subject: [PATCH net-next v7 6/6] arm64: dts: allwinner: t527: orangepi-4a: Enable Ethernet port Date: Tue, 23 Sep 2025 22:02:46 +0800 Message-ID: <20250923140247.2622602-7-wens@kernel.org> X-Mailer: git-send-email 2.47.3 In-Reply-To: <20250923140247.2622602-1-wens@kernel.org> References: <20250923140247.2622602-1-wens@kernel.org> Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Content-Type: text/plain; charset="utf-8" From: Chen-Yu Tsai On the Orangepi 4A board, the second Ethernet controller, aka the GMAC200, is connected to an external Motorcomm YT8531 PHY. The PHY uses an external 25MHz crystal, has the SoC's PI15 pin connected to its reset pin, and the PI16 pin for its interrupt pin. Enable it. Acked-by: Jernej Skrabec Reviewed-by: Andrew Lunn Signed-off-by: Chen-Yu Tsai --- Changes since v1: - Switch to generic (tx|rx)-internal-delay-ps properties --- .../dts/allwinner/sun55i-t527-orangepi-4a.dts | 23 +++++++++++++++++++ 1 file changed, 23 insertions(+) diff --git a/arch/arm64/boot/dts/allwinner/sun55i-t527-orangepi-4a.dts b/ar= ch/arm64/boot/dts/allwinner/sun55i-t527-orangepi-4a.dts index 39a4e194712a..9e6b21cf293e 100644 --- a/arch/arm64/boot/dts/allwinner/sun55i-t527-orangepi-4a.dts +++ b/arch/arm64/boot/dts/allwinner/sun55i-t527-orangepi-4a.dts @@ -15,6 +15,7 @@ / { compatible =3D "xunlong,orangepi-4a", "allwinner,sun55i-t527"; =20 aliases { + ethernet0 =3D &gmac1; serial0 =3D &uart0; }; =20 @@ -102,11 +103,33 @@ &ehci1 { status =3D "okay"; }; =20 +&gmac1 { + phy-mode =3D "rgmii-id"; + phy-handle =3D <&ext_rgmii_phy>; + phy-supply =3D <®_cldo4>; + + tx-internal-delay-ps =3D <0>; + rx-internal-delay-ps =3D <300>; + + status =3D "okay"; +}; + &gpu { mali-supply =3D <®_dcdc2>; status =3D "okay"; }; =20 +&mdio1 { + ext_rgmii_phy: ethernet-phy@1 { + compatible =3D "ethernet-phy-ieee802.3-c22"; + reg =3D <1>; + interrupts-extended =3D <&pio 8 16 IRQ_TYPE_LEVEL_LOW>; /* PI16 */ + reset-gpios =3D <&pio 8 15 GPIO_ACTIVE_LOW>; /* PI15 */ + reset-assert-us =3D <10000>; + reset-deassert-us =3D <150000>; + }; +}; + &mmc0 { vmmc-supply =3D <®_cldo3>; cd-gpios =3D <&pio 5 6 (GPIO_ACTIVE_LOW | GPIO_PULL_UP)>; /* PF6 */ --=20 2.47.3