From nobody Thu Oct 2 04:50:31 2025 Received: from szxga03-in.huawei.com (szxga03-in.huawei.com [45.249.212.189]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id 4785F32341D for ; Tue, 23 Sep 2025 13:15:26 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=none smtp.client-ip=45.249.212.189 ARC-Seal: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1758633329; cv=none; b=TtFBYbalME4oULMpndYdYuIHNi6NeN/k2JTFl/vWePuumuOm3WXFN/JUjXanq193suzSQonsD7qqoyU6jxnRr+4r7uTx/a1Sj8nQ0auOypVEVPZAgekoFxlobcB2zWZVA7HehV7yS5J1vWFuPR/3gbAPfgdkWSfME4LDDp1CNFI= ARC-Message-Signature: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1758633329; c=relaxed/simple; bh=hUy9cPtn+0FbMG70hQxrb1OaBE0M7sholQty5UpEPJ8=; h=From:To:CC:Subject:Date:Message-ID:In-Reply-To:References: MIME-Version:Content-Type; b=e3CAAJ8zrNRut94FserYQdEuTVtrIZXj5hX4t+hCqjmRDk/0T9kZyf/iKgFug9YQw2I5WSuF1/3R52nBLdeKn+sbSnfbKCHD2/GyxgNoNHsMKhMSGYwwpXCRztdG23jHsU2bA3L4YQkiqPzO88NY72bQ2LfZ6/fLbp32YbClqhM= ARC-Authentication-Results: i=1; smtp.subspace.kernel.org; dmarc=pass (p=quarantine dis=none) header.from=huawei.com; spf=pass smtp.mailfrom=huawei.com; arc=none smtp.client-ip=45.249.212.189 Authentication-Results: smtp.subspace.kernel.org; dmarc=pass (p=quarantine dis=none) header.from=huawei.com Authentication-Results: smtp.subspace.kernel.org; spf=pass smtp.mailfrom=huawei.com Received: from mail.maildlp.com (unknown [172.19.163.174]) by szxga03-in.huawei.com (SkyGuard) with ESMTP id 4cWL2G2QgpzddNf; Tue, 23 Sep 2025 21:10:46 +0800 (CST) Received: from dggemv705-chm.china.huawei.com (unknown [10.3.19.32]) by mail.maildlp.com (Postfix) with ESMTPS id BAA791402CB; Tue, 23 Sep 2025 21:15:24 +0800 (CST) Received: from kwepemq100007.china.huawei.com (7.202.195.175) by dggemv705-chm.china.huawei.com (10.3.19.32) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_256_GCM_SHA384) id 15.2.1544.11; Tue, 23 Sep 2025 21:15:24 +0800 Received: from localhost.huawei.com (10.169.71.169) by kwepemq100007.china.huawei.com (7.202.195.175) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_256_GCM_SHA384) id 15.2.1544.11; Tue, 23 Sep 2025 21:15:24 +0800 From: Yongbang Shi To: , , , , , , , , CC: , , , , , , , , Subject: [PATCH v7 drm-dp 4/4] drm/hisilicon/hibmc: Adding reset colorbar cfg in dp init. Date: Tue, 23 Sep 2025 21:04:11 +0800 Message-ID: <20250923130411.2522339-5-shiyongbang@huawei.com> X-Mailer: git-send-email 2.33.0 In-Reply-To: <20250923130411.2522339-1-shiyongbang@huawei.com> References: <20250923130411.2522339-1-shiyongbang@huawei.com> Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable X-ClientProxiedBy: kwepems100001.china.huawei.com (7.221.188.238) To kwepemq100007.china.huawei.com (7.202.195.175) Content-Type: text/plain; charset="utf-8" From: Baihan Li Add colorbar disable operation before reset chontroller, to make sure colorbar status is clear in the DP init, so if rmmod the driver and the previous colorbar configuration will not affect the next time insmod the driver. Fixes: 3c7623fb5bb6 ("drm/hisilicon/hibmc: Enable this hot plug detect of i= rq feature") Signed-off-by: Baihan Li Signed-off-by: Yongbang Shi Reviewed-by: Dmitry Baryshkov --- drivers/gpu/drm/hisilicon/hibmc/dp/dp_hw.c | 2 ++ 1 file changed, 2 insertions(+) diff --git a/drivers/gpu/drm/hisilicon/hibmc/dp/dp_hw.c b/drivers/gpu/drm/h= isilicon/hibmc/dp/dp_hw.c index 2954e3066923..b458cb7628d5 100644 --- a/drivers/gpu/drm/hisilicon/hibmc/dp/dp_hw.c +++ b/drivers/gpu/drm/hisilicon/hibmc/dp/dp_hw.c @@ -180,6 +180,8 @@ int hibmc_dp_hw_init(struct hibmc_dp *dp) /* int init */ writel(0, dp_dev->base + HIBMC_DP_INTR_ENABLE); writel(HIBMC_DP_INT_RST, dp_dev->base + HIBMC_DP_INTR_ORIGINAL_STATUS); + /* clr colorbar */ + writel(0, dp_dev->base + HIBMC_DP_COLOR_BAR_CTRL); /* rst */ writel(0, dp_dev->base + HIBMC_DP_DPTX_RST_CTRL); usleep_range(30, 50); --=20 2.33.0