From nobody Thu Oct 2 03:30:49 2025 Received: from zg8tmja5ljk3lje4mi4ymjia.icoremail.net (zg8tmja5ljk3lje4mi4ymjia.icoremail.net [209.97.182.222]) by smtp.subspace.kernel.org (Postfix) with ESMTP id C66AF1FBEB0; Tue, 23 Sep 2025 12:12:24 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=none smtp.client-ip=209.97.182.222 ARC-Seal: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1758629548; cv=none; b=KcR/YR5DmK27Lx4+qJoFsKLXMjGByivIpzX5qkHqKftBjwike8NeBIogXvosvqhZAAnDGRmR0k/03g6sh9LmHSis7DqU39CQhPYAcQzlrBmbcchXHPa6WKYuCUjANh0CIwgTYvs7g1K9cjGbsCjHZEIxD7sOytEp1dWcpxyfsZQ= ARC-Message-Signature: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1758629548; c=relaxed/simple; bh=/6tcggY9PuJaW18j/AURzVRFMAu5mMPf+O7rN81ULxo=; h=From:To:Cc:Subject:Date:Message-ID:In-Reply-To:References: MIME-Version; b=J3WEtnKDBKVg9o9fiRn7YNBNm4SojXdC2+gRl36KQ/ncjL/e7JXgzAlSlOOCyYFkbJdNnUCeVh/lPKvQDesyzohlOEWJgE5OBT0dz70DEr4qBxqhk0fWzHNSrOnaoS+x4DvlGCIUjjZtZbYd/8zCp1gLfXOAnLlM8wT5MFUlIhs= ARC-Authentication-Results: i=1; smtp.subspace.kernel.org; dmarc=none (p=none dis=none) header.from=eswincomputing.com; spf=pass smtp.mailfrom=eswincomputing.com; arc=none smtp.client-ip=209.97.182.222 Authentication-Results: smtp.subspace.kernel.org; dmarc=none (p=none dis=none) header.from=eswincomputing.com Authentication-Results: smtp.subspace.kernel.org; spf=pass smtp.mailfrom=eswincomputing.com Received: from E0004758DT.eswin.cn (unknown [10.12.96.83]) by app2 (Coremail) with SMTP id TQJkCgAHmZKTjtJomSnYAA--.60230S2; Tue, 23 Sep 2025 20:12:05 +0800 (CST) From: zhangsenchuan@eswincomputing.com To: bhelgaas@google.com, lpieralisi@kernel.org, kwilczynski@kernel.org, mani@kernel.org, robh@kernel.org, krzk+dt@kernel.org, conor+dt@kernel.org, linux-pci@vger.kernel.org, devicetree@vger.kernel.org, linux-kernel@vger.kernel.org, p.zabel@pengutronix.de, johan+linaro@kernel.org, quic_schintav@quicinc.com, shradha.t@samsung.com, cassel@kernel.org, thippeswamy.havalige@amd.com, mayank.rana@oss.qualcomm.com, inochiama@gmail.com Cc: ningyu@eswincomputing.com, linmin@eswincomputing.com, pinkesh.vaghela@einfochips.com, Senchuan Zhang , Yanghui Ou Subject: [PATCH v3 1/2] dt-bindings: PCI: EIC7700: Add Eswin PCIe host controller Date: Tue, 23 Sep 2025 20:12:00 +0800 Message-ID: <20250923121200.1235-1-zhangsenchuan@eswincomputing.com> X-Mailer: git-send-email 2.49.0.windows.1 In-Reply-To: <20250923120946.1218-1-zhangsenchuan@eswincomputing.com> References: <20250923120946.1218-1-zhangsenchuan@eswincomputing.com> Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable X-CM-TRANSID: TQJkCgAHmZKTjtJomSnYAA--.60230S2 X-Coremail-Antispam: 1UD129KBjvJXoWxZw4UKr1kCFW7JrW5tF4xJFb_yoWrCF1rpF ZxGFy8Wr48Xr13Z3y5XF4jkFnxJwsYkFnYkr1xWa13tr9Yqa4qqw43K3W5Aa43Gr4jq34Y qFsIvr1xtw17A3DanT9S1TB71UUUUU7qnTZGkaVYY2UrUUUUjbIjqfuFe4nvWSU5nxnvy2 9KBjDU0xBIdaVrnRJUUUBv14x267AKxVW5JVWrJwAFc2x0x2IEx4CE42xK8VAvwI8IcIk0 rVWrJVCq3wAFIxvE14AKwVWUJVWUGwA2ocxC64kIII0Yj41l84x0c7CEw4AK67xGY2AK02 1l84ACjcxK6xIIjxv20xvE14v26ryj6F1UM28EF7xvwVC0I7IYx2IY6xkF7I0E14v26r4U JVWxJr1l84ACjcxK6I8E87Iv67AKxVW0oVCq3wA2z4x0Y4vEx4A2jsIEc7CjxVAFwI0_Gc CE3s1le2I262IYc4CY6c8Ij28IcVAaY2xG8wAqx4xG64xvF2IEw4CE5I8CrVC2j2WlYx0E 2Ix0cI8IcVAFwI0_JrI_JrylYx0Ex4A2jsIE14v26r1j6r4UMcvjeVCFs4IE7xkEbVWUJV W8JwACjcxG0xvY0x0EwIxGrwACjI8F5VA0II8E6IAqYI8I648v4I1lFIxGxcIEc7CjxVA2 Y2ka0xkIwI1lw4CEc2x0rVAKj4xxMxkF7I0En4kS14v26r4a6rW5MxkIecxEwVCm-wCF04 k20xvY0x0EwIxGrwCFx2IqxVCFs4IE7xkEbVWUJVW8JwC20s026c02F40E14v26r1j6r18 MI8I3I0E7480Y4vE14v26r106r1rMI8E67AF67kF1VAFwI0_GFv_WrylIxkGc2Ij64vIr4 1lIxAIcVC0I7IYx2IY67AKxVWUJVWUCwCI42IY6xIIjxv20xvEc7CjxVAFwI0_Gr0_Cr1l IxAIcVCF04k26cxKx2IYs7xG6r1j6r1xMIIF0xvEx4A2jsIE14v26r1j6r4UMIIF0xvEx4 A2jsIEc7CjxVAFwI0_Gr0_Gr1UYxBIdaVFxhVjvjDU0xZFpf9x0pRuHqcUUUUU= X-CM-SenderInfo: x2kd0wpvhquxxxdqqvxvzl0uprps33xlqjhudrp/ Content-Type: text/plain; charset="utf-8" From: Senchuan Zhang Add Device Tree binding documentation for the Eswin EIC7700 PCIe controller module, the PCIe controller enables the core to correctly initialize and manage the PCIe bus and connected devices. Signed-off-by: Yu Ning Signed-off-by: Yanghui Ou Signed-off-by: Senchuan Zhang --- .../bindings/pci/eswin,eic7700-pcie.yaml | 173 ++++++++++++++++++ 1 file changed, 173 insertions(+) create mode 100644 Documentation/devicetree/bindings/pci/eswin,eic7700-pci= e.yaml diff --git a/Documentation/devicetree/bindings/pci/eswin,eic7700-pcie.yaml = b/Documentation/devicetree/bindings/pci/eswin,eic7700-pcie.yaml new file mode 100644 index 000000000000..2f105d09e38e --- /dev/null +++ b/Documentation/devicetree/bindings/pci/eswin,eic7700-pcie.yaml @@ -0,0 +1,173 @@ +# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause) +%YAML 1.2 +--- +$id: http://devicetree.org/schemas/pci/eswin,eic7700-pcie.yaml# +$schema: http://devicetree.org/meta-schemas/core.yaml# + +title: Eswin EIC7700 PCIe host controller + +maintainers: + - Yu Ning + - Senchuan Zhang + - Yanghui Ou + +description: + The PCIe controller on EIC7700 SoC. + +allOf: + - $ref: /schemas/pci/pci-host-bridge.yaml# + +properties: + compatible: + const: eswin,eic7700-pcie + + reg: + maxItems: 3 + + reg-names: + items: + - const: dbi + - const: config + - const: mgmt + + ranges: + maxItems: 3 + + num-lanes: + maximum: 4 + + '#interrupt-cells': + const: 1 + + interrupts: + maxItems: 9 + + interrupt-names: + items: + - const: msi + - const: inta # Assert_INTA + - const: intb # Assert_INTB + - const: intc # Assert_INTC + - const: intd # Assert_INTD + - const: inte # Desassert_INTA + - const: intf # Desassert_INTB + - const: intg # Desassert_INTC + - const: inth # Desassert_INTD + + interrupt-map: + maxItems: 4 + + interrupt-map-mask: + items: + - const: 0 + - const: 0 + - const: 0 + - const: 7 + + clocks: + maxItems: 4 + + clock-names: + items: + - const: mstr + - const: dbi + - const: pclk + - const: aux + + resets: + maxItems: 2 + + reset-names: + items: + - const: cfg + - const: powerup + +patternProperties: + "^pcie@": + type: object + $ref: /schemas/pci/pci-pci-bridge.yaml# + + properties: + reg: + maxItems: 1 + + resets: + maxItems: 1 + + reset-names: + items: + - const: perst + + required: + - reg + - ranges + - resets + - reset-names + + unevaluatedProperties: false + +required: + - compatible + - reg + - ranges + - interrupts + - interrupt-names + - interrupt-map-mask + - interrupt-map + - '#interrupt-cells' + - clocks + - clock-names + - resets + - reset-names + +unevaluatedProperties: false + +examples: + - | + soc { + #address-cells =3D <2>; + #size-cells =3D <2>; + + pcie@54000000 { + compatible =3D "eswin,eic7700-pcie"; + reg =3D <0x0 0x54000000 0x0 0x4000000>, + <0x0 0x40000000 0x0 0x800000>, + <0x0 0x50000000 0x0 0x100000>; + reg-names =3D "dbi", "config", "mgmt"; + #address-cells =3D <3>; + #size-cells =3D <2>; + #interrupt-cells =3D <1>; + ranges =3D <0x01000000 0x0 0x40800000 0x0 0x40800000 0x0 0x800= 000>, + <0x02000000 0x0 0x41000000 0x0 0x41000000 0x0 0xf0000= 00>, + <0x43000000 0x80 0x00000000 0x80 0x00000000 0x2 0x000= 00000>; + bus-range =3D <0x00 0xff>; + clocks =3D <&clock 203>, + <&clock 204>, + <&clock 205>, + <&clock 206>; + clock-names =3D "mstr", "dbi", "pclk", "aux"; + resets =3D <&reset 97>, + <&reset 98>; + reset-names =3D "cfg", "powerup"; + interrupts =3D <220>, <179>, <180>, <181>, <182>, <183>, <184>= , <185>, <186>; + interrupt-names =3D "msi", "inta", "intb", "intc", "intd", + "inte", "intf", "intg", "inth"; + interrupt-parent =3D <&plic>; + interrupt-map-mask =3D <0x0 0x0 0x0 0x7>; + interrupt-map =3D <0x0 0x0 0x0 0x1 &plic 179>, + <0x0 0x0 0x0 0x2 &plic 180>, + <0x0 0x0 0x0 0x3 &plic 181>, + <0x0 0x0 0x0 0x4 &plic 182>; + device_type =3D "pci"; + pcie@0 { + reg =3D <0x0 0x0 0x0 0x0 0x0>; + #address-cells =3D <3>; + #size-cells =3D <2>; + ranges; + device_type =3D "pci"; + num-lanes =3D <4>; + resets =3D <&reset 99>; + reset-names =3D "perst"; + }; + }; + }; --=20 2.25.1 From nobody Thu Oct 2 03:30:49 2025 Received: from azure-sdnproxy.icoremail.net (azure-sdnproxy.icoremail.net [4.193.249.245]) by smtp.subspace.kernel.org (Postfix) with ESMTP id 7EE42322C9A; Tue, 23 Sep 2025 12:12:44 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=none smtp.client-ip=4.193.249.245 ARC-Seal: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1758629567; cv=none; b=VpxFLkQHG7AvTM4otrgTynai2RU6sS+tZyP7bwGz39h/gQLKbDfmDS+Fp72dhdCGEjKrVTesxKHkdT6j6x/F1vqQoJSicv2UzIESNKl1961IzCdeQOkcps2ONkS/ltPcfyyzQ4pu8jXFlv4e1G2apk1bfZzfQutbWN0moCHQj7M= ARC-Message-Signature: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1758629567; c=relaxed/simple; bh=tLI9jm8gb4Eu7bXtPLfdul04UNRf5f6d+L4oBECjJ8U=; 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charset="utf-8" From: Senchuan Zhang Add driver for the Eswin EIC7700 PCIe host controller,the controller is based on the DesignWare PCIe core, IP revision 6.00a The PCIe Gen.3 controller supports a data rate of 8 GT/s and 4 channels, support INTX and MSI interrupts. Signed-off-by: Yu Ning Signed-off-by: Yanghui Ou Signed-off-by: Senchuan Zhang --- drivers/pci/controller/dwc/Kconfig | 11 + drivers/pci/controller/dwc/Makefile | 1 + drivers/pci/controller/dwc/pcie-eic7700.c | 446 ++++++++++++++++++++++ 3 files changed, 458 insertions(+) create mode 100644 drivers/pci/controller/dwc/pcie-eic7700.c diff --git a/drivers/pci/controller/dwc/Kconfig b/drivers/pci/controller/dw= c/Kconfig index ff6b6d9e18ec..8474bc6356f7 100644 --- a/drivers/pci/controller/dwc/Kconfig +++ b/drivers/pci/controller/dwc/Kconfig @@ -375,6 +375,17 @@ config PCI_EXYNOS hardware and therefore the driver re-uses the DesignWare core functions to implement the driver. =20 +config PCIE_EIC7700 + bool "ESWIN PCIe controller" + depends on ARCH_ESWIN || COMPILE_TEST + depends on PCI_MSI + select PCIE_DW_HOST + help + Say Y here if you want PCIe controller support for the ESWIN. + The PCIe controller on Eswin is based on DesignWare hardware, + enables support for the PCIe controller in the Eswin SoC to + work in host mode. + config PCIE_FU740 bool "SiFive FU740 PCIe controller" depends on PCI_MSI diff --git a/drivers/pci/controller/dwc/Makefile b/drivers/pci/controller/d= wc/Makefile index 6919d27798d1..97b2ac4eb949 100644 --- a/drivers/pci/controller/dwc/Makefile +++ b/drivers/pci/controller/dwc/Makefile @@ -8,6 +8,7 @@ obj-$(CONFIG_PCIE_AMD_MDB) +=3D pcie-amd-mdb.o obj-$(CONFIG_PCIE_BT1) +=3D pcie-bt1.o obj-$(CONFIG_PCI_DRA7XX) +=3D pci-dra7xx.o obj-$(CONFIG_PCI_EXYNOS) +=3D pci-exynos.o +obj-$(CONFIG_PCIE_EIC7700) +=3D pcie-eic7700.o obj-$(CONFIG_PCIE_FU740) +=3D pcie-fu740.o obj-$(CONFIG_PCI_IMX6) +=3D pci-imx6.o obj-$(CONFIG_PCIE_SPEAR13XX) +=3D pcie-spear13xx.o diff --git a/drivers/pci/controller/dwc/pcie-eic7700.c b/drivers/pci/contro= ller/dwc/pcie-eic7700.c new file mode 100644 index 000000000000..32da4a645bef --- /dev/null +++ b/drivers/pci/controller/dwc/pcie-eic7700.c @@ -0,0 +1,446 @@ +// SPDX-License-Identifier: GPL-2.0 +/* + * ESWIN PCIe root complex driver + * + * Copyright 2025, Beijing ESWIN Computing Technology Co., Ltd. + * + * Authors: Yu Ning + * Senchuan Zhang + * Yanghui Ou + */ + +#include +#include +#include +#include +#include +#include +#include +#include +#include + +#include "pcie-designware.h" + +/* PCIe top csr registers */ +#define PCIEMGMT_CTRL0_OFFSET 0x0 +#define PCIEMGMT_STATUS0_OFFSET 0x100 + +/* LTSSM register fields */ +#define PCIEMGMT_APP_LTSSM_ENABLE BIT(5) + +/* APP_HOLD_PHY_RST register fields */ +#define PCIEMGMT_APP_HOLD_PHY_RST BIT(6) + +/* PM_SEL_AUX_CLK register fields */ +#define PCIEMGMT_PM_SEL_AUX_CLK BIT(16) + +/* ROOT_PORT register fields */ +#define PCIEMGMT_CTRL0_ROOT_PORT_MASK GENMASK(3, 0) + +/* Vendor and device id value */ +#define VENDOR_ID_VALUE 0x1fe1 +#define DEVICE_ID_VALUE 0x2030 + +/* Disable MSI-X cap register fields */ +#define PCIE_MSIX_DISABLE_MASK GENMASK(15, 8) + +struct eswin_pcie_data { + bool msix_cap; +}; + +struct eswin_pcie_port { + struct list_head list; + struct reset_control *perst; + int num_lanes; +}; + +struct eswin_pcie { + struct dw_pcie pci; + void __iomem *mgmt_base; + struct clk_bulk_data *clks; + struct reset_control *powerup_rst; + struct reset_control *cfg_rst; + struct list_head ports; + int num_clks; + bool suspended; + bool msix_cap; +}; + +#define to_eswin_pcie(x) dev_get_drvdata((x)->dev) + +static int eswin_pcie_start_link(struct dw_pcie *pci) +{ + struct eswin_pcie *pcie =3D to_eswin_pcie(pci); + u32 val; + + /* Enable LTSSM */ + val =3D readl_relaxed(pcie->mgmt_base + PCIEMGMT_CTRL0_OFFSET); + val |=3D PCIEMGMT_APP_LTSSM_ENABLE; + writel_relaxed(val, pcie->mgmt_base + PCIEMGMT_CTRL0_OFFSET); + + return 0; +} + +static bool eswin_pcie_link_up(struct dw_pcie *pci) +{ + u16 offset =3D dw_pcie_find_capability(pci, PCI_CAP_ID_EXP); + u16 val =3D readw(pci->dbi_base + offset + PCI_EXP_LNKSTA); + + return val & PCI_EXP_LNKSTA_DLLLA; +} + +static int eswin_pcie_deassert(struct eswin_pcie *pcie) +{ + int ret; + + ret =3D reset_control_deassert(pcie->cfg_rst); + if (ret) { + dev_err(pcie->pci.dev, "Failed to deassert CFG#"); + return ret; + } + + ret =3D reset_control_deassert(pcie->powerup_rst); + if (ret) { + dev_err(pcie->pci.dev, "Failed to deassert POWERUP#"); + goto err_powerup; + } + + return 0; + +err_powerup: + reset_control_assert(pcie->cfg_rst); + + return ret; +} + +static void eswin_pcie_assert(struct eswin_pcie *pcie) +{ + reset_control_assert(pcie->powerup_rst); + reset_control_assert(pcie->cfg_rst); +} + +static int eswin_pcie_perst_deassert(struct eswin_pcie_port *port, + struct eswin_pcie *pcie) +{ + int ret; + + ret =3D reset_control_assert(port->perst); + if (ret) { + dev_err(pcie->pci.dev, "Failed to assert PERST#"); + goto err_perst; + } + + /* Ensure that PERST has been asserted for at least 100 ms */ + msleep(PCIE_T_PVPERL_MS); + + ret =3D reset_control_deassert(port->perst); + if (ret) { + dev_err(pcie->pci.dev, "Failed to deassert PERST#"); + goto err_perst; + } + + return 0; + +err_perst: + list_for_each_entry(port, &pcie->ports, list) + reset_control_put(port->perst); + + return ret; +} + +static int eswin_pcie_parse_port(struct eswin_pcie *pcie, + struct device_node *node) +{ + struct device *dev =3D pcie->pci.dev; + struct eswin_pcie_port *port; + + port =3D devm_kzalloc(dev, sizeof(*port), GFP_KERNEL); + if (!port) + return -ENOMEM; + + port->perst =3D of_reset_control_get(node, "perst"); + if (IS_ERR(port->perst)) { + dev_err(dev, "Failed to get perst reset\n"); + return PTR_ERR(port->perst); + } + + /* + * Since the root port node is separated out by pcie devicetree, the + * DWC core initialization code cannot parse the num-lanes attribute + * in the root port. Before entering the DWC core initialization code, + * the platform driver code parses the root port node. The EIC7700 only + * supports one root port node, and the num-lanes attribute is suitable + * for the case of one root port. + */ + of_property_read_u32(node, "num-lanes", &port->num_lanes); + pcie->pci.num_lanes =3D port->num_lanes; + + INIT_LIST_HEAD(&port->list); + list_add_tail(&port->list, &pcie->ports); + + return 0; +} + +static int eswin_pcie_parse_ports(struct eswin_pcie *pcie) +{ + struct device *dev =3D pcie->pci.dev; + struct eswin_pcie_port *port, *tmp; + int ret; + + for_each_available_child_of_node_scoped(dev->of_node, of_port) { + ret =3D eswin_pcie_parse_port(pcie, of_port); + if (ret) + goto err_port; + } + + return ret; + +err_port: + list_for_each_entry_safe(port, tmp, &pcie->ports, list) + list_del(&port->list); + return ret; +} + +static void eswin_pcie_hide_broken_msix_cap(struct dw_pcie *pci) +{ + u16 offset, val; + + /* + * Hardware doesn't support MSI-X but it advertises MSI-X capability, + * to avoid this problem, the MSI-X capability in the PCIe capabilities + * linked-list needs to be disabled. Since the PCI Express capability + * structure's next pointer points to the MSI-X capability, and the + * MSI-X capability's next pointer is null (00H), so only the PCI + * Express capability structure's next pointer needs to be set 00H. + */ + offset =3D dw_pcie_find_capability(pci, PCI_CAP_ID_EXP); + val =3D dw_pcie_readl_dbi(pci, offset); + val &=3D ~PCIE_MSIX_DISABLE_MASK; + dw_pcie_writel_dbi(pci, offset, val); +} + +static int eswin_pcie_host_init(struct dw_pcie_rp *pp) +{ + struct dw_pcie *pci =3D to_dw_pcie_from_pp(pp); + struct eswin_pcie *pcie =3D to_eswin_pcie(pci); + struct eswin_pcie_port *port; + u32 retries; + u8 msi_cap; + u32 val; + int ret; + + pcie->num_clks =3D devm_clk_bulk_get_all_enabled(pci->dev, &pcie->clks); + if (pcie->num_clks < 0) + return dev_err_probe(pci->dev, pcie->num_clks, + "Failed to get pcie clocks\n"); + + ret =3D eswin_pcie_deassert(pcie); + if (ret) + return ret; + + /* Configure root port type */ + val =3D readl_relaxed(pcie->mgmt_base + PCIEMGMT_CTRL0_OFFSET); + val &=3D ~PCIEMGMT_CTRL0_ROOT_PORT_MASK; + writel_relaxed(val | PCI_EXP_TYPE_ROOT_PORT, + pcie->mgmt_base + PCIEMGMT_CTRL0_OFFSET); + + list_for_each_entry(port, &pcie->ports, list) { + ret =3D eswin_pcie_perst_deassert(port, pcie); + if (ret) + goto err_perst; + } + + /* Configure app_hold_phy_rst */ + val =3D readl_relaxed(pcie->mgmt_base + PCIEMGMT_CTRL0_OFFSET); + val &=3D ~PCIEMGMT_APP_HOLD_PHY_RST; + writel_relaxed(val, pcie->mgmt_base + PCIEMGMT_CTRL0_OFFSET); + + /* The maximum waiting time for the clock switch lock is 20ms */ + retries =3D 20; + do { + val =3D readl_relaxed(pcie->mgmt_base + PCIEMGMT_STATUS0_OFFSET); + if (!(val & PCIEMGMT_PM_SEL_AUX_CLK)) + break; + fsleep(1000); + retries--; + } while (retries); + + if (!retries) { + dev_err(pci->dev, "Timeout waiting for PM_SEL_AUX_CLK ready\n"); + ret =3D -ETIMEDOUT; + goto err_phy_init; + } + + /* + * Configure ESWIN VID:DID for Root Port as the default values are + * invalid. + */ + dw_pcie_writew_dbi(pci, PCI_VENDOR_ID, VENDOR_ID_VALUE); + dw_pcie_writew_dbi(pci, PCI_DEVICE_ID, DEVICE_ID_VALUE); + + /* Configure support 32 MSI vectors */ + msi_cap =3D dw_pcie_find_capability(pci, PCI_CAP_ID_MSI); + val =3D dw_pcie_readw_dbi(pci, msi_cap + PCI_MSI_FLAGS); + val &=3D ~PCI_MSI_FLAGS_QMASK; + val |=3D FIELD_PREP(PCI_MSI_FLAGS_QMASK, 5); + dw_pcie_writew_dbi(pci, msi_cap + PCI_MSI_FLAGS, val); + + /* Configure disable MSI-X cap */ + if (!pcie->msix_cap) + eswin_pcie_hide_broken_msix_cap(pci); + + return 0; + +err_phy_init: + list_for_each_entry(port, &pcie->ports, list) + reset_control_assert(port->perst); +err_perst: + eswin_pcie_assert(pcie); + + return ret; +} + +static const struct dw_pcie_host_ops eswin_pcie_host_ops =3D { + .init =3D eswin_pcie_host_init, +}; + +static const struct dw_pcie_ops dw_pcie_ops =3D { + .start_link =3D eswin_pcie_start_link, + .link_up =3D eswin_pcie_link_up, +}; + +static int eswin_pcie_probe(struct platform_device *pdev) +{ + const struct eswin_pcie_data *data; + struct eswin_pcie_port *port, *tmp; + struct device *dev =3D &pdev->dev; + struct eswin_pcie *pcie; + struct dw_pcie *pci; + int ret; + + data =3D of_device_get_match_data(dev); + if (!data) + return dev_err_probe(dev, -EINVAL, "OF data missing\n"); + + pcie =3D devm_kzalloc(dev, sizeof(*pcie), GFP_KERNEL); + if (!pcie) + return -ENOMEM; + + INIT_LIST_HEAD(&pcie->ports); + + pci =3D &pcie->pci; + pci->dev =3D dev; + pci->ops =3D &dw_pcie_ops; + pci->pp.ops =3D &eswin_pcie_host_ops; + pcie->msix_cap =3D data->msix_cap; + + pcie->mgmt_base =3D devm_platform_ioremap_resource_byname(pdev, "mgmt"); + if (IS_ERR(pcie->mgmt_base)) + return dev_err_probe(dev, PTR_ERR(pcie->mgmt_base), + "Failed to map mgmt registers\n"); + + pcie->powerup_rst =3D devm_reset_control_get(&pdev->dev, "powerup"); + if (IS_ERR(pcie->powerup_rst)) + return dev_err_probe(dev, PTR_ERR(pcie->powerup_rst), + "Failed to get powerup reset\n"); + + pcie->cfg_rst =3D devm_reset_control_get(&pdev->dev, "cfg"); + if (IS_ERR(pcie->cfg_rst)) + return dev_err_probe(dev, PTR_ERR(pcie->cfg_rst), + "Failed to get cfg reset\n"); + + ret =3D eswin_pcie_parse_ports(pcie); + if (ret) + dev_err_probe(pci->dev, ret, + "Failed to parse Root Port: %d\n", ret); + + platform_set_drvdata(pdev, pcie); + + ret =3D dw_pcie_host_init(&pci->pp); + if (ret) { + dev_err(dev, "Failed to initialize host\n"); + goto err_init; + } + + return ret; + +err_init: + list_for_each_entry_safe(port, tmp, &pcie->ports, list) { + list_del(&port->list); + reset_control_put(port->perst); + } + return ret; +} + +static int eswin_pcie_suspend(struct device *dev) +{ + struct eswin_pcie *pcie =3D dev_get_drvdata(dev); + struct eswin_pcie_port *port; + + /* + * For controllers with active devices, resources are retained and + * cannot be turned off. + */ + if (!dw_pcie_link_up(&pcie->pci)) { + list_for_each_entry(port, &pcie->ports, list) + reset_control_assert(port->perst); + eswin_pcie_assert(pcie); + clk_bulk_disable_unprepare(pcie->num_clks, pcie->clks); + pcie->suspended =3D true; + } + + return 0; +} + +static int eswin_pcie_resume(struct device *dev) +{ + struct eswin_pcie *pcie =3D dev_get_drvdata(dev); + int ret; + + if (!pcie->suspended) + return 0; + + ret =3D eswin_pcie_host_init(&pcie->pci.pp); + if (ret) { + dev_err(dev, "Failed to init host: %d\n", ret); + return ret; + } + + dw_pcie_setup_rc(&pcie->pci.pp); + eswin_pcie_start_link(&pcie->pci); + dw_pcie_wait_for_link(&pcie->pci); + + pcie->suspended =3D false; + + return 0; +} + +static const struct dev_pm_ops eswin_pcie_pm_ops =3D { + NOIRQ_SYSTEM_SLEEP_PM_OPS(eswin_pcie_suspend, eswin_pcie_resume) +}; + +static const struct eswin_pcie_data eswin_7700_data =3D { + .msix_cap =3D false, +}; + +static const struct of_device_id eswin_pcie_of_match[] =3D { + { .compatible =3D "eswin,eic7700-pcie", .data =3D &eswin_7700_data }, + {}, +}; + +static struct platform_driver eswin_pcie_driver =3D { + .probe =3D eswin_pcie_probe, + .driver =3D { + .name =3D "eic7700-pcie", + .of_match_table =3D eswin_pcie_of_match, + .suppress_bind_attrs =3D true, + .pm =3D &eswin_pcie_pm_ops, + }, +}; +builtin_platform_driver(eswin_pcie_driver); + +MODULE_DESCRIPTION("PCIe host controller driver for EIC7700 SoCs"); +MODULE_AUTHOR("Yu Ning "); +MODULE_AUTHOR("Senchuan Zhang "); +MODULE_AUTHOR("Yanghui Ou "); +MODULE_LICENSE("GPL"); --=20 2.25.1