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X-OriginatorOrg: Nvidia.com X-MS-Exchange-CrossTenant-OriginalArrivalTime: 23 Sep 2025 10:45:11.9041 (UTC) X-MS-Exchange-CrossTenant-Network-Message-Id: 8ec5a9c9-e63b-48b5-a0aa-08ddfa8e45dd X-MS-Exchange-CrossTenant-Id: 43083d15-7273-40c1-b7db-39efd9ccc17a X-MS-Exchange-CrossTenant-OriginalAttributedTenantConnectingIp: TenantId=43083d15-7273-40c1-b7db-39efd9ccc17a;Ip=[216.228.118.233];Helo=[mail.nvidia.com] X-MS-Exchange-CrossTenant-AuthSource: BN2PEPF000044AC.namprd04.prod.outlook.com X-MS-Exchange-CrossTenant-AuthAs: Anonymous X-MS-Exchange-CrossTenant-FromEntityHeader: HybridOnPrem X-MS-Exchange-Transport-CrossTenantHeadersStamped: DM4PR12MB5841 Content-Type: text/plain; charset="utf-8" Add fields for interrupt storm handling. Extend structure mlxreg_core_data with the following fields: 'wmark_cntr' - interrupt storm counter. 'wmark_window' - time window to count interrupts to check for storm. Extend structure mlxreg_core_item with the following field: 'storming_bits' - interrupt storming bits mask. Reviewed-by: Vadim Pasternak Signed-off-by: Ciju Rajan K --- include/linux/platform_data/mlxreg.h | 6 ++++++ 1 file changed, 6 insertions(+) diff --git a/include/linux/platform_data/mlxreg.h b/include/linux/platform_= data/mlxreg.h index f6cca7a035c7..453c8dfd7eb9 100644 --- a/include/linux/platform_data/mlxreg.h +++ b/include/linux/platform_data/mlxreg.h @@ -131,6 +131,8 @@ struct mlxreg_hotplug_device { * @regnum: number of registers occupied by multi-register attribute; * @slot: slot number, at which device is located; * @secured: if set indicates that entry access is secured; + * @wmark_cntr: interrupt storm counter; + * @wmark_window: time window to count interrupts to check for storm; */ struct mlxreg_core_data { char label[MLXREG_CORE_LABEL_MAX_SIZE]; @@ -151,6 +153,8 @@ struct mlxreg_core_data { u8 regnum; u8 slot; u8 secured; + unsigned int wmark_cntr; + unsigned long wmark_window; }; =20 /** @@ -167,6 +171,7 @@ struct mlxreg_core_data { * @ind: element's index inside the group; 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Tue, 23 Sep 2025 03:45:04 -0700 Received: from drhqmail203.nvidia.com (10.126.190.182) by drhqmail202.nvidia.com (10.126.190.181) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_256_GCM_SHA384) id 15.2.2562.20; Tue, 23 Sep 2025 03:45:04 -0700 Received: from r-build-bsp-02.mtr.labs.mlnx (10.127.8.9) by mail.nvidia.com (10.126.190.182) with Microsoft SMTP Server id 15.2.2562.20 via Frontend Transport; Tue, 23 Sep 2025 03:45:01 -0700 From: Ciju Rajan K To: , , , , CC: , , , Ciju Rajan K Subject: [PATCH platform-next v2 2/2] [PATCH platform-next 2/2] platform/mellanox: mlxreg-hotplug: Add support for handling interrupt storm Date: Tue, 23 Sep 2025 13:44:52 +0300 Message-ID: <20250923104452.2407460-3-crajank@nvidia.com> X-Mailer: git-send-email 2.47.2 In-Reply-To: <20250923104452.2407460-1-crajank@nvidia.com> References: <20250923104452.2407460-1-crajank@nvidia.com> Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable X-NV-OnPremToCloud: ExternallySecured X-EOPAttributedMessage: 0 X-MS-PublicTrafficType: Email X-MS-TrafficTypeDiagnostic: DS2PEPF00003439:EE_|IA0PR12MB9012:EE_ X-MS-Office365-Filtering-Correlation-Id: fb9e8b3e-7627-4ec6-9f07-08ddfa8e44c8 X-MS-Exchange-SenderADCheck: 1 X-MS-Exchange-AntiSpam-Relay: 0 X-Microsoft-Antispam: BCL:0;ARA:13230040|36860700013|376014|1800799024|82310400026; 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X-OriginatorOrg: Nvidia.com X-MS-Exchange-CrossTenant-OriginalArrivalTime: 23 Sep 2025 10:45:10.1411 (UTC) X-MS-Exchange-CrossTenant-Network-Message-Id: fb9e8b3e-7627-4ec6-9f07-08ddfa8e44c8 X-MS-Exchange-CrossTenant-Id: 43083d15-7273-40c1-b7db-39efd9ccc17a X-MS-Exchange-CrossTenant-OriginalAttributedTenantConnectingIp: TenantId=43083d15-7273-40c1-b7db-39efd9ccc17a;Ip=[216.228.118.232];Helo=[mail.nvidia.com] X-MS-Exchange-CrossTenant-AuthSource: DS2PEPF00003439.namprd02.prod.outlook.com X-MS-Exchange-CrossTenant-AuthAs: Anonymous X-MS-Exchange-CrossTenant-FromEntityHeader: HybridOnPrem X-MS-Exchange-Transport-CrossTenantHeadersStamped: IA0PR12MB9012 Content-Type: text/plain; charset="utf-8" In case of broken hardware, it is possible that broken device will flood interrupt handler with false events. For example, if fan or power supply has damaged presence pin, it will cause permanent generation of plugged in / plugged out events. As a result, interrupt handler will consume a lot of CPU resources and will keep raising "UDEV" events to the user space. This patch provides a mechanism to detect device causing interrupt flooding and mask interrupt for this specific device, to isolate from interrupt handling flow. Use the following criteria: if the specific interrupt was generated 'N' times during 'T' seconds, such device is to be considered as broken and will be closed for getting interrupts. User will be notified through the log error and will be instructed to replace broken device. Reviewed-by: Vadim Pasternak Signed-off-by: Ciju Rajan K --- drivers/platform/mellanox/mlxreg-hotplug.c | 32 ++++++++++++++++++++-- 1 file changed, 30 insertions(+), 2 deletions(-) diff --git a/drivers/platform/mellanox/mlxreg-hotplug.c b/drivers/platform/= mellanox/mlxreg-hotplug.c index d246772aafd6..ae0115ea1fd1 100644 --- a/drivers/platform/mellanox/mlxreg-hotplug.c +++ b/drivers/platform/mellanox/mlxreg-hotplug.c @@ -11,6 +11,7 @@ #include #include #include +#include #include #include #include @@ -30,6 +31,11 @@ #define MLXREG_HOTPLUG_ATTRS_MAX 128 #define MLXREG_HOTPLUG_NOT_ASSERT 3 =20 +/* Interrupt storm definitions */ +#define MLXREG_HOTPLUG_WM_COUNTER 100 +/* Time window in milliseconds */ +#define MLXREG_HOTPLUG_WM_WINDOW_MS 3000 + /** * struct mlxreg_hotplug_priv_data - platform private data: * @irq: platform device interrupt number; @@ -366,11 +372,33 @@ mlxreg_hotplug_work_helper(struct mlxreg_hotplug_priv= _data *priv, for_each_set_bit(bit, &asserted, 8) { int pos; =20 + /* Skip already marked storming bit. */ + if (item->storming_bits & BIT(bit)) + continue; + pos =3D mlxreg_hotplug_item_label_index_get(item->mask, bit); if (pos < 0) goto out; =20 data =3D item->data + pos; + + /* Interrupt storm handling logic. */ + if (data->wmark_cntr =3D=3D 0) + data->wmark_window =3D jiffies + + msecs_to_jiffies(MLXREG_HOTPLUG_WM_WINDOW_MS); + + if (data->wmark_cntr >=3D MLXREG_HOTPLUG_WM_COUNTER - 1) { + if (time_after(data->wmark_window, jiffies)) { + dev_err(priv->dev, + "Storming bit %d (label: %s) - interrupt masked permanently. Replace = broken HW.", + bit, data->label); + /* Mark bit as storming. */ + item->storming_bits |=3D BIT(bit); + continue; + } + data->wmark_cntr =3D 0; + } + data->wmark_cntr++; if (regval & BIT(bit)) { if (item->inversed) mlxreg_hotplug_device_destroy(priv, data, item->kind); @@ -390,9 +418,9 @@ mlxreg_hotplug_work_helper(struct mlxreg_hotplug_priv_d= ata *priv, if (ret) goto out; =20 - /* Unmask event. */ + /* Unmask event, exclude storming bits. */ ret =3D regmap_write(priv->regmap, item->reg + MLXREG_HOTPLUG_MASK_OFF, - item->mask); + item->mask & ~item->storming_bits); =20 out: if (ret) --=20 2.47.2