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X-OriginatorOrg: amd.com X-MS-Exchange-CrossTenant-OriginalArrivalTime: 23 Sep 2025 05:03:47.3808 (UTC) X-MS-Exchange-CrossTenant-Network-Message-Id: f47ccb9d-3f1e-482b-46c5-08ddfa5e941b X-MS-Exchange-CrossTenant-Id: 3dd8961f-e488-4e60-8e11-a82d994e183d X-MS-Exchange-CrossTenant-OriginalAttributedTenantConnectingIp: TenantId=3dd8961f-e488-4e60-8e11-a82d994e183d;Ip=[165.204.84.17];Helo=[satlexmb07.amd.com] X-MS-Exchange-CrossTenant-AuthSource: MWH0EPF000971E5.namprd02.prod.outlook.com X-MS-Exchange-CrossTenant-AuthAs: Anonymous X-MS-Exchange-CrossTenant-FromEntityHeader: HybridOnPrem X-MS-Exchange-Transport-CrossTenantHeadersStamped: CH3PR12MB9028 Content-Type: text/plain; charset="utf-8" The existing guest_apic_protected boolean flag is insufficient for handling different protected guest technologies. While both Intel TDX and AMD SNP (with Secure AVIC) protect the virtual APIC, they use fundamentally different interrupt delivery mechanisms. TDX relies on hardware-managed Posted Interrupts, whereas Secure AVIC requires KVM to perform explicit software-based interrupt injection. The current flag cannot distinguish between these two models. To address this, introduce a new flag, prot_apic_intr_inject. This flag is true for protected guests that require KVM to inject interrupts and false for those that use a hardware-managed delivery mechanism. This preparatory change allows subsequent commits to implement the correct interrupt handling logic for Secure AVIC. Signed-off-by: Neeraj Upadhyay --- arch/x86/kvm/lapic.h | 5 ++++- 1 file changed, 4 insertions(+), 1 deletion(-) diff --git a/arch/x86/kvm/lapic.h b/arch/x86/kvm/lapic.h index 72de14527698..f48218fd4638 100644 --- a/arch/x86/kvm/lapic.h +++ b/arch/x86/kvm/lapic.h @@ -70,7 +70,10 @@ struct kvm_lapic { bool irr_pending; bool lvt0_in_nmi_mode; /* Select registers in the vAPIC cannot be read/written. */ - bool guest_apic_protected; + struct { + bool guest_apic_protected; + bool prot_apic_intr_inject; + }; /* Number of bits set in ISR. */ s16 isr_count; /* The highest vector set in ISR; if -1 - invalid, must scan ISR. */ --=20 2.34.1 From nobody Thu Oct 2 03:27:31 2025 Received: from SA9PR02CU001.outbound.protection.outlook.com (mail-southcentralusazon11013068.outbound.protection.outlook.com [40.93.196.68]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id ECCCD2594B9; Tue, 23 Sep 2025 05:04:20 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; 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Mon, 22 Sep 2025 22:03:59 -0700 From: Neeraj Upadhyay To: , , CC: , , , , , , , , , , Subject: [RFC PATCH v2 02/17] x86/cpufeatures: Add Secure AVIC CPU feature Date: Tue, 23 Sep 2025 10:33:02 +0530 Message-ID: <20250923050317.205482-3-Neeraj.Upadhyay@amd.com> X-Mailer: git-send-email 2.34.1 In-Reply-To: <20250923050317.205482-1-Neeraj.Upadhyay@amd.com> References: <20250923050317.205482-1-Neeraj.Upadhyay@amd.com> Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable X-ClientProxiedBy: satlexmb07.amd.com (10.181.42.216) To satlexmb07.amd.com (10.181.42.216) X-EOPAttributedMessage: 0 X-MS-PublicTrafficType: Email X-MS-TrafficTypeDiagnostic: MWH0EPF000971E6:EE_|CH3PR12MB8934:EE_ X-MS-Office365-Filtering-Correlation-Id: 14ed459a-a94e-4c7a-b451-08ddfa5ea395 X-MS-Exchange-SenderADCheck: 1 X-MS-Exchange-AntiSpam-Relay: 0 X-Microsoft-Antispam: BCL:0;ARA:13230040|36860700013|1800799024|376014|82310400026; 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X-OriginatorOrg: amd.com X-MS-Exchange-CrossTenant-OriginalArrivalTime: 23 Sep 2025 05:04:13.3393 (UTC) X-MS-Exchange-CrossTenant-Network-Message-Id: 14ed459a-a94e-4c7a-b451-08ddfa5ea395 X-MS-Exchange-CrossTenant-Id: 3dd8961f-e488-4e60-8e11-a82d994e183d X-MS-Exchange-CrossTenant-OriginalAttributedTenantConnectingIp: TenantId=3dd8961f-e488-4e60-8e11-a82d994e183d;Ip=[165.204.84.17];Helo=[satlexmb07.amd.com] X-MS-Exchange-CrossTenant-AuthSource: MWH0EPF000971E6.namprd02.prod.outlook.com X-MS-Exchange-CrossTenant-AuthAs: Anonymous X-MS-Exchange-CrossTenant-FromEntityHeader: HybridOnPrem X-MS-Exchange-Transport-CrossTenantHeadersStamped: CH3PR12MB8934 Content-Type: text/plain; charset="utf-8" Add CPU feature detection for Secure AVIC. The Secure AVIC feature provides hardware acceleration for performance sensitive APIC accesses and support for managing guest-owned APIC state for the SEV-SNP guests. Signed-off-by: Kishon Vijay Abraham I Signed-off-by: Neeraj Upadhyay --- arch/x86/include/asm/cpufeatures.h | 1 + 1 file changed, 1 insertion(+) diff --git a/arch/x86/include/asm/cpufeatures.h b/arch/x86/include/asm/cpuf= eatures.h index 06fc0479a23f..d855825b1b9e 100644 --- a/arch/x86/include/asm/cpufeatures.h +++ b/arch/x86/include/asm/cpufeatures.h @@ -449,6 +449,7 @@ #define X86_FEATURE_DEBUG_SWAP (19*32+14) /* "debug_swap" SEV-ES full deb= ug state swap support */ #define X86_FEATURE_RMPREAD (19*32+21) /* RMPREAD instruction */ #define X86_FEATURE_SEGMENTED_RMP (19*32+23) /* Segmented RMP support */ +#define X86_FEATURE_SECURE_AVIC (19*32+26) /* Secure AVIC */ #define X86_FEATURE_ALLOWED_SEV_FEATURES (19*32+27) /* Allowed SEV Feature= s */ #define X86_FEATURE_SVSM (19*32+28) /* "svsm" SVSM present */ #define X86_FEATURE_HV_INUSE_WR_ALLOWED (19*32+30) /* Allow Write to in-us= e hypervisor-owned pages */ --=20 2.34.1 From nobody Thu Oct 2 03:27:31 2025 Received: from PH0PR06CU001.outbound.protection.outlook.com (mail-westus3azon11011057.outbound.protection.outlook.com [40.107.208.57]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id F229026E16F; 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X-OriginatorOrg: amd.com X-MS-Exchange-CrossTenant-OriginalArrivalTime: 23 Sep 2025 05:04:34.5338 (UTC) X-MS-Exchange-CrossTenant-Network-Message-Id: 91da916c-10f8-4747-6076-08ddfa5eb037 X-MS-Exchange-CrossTenant-Id: 3dd8961f-e488-4e60-8e11-a82d994e183d X-MS-Exchange-CrossTenant-OriginalAttributedTenantConnectingIp: TenantId=3dd8961f-e488-4e60-8e11-a82d994e183d;Ip=[165.204.84.17];Helo=[satlexmb07.amd.com] X-MS-Exchange-CrossTenant-AuthSource: MWH0EPF000971E5.namprd02.prod.outlook.com X-MS-Exchange-CrossTenant-AuthAs: Anonymous X-MS-Exchange-CrossTenant-FromEntityHeader: HybridOnPrem X-MS-Exchange-Transport-CrossTenantHeadersStamped: PH7PR12MB5596 Content-Type: text/plain; charset="utf-8" Add support to KVM for determining if a system is capable of supporting Secure AVIC feature. Secure AVIC feature support is determined based on: - secure_avic module parameter is set. - X86_FEATURE_SECURE_AVIC CPU feature bit is set. - SNP feature is supported. Co-developed-by: Kishon Vijay Abraham I Signed-off-by: Kishon Vijay Abraham I Signed-off-by: Neeraj Upadhyay --- arch/x86/include/asm/svm.h | 1 + arch/x86/kvm/svm/sev.c | 9 +++++++++ 2 files changed, 10 insertions(+) diff --git a/arch/x86/include/asm/svm.h b/arch/x86/include/asm/svm.h index ffc27f676243..ab3d55654c77 100644 --- a/arch/x86/include/asm/svm.h +++ b/arch/x86/include/asm/svm.h @@ -299,6 +299,7 @@ static_assert((X2AVIC_MAX_PHYSICAL_ID & AVIC_PHYSICAL_M= AX_INDEX_MASK) =3D=3D X2AVIC_ #define SVM_SEV_FEAT_RESTRICTED_INJECTION BIT(3) #define SVM_SEV_FEAT_ALTERNATE_INJECTION BIT(4) #define SVM_SEV_FEAT_DEBUG_SWAP BIT(5) +#define SVM_SEV_FEAT_SECURE_AVIC BIT(16) =20 #define VMCB_ALLOWED_SEV_FEATURES_VALID BIT_ULL(63) =20 diff --git a/arch/x86/kvm/svm/sev.c b/arch/x86/kvm/svm/sev.c index 5bac4d20aec0..b2eae102681c 100644 --- a/arch/x86/kvm/svm/sev.c +++ b/arch/x86/kvm/svm/sev.c @@ -59,6 +59,10 @@ static bool sev_es_debug_swap_enabled =3D true; module_param_named(debug_swap, sev_es_debug_swap_enabled, bool, 0444); static u64 sev_supported_vmsa_features; =20 +/* enable/disable SEV-SNP Secure AVIC support */ +bool sev_snp_savic_enabled =3D true; +module_param_named(secure_avic, sev_snp_savic_enabled, bool, 0444); + #define AP_RESET_HOLD_NONE 0 #define AP_RESET_HOLD_NAE_EVENT 1 #define AP_RESET_HOLD_MSR_PROTO 2 @@ -2911,6 +2915,8 @@ void __init sev_set_cpu_caps(void) kvm_cpu_cap_set(X86_FEATURE_SEV_SNP); kvm_caps.supported_vm_types |=3D BIT(KVM_X86_SNP_VM); } + if (sev_snp_savic_enabled) + kvm_cpu_cap_set(X86_FEATURE_SECURE_AVIC); } =20 static bool is_sev_snp_initialized(void) @@ -3075,6 +3081,9 @@ void __init sev_hardware_setup(void) !cpu_feature_enabled(X86_FEATURE_NO_NESTED_DATA_BP)) sev_es_debug_swap_enabled =3D false; =20 + if (!sev_snp_supported || !cpu_feature_enabled(X86_FEATURE_SECURE_AVIC)) + sev_snp_savic_enabled =3D false; + sev_supported_vmsa_features =3D 0; if (sev_es_debug_swap_enabled) sev_supported_vmsa_features |=3D SVM_SEV_FEAT_DEBUG_SWAP; --=20 2.34.1 From nobody Thu Oct 2 03:27:31 2025 Received: from BL0PR03CU003.outbound.protection.outlook.com (mail-eastusazon11012050.outbound.protection.outlook.com [52.101.53.50]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id 2AA78274671; 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X-OriginatorOrg: amd.com X-MS-Exchange-CrossTenant-OriginalArrivalTime: 23 Sep 2025 05:04:44.8087 (UTC) X-MS-Exchange-CrossTenant-Network-Message-Id: de20d218-9808-460c-2781-08ddfa5eb657 X-MS-Exchange-CrossTenant-Id: 3dd8961f-e488-4e60-8e11-a82d994e183d X-MS-Exchange-CrossTenant-OriginalAttributedTenantConnectingIp: TenantId=3dd8961f-e488-4e60-8e11-a82d994e183d;Ip=[165.204.84.17];Helo=[satlexmb07.amd.com] X-MS-Exchange-CrossTenant-AuthSource: MWH0EPF000971E5.namprd02.prod.outlook.com X-MS-Exchange-CrossTenant-AuthAs: Anonymous X-MS-Exchange-CrossTenant-FromEntityHeader: HybridOnPrem X-MS-Exchange-Transport-CrossTenantHeadersStamped: IA0PR12MB8277 Content-Type: text/plain; charset="utf-8" Secure AVIC provides a hardware-backed, protected virtual APIC for SNP guests. When this feature is active, KVM cannot directly access the virtual APIC state and must use software-based interrupt injection to deliver interrupts to the guest. Introduce a helper, sev_savic_active(), to detect when a VM has Secure AVIC enabled based on its VMSA features. At vCPU creation time, use this helper to set the appropriate APIC flags: - guest_apic_protected is set to true, as the APIC state is not visible to KVM. - prot_apic_intr_inject is set to true to signal that the software injection path must be used for interrupt delivery. This ensures that the core APIC code can correctly identify and handle Secure AVIC guests. This is only an initialization commit and actual support for creating Secure AVIC enabled guests and injecting interrupts will be added in later commits. Signed-off-by: Neeraj Upadhyay --- arch/x86/kvm/svm/svm.c | 5 +++++ arch/x86/kvm/svm/svm.h | 5 +++++ 2 files changed, 10 insertions(+) diff --git a/arch/x86/kvm/svm/svm.c b/arch/x86/kvm/svm/svm.c index 8a66e2e985a4..064ec98d7e67 100644 --- a/arch/x86/kvm/svm/svm.c +++ b/arch/x86/kvm/svm/svm.c @@ -1300,6 +1300,11 @@ static int svm_vcpu_create(struct kvm_vcpu *vcpu) if (err) goto error_free_vmsa_page; =20 + if (sev_savic_active(vcpu->kvm)) { + vcpu->arch.apic->guest_apic_protected =3D true; + vcpu->arch.apic->prot_apic_intr_inject =3D true; + } + svm->msrpm =3D svm_vcpu_alloc_msrpm(); if (!svm->msrpm) { err =3D -ENOMEM; diff --git a/arch/x86/kvm/svm/svm.h b/arch/x86/kvm/svm/svm.h index 70df7c6413cf..1090a48adeda 100644 --- a/arch/x86/kvm/svm/svm.h +++ b/arch/x86/kvm/svm/svm.h @@ -869,6 +869,10 @@ void sev_gmem_invalidate(kvm_pfn_t start, kvm_pfn_t en= d); int sev_gmem_max_mapping_level(struct kvm *kvm, kvm_pfn_t pfn, bool is_pri= vate); struct vmcb_save_area *sev_decrypt_vmsa(struct kvm_vcpu *vcpu); void sev_free_decrypted_vmsa(struct kvm_vcpu *vcpu, struct vmcb_save_area = *vmsa); +static inline bool sev_savic_active(struct kvm *kvm) +{ + return to_kvm_sev_info(kvm)->vmsa_features & SVM_SEV_FEAT_SECURE_AVIC; +} #else static inline struct page *snp_safe_alloc_page_node(int node, gfp_t gfp) { @@ -899,6 +903,7 @@ static inline int sev_gmem_max_mapping_level(struct kvm= *kvm, kvm_pfn_t pfn, boo { return 0; } +static inline bool sev_savic_active(struct kvm *kvm) { return false; } =20 static inline struct vmcb_save_area *sev_decrypt_vmsa(struct kvm_vcpu *vcp= u) { --=20 2.34.1 From nobody Thu Oct 2 03:27:31 2025 Received: from BL0PR03CU003.outbound.protection.outlook.com (mail-eastusazon11012047.outbound.protection.outlook.com [52.101.53.47]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id A7AF478F20; Tue, 23 Sep 2025 05:05:05 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; 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X-OriginatorOrg: amd.com X-MS-Exchange-CrossTenant-OriginalArrivalTime: 23 Sep 2025 05:04:59.6418 (UTC) X-MS-Exchange-CrossTenant-Network-Message-Id: 556b5140-4cc4-46fe-ae37-08ddfa5ebf2e X-MS-Exchange-CrossTenant-Id: 3dd8961f-e488-4e60-8e11-a82d994e183d X-MS-Exchange-CrossTenant-OriginalAttributedTenantConnectingIp: TenantId=3dd8961f-e488-4e60-8e11-a82d994e183d;Ip=[165.204.84.17];Helo=[satlexmb07.amd.com] X-MS-Exchange-CrossTenant-AuthSource: MWH0EPF000971E8.namprd02.prod.outlook.com X-MS-Exchange-CrossTenant-AuthAs: Anonymous X-MS-Exchange-CrossTenant-FromEntityHeader: HybridOnPrem X-MS-Exchange-Transport-CrossTenantHeadersStamped: PH7PR12MB6540 Content-Type: text/plain; charset="utf-8" Disable interception for SECURE_AVIC_CONTROL MSR for Secure AVIC enabled guests. The SECURE_AVIC_CONTROL MSR holds the GPA of the guest APIC backing page and bitfields to control enablement of Secure AVIC and whether the guest allows NMIs to be injected by the hypervisor. This MSR is populated by the guest and can be read by the guest to get the GPA of the APIC backing page. The MSR can only be accessed in Secure AVIC mode; accessing it when not in Secure AVIC mode results in #GP. So, KVM should not intercept it. Co-developed-by: Kishon Vijay Abraham I Signed-off-by: Kishon Vijay Abraham I Signed-off-by: Neeraj Upadhyay --- arch/x86/include/asm/msr-index.h | 1 + arch/x86/kvm/svm/sev.c | 6 +++++- 2 files changed, 6 insertions(+), 1 deletion(-) diff --git a/arch/x86/include/asm/msr-index.h b/arch/x86/include/asm/msr-in= dex.h index b65c3ba5fa14..9f16030dd849 100644 --- a/arch/x86/include/asm/msr-index.h +++ b/arch/x86/include/asm/msr-index.h @@ -707,6 +707,7 @@ #define MSR_AMD64_SEG_RMP_ENABLED_BIT 0 #define MSR_AMD64_SEG_RMP_ENABLED BIT_ULL(MSR_AMD64_SEG_RMP_ENABLED_BIT) #define MSR_AMD64_RMP_SEGMENT_SHIFT(x) (((x) & GENMASK_ULL(13, 8)) >> 8) +#define MSR_AMD64_SAVIC_CONTROL 0xc0010138 =20 #define MSR_SVSM_CAA 0xc001f000 =20 diff --git a/arch/x86/kvm/svm/sev.c b/arch/x86/kvm/svm/sev.c index b2eae102681c..afe4127a1918 100644 --- a/arch/x86/kvm/svm/sev.c +++ b/arch/x86/kvm/svm/sev.c @@ -4487,7 +4487,8 @@ void sev_vcpu_after_set_cpuid(struct vcpu_svm *svm) =20 static void sev_es_init_vmcb(struct vcpu_svm *svm) { - struct kvm_sev_info *sev =3D to_kvm_sev_info(svm->vcpu.kvm); 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X-OriginatorOrg: amd.com X-MS-Exchange-CrossTenant-OriginalArrivalTime: 23 Sep 2025 05:05:15.7252 (UTC) X-MS-Exchange-CrossTenant-Network-Message-Id: 489abcfd-5460-4d0e-6452-08ddfa5ec8c1 X-MS-Exchange-CrossTenant-Id: 3dd8961f-e488-4e60-8e11-a82d994e183d X-MS-Exchange-CrossTenant-OriginalAttributedTenantConnectingIp: TenantId=3dd8961f-e488-4e60-8e11-a82d994e183d;Ip=[165.204.84.17];Helo=[satlexmb07.amd.com] X-MS-Exchange-CrossTenant-AuthSource: MWH0EPF000971E5.namprd02.prod.outlook.com X-MS-Exchange-CrossTenant-AuthAs: Anonymous X-MS-Exchange-CrossTenant-FromEntityHeader: HybridOnPrem X-MS-Exchange-Transport-CrossTenantHeadersStamped: BY5PR12MB4081 Content-Type: text/plain; charset="utf-8" For AMD SEV-SNP guests with Secure AVIC, the virtual APIC state is not visible to KVM and managed by the hardware. This renders the traditional interrupt injection mechanism, which directly modifies guest state, unusable. Instead, interrupt delivery must be mediated through a new interface in the VMCB. Implement support for this mechanism. First, new VMCB control fields, requested_irr and update_irr, are defined to allow KVM to communicate pending interrupts to the hardware before VMRUN. Hook the core interrupt injection path, svm_inject_irq(). Instead of injecting directly, transfer pending interrupts from KVM's software IRR to the new requested_irr VMCB field and delegate final delivery to the hardware. Since the hardware is now responsible for the timing and delivery of interrupts to the guest (including managing the guest's RFLAGS.IF and vAPIC state), bypass the standard KVM interrupt window checks in svm_interrupt_allowed() and svm_enable_irq_window(). Similarly, interrupt re-injection is handled by the hardware and requires no explicit KVM involvement. Finally, update the logic for detecting pending interrupts. Add the vendor op, protected_apic_has_interrupt(), to check only KVM's software vAPIC IRR state. Co-developed-by: Kishon Vijay Abraham I Signed-off-by: Kishon Vijay Abraham I Signed-off-by: Neeraj Upadhyay --- arch/x86/include/asm/svm.h | 8 +++++-- arch/x86/kvm/lapic.c | 17 ++++++++++++--- arch/x86/kvm/svm/sev.c | 44 ++++++++++++++++++++++++++++++++++++++ arch/x86/kvm/svm/svm.c | 13 +++++++++++ arch/x86/kvm/svm/svm.h | 4 ++++ arch/x86/kvm/x86.c | 15 ++++++++++++- 6 files changed, 95 insertions(+), 6 deletions(-) diff --git a/arch/x86/include/asm/svm.h b/arch/x86/include/asm/svm.h index ab3d55654c77..0faf262f9f9f 100644 --- a/arch/x86/include/asm/svm.h +++ b/arch/x86/include/asm/svm.h @@ -162,10 +162,14 @@ struct __attribute__ ((__packed__)) vmcb_control_area= { u64 vmsa_pa; /* Used for an SEV-ES guest */ u8 reserved_8[16]; u16 bus_lock_counter; /* Offset 0x120 */ - u8 reserved_9[22]; + u8 reserved_9[18]; + u8 update_irr; /* Offset 0x134 */ + u8 reserved_10[3]; u64 allowed_sev_features; /* Offset 0x138 */ u64 guest_sev_features; /* Offset 0x140 */ - u8 reserved_10[664]; + u8 reserved_11[8]; + u32 requested_irr[8]; /* Offset 0x150 */ + u8 reserved_12[624]; /* * Offset 0x3e0, 32 bytes reserved * for use by hypervisor/software. diff --git a/arch/x86/kvm/lapic.c b/arch/x86/kvm/lapic.c index 5fc437341e03..3199c7c6db05 100644 --- a/arch/x86/kvm/lapic.c +++ b/arch/x86/kvm/lapic.c @@ -2938,11 +2938,22 @@ int kvm_apic_has_interrupt(struct kvm_vcpu *vcpu) if (!kvm_apic_present(vcpu)) return -1; =20 - if (apic->guest_apic_protected) + if (!apic->guest_apic_protected) { + __apic_update_ppr(apic, &ppr); + return apic_has_interrupt_for_ppr(apic, ppr); + } + + if (!apic->prot_apic_intr_inject) return -1; =20 - __apic_update_ppr(apic, &ppr); - return apic_has_interrupt_for_ppr(apic, ppr); + /* + * For guest-protected virtual APIC, hardware manages the virtual + * PPR and interrupt delivery to the guest. So, checking the KVM + * managed virtual APIC's APIC_IRR state for any pending vectors + * is the only thing required here. + */ + return apic_search_irr(apic); + } EXPORT_SYMBOL_GPL(kvm_apic_has_interrupt); =20 diff --git a/arch/x86/kvm/svm/sev.c b/arch/x86/kvm/svm/sev.c index afe4127a1918..78cefc14a2ee 100644 --- a/arch/x86/kvm/svm/sev.c +++ b/arch/x86/kvm/svm/sev.c @@ -28,6 +28,7 @@ #include #include #include +#include =20 #include "mmu.h" #include "x86.h" @@ -35,6 +36,7 @@ #include "svm_ops.h" #include "cpuid.h" #include "trace.h" +#include "lapic.h" =20 #define GHCB_VERSION_MAX 2ULL #define GHCB_VERSION_DEFAULT 2ULL @@ -5064,3 +5066,45 @@ void sev_free_decrypted_vmsa(struct kvm_vcpu *vcpu, = struct vmcb_save_area *vmsa) =20 free_page((unsigned long)vmsa); } + +void sev_savic_set_requested_irr(struct vcpu_svm *svm, bool reinjected) +{ + unsigned int i, vec, vec_pos, vec_start; + struct kvm_lapic *apic; + bool has_interrupts; + u32 val; + + /* Secure AVIC HW takes care of re-injection */ + if (reinjected) + return; + + apic =3D svm->vcpu.arch.apic; + has_interrupts =3D false; + + for (i =3D 0; i < ARRAY_SIZE(svm->vmcb->control.requested_irr); i++) { + val =3D apic_get_reg(apic->regs, APIC_IRR + i * 0x10); + if (!val) + continue; + has_interrupts =3D true; + svm->vmcb->control.requested_irr[i] |=3D val; + vec_start =3D i * 32; + /* + * Clear each vector one by one to avoid race with concurrent + * APIC_IRR updates from the deliver_interrupt() path. + */ + do { + vec_pos =3D __ffs(val); + vec =3D vec_start + vec_pos; + apic_clear_vector(vec, apic->regs + APIC_IRR); + val =3D val & ~BIT(vec_pos); + } while (val); + } + + if (has_interrupts) + svm->vmcb->control.update_irr |=3D BIT(0); +} + +bool sev_savic_has_pending_interrupt(struct kvm_vcpu *vcpu) +{ + return kvm_apic_has_interrupt(vcpu) !=3D -1; +} diff --git a/arch/x86/kvm/svm/svm.c b/arch/x86/kvm/svm/svm.c index 064ec98d7e67..7811a87bc111 100644 --- a/arch/x86/kvm/svm/svm.c +++ b/arch/x86/kvm/svm/svm.c @@ -52,6 +52,8 @@ #include "svm.h" #include "svm_ops.h" =20 +#include "lapic.h" + #include "kvm_onhyperv.h" #include "svm_onhyperv.h" =20 @@ -3689,6 +3691,9 @@ static void svm_inject_irq(struct kvm_vcpu *vcpu, boo= l reinjected) struct vcpu_svm *svm =3D to_svm(vcpu); u32 type; =20 + if (sev_savic_active(vcpu->kvm)) + return sev_savic_set_requested_irr(svm, reinjected); + if (vcpu->arch.interrupt.soft) { if (svm_update_soft_interrupt_rip(vcpu)) return; @@ -3870,6 +3875,9 @@ static int svm_interrupt_allowed(struct kvm_vcpu *vcp= u, bool for_injection) { struct vcpu_svm *svm =3D to_svm(vcpu); =20 + if (sev_savic_active(vcpu->kvm)) + return 1; + if (svm->nested.nested_run_pending) return -EBUSY; =20 @@ -3890,6 +3898,9 @@ static void svm_enable_irq_window(struct kvm_vcpu *vc= pu) { struct vcpu_svm *svm =3D to_svm(vcpu); =20 + if (sev_savic_active(vcpu->kvm)) + return; + /* * In case GIF=3D0 we can't rely on the CPU to tell us when GIF becomes * 1, because that's a separate STGI/VMRUN intercept. The next time we @@ -5132,6 +5143,8 @@ static struct kvm_x86_ops svm_x86_ops __initdata =3D { .apicv_post_state_restore =3D avic_apicv_post_state_restore, .required_apicv_inhibits =3D AVIC_REQUIRED_APICV_INHIBITS, =20 + .protected_apic_has_interrupt =3D sev_savic_has_pending_interrupt, + .get_exit_info =3D svm_get_exit_info, .get_entry_info =3D svm_get_entry_info, =20 diff --git a/arch/x86/kvm/svm/svm.h b/arch/x86/kvm/svm/svm.h index 1090a48adeda..60dc424d62c4 100644 --- a/arch/x86/kvm/svm/svm.h +++ b/arch/x86/kvm/svm/svm.h @@ -873,6 +873,8 @@ static inline bool sev_savic_active(struct kvm *kvm) { return to_kvm_sev_info(kvm)->vmsa_features & SVM_SEV_FEAT_SECURE_AVIC; } +void sev_savic_set_requested_irr(struct vcpu_svm *svm, bool reinjected); +bool sev_savic_has_pending_interrupt(struct kvm_vcpu *vcpu); #else static inline struct page *snp_safe_alloc_page_node(int node, gfp_t gfp) { @@ -910,6 +912,8 @@ static inline struct vmcb_save_area *sev_decrypt_vmsa(s= truct kvm_vcpu *vcpu) return NULL; } static inline void sev_free_decrypted_vmsa(struct kvm_vcpu *vcpu, struct v= mcb_save_area *vmsa) {} +static inline void sev_savic_set_requested_irr(struct vcpu_svm *svm, bool = reinjected) {} +static inline bool sev_savic_has_pending_interrupt(struct kvm_vcpu *vcpu) = { return false; } #endif =20 /* vmenter.S */ diff --git a/arch/x86/kvm/x86.c b/arch/x86/kvm/x86.c index 33fba801b205..65ebdc6deb92 100644 --- a/arch/x86/kvm/x86.c +++ b/arch/x86/kvm/x86.c @@ -10369,7 +10369,20 @@ static int kvm_check_and_inject_events(struct kvm_= vcpu *vcpu, if (r < 0) goto out; if (r) { - int irq =3D kvm_cpu_get_interrupt(vcpu); + int irq; + + /* + * Do not ack the interrupt here for guest-protected VAPIC + * which requires interrupt injection to the guest. + * + * ->inject_irq reads the KVM's VAPIC's APIC_IRR state and + * clears it. + */ + if (vcpu->arch.apic->guest_apic_protected && + vcpu->arch.apic->prot_apic_intr_inject) + irq =3D kvm_apic_has_interrupt(vcpu); + else + irq =3D kvm_cpu_get_interrupt(vcpu); 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X-OriginatorOrg: amd.com X-MS-Exchange-CrossTenant-OriginalArrivalTime: 23 Sep 2025 05:05:29.6717 (UTC) X-MS-Exchange-CrossTenant-Network-Message-Id: 07590adb-0de4-4c39-629e-08ddfa5ed113 X-MS-Exchange-CrossTenant-Id: 3dd8961f-e488-4e60-8e11-a82d994e183d X-MS-Exchange-CrossTenant-OriginalAttributedTenantConnectingIp: TenantId=3dd8961f-e488-4e60-8e11-a82d994e183d;Ip=[165.204.84.17];Helo=[satlexmb07.amd.com] X-MS-Exchange-CrossTenant-AuthSource: SJ5PEPF000001D6.namprd05.prod.outlook.com X-MS-Exchange-CrossTenant-AuthAs: Anonymous X-MS-Exchange-CrossTenant-FromEntityHeader: HybridOnPrem X-MS-Exchange-Transport-CrossTenantHeadersStamped: CH3PR12MB7761 Content-Type: text/plain; charset="utf-8" Secure AVIC hardware only accelerates Self-IPI, i.e. on WRMSR to APIC_SELF_IPI and APIC_ICR (with destination shorthand equal to "self") registers, hardware takes care of updating the APIC_IRR in the guest-owned APIC backing page of the vCPU. For other IPI types (cross-vCPU, broadcast IPIs), software needs to take care of updating the APIC_IRR state in the target vCPUs' APIC backing page and to ensure that the target vCPU notices the new pending interrupt. To ensure that the remote vCPU notices the new pending interrupt, the guest sends a APIC_ICR MSR-write GHCB protocol event to the hypervisor. Handle the APIC_ICR write MSR exits for Secure AVIC guests by either sending an AVIC doorbell (if the target vCPU is running) or by waking up the non-running target vCPU thread. To ensure that the target vCPU observes the new IPI request, introduce a new per-vcpu flag, sev_savic_has_pending_ipi. This flag acts as a reliable "sticky bit" that signals a pending IPI, ensuring the event is not lost even if the primary wakeup mechanism is missed. Update sev_savic_has_pending_interrupt() to return true if sev_savic_has_pending_ipi is set. This ensures that when a vCPU is about to block (in kvm_vcpu_block()), it correctly recognizes that it has work to do and will not go to sleep. Clear the sev_savic_has_pending_ipi flag in pre_sev_run() just before the next VM-entry. This resets the one-shot signal, as the pending interrupt is now about to be processed by the hardware upon VMRUN. During APIC_ICR write GHCB request handling, unconditionally set sev_savic_has_pending_ipi for the target vCPU irrespective of whether the target vCPU is in guest mode or not. If the target vCPU does not take any other VMEXIT before taking next hlt exit, the vCPU blocking fails as sev_savic_has_pending_ipi remains set. The sev_savic_has_pending_ipi is cleared before next VMRUN and on subsequent hlt exit the vCPU thread would block. Following are the race conditions which can occur between target vCPU doing hlt and the source vCPU's IPI request handling. a. VMEXIT before HLT when RFLAGS.IF =3D 0 or Interrupt shadow is active. #Source-vCPU #Target-VCPU 1. sev_savic_has_pending_ipi =3D true 2. smp_mb(); 3. Disable interrupts 4. Target vCPU is in guest mode 5. Raise AVIC doorbell to target vCPU's physical APIC_ID 6. VMEXIT 7. sev_savic_has_pending_ipi =3D false 8. VMRUN 9. HLT 10. VMEXIT 11. kvm_arch_vcpu_runnable() returns false 12. vCPU thread blocks In this scenario IDLE HLT intercept ensures that the target vCPU does not take hlt intercept as V_INTR is set (AVIC doorbell by source vCPU triggers evaluation of Secure AVIC backing page of the target vCPU and sets V_INTR). b. Target vCPU takes HLT VMEXIT but hasn't cleared IN_GUEST_MODE at the time when doorbell write is issued by source CPU. #Source-vCPU #Target-VCPU 1. sev_savic_has_pending_ipi =3D true 2. smp_mb(); 3. Target vCPU is in guest mode 4. HLT 5. VMEXIT 6. Raise AVIC doorbell to the target physical CPU. 7. vcpu->mode =3D OUTSIDE_GUEST_MODE 8. kvm_cpu_has_interrupt() protected_..._interrupt() smp_mb() sev_savic_has_pending_ipi is true In this case, the smp_mb() barriers at 2, 8 guarantee that the target vCPU's thread observes sev_savic_has_pending_ipi is set and returns to the guest mode without blocking. c. For other cases, where the source vCPU thread observes the target vCPU to be outside of the guest mode, memory barriers in rcuwait_wake_up() (source vCPU thread) and set_current_state() (target vCPU thread) provides the required ordering and ensures that read of sev_savic_has_pending_ipi in kvm_vcpu_check_block() observes the write by the source vCPU. #Source-vCPU #Target-VCPU rcuwait_wake_up() smp_mb() task =3D rcu_dereference(w->task); if (task) wake_up_process() prepare_to_rcuwait() w->task =3D current set_current_state( TASK_INTERRUPTIBLE) smp_mb() kvm_vcpu_check_block() kvm_cpu_has_interrupt() Co-developed-by: Kishon Vijay Abraham I Signed-off-by: Kishon Vijay Abraham I Signed-off-by: Neeraj Upadhyay --- arch/x86/kvm/svm/sev.c | 218 ++++++++++++++++++++++++++++++++++++++++- arch/x86/kvm/svm/svm.h | 2 + 2 files changed, 219 insertions(+), 1 deletion(-) diff --git a/arch/x86/kvm/svm/sev.c b/arch/x86/kvm/svm/sev.c index 78cefc14a2ee..a64fcc7637c7 100644 --- a/arch/x86/kvm/svm/sev.c +++ b/arch/x86/kvm/svm/sev.c @@ -3511,6 +3511,89 @@ int pre_sev_run(struct vcpu_svm *svm, int cpu) if (!cpumask_test_cpu(cpu, to_kvm_sev_info(kvm)->have_run_cpus)) cpumask_set_cpu(cpu, to_kvm_sev_info(kvm)->have_run_cpus); =20 + /* + * It should be safe to clear sev_savic_has_pending_ipi here. + * + * Following are the scenarios possible: + * + * Scenario 1: sev_savic_has_pending_ipi is set before hlt exit of the + * target vCPU. + * + * Source vCPU Target vCPU + * + * 1. Set APIC_IRR of target + * vCPU. + * + * 2. VMGEXIT + * + * 3. Set ...has_pending_ipi + * + * savic_handle_icr_write() + * ..._has_pending_ipi =3D true + * + * 4. avic_ring_doorbell() + * - VS - + * + * 4. VMEXIT + * + * 5. ..._has_pending_ipi =3D false + * + * 6. VM entry + * + * 7. hlt exit + * + * In this case, any VM exit taken by target vCPU before hlt exit + * clears sev_savic_has_pending_ipi. On hlt exit, idle halt intercept + * would find the V_INTR set and skip hlt exit. + * + * Scenario 2: sev_savic_has_pending_ipi is set when target vCPU + * has taken hlt exit. + * + * Source vCPU Target vCPU + * + * 1. hlt exit + * + * 2. Set ...has_pending_ipi + * 3. kvm_vcpu_has_events() returns true + * and VM is reentered. + * + * vcpu_block() + * kvm_arch_vcpu_runnable() + * kvm_vcpu_has_events() + * + * + * 4. On VM entry, APIC_IRR state is re-e= valuated + * and V_INTR is set and interrupt is = delivered + * to vCPU. + * + * + * Scenario 3: sev_savic_has_pending_ipi is set while halt exit is happen= ing: + * + * + * Source vCPU Target vCPU + * + * 1. hlt + * Hardware check V_INTR to determi= ne + * if hlt exit need to be taken. No= other + * exit such as intr exit can be ta= ken + * while this sequence is being exe= cuted. + * + * 2. Set APIC_IRR of target vCPU. + * + * 3. Set ...has_pending_ipi + * 4. hlt exit taken. + * + * 5. ...has_pending_ipi being set is ob= served + * by target vCPU and the vCPU is res= umed. + * + * In this scenario, hardware ensures that target vCPU does not take any = exit + * between checking V_INTR state and halt exit. So, sev_savic_has_pending= _ipi + * remains set when vCPU takes hlt exit. + */ + if (READ_ONCE(svm->sev_savic_has_pending_ipi)) + WRITE_ONCE(svm->sev_savic_has_pending_ipi, false); + /* Assign the asid allocated with this SEV guest */ svm->asid =3D asid; =20 @@ -4281,6 +4364,129 @@ static int sev_handle_vmgexit_msr_protocol(struct v= cpu_svm *svm) return 0; } =20 +static void savic_handle_icr_write(struct kvm_vcpu *kvm_vcpu, u64 icr) +{ + struct kvm *kvm =3D kvm_vcpu->kvm; + struct kvm_vcpu *vcpu; + u32 icr_low, icr_high; + bool in_guest_mode; + unsigned long i; + + icr_low =3D lower_32_bits(icr); + icr_high =3D upper_32_bits(icr); + + /* + * TODO: Instead of scanning all the vCPUS, get fastpath working which sh= ould + * look similar to avic_kick_target_vcpus_fast(). + */ + kvm_for_each_vcpu(i, vcpu, kvm) { + if (!kvm_apic_match_dest(vcpu, kvm_vcpu->arch.apic, icr_low & APIC_SHORT= _MASK, + icr_high, icr_low & APIC_DEST_MASK)) + continue; + + /* + * Setting sev_savic_has_pending_ipi could result in a spurious + * return from hlt (as kvm_cpu_has_interrupt() would return true) + * if destination CPU is in guest mode and the guest takes a hlt + * exit after handling the IPI. sev_savic_has_pending_ipi gets cleared + * on VM entry, so there can be at most one spurious return per IPI. + * For vcpu->mode =3D=3D IN_GUEST_MODE, sev_savic_has_pending_ipi need + * to be set to handle the case where the destination vCPU has taken + * hlt exit and the source CPU has not observed (target)vcpu->mode !=3D + * IN_GUEST_MODE. + */ + WRITE_ONCE(to_svm(vcpu)->sev_savic_has_pending_ipi, true); + /* Order sev_savic_has_pending_ipi write and vcpu->mode read. */ + smp_mb(); + /* Pairs with smp_store_release in vcpu_enter_guest. */ + in_guest_mode =3D (smp_load_acquire(&vcpu->mode) =3D=3D IN_GUEST_MODE); + if (in_guest_mode) { + /* + * Signal the doorbell to tell hardware to inject the IRQ. + * + * If the vCPU exits the guest before the doorbell chimes, + * below memory ordering guarantees that the destination vCPU + * observes sev_savic_has_pending_ipi =3D=3D true before + * blocking. + * + * Src-CPU Dest-CPU + * + * savic_handle_icr_write() + * sev_savic_has_pending_ipi =3D true + * smp_mb() + * smp_load_acquire(&vcpu->mode) + * + * - VS - + * vcpu->mode =3D OUTSIDE_GUEST_MODE + * __kvm_emulate_halt() + * kvm_cpu_has_interrupt() + * smp_mb() + * if (sev_savic_has_pending_ipi) + * return true; + * + * [S1] + * sev_savic_has_pending_ipi =3D true + * + * SMP_MB + * + * [L1] + * vcpu->mode + * [S2] + * vcpu->mode =3D OUTSIDE_GUEST_MODE + * + * + * SMP_MB + * + * [L2] sev_savic_has_pending_ipi =3D= =3D true + * + * exists (L1=3DIN_GUEST_MODE /\ L2=3Dfalse) + * + * Above condition does not exit. So, if the source CPU observes + * vcpu->mode =3D IN_GUEST_MODE (L1), sev_savic_has_pending_ipi load = by + * the destination CPU (L2) should observe the store (S1) from the + * source CPU. + */ + avic_ring_doorbell(vcpu); + } else { + /* + * Wakeup the vCPU if it was blocking. + * + * Memory ordering is provided by smp_mb() in rcuwait_wake_up() on the + * source CPU and smp_mb() in set_current_state() inside kvm_vcpu_block= () + * on the destination CPU. + */ + kvm_vcpu_kick(vcpu); + } + } +} + +static bool savic_handle_msr_exit(struct kvm_vcpu *vcpu) +{ + u32 msr, reg; + + msr =3D kvm_rcx_read(vcpu); + reg =3D (msr - APIC_BASE_MSR) << 4; + + switch (reg) { + case APIC_ICR: + /* + * Only APIC_ICR WRMSR requires special handling for Secure AVIC + * guests to wake up destination vCPUs. + */ + if (to_svm(vcpu)->vmcb->control.exit_info_1) { + u64 data =3D kvm_read_edx_eax(vcpu); + + savic_handle_icr_write(vcpu, data); + return true; + } + break; + default: + break; + } + + return false; +} + int sev_handle_vmgexit(struct kvm_vcpu *vcpu) { struct vcpu_svm *svm =3D to_svm(vcpu); @@ -4419,6 +4625,11 @@ int sev_handle_vmgexit(struct kvm_vcpu *vcpu) control->exit_info_1, control->exit_info_2); ret =3D -EINVAL; break; + case SVM_EXIT_MSR: + if (sev_savic_active(vcpu->kvm) && savic_handle_msr_exit(vcpu)) + return 1; + + fallthrough; default: ret =3D svm_invoke_exit_handler(vcpu, exit_code); } @@ -5106,5 +5317,10 @@ void sev_savic_set_requested_irr(struct vcpu_svm *sv= m, bool reinjected) =20 bool sev_savic_has_pending_interrupt(struct kvm_vcpu *vcpu) { - return kvm_apic_has_interrupt(vcpu) !=3D -1; + /* + * See memory ordering description in savic_handle_icr_write(). + */ + smp_mb(); + return READ_ONCE(to_svm(vcpu)->sev_savic_has_pending_ipi) || + kvm_apic_has_interrupt(vcpu) !=3D -1; } diff --git a/arch/x86/kvm/svm/svm.h b/arch/x86/kvm/svm/svm.h index 60dc424d62c4..a3edb6e720cd 100644 --- a/arch/x86/kvm/svm/svm.h +++ b/arch/x86/kvm/svm/svm.h @@ -335,6 +335,8 @@ struct vcpu_svm { =20 /* Guest GIF value, used when vGIF is not enabled */ bool guest_gif; + + bool sev_savic_has_pending_ipi; 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X-OriginatorOrg: amd.com X-MS-Exchange-CrossTenant-OriginalArrivalTime: 23 Sep 2025 05:05:46.8508 (UTC) X-MS-Exchange-CrossTenant-Network-Message-Id: e58eef34-3315-4c31-493d-08ddfa5edb52 X-MS-Exchange-CrossTenant-Id: 3dd8961f-e488-4e60-8e11-a82d994e183d X-MS-Exchange-CrossTenant-OriginalAttributedTenantConnectingIp: TenantId=3dd8961f-e488-4e60-8e11-a82d994e183d;Ip=[165.204.84.17];Helo=[satlexmb07.amd.com] X-MS-Exchange-CrossTenant-AuthSource: MWH0EPF000971E5.namprd02.prod.outlook.com X-MS-Exchange-CrossTenant-AuthAs: Anonymous X-MS-Exchange-CrossTenant-FromEntityHeader: HybridOnPrem X-MS-Exchange-Transport-CrossTenantHeadersStamped: IA1PR12MB6433 Content-Type: text/plain; charset="utf-8" From: Kishon Vijay Abraham I Secure AVIC does not support injecting exception from the hypervisor. Take an early return from svm_inject_exception() for Secure AVIC enabled guests. Hardware takes care of delivering exceptions initiated by the guest as well as re-injecting exceptions initiated by the guest (in case there's an intercept before delivering the exception). Signed-off-by: Kishon Vijay Abraham I Signed-off-by: Neeraj Upadhyay --- arch/x86/kvm/svm/svm.c | 3 +++ 1 file changed, 3 insertions(+) diff --git a/arch/x86/kvm/svm/svm.c b/arch/x86/kvm/svm/svm.c index 7811a87bc111..fdd612c975ae 100644 --- a/arch/x86/kvm/svm/svm.c +++ b/arch/x86/kvm/svm/svm.c @@ -374,6 +374,9 @@ static void svm_inject_exception(struct kvm_vcpu *vcpu) struct kvm_queued_exception *ex =3D &vcpu->arch.exception; struct vcpu_svm *svm =3D to_svm(vcpu); =20 + if (sev_savic_active(vcpu->kvm)) + return; + kvm_deliver_exception_payload(vcpu, ex); =20 if (kvm_exception_is_soft(ex->vector) && --=20 2.34.1 From nobody Thu Oct 2 03:27:32 2025 Received: from SN4PR2101CU001.outbound.protection.outlook.com (mail-southcentralusazon11012070.outbound.protection.outlook.com [40.93.195.70]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id 6FEF2274671; Tue, 23 Sep 2025 05:06:13 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; 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X-OriginatorOrg: amd.com X-MS-Exchange-CrossTenant-OriginalArrivalTime: 23 Sep 2025 05:06:09.1114 (UTC) X-MS-Exchange-CrossTenant-Network-Message-Id: cce6148d-7dec-4efa-ceba-08ddfa5ee896 X-MS-Exchange-CrossTenant-Id: 3dd8961f-e488-4e60-8e11-a82d994e183d X-MS-Exchange-CrossTenant-OriginalAttributedTenantConnectingIp: TenantId=3dd8961f-e488-4e60-8e11-a82d994e183d;Ip=[165.204.84.17];Helo=[satlexmb07.amd.com] X-MS-Exchange-CrossTenant-AuthSource: MWH0EPF000971E4.namprd02.prod.outlook.com X-MS-Exchange-CrossTenant-AuthAs: Anonymous X-MS-Exchange-CrossTenant-FromEntityHeader: HybridOnPrem X-MS-Exchange-Transport-CrossTenantHeadersStamped: BY5PR12MB4098 Content-Type: text/plain; charset="utf-8" Exceptions cannot be explicitly injected from the hypervisor to Secure AVIC enabled guests. So, KVM cannot inject exceptions into a Secure AVIC guest. If KVM were to intercept an exception (e.g., #PF or #GP), it would be unable to deliver it back to the guest, effectively dropping the event and leading to guest misbehavior or hangs. So, clear exception intercepts so that all exceptions are handled directly by the guest without KVM intervention. Signed-off-by: Neeraj Upadhyay --- arch/x86/kvm/svm/sev.c | 11 ++++++++++- 1 file changed, 10 insertions(+), 1 deletion(-) diff --git a/arch/x86/kvm/svm/sev.c b/arch/x86/kvm/svm/sev.c index a64fcc7637c7..837ab55a3330 100644 --- a/arch/x86/kvm/svm/sev.c +++ b/arch/x86/kvm/svm/sev.c @@ -4761,8 +4761,17 @@ static void sev_es_init_vmcb(struct vcpu_svm *svm) /* Can't intercept XSETBV, HV can't modify XCR0 directly */ svm_clr_intercept(svm, INTERCEPT_XSETBV); =20 - if (sev_savic_active(vcpu->kvm)) + if (sev_savic_active(vcpu->kvm)) { svm_set_intercept_for_msr(vcpu, MSR_AMD64_SAVIC_CONTROL, MSR_TYPE_RW, fa= lse); + + /* Clear all exception intercepts. */ + clr_exception_intercept(svm, PF_VECTOR); + clr_exception_intercept(svm, UD_VECTOR); + clr_exception_intercept(svm, MC_VECTOR); + clr_exception_intercept(svm, AC_VECTOR); + clr_exception_intercept(svm, DB_VECTOR); + clr_exception_intercept(svm, GP_VECTOR); + } } =20 void sev_init_vmcb(struct vcpu_svm *svm) --=20 2.34.1 From nobody Thu Oct 2 03:27:32 2025 Received: from CY7PR03CU001.outbound.protection.outlook.com (mail-westcentralusazon11010016.outbound.protection.outlook.com [40.93.198.16]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id 0A19630E0F7; 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X-OriginatorOrg: amd.com X-MS-Exchange-CrossTenant-OriginalArrivalTime: 23 Sep 2025 05:06:19.7950 (UTC) X-MS-Exchange-CrossTenant-Network-Message-Id: d8658dba-d3f6-426a-3dca-08ddfa5eeef5 X-MS-Exchange-CrossTenant-Id: 3dd8961f-e488-4e60-8e11-a82d994e183d X-MS-Exchange-CrossTenant-OriginalAttributedTenantConnectingIp: TenantId=3dd8961f-e488-4e60-8e11-a82d994e183d;Ip=[165.204.84.17];Helo=[satlexmb07.amd.com] X-MS-Exchange-CrossTenant-AuthSource: MWH0EPF000971E4.namprd02.prod.outlook.com X-MS-Exchange-CrossTenant-AuthAs: Anonymous X-MS-Exchange-CrossTenant-FromEntityHeader: HybridOnPrem X-MS-Exchange-Transport-CrossTenantHeadersStamped: SA3PR12MB8802 Content-Type: text/plain; charset="utf-8" From: Kishon Vijay Abraham I Unlike standard SVM which uses the V_GIF (Virtual Global Interrupt Flag) bit in the VMCB, Secure AVIC ignores this field. Instead, the hardware requires an equivalent V_GIF bit to be set within the vintr_ctrl field of the VMSA (Virtual Machine Save Area). Failure to set this bit will cause the hardware to block all interrupt delivery, rendering the guest non-functional. To enable interrupts for Secure AVIC guests, modify sev_es_sync_vmsa() to unconditionally set the V_GIF_MASK in the VMSA's vintr_ctrl field whenever Secure AVIC is active. This ensures the hardware correctly identifies the guest as interruptible. Signed-off-by: Kishon Vijay Abraham I Signed-off-by: Neeraj Upadhyay --- arch/x86/kvm/svm/sev.c | 3 +++ 1 file changed, 3 insertions(+) diff --git a/arch/x86/kvm/svm/sev.c b/arch/x86/kvm/svm/sev.c index 837ab55a3330..2dee210efb37 100644 --- a/arch/x86/kvm/svm/sev.c +++ b/arch/x86/kvm/svm/sev.c @@ -884,6 +884,9 @@ static int sev_es_sync_vmsa(struct vcpu_svm *svm) =20 save->sev_features =3D sev->vmsa_features; =20 + if (sev_savic_active(vcpu->kvm)) + save->vintr_ctrl |=3D V_GIF_MASK; + /* * Skip FPU and AVX setup with KVM_SEV_ES_INIT to avoid * breaking older measurements. --=20 2.34.1 From nobody Thu Oct 2 03:27:32 2025 Received: from SA9PR02CU001.outbound.protection.outlook.com (mail-southcentralusazon11013017.outbound.protection.outlook.com [40.93.196.17]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id 6AFB12E92B7; Tue, 23 Sep 2025 05:06:42 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; 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Mon, 22 Sep 2025 22:06:32 -0700 From: Neeraj Upadhyay To: , , CC: , , , , , , , , , , Subject: [RFC PATCH v2 11/17] KVM: SVM: Enable NMI support for Secure AVIC guests Date: Tue, 23 Sep 2025 10:33:11 +0530 Message-ID: <20250923050317.205482-12-Neeraj.Upadhyay@amd.com> X-Mailer: git-send-email 2.34.1 In-Reply-To: <20250923050317.205482-1-Neeraj.Upadhyay@amd.com> References: <20250923050317.205482-1-Neeraj.Upadhyay@amd.com> Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable X-ClientProxiedBy: satlexmb07.amd.com (10.181.42.216) To satlexmb07.amd.com (10.181.42.216) X-EOPAttributedMessage: 0 X-MS-PublicTrafficType: Email X-MS-TrafficTypeDiagnostic: MWH0EPF000971E9:EE_|DM3PR12MB9434:EE_ X-MS-Office365-Filtering-Correlation-Id: e59d6341-6f80-4958-46b5-08ddfa5ef92d X-MS-Exchange-SenderADCheck: 1 X-MS-Exchange-AntiSpam-Relay: 0 X-Microsoft-Antispam: BCL:0;ARA:13230040|36860700013|1800799024|376014|82310400026; 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X-OriginatorOrg: amd.com X-MS-Exchange-CrossTenant-OriginalArrivalTime: 23 Sep 2025 05:06:36.9475 (UTC) X-MS-Exchange-CrossTenant-Network-Message-Id: e59d6341-6f80-4958-46b5-08ddfa5ef92d X-MS-Exchange-CrossTenant-Id: 3dd8961f-e488-4e60-8e11-a82d994e183d X-MS-Exchange-CrossTenant-OriginalAttributedTenantConnectingIp: TenantId=3dd8961f-e488-4e60-8e11-a82d994e183d;Ip=[165.204.84.17];Helo=[satlexmb07.amd.com] X-MS-Exchange-CrossTenant-AuthSource: MWH0EPF000971E9.namprd02.prod.outlook.com X-MS-Exchange-CrossTenant-AuthAs: Anonymous X-MS-Exchange-CrossTenant-FromEntityHeader: HybridOnPrem X-MS-Exchange-Transport-CrossTenantHeadersStamped: DM3PR12MB9434 Content-Type: text/plain; charset="utf-8" The Secure AVIC hardware introduces a new model for handling Non-Maskable Interrupts (NMIs). This model differs significantly from standard SVM, as guest NMI state is managed by the hardware and is not visible to KVM. Consequently, KVM can no longer use the generic EVENT_INJ mechanism and must not track NMI masking state in software. Instead, it must adopt the vNMI (Virtual NMI) flow, which is the only mechanism supported by Secure AVIC. Enable NMI support by making three key changes: 1. Enable NMI in VMSA: Set the V_NMI_ENABLE_MASK bit in the VMSA's vintr_ctr field. This is a hardware prerequisite to enable the vNMI feature for the guest. 2. Use vNMI for Injection: Modify svm_inject_nmi() to use the vNMI flow for Secure AVIC guests. When an NMI is requested, set the V_NMI_PENDING_MASK in the VMCB instead of using EVENT_INJ. 3. Update NMI Windowing: Modify svm_nmi_allowed() to reflect that hardware now manages NMI blocking. KVM's only responsibility is to avoid queuing a new vNMI if one is already pending. The check is now simplified to whether V_NMI_PENDING_MASK is already set. Co-developed-by: Kishon Vijay Abraham I Signed-off-by: Kishon Vijay Abraham I Signed-off-by: Neeraj Upadhyay --- arch/x86/kvm/svm/sev.c | 2 +- arch/x86/kvm/svm/svm.c | 56 ++++++++++++++++++++++++++---------------- 2 files changed, 36 insertions(+), 22 deletions(-) diff --git a/arch/x86/kvm/svm/sev.c b/arch/x86/kvm/svm/sev.c index 2dee210efb37..7c66aefe428a 100644 --- a/arch/x86/kvm/svm/sev.c +++ b/arch/x86/kvm/svm/sev.c @@ -885,7 +885,7 @@ static int sev_es_sync_vmsa(struct vcpu_svm *svm) save->sev_features =3D sev->vmsa_features; =20 if (sev_savic_active(vcpu->kvm)) - save->vintr_ctrl |=3D V_GIF_MASK; + save->vintr_ctrl |=3D V_GIF_MASK | V_NMI_ENABLE_MASK; =20 /* * Skip FPU and AVX setup with KVM_SEV_ES_INIT to avoid diff --git a/arch/x86/kvm/svm/svm.c b/arch/x86/kvm/svm/svm.c index fdd612c975ae..a945bc094c1a 100644 --- a/arch/x86/kvm/svm/svm.c +++ b/arch/x86/kvm/svm/svm.c @@ -3635,27 +3635,6 @@ static int pre_svm_run(struct kvm_vcpu *vcpu) return 0; } =20 -static void svm_inject_nmi(struct kvm_vcpu *vcpu) -{ - struct vcpu_svm *svm =3D to_svm(vcpu); - - svm->vmcb->control.event_inj =3D SVM_EVTINJ_VALID | SVM_EVTINJ_TYPE_NMI; - - if (svm->nmi_l1_to_l2) - return; - - /* - * No need to manually track NMI masking when vNMI is enabled, hardware - * automatically sets V_NMI_BLOCKING_MASK as appropriate, including the - * case where software directly injects an NMI. - */ - if (!is_vnmi_enabled(svm)) { - svm->nmi_masked =3D true; - svm_set_iret_intercept(svm); - } - ++vcpu->stat.nmi_injections; -} - static bool svm_is_vnmi_pending(struct kvm_vcpu *vcpu) { struct vcpu_svm *svm =3D to_svm(vcpu); @@ -3689,6 +3668,33 @@ static bool svm_set_vnmi_pending(struct kvm_vcpu *vc= pu) return true; } =20 +static void svm_inject_nmi(struct kvm_vcpu *vcpu) +{ + struct vcpu_svm *svm =3D to_svm(vcpu); + + if (sev_savic_active(vcpu->kvm)) { + svm_set_vnmi_pending(vcpu); + ++vcpu->stat.nmi_injections; + return; + } + + svm->vmcb->control.event_inj =3D SVM_EVTINJ_VALID | SVM_EVTINJ_TYPE_NMI; + + if (svm->nmi_l1_to_l2) + return; + + /* + * No need to manually track NMI masking when vNMI is enabled, hardware + * automatically sets V_NMI_BLOCKING_MASK as appropriate, including the + * case where software directly injects an NMI. + */ + if (!is_vnmi_enabled(svm)) { + svm->nmi_masked =3D true; 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Mon, 22 Sep 2025 22:06:49 -0700 From: Neeraj Upadhyay To: , , CC: , , , , , , , , , , Subject: [RFC PATCH v2 12/17] KVM: SVM: Add VMGEXIT handler for Secure AVIC backing page Date: Tue, 23 Sep 2025 10:33:12 +0530 Message-ID: <20250923050317.205482-13-Neeraj.Upadhyay@amd.com> X-Mailer: git-send-email 2.34.1 In-Reply-To: <20250923050317.205482-1-Neeraj.Upadhyay@amd.com> References: <20250923050317.205482-1-Neeraj.Upadhyay@amd.com> Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable X-ClientProxiedBy: satlexmb07.amd.com (10.181.42.216) To satlexmb07.amd.com (10.181.42.216) X-EOPAttributedMessage: 0 X-MS-PublicTrafficType: Email X-MS-TrafficTypeDiagnostic: MWH0EPF000971E2:EE_|IA1PR12MB8263:EE_ X-MS-Office365-Filtering-Correlation-Id: 5c7cf22a-f3cf-4b0d-f294-08ddfa5f0322 X-MS-Exchange-SenderADCheck: 1 X-MS-Exchange-AntiSpam-Relay: 0 X-Microsoft-Antispam: BCL:0;ARA:13230040|1800799024|376014|82310400026|36860700013; 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X-OriginatorOrg: amd.com X-MS-Exchange-CrossTenant-OriginalArrivalTime: 23 Sep 2025 05:06:53.6316 (UTC) X-MS-Exchange-CrossTenant-Network-Message-Id: 5c7cf22a-f3cf-4b0d-f294-08ddfa5f0322 X-MS-Exchange-CrossTenant-Id: 3dd8961f-e488-4e60-8e11-a82d994e183d X-MS-Exchange-CrossTenant-OriginalAttributedTenantConnectingIp: TenantId=3dd8961f-e488-4e60-8e11-a82d994e183d;Ip=[165.204.84.17];Helo=[satlexmb07.amd.com] X-MS-Exchange-CrossTenant-AuthSource: MWH0EPF000971E2.namprd02.prod.outlook.com X-MS-Exchange-CrossTenant-AuthAs: Anonymous X-MS-Exchange-CrossTenant-FromEntityHeader: HybridOnPrem X-MS-Exchange-Transport-CrossTenantHeadersStamped: IA1PR12MB8263 Content-Type: text/plain; charset="utf-8" The Secure AVIC hardware requires uninterrupted access to the guest's APIC backing page. If this page is not present in the Nested Page Table (NPT) during a hardware access, a non-recoverable nested page fault occurs. This sets a BUSY flag in the VMSA and causes subsequent VMRUNs to fail with an unrecoverable VMEXIT_BUSY, effectively killing the vCPU. This situation can arise if the backing page resides within a 2MB large page in the NPT. If other parts of that large page are modified (e.g., memory state changes), KVM would split the 2MB NPT entry into 4KB entries. This process can temporarily zap the PTE for the backing page, creating a window for the fatal hardware access. Introduce a new GHCB VMGEXIT protocol, SVM_VMGEXIT_SECURE_AVIC, to allow the guest to explicitly inform KVM of the APIC backing page's location, thereby enabling KVM to guarantee its presence in the NPT. Implement two actions for this protocol: - SVM_VMGEXIT_SAVIC_REGISTER_BACKING_PAGE: On this request, KVM receives the GPA of the backing page. To prevent the 2MB page-split issue, immediately perform a PSMASH on the GPA by calling sev_handle_rmp_fault(). This proactively breaks any containing 2MB NPT entry into 4KB pages, isolating the backing page's PTE and guaranteeing its presence. Store the GPA for future reference. - SVM_VMGEXIT_SAVIC_UNREGISTER_BACKING_PAGE: On this request, clear the stored GPA, releasing KVM from its obligation to maintain the NPT entry. Return the previously registered GPA to the guest. This mechanism ensures the stability of the APIC backing page mapping, which is critical for the correct operation of Secure AVIC. Co-developed-by: Kishon Vijay Abraham I Signed-off-by: Kishon Vijay Abraham I Signed-off-by: Neeraj Upadhyay --- arch/x86/include/uapi/asm/svm.h | 3 ++ arch/x86/kvm/svm/sev.c | 59 +++++++++++++++++++++++++++++++++ arch/x86/kvm/svm/svm.h | 1 + 3 files changed, 63 insertions(+) diff --git a/arch/x86/include/uapi/asm/svm.h b/arch/x86/include/uapi/asm/sv= m.h index 9c640a521a67..f1ef52e0fab1 100644 --- a/arch/x86/include/uapi/asm/svm.h +++ b/arch/x86/include/uapi/asm/svm.h @@ -118,6 +118,9 @@ #define SVM_VMGEXIT_AP_CREATE 1 #define SVM_VMGEXIT_AP_DESTROY 2 #define SVM_VMGEXIT_SNP_RUN_VMPL 0x80000018 +#define SVM_VMGEXIT_SECURE_AVIC 0x8000001a +#define SVM_VMGEXIT_SAVIC_REGISTER_BACKING_PAGE 0 +#define SVM_VMGEXIT_SAVIC_UNREGISTER_BACKING_PAGE 1 #define SVM_VMGEXIT_HV_FEATURES 0x8000fffd #define SVM_VMGEXIT_TERM_REQUEST 0x8000fffe #define SVM_VMGEXIT_TERM_REASON(reason_set, reason_code) \ diff --git a/arch/x86/kvm/svm/sev.c b/arch/x86/kvm/svm/sev.c index 7c66aefe428a..3e9cc50f2705 100644 --- a/arch/x86/kvm/svm/sev.c +++ b/arch/x86/kvm/svm/sev.c @@ -3399,6 +3399,15 @@ static int sev_es_validate_vmgexit(struct vcpu_svm *= svm) !kvm_ghcb_rcx_is_valid(svm)) goto vmgexit_err; break; + case SVM_VMGEXIT_SECURE_AVIC: + if (!sev_savic_active(vcpu->kvm)) + goto vmgexit_err; + if (!kvm_ghcb_rax_is_valid(svm)) + goto vmgexit_err; + if (svm->vmcb->control.exit_info_1 =3D=3D SVM_VMGEXIT_SAVIC_REGISTER_BAC= KING_PAGE) + if (!kvm_ghcb_rbx_is_valid(svm)) + goto vmgexit_err; + break; case SVM_VMGEXIT_MMIO_READ: case SVM_VMGEXIT_MMIO_WRITE: if (!kvm_ghcb_sw_scratch_is_valid(svm)) @@ -4490,6 +4499,53 @@ static bool savic_handle_msr_exit(struct kvm_vcpu *v= cpu) return false; } =20 +static int sev_handle_savic_vmgexit(struct vcpu_svm *svm) +{ + struct kvm_vcpu *vcpu =3D NULL; + u64 apic_id; + + apic_id =3D kvm_rax_read(&svm->vcpu); + + if (apic_id =3D=3D -1ULL) { + vcpu =3D &svm->vcpu; + } else { + vcpu =3D kvm_get_vcpu_by_id(vcpu->kvm, apic_id); + if (!vcpu) + goto savic_request_invalid; + } + + switch (svm->vmcb->control.exit_info_1) { + case SVM_VMGEXIT_SAVIC_REGISTER_BACKING_PAGE: + gpa_t gpa; + + gpa =3D kvm_rbx_read(&svm->vcpu); + if (!PAGE_ALIGNED(gpa)) + goto savic_request_invalid; + + /* + * sev_handle_rmp_fault() invocation would result in PSMASH if + * NPTE size is 2M. + */ + sev_handle_rmp_fault(vcpu, gpa, 0); + to_svm(vcpu)->sev_savic_gpa =3D gpa; + break; + case SVM_VMGEXIT_SAVIC_UNREGISTER_BACKING_PAGE: + kvm_rbx_write(&svm->vcpu, to_svm(vcpu)->sev_savic_gpa); + to_svm(vcpu)->sev_savic_gpa =3D 0; + break; + default: + goto savic_request_invalid; + } + + return 1; + +savic_request_invalid: + ghcb_set_sw_exit_info_1(svm->sev_es.ghcb, 2); + ghcb_set_sw_exit_info_2(svm->sev_es.ghcb, GHCB_ERR_INVALID_INPUT); + + return 1; +} + int sev_handle_vmgexit(struct kvm_vcpu *vcpu) { struct vcpu_svm *svm =3D to_svm(vcpu); @@ -4628,6 +4684,9 @@ int sev_handle_vmgexit(struct kvm_vcpu *vcpu) control->exit_info_1, control->exit_info_2); ret =3D -EINVAL; break; + case SVM_VMGEXIT_SECURE_AVIC: + ret =3D sev_handle_savic_vmgexit(svm); + break; case SVM_EXIT_MSR: if (sev_savic_active(vcpu->kvm) && savic_handle_msr_exit(vcpu)) return 1; diff --git a/arch/x86/kvm/svm/svm.h b/arch/x86/kvm/svm/svm.h index a3edb6e720cd..8043833a1a8c 100644 --- a/arch/x86/kvm/svm/svm.h +++ b/arch/x86/kvm/svm/svm.h @@ -337,6 +337,7 @@ struct vcpu_svm { bool guest_gif; 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X-OriginatorOrg: amd.com X-MS-Exchange-CrossTenant-OriginalArrivalTime: 23 Sep 2025 05:07:10.9160 (UTC) X-MS-Exchange-CrossTenant-Network-Message-Id: 1cf72620-ff5a-48a2-b721-08ddfa5f0d6d X-MS-Exchange-CrossTenant-Id: 3dd8961f-e488-4e60-8e11-a82d994e183d X-MS-Exchange-CrossTenant-OriginalAttributedTenantConnectingIp: TenantId=3dd8961f-e488-4e60-8e11-a82d994e183d;Ip=[165.204.84.17];Helo=[satlexmb07.amd.com] X-MS-Exchange-CrossTenant-AuthSource: MWH0EPF000971E6.namprd02.prod.outlook.com X-MS-Exchange-CrossTenant-AuthAs: Anonymous X-MS-Exchange-CrossTenant-FromEntityHeader: HybridOnPrem X-MS-Exchange-Transport-CrossTenantHeadersStamped: IA0PPFDC28CEE69 Content-Type: text/plain; charset="utf-8" While Secure AVIC hardware accelerates End-of-Interrupt (EOI) processing for edge-triggered interrupts, it requires hypervisor assistance for level-triggered interrupts originating from the IOAPIC. For these interrupts, a guest write to the EOI MSR triggers a VM-Exit. The primary challenge in handling this exit is that the guest's real In-Service Register (ISR) is not visible to KVM. When KVM receives an EOI, it has no direct way of knowing which interrupt vector is being acknowledged. To solve this, use KVM's software vAPIC state as a shadow tracking mechanism for active, level-triggered interrupts. The implementation follows this flow: 1. On interrupt injection (sev_savic_set_requested_irr), check KVM's software vAPIC Trigger Mode Register (TMR) to identify if the interrupt is level-triggered. 2. If it is, set the corresponding vector in KVM's software shadow ISR. This marks the interrupt as "in-service" from KVM's perspective. 3. When the guest later issues an EOI, the APIC_EOI MSR write exit handler finds the highest vector set in this shadow ISR. 4. The handler then clears the vector from the shadow ISR and calls kvm_apic_set_eoi_accelerated() to propagate the EOI to the virtual IOAPIC, allowing it to de-assert the interrupt line. This enables correct EOI handling for level-triggered interrupts in Secure AVIC guests, despite the hardware-enforced opacity of the guest's APIC state. Signed-off-by: Neeraj Upadhyay --- arch/x86/kvm/svm/sev.c | 10 ++++++++++ 1 file changed, 10 insertions(+) diff --git a/arch/x86/kvm/svm/sev.c b/arch/x86/kvm/svm/sev.c index 3e9cc50f2705..5be2956fb812 100644 --- a/arch/x86/kvm/svm/sev.c +++ b/arch/x86/kvm/svm/sev.c @@ -4474,7 +4474,9 @@ static void savic_handle_icr_write(struct kvm_vcpu *k= vm_vcpu, u64 icr) =20 static bool savic_handle_msr_exit(struct kvm_vcpu *vcpu) { + struct kvm_lapic *apic; u32 msr, reg; + int vec; =20 msr =3D kvm_rcx_read(vcpu); reg =3D (msr - APIC_BASE_MSR) << 4; @@ -4492,6 +4494,12 @@ static bool savic_handle_msr_exit(struct kvm_vcpu *v= cpu) return true; } break; + case APIC_EOI: + apic =3D vcpu->arch.apic; + vec =3D apic_find_highest_vector(apic->regs + APIC_ISR); + apic_clear_vector(vec, apic->regs + APIC_ISR); + kvm_apic_set_eoi_accelerated(vcpu, vec); + return true; default: break; } @@ -5379,6 +5387,8 @@ void sev_savic_set_requested_irr(struct vcpu_svm *svm= , bool reinjected) vec =3D vec_start + vec_pos; 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X-OriginatorOrg: amd.com X-MS-Exchange-CrossTenant-OriginalArrivalTime: 23 Sep 2025 05:07:27.9548 (UTC) X-MS-Exchange-CrossTenant-Network-Message-Id: 8ead4741-3bfe-4c34-3c47-08ddfa5f1798 X-MS-Exchange-CrossTenant-Id: 3dd8961f-e488-4e60-8e11-a82d994e183d X-MS-Exchange-CrossTenant-OriginalAttributedTenantConnectingIp: TenantId=3dd8961f-e488-4e60-8e11-a82d994e183d;Ip=[165.204.84.17];Helo=[satlexmb07.amd.com] X-MS-Exchange-CrossTenant-AuthSource: MWH0EPF000971E7.namprd02.prod.outlook.com X-MS-Exchange-CrossTenant-AuthAs: Anonymous X-MS-Exchange-CrossTenant-FromEntityHeader: HybridOnPrem X-MS-Exchange-Transport-CrossTenantHeadersStamped: CH2PR12MB4104 Content-Type: text/plain; charset="utf-8" KVM tracks End-of-Interrupts (EOIs) for the legacy RTC interrupt (GSI 8) to detect and report coalesced interrupts to userspace. This mechanism fundamentally relies on KVM having visibility into the guest's interrupt acknowledgment state. This assumption is invalid for guests with a protected APIC (e.g., Secure AVIC) for two main reasons: a. The guest's true In-Service Register (ISR) is not visible to KVM, making it impossible to know if the previous interrupt is still active. So, lazy pending EOI checks cannot be done. b. The RTC interrupt is edge-triggered, and its EOI is accelerated by the hardware without a VM-Exit. KVM never sees the EOI event. Since KVM can observe neither the interrupt's service status nor its EOI, the tracking logic is invalid. So, disable this feature for all protected APIC guests. This change means that userspace will no longer be able to detect coalesced RTC interrupts for these specific guest types. Signed-off-by: Neeraj Upadhyay --- arch/x86/kvm/ioapic.c | 8 +++++++- 1 file changed, 7 insertions(+), 1 deletion(-) diff --git a/arch/x86/kvm/ioapic.c b/arch/x86/kvm/ioapic.c index 2b5d389bca5f..308778ba4f58 100644 --- a/arch/x86/kvm/ioapic.c +++ b/arch/x86/kvm/ioapic.c @@ -113,6 +113,9 @@ static void __rtc_irq_eoi_tracking_restore_one(struct k= vm_vcpu *vcpu) struct dest_map *dest_map =3D &ioapic->rtc_status.dest_map; union kvm_ioapic_redirect_entry *e; =20 + if (vcpu->arch.apic->guest_apic_protected) + return; + e =3D &ioapic->redirtbl[RTC_GSI]; if (!kvm_apic_match_dest(vcpu, NULL, APIC_DEST_NOSHORT, e->fields.dest_id, @@ -476,6 +479,7 @@ static int ioapic_service(struct kvm_ioapic *ioapic, in= t irq, bool line_status) { union kvm_ioapic_redirect_entry *entry =3D &ioapic->redirtbl[irq]; struct kvm_lapic_irq irqe; + struct kvm_vcpu *vcpu; int ret; =20 if (entry->fields.mask || @@ -505,7 +509,9 @@ static int ioapic_service(struct kvm_ioapic *ioapic, in= t irq, bool line_status) BUG_ON(ioapic->rtc_status.pending_eoi !=3D 0); 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X-OriginatorOrg: amd.com X-MS-Exchange-CrossTenant-OriginalArrivalTime: 23 Sep 2025 05:07:44.9664 (UTC) X-MS-Exchange-CrossTenant-Network-Message-Id: baadc375-30fa-450d-417a-08ddfa5f21b9 X-MS-Exchange-CrossTenant-Id: 3dd8961f-e488-4e60-8e11-a82d994e183d X-MS-Exchange-CrossTenant-OriginalAttributedTenantConnectingIp: TenantId=3dd8961f-e488-4e60-8e11-a82d994e183d;Ip=[165.204.84.17];Helo=[satlexmb07.amd.com] X-MS-Exchange-CrossTenant-AuthSource: MWH0EPF000971E9.namprd02.prod.outlook.com X-MS-Exchange-CrossTenant-AuthAs: Anonymous X-MS-Exchange-CrossTenant-FromEntityHeader: HybridOnPrem X-MS-Exchange-Transport-CrossTenantHeadersStamped: IA0PR12MB8894 Content-Type: text/plain; charset="utf-8" The kvm_wait_lapic_expire() function is a pre-VMRUN optimization that allows a vCPU to wait for an imminent LAPIC timer interrupt. However, this function is not fully compatible with protected APIC models like Secure AVIC because it relies on inspecting KVM's software vAPIC state. For Secure AVIC, the true timer state is hardware-managed and opaque to KVM. For this reason, kvm_wait_lapic_expire() does not check whether timer interrupt is injected for the guests which have protected APIC state. For the protected APIC guests, the check for injected timer need to be done by the callers of kvm_wait_lapic_expire(). So, for Secure AVIC guests, check to be injected vectors in the requested_IRR for injected timer interrupt before doing a kvm_wait_lapic_expire(). Signed-off-by: Neeraj Upadhyay --- arch/x86/kvm/svm/sev.c | 8 ++++++++ arch/x86/kvm/svm/svm.c | 3 ++- arch/x86/kvm/svm/svm.h | 2 ++ 3 files changed, 12 insertions(+), 1 deletion(-) diff --git a/arch/x86/kvm/svm/sev.c b/arch/x86/kvm/svm/sev.c index 5be2956fb812..3f6cf8d5068a 100644 --- a/arch/x86/kvm/svm/sev.c +++ b/arch/x86/kvm/svm/sev.c @@ -5405,3 +5405,11 @@ bool sev_savic_has_pending_interrupt(struct kvm_vcpu= *vcpu) return READ_ONCE(to_svm(vcpu)->sev_savic_has_pending_ipi) || kvm_apic_has_interrupt(vcpu) !=3D -1; } + +bool sev_savic_timer_int_injected(struct kvm_vcpu *vcpu) +{ + u32 reg =3D kvm_lapic_get_reg(vcpu->arch.apic, APIC_LVTT); + int vec =3D reg & APIC_VECTOR_MASK; + + return to_svm(vcpu)->vmcb->control.requested_irr[vec / 32] & BIT(vec % 32= ); +} diff --git a/arch/x86/kvm/svm/svm.c b/arch/x86/kvm/svm/svm.c index a945bc094c1a..d0d972731ea7 100644 --- a/arch/x86/kvm/svm/svm.c +++ b/arch/x86/kvm/svm/svm.c @@ -4335,7 +4335,8 @@ static __no_kcsan fastpath_t svm_vcpu_run(struct kvm_= vcpu *vcpu, u64 run_flags) vcpu->arch.host_debugctl !=3D svm->vmcb->save.dbgctl) update_debugctlmsr(svm->vmcb->save.dbgctl); =20 - kvm_wait_lapic_expire(vcpu); + if (!sev_savic_active(vcpu->kvm) || sev_savic_timer_int_injected(vcpu)) + kvm_wait_lapic_expire(vcpu); =20 /* * If this vCPU has touched SPEC_CTRL, restore the guest's value if diff --git a/arch/x86/kvm/svm/svm.h b/arch/x86/kvm/svm/svm.h index 8043833a1a8c..ecc4ea11822d 100644 --- a/arch/x86/kvm/svm/svm.h +++ b/arch/x86/kvm/svm/svm.h @@ -878,6 +878,7 @@ static inline bool sev_savic_active(struct kvm *kvm) } void sev_savic_set_requested_irr(struct vcpu_svm *svm, bool reinjected); bool sev_savic_has_pending_interrupt(struct kvm_vcpu *vcpu); +bool sev_savic_timer_int_injected(struct kvm_vcpu *vcpu); #else static inline struct page *snp_safe_alloc_page_node(int node, gfp_t gfp) { @@ -917,6 +918,7 @@ static inline struct vmcb_save_area *sev_decrypt_vmsa(s= truct kvm_vcpu *vcpu) static inline void sev_free_decrypted_vmsa(struct kvm_vcpu *vcpu, struct v= mcb_save_area *vmsa) {} static inline void sev_savic_set_requested_irr(struct vcpu_svm *svm, bool = reinjected) {} static inline bool sev_savic_has_pending_interrupt(struct kvm_vcpu *vcpu) = { return false; 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X-OriginatorOrg: amd.com X-MS-Exchange-CrossTenant-OriginalArrivalTime: 23 Sep 2025 05:08:01.5981 (UTC) X-MS-Exchange-CrossTenant-Network-Message-Id: 59e65c60-4288-413a-6279-08ddfa5f2b95 X-MS-Exchange-CrossTenant-Id: 3dd8961f-e488-4e60-8e11-a82d994e183d X-MS-Exchange-CrossTenant-OriginalAttributedTenantConnectingIp: TenantId=3dd8961f-e488-4e60-8e11-a82d994e183d;Ip=[165.204.84.17];Helo=[satlexmb07.amd.com] X-MS-Exchange-CrossTenant-AuthSource: CH2PEPF00000145.namprd02.prod.outlook.com X-MS-Exchange-CrossTenant-AuthAs: Anonymous X-MS-Exchange-CrossTenant-FromEntityHeader: HybridOnPrem X-MS-Exchange-Transport-CrossTenantHeadersStamped: PH7PR12MB7020 Content-Type: text/plain; charset="utf-8" The paravirtualized APIC features, PV_EOI and PV_SEND_IPI, are predicated on KVM having full visibility and control over the guest's vAPIC state. This assumption is invalid for guests with a protected APIC (e.g., AMD SEV-SNP with Secure AVIC, Intel TDX), where the APIC state is opaque to the hypervisor and managed by the hardware. - PV_EOI: KVM cannot service a PV_EOI MSR write because it has no access to the guest's true In-Service Register (ISR). For these guests, EOIs are either accelerated by hardware or virtualized via a different, technology-specific VM-Exit, not the PV MSR. - PV_SEND_IPI: Protected guest models have their own specific IPI virtualization flows (e.g., VMGEXIT on ICR write for Secure AVIC). Exposing the generic PV_SEND_IPI hypercall would provide a conflicting, incorrect path that bypasses the required secure flow. To prevent the guest from using these incompatible interfaces, clear the KVM_FEATURE_PV_EOI and KVM_FEATURE_PV_SEND_IPI PV feature CPUID bits when for guests with protected APIC. Signed-off-by: Neeraj Upadhyay --- arch/x86/kvm/cpuid.c | 4 ++++ 1 file changed, 4 insertions(+) diff --git a/arch/x86/kvm/cpuid.c b/arch/x86/kvm/cpuid.c index e2836a255b16..01b3c4e88282 100644 --- a/arch/x86/kvm/cpuid.c +++ b/arch/x86/kvm/cpuid.c @@ -245,6 +245,10 @@ static u32 kvm_apply_cpuid_pv_features_quirk(struct kv= m_vcpu *vcpu) if (kvm_hlt_in_guest(vcpu->kvm)) best->eax &=3D ~(1 << KVM_FEATURE_PV_UNHALT); =20 + if (vcpu->arch.apic->guest_apic_protected) + best->eax &=3D ~((1 << KVM_FEATURE_PV_EOI) | + (1 << KVM_FEATURE_PV_SEND_IPI)); + return best->eax; } =20 --=20 2.34.1 From nobody Thu Oct 2 03:27:32 2025 Received: from CO1PR03CU002.outbound.protection.outlook.com (mail-westus2azon11010025.outbound.protection.outlook.com [52.101.46.25]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id 44E151C84BC; Tue, 23 Sep 2025 05:08:21 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; 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Mon, 22 Sep 2025 22:08:14 -0700 From: Neeraj Upadhyay To: , , CC: , , , , , , , , , , Subject: [RFC PATCH v2 17/17] KVM: SVM: Advertise Secure AVIC support for SNP guests Date: Tue, 23 Sep 2025 10:33:17 +0530 Message-ID: <20250923050317.205482-18-Neeraj.Upadhyay@amd.com> X-Mailer: git-send-email 2.34.1 In-Reply-To: <20250923050317.205482-1-Neeraj.Upadhyay@amd.com> References: <20250923050317.205482-1-Neeraj.Upadhyay@amd.com> Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable X-ClientProxiedBy: satlexmb07.amd.com (10.181.42.216) To satlexmb07.amd.com (10.181.42.216) X-EOPAttributedMessage: 0 X-MS-PublicTrafficType: Email X-MS-TrafficTypeDiagnostic: CH2PEPF00000148:EE_|LV2PR12MB5821:EE_ X-MS-Office365-Filtering-Correlation-Id: ca090d14-752c-4801-790c-08ddfa5f35be X-MS-Exchange-SenderADCheck: 1 X-MS-Exchange-AntiSpam-Relay: 0 X-Microsoft-Antispam: BCL:0;ARA:13230040|82310400026|376014|36860700013|1800799024; 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X-OriginatorOrg: amd.com X-MS-Exchange-CrossTenant-OriginalArrivalTime: 23 Sep 2025 05:08:18.6443 (UTC) X-MS-Exchange-CrossTenant-Network-Message-Id: ca090d14-752c-4801-790c-08ddfa5f35be X-MS-Exchange-CrossTenant-Id: 3dd8961f-e488-4e60-8e11-a82d994e183d X-MS-Exchange-CrossTenant-OriginalAttributedTenantConnectingIp: TenantId=3dd8961f-e488-4e60-8e11-a82d994e183d;Ip=[165.204.84.17];Helo=[satlexmb07.amd.com] X-MS-Exchange-CrossTenant-AuthSource: CH2PEPF00000148.namprd02.prod.outlook.com X-MS-Exchange-CrossTenant-AuthAs: Anonymous X-MS-Exchange-CrossTenant-FromEntityHeader: HybridOnPrem X-MS-Exchange-Transport-CrossTenantHeadersStamped: LV2PR12MB5821 Content-Type: text/plain; charset="utf-8" The preceding patches have implemented all the necessary KVM infrastructure to support the Secure AVIC feature for SEV-SNP guests, including interrupt/NMI injection, IPI virtualization, and EOI handling. Despite the backend support being complete, KVM does not yet advertise this capability. As a result, userspace tools cannot create VMs that utilize this feature. To enable the feature, add the SVM_SEV_FEAT_SECURE_AVIC flag to the sev_supported_vmsa_features bitmask. This bitmask communicates KVM's supported VMSA features to userspace. This is the final enabling patch in the series, allowing the creation of Secure AVIC-enabled virtual machines. Signed-off-by: Neeraj Upadhyay --- arch/x86/kvm/svm/sev.c | 3 +++ 1 file changed, 3 insertions(+) diff --git a/arch/x86/kvm/svm/sev.c b/arch/x86/kvm/svm/sev.c index 3f6cf8d5068a..fe3d65c50afd 100644 --- a/arch/x86/kvm/svm/sev.c +++ b/arch/x86/kvm/svm/sev.c @@ -3092,6 +3092,9 @@ void __init sev_hardware_setup(void) sev_supported_vmsa_features =3D 0; if (sev_es_debug_swap_enabled) sev_supported_vmsa_features |=3D SVM_SEV_FEAT_DEBUG_SWAP; + + if (sev_snp_savic_enabled) + sev_supported_vmsa_features |=3D SVM_SEV_FEAT_SECURE_AVIC; } =20 void sev_hardware_unsetup(void) --=20 2.34.1