From nobody Thu Oct 2 03:27:35 2025 Received: from mail-pg1-f202.google.com (mail-pg1-f202.google.com [209.85.215.202]) (using TLSv1.2 with cipher ECDHE-RSA-AES128-GCM-SHA256 (128/128 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id 9C74F26C386 for ; Tue, 23 Sep 2025 04:18:50 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=none smtp.client-ip=209.85.215.202 ARC-Seal: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1758601132; cv=none; b=G+XDggTticbuTYY0+i/di5FyPe8i/cvc+1Np0WEIknW9k6EWRr3CMT6n21lFPrhksSzw0wb0HjlYSfihwuLRuohcE7TP+J4Cal/U/PlZifvDdfW3htCvfhOewJ9kkaHm0OUXAWjMPiIqZfbk4acWxnyN49JRCYN5mSQAZP3Ed0w= ARC-Message-Signature: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1758601132; c=relaxed/simple; bh=kZUHpU6S8UVYRUQDdu4Y2Rk+Jy5km31ZCsLgDDgmx3s=; h=Date:In-Reply-To:Mime-Version:References:Message-ID:Subject:From: To:Content-Type; b=CeItpbMCga/9RatBv6WVEgmNsQIFjEDE2KNrXZpNNBqnf/HQSbzXo9S+IR/heHhrl+saFl9vJK6fqvcHuiJYHn4NauFMQWII3qB6nomwGck8yM7o998nUV8htw185/D4p8H/zYkg5Sp0XSQ8ePN3SOUQvjc+9nzTKtSnZfHlp/s= ARC-Authentication-Results: i=1; smtp.subspace.kernel.org; dmarc=pass (p=reject dis=none) header.from=google.com; spf=pass smtp.mailfrom=flex--irogers.bounces.google.com; dkim=pass (2048-bit key) header.d=google.com header.i=@google.com header.b=2oDf8trK; arc=none smtp.client-ip=209.85.215.202 Authentication-Results: smtp.subspace.kernel.org; dmarc=pass (p=reject dis=none) header.from=google.com Authentication-Results: smtp.subspace.kernel.org; spf=pass smtp.mailfrom=flex--irogers.bounces.google.com Authentication-Results: smtp.subspace.kernel.org; dkim=pass (2048-bit key) header.d=google.com header.i=@google.com header.b="2oDf8trK" Received: by mail-pg1-f202.google.com with SMTP id 41be03b00d2f7-b522037281bso3942990a12.3 for ; Mon, 22 Sep 2025 21:18:50 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=20230601; t=1758601130; x=1759205930; darn=vger.kernel.org; h=to:from:subject:message-id:references:mime-version:in-reply-to:date :from:to:cc:subject:date:message-id:reply-to; bh=wAneJQAQnPj35Q6fil29jmDxaONd3Bnz5JZuwitT6KQ=; b=2oDf8trK5Mpjy18SHbfWQQfK6Kog4/izu9Kjj4hQcpLLKJVwi/myF7kAe07RapFNw1 +xWGRDWDhZp/+/Kd03Y8yLHPs7U2Ih521WeY7jbEUBmCdgFUZpJZYL7YBjCYhxrftZlF hAHYyOjvKrlCahTc8pRCek7A0x9zNM+rFOw4FVWo+o5YBTC2NgmSwgpcDcxVnptCykXj TzV6k2oermnv+Pt+sZNB4MH+/tVix9us0ccYxdBXvKG9spHYa6INOXj2NzTtoHmPOgD9 ODq5sKhcZ8a6z1I7Gms2ZYbm2phEdFRAt+muX/KIf3e/m46IMIuBDSGVuilSRilqgZVS dZ2w== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20230601; t=1758601130; x=1759205930; h=to:from:subject:message-id:references:mime-version:in-reply-to:date :x-gm-message-state:from:to:cc:subject:date:message-id:reply-to; bh=wAneJQAQnPj35Q6fil29jmDxaONd3Bnz5JZuwitT6KQ=; b=EHlrUi+zrkXOFDeeT2aMOq0N3jZiyQIvzWg+nKg6fAEOKpUB7NQAbzxPjpiRJZCKym ZadTVldQWBkzoJ8luP4zt2OF2W6weW6Jc76kXu7odryDagNiFoEV48GFqBNmh3tnNpFJ /fIo0X4bNvDMn0yqViq6KhfRLfnCoVztmui67+MSDtN7b2iDAbYcg0j5BmZgFZbsKEzQ oZr6qRk38MIC9FaEPeSNJ8ewJUXJtKgiNIsfnde6lhTsWH+OJE9LUPqGrS3pmDf9x98d MEDTpRl3T7I7uMr9nxmbdN2VqllLNU67ApzrplBU3BIa2KYR4oGXmeGUOgJTDetbAT8D bLuQ== X-Forwarded-Encrypted: i=1; AJvYcCXnauyvFzBqaZrAWFUzAfuYOwBmOu7UpT+nqOzeZ039l0cLuDpAXvp+qA1XW5wNJCm9fiG3PDjCPH0K/dQ=@vger.kernel.org X-Gm-Message-State: AOJu0YzgDcLl4sT+m79y8R651QH0n9GA+VArHa4FXi3axHR8eGTH1WeC Nn8UP3ENONPzsVcf0JYDf51J7KsgVB0x2BGqeQQLzC8KneHxfjholXhayvsHgXTxV4EHz29qYL2 0z+IlpmOJeQ== X-Google-Smtp-Source: AGHT+IF6cYJDVK0H1bznB4eKbhN5Iu7fH1Fhc2pqoTFchudp7dMnQGWMpjFfFdl4jZSERPz88R1Nl3DJuiwZ X-Received: from pgbds10.prod.google.com ([2002:a05:6a02:430a:b0:b4e:3302:ce42]) (user=irogers job=prod-delivery.src-stubby-dispatcher) by 2002:a05:6a21:9990:b0:246:354:e0ff with SMTP id adf61e73a8af0-2cfd603fad0mr1701034637.8.1758601130012; Mon, 22 Sep 2025 21:18:50 -0700 (PDT) Date: Mon, 22 Sep 2025 21:18:20 -0700 In-Reply-To: <20250923041844.400164-1-irogers@google.com> Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: Mime-Version: 1.0 References: <20250923041844.400164-1-irogers@google.com> X-Mailer: git-send-email 2.51.0.534.gc79095c0ca-goog Message-ID: <20250923041844.400164-2-irogers@google.com> Subject: [PATCH v5 01/25] perf stat: Allow retry for default events From: Ian Rogers To: Peter Zijlstra , Ingo Molnar , Arnaldo Carvalho de Melo , Namhyung Kim , Mark Rutland , Alexander Shishkin , Jiri Olsa , Ian Rogers , Adrian Hunter , Kan Liang , James Clark , Xu Yang , Thomas Falcon , Andi Kleen , linux-kernel@vger.kernel.org, linux-perf-users@vger.kernel.org, bpf@vger.kernel.org, Atish Patra , Beeman Strong , Leo Yan , Vince Weaver Content-Transfer-Encoding: quoted-printable Content-Type: text/plain; charset="utf-8" Default events are marked skippable. Checking skippable first means retrying and adding modifiers like exclude kernel isn't performed. Push the skippable checking after fallbacks are tried and avoid warning multiple times for the event. Fixes: 9eac5612da1c ("perf stat: Don't skip failing group events") Signed-off-by: Ian Rogers --- tools/perf/builtin-stat.c | 38 +++++++++++++++++++++++--------------- 1 file changed, 23 insertions(+), 15 deletions(-) diff --git a/tools/perf/builtin-stat.c b/tools/perf/builtin-stat.c index ab567919b89a..303628189004 100644 --- a/tools/perf/builtin-stat.c +++ b/tools/perf/builtin-stat.c @@ -616,16 +616,7 @@ enum counter_recovery { static enum counter_recovery stat_handle_error(struct evsel *counter, int = err) { char msg[BUFSIZ]; - - if (counter->skippable) { - if (verbose > 0) { - ui__warning("skipping event %s that kernel failed to open .\n", - evsel__name(counter)); - } - counter->supported =3D false; - counter->errored =3D true; - return COUNTER_SKIP; - } + bool warned =3D false; =20 /* * PPC returns ENXIO for HW counters until 2.6.37 @@ -635,6 +626,7 @@ static enum counter_recovery stat_handle_error(struct e= vsel *counter, int err) if (verbose > 0) { ui__warning("%s event is not supported by the kernel.\n", evsel__name(counter)); + warned =3D true; } counter->supported =3D false; /* @@ -642,13 +634,15 @@ static enum counter_recovery stat_handle_error(struct= evsel *counter, int err) * cpu event had a problem and needs to be reexamined. */ counter->errored =3D true; - } else if (evsel__fallback(counter, &target, err, msg, sizeof(msg))) { + goto skip_or_fatal; + } + if (evsel__fallback(counter, &target, err, msg, sizeof(msg))) { if (verbose > 0) ui__warning("%s\n", msg); return COUNTER_RETRY; - } else if (target__has_per_thread(&target) && err !=3D EOPNOTSUPP && - evsel_list->core.threads && - evsel_list->core.threads->err_thread !=3D -1) { + } + if (target__has_per_thread(&target) && err !=3D EOPNOTSUPP && + evsel_list->core.threads && evsel_list->core.threads->err_thread !=3D= -1) { /* * For global --per-thread case, skip current * error thread. @@ -658,15 +652,29 @@ static enum counter_recovery stat_handle_error(struct= evsel *counter, int err) evsel_list->core.threads->err_thread =3D -1; return COUNTER_RETRY; } - } else if (err =3D=3D EOPNOTSUPP) { + goto skip_or_fatal; + } + if (err =3D=3D EOPNOTSUPP) { if (verbose > 0) { ui__warning("%s event is not supported by the kernel.\n", evsel__name(counter)); + warned =3D true; } counter->supported =3D false; counter->errored =3D true; } =20 +skip_or_fatal: + if (counter->skippable) { + if (verbose > 0 && !warned) { + ui__warning("skipping event %s that kernel failed to open .\n", + evsel__name(counter)); + } + counter->supported =3D false; + counter->errored =3D true; + return COUNTER_SKIP; + } + evsel__open_strerror(counter, &target, err, msg, sizeof(msg)); ui__error("%s\n", msg); =20 --=20 2.51.0.534.gc79095c0ca-goog From nobody Thu Oct 2 03:27:35 2025 Received: from mail-pg1-f201.google.com (mail-pg1-f201.google.com [209.85.215.201]) (using TLSv1.2 with cipher ECDHE-RSA-AES128-GCM-SHA256 (128/128 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id D9E7F274FF5 for ; Tue, 23 Sep 2025 04:18:52 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; 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Mon, 22 Sep 2025 21:18:52 -0700 (PDT) Date: Mon, 22 Sep 2025 21:18:21 -0700 In-Reply-To: <20250923041844.400164-1-irogers@google.com> Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: Mime-Version: 1.0 References: <20250923041844.400164-1-irogers@google.com> X-Mailer: git-send-email 2.51.0.534.gc79095c0ca-goog Message-ID: <20250923041844.400164-3-irogers@google.com> Subject: [PATCH v5 02/25] perf parse-events: Fix legacy cache events if event is duplicated in a PMU From: Ian Rogers To: Peter Zijlstra , Ingo Molnar , Arnaldo Carvalho de Melo , Namhyung Kim , Mark Rutland , Alexander Shishkin , Jiri Olsa , Ian Rogers , Adrian Hunter , Kan Liang , James Clark , Xu Yang , Thomas Falcon , Andi Kleen , linux-kernel@vger.kernel.org, linux-perf-users@vger.kernel.org, bpf@vger.kernel.org, Atish Patra , Beeman Strong , Leo Yan , Vince Weaver Cc: Thomas Richter Content-Transfer-Encoding: quoted-printable Content-Type: text/plain; charset="utf-8" The term list when adding an event to a PMU is expected to have the event name for the alias lookup. Also, set found_supported so that -EINVAL isn't returned. Fixes: 62593394f66a ("perf parse-events: Legacy cache names on all PMUs and lower priority") Tested-by: Thomas Richter Signed-off-by: Ian Rogers --- tools/perf/util/parse-events.c | 28 +++++++++++++++++++++++++++- tools/perf/util/parse-events.h | 3 ++- tools/perf/util/parse-events.y | 2 +- 3 files changed, 30 insertions(+), 3 deletions(-) diff --git a/tools/perf/util/parse-events.c b/tools/perf/util/parse-events.c index 452f12191f6e..d5675471afc5 100644 --- a/tools/perf/util/parse-events.c +++ b/tools/perf/util/parse-events.c @@ -475,8 +475,10 @@ static int parse_events_add_pmu(struct parse_events_st= ate *parse_state, =20 int parse_events_add_cache(struct list_head *list, int *idx, const char *n= ame, struct parse_events_state *parse_state, - struct parse_events_terms *parsed_terms) + struct parse_events_terms *parsed_terms, + void *loc_) { + YYLTYPE *loc =3D loc_; struct perf_pmu *pmu =3D NULL; bool found_supported =3D false; const char *config_name =3D get_config_name(parsed_terms); @@ -497,12 +499,36 @@ int parse_events_add_cache(struct list_head *list, in= t *idx, const char *name, * The PMU has the event so add as not a legacy cache * event. */ + struct parse_events_terms temp_terms; + struct parse_events_term *term; + char *config =3D strdup(name); + + if (!config) + goto out_err; + + parse_events_terms__init(&temp_terms); + if (!parsed_terms) + parsed_terms =3D &temp_terms; + + if (parse_events_term__num(&term, + PARSE_EVENTS__TERM_TYPE_USER, + config, /*num=3D*/1, /*novalue=3D*/true, + loc, /*loc_val=3D*/NULL) < 0) { + zfree(&config); + goto out_err; + } + list_add(&term->list, &parsed_terms->terms); + ret =3D parse_events_add_pmu(parse_state, list, pmu, parsed_terms, first_wildcard_match, /*alternate_hw_config=3D*/PERF_COUNT_HW_MAX); + list_del_init(&term->list); + parse_events_term__delete(term); + parse_events_terms__exit(&temp_terms); if (ret) goto out_err; + found_supported =3D true; if (first_wildcard_match =3D=3D NULL) first_wildcard_match =3D container_of(list->prev, struct evsel, core.node); diff --git a/tools/perf/util/parse-events.h b/tools/perf/util/parse-events.h index a5c5fc39fd6f..be8d2ac1e4e4 100644 --- a/tools/perf/util/parse-events.h +++ b/tools/perf/util/parse-events.h @@ -236,7 +236,8 @@ int parse_events_add_numeric(struct parse_events_state = *parse_state, bool wildcard); int parse_events_add_cache(struct list_head *list, int *idx, const char *n= ame, struct parse_events_state *parse_state, - struct parse_events_terms *parsed_terms); + struct parse_events_terms *parsed_terms, + void *loc); int parse_events__decode_legacy_cache(const char *name, int pmu_type, __u6= 4 *config); int parse_events_add_breakpoint(struct parse_events_state *parse_state, struct list_head *list, diff --git a/tools/perf/util/parse-events.y b/tools/perf/util/parse-events.y index a2361c0040d7..ced26c549c33 100644 --- a/tools/perf/util/parse-events.y +++ b/tools/perf/util/parse-events.y @@ -353,7 +353,7 @@ PE_LEGACY_CACHE opt_event_config if (!list) YYNOMEM; =20 - err =3D parse_events_add_cache(list, &parse_state->idx, $1, parse_state, = $2); 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charset="utf-8" Scan the software PMU first rather than last as it is the least likely to fail the probe. Specifying the software PMU by name was enabled by commit 9957d8c801fe ("perf jevents: Add common software event json"). For hardware events, add core PMU names when getting events to probe so that not all PMUs are scanned. For example, when legacy events support wildcards and for the event "cycles:u" on x86, we want to only scan the "cpu" PMU and not all uncore PMUs for the event too. Tested-by: Thomas Richter Signed-off-by: Ian Rogers --- tools/perf/util/perf_api_probe.c | 27 +++++++++++++++++++-------- 1 file changed, 19 insertions(+), 8 deletions(-) diff --git a/tools/perf/util/perf_api_probe.c b/tools/perf/util/perf_api_pr= obe.c index 1de3b69cdf4a..6ecf38314f01 100644 --- a/tools/perf/util/perf_api_probe.c +++ b/tools/perf/util/perf_api_probe.c @@ -59,10 +59,10 @@ static int perf_do_probe_api(setup_probe_fn_t fn, struc= t perf_cpu cpu, const cha =20 static bool perf_probe_api(setup_probe_fn_t fn) { - const char *try[] =3D {"cycles:u", "instructions:u", "cpu-clock:u", NULL}; + struct perf_pmu *pmu; struct perf_cpu_map *cpus; struct perf_cpu cpu; - int ret, i =3D 0; + int ret =3D 0; =20 cpus =3D perf_cpu_map__new_online_cpus(); if (!cpus) @@ -70,12 +70,23 @@ static bool perf_probe_api(setup_probe_fn_t fn) cpu =3D perf_cpu_map__cpu(cpus, 0); perf_cpu_map__put(cpus); =20 - do { - ret =3D perf_do_probe_api(fn, cpu, try[i++]); - if (!ret) - return true; - } while (ret =3D=3D -EAGAIN && try[i]); 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charset="utf-8" Whilst for many tools it is an expected behavior that failure to open a perf event is a failure, ARM decided to name PMU events the same as legacy events and then failed to rename such events on a server uncore SLC PMU. As perf's default behavior when no PMU is specified is to open the event on all PMUs that advertise/"have" the event, this yielded failures when trying to make the priority of legacy and sysfs/json events uniform - something requested by RISC-V and ARM. A legacy event user on ARM hardware may find their event opened on an uncore PMU which for perf record will fail. Arnaldo suggested skipping such events which this patch implements. Rather than have the skipping conditional on running on ARM, the skipping is done on all architectures as such a fundamental behavioral difference could lead to problems with tools built/depending on perf. An example of perf record failing to open events on x86 is: ``` $ perf record -e data_read,cycles,LLC-prefetch-read -a sleep 0.1 Error: Failure to open event 'data_read' on PMU 'uncore_imc_free_running_0' which = will be removed. The sys_perf_event_open() syscall returned with 22 (Invalid argument) for e= vent (data_read). "dmesg | grep -i perf" may provide additional information. Error: Failure to open event 'data_read' on PMU 'uncore_imc_free_running_1' which = will be removed. The sys_perf_event_open() syscall returned with 22 (Invalid argument) for e= vent (data_read). "dmesg | grep -i perf" may provide additional information. Error: Failure to open event 'LLC-prefetch-read' on PMU 'cpu' which will be remove= d. The LLC-prefetch-read event is not supported. [ perf record: Woken up 1 times to write data ] [ perf record: Captured and wrote 2.188 MB perf.data (87 samples) ] $ perf report --stats Aggregated stats: TOTAL events: 17255 MMAP events: 284 ( 1.6%) COMM events: 1961 (11.4%) EXIT events: 1 ( 0.0%) FORK events: 1960 (11.4%) SAMPLE events: 87 ( 0.5%) MMAP2 events: 12836 (74.4%) KSYMBOL events: 83 ( 0.5%) BPF_EVENT events: 36 ( 0.2%) FINISHED_ROUND events: 2 ( 0.0%) ID_INDEX events: 1 ( 0.0%) THREAD_MAP events: 1 ( 0.0%) CPU_MAP events: 1 ( 0.0%) TIME_CONV events: 1 ( 0.0%) FINISHED_INIT events: 1 ( 0.0%) cycles stats: SAMPLE events: 87 ``` If all events fail to open then the perf record will fail: ``` $ perf record -e LLC-prefetch-read true Error: Failure to open event 'LLC-prefetch-read' on PMU 'cpu' which will be remove= d. The LLC-prefetch-read event is not supported. Error: Failure to open any events for recording ``` As an evlist may have dummy events that open when all command line events fail we ignore dummy events when detecting if at least some events open. This still permits the dummy event on its own to be used as a permission check: ``` $ perf record -e dummy true [ perf record: Woken up 1 times to write data ] [ perf record: Captured and wrote 0.046 MB perf.data ] ``` but allows failure when a dummy event is implicilty inserted or when there are insufficient permissions to open it: ``` $ perf record -e LLC-prefetch-read -a true Error: Failure to open event 'LLC-prefetch-read' on PMU 'cpu' which will be remove= d. The LLC-prefetch-read event is not supported. Error: Failure to open any events for recording ``` As the first parsed event in an evlist is marked as tracking, removing this event can remove tracking from the evlist, removing mmap events and breaking symbolization. To avoid this, if a tracking event is removed then the next event has tracking added. The issue with legacy events is that on RISC-V they want the driver to not have mappings from legacy to non-legacy config encodings for each vendor/model due to size, complexity and difficulty to update. It was reported that on ARM Apple-M? CPUs the legacy mapping in the driver was broken and the sysfs/json events should always take precedent, however, it isn't clear this is still the case. It is the case that without working around this issue a legacy event like cycles without a PMU can encode differently than when specified with a PMU - the non-PMU version favoring legacy encodings, the PMU one avoiding legacy encodings. Legacy events are also case sensitive while sysfs/json events are not. The patch removes events and then adjusts the idx value for each evsel. This is done so that the dense xyarrays used for file descriptors, etc. don't contain broken entries. On ARM it could be common following this change to see a lot of warnings for the cycles event due to many ARM PMUs advertising the cycles event (ARM inconsistently have events bus_cycles and then cycles implying CPU cycles, they also sometimes have a cpu_cycles event). As cycles is a popular event, avoid potentially spamming users with error messages on ARM when there are multiple cycles events in the evlist, the error is still shown when verbose is enabled. Prior versions without adding the tracking data and not warning for cycles on ARM was: Suggested-by: Arnaldo Carvalho de Melo Tested-by: James Clark Tested-by: Leo Yan Tested-by: Atish Patra Tested-by: Thomas Richter Signed-off-by: Ian Rogers --- tools/perf/builtin-record.c | 89 ++++++++++++++++++++++++++++++++++--- 1 file changed, 82 insertions(+), 7 deletions(-) diff --git a/tools/perf/builtin-record.c b/tools/perf/builtin-record.c index 7ea3a11aca70..effe6802c1a3 100644 --- a/tools/perf/builtin-record.c +++ b/tools/perf/builtin-record.c @@ -983,7 +983,6 @@ static int record__config_tracking_events(struct record= *rec) */ if (opts->target.initial_delay || target__has_cpu(&opts->target) || perf_pmus__num_core_pmus() > 1) { - /* * User space tasks can migrate between CPUs, so when tracing * selected CPUs, sideband for all CPUs is still needed. @@ -1388,10 +1387,27 @@ static int record__open(struct record *rec) struct perf_session *session =3D rec->session; struct record_opts *opts =3D &rec->opts; int rc =3D 0; + bool skipped =3D false; + bool removed_tracking =3D false; =20 evlist__for_each_entry(evlist, pos) { + if (removed_tracking) { + /* + * Normally the head of the list has tracking enabled + * for sideband data like mmaps. If this event is + * removed, make sure to add tracking to the next + * processed event. + */ + if (!pos->tracking) { + pos->tracking =3D true; + evsel__config(pos, opts, &callchain_param); + } + removed_tracking =3D false; + } try_again: if (evsel__open(pos, pos->core.cpus, pos->core.threads) < 0) { + bool report_error =3D true; + if (evsel__fallback(pos, &opts->target, errno, msg, sizeof(msg))) { if (verbose > 0) ui__warning("%s\n", msg); @@ -1403,15 +1419,74 @@ static int record__open(struct record *rec) pos =3D evlist__reset_weak_group(evlist, pos, true); goto try_again; } - rc =3D -errno; - evsel__open_strerror(pos, &opts->target, errno, msg, sizeof(msg)); - ui__error("%s\n", msg); - goto out; +#if defined(__aarch64__) || defined(__arm__) + if (strstr(evsel__name(pos), "cycles")) { + struct evsel *pos2; + /* + * Unfortunately ARM has many events named + * "cycles" on PMUs like the system-level (L3) + * cache which don't support sampling. Only + * display such failures to open when there is + * only 1 cycles event or verbose is enabled. + */ + evlist__for_each_entry(evlist, pos2) { + if (pos2 =3D=3D pos) + continue; + if (strstr(evsel__name(pos2), "cycles")) { + report_error =3D false; + break; + } + } + } +#endif + if (report_error || verbose > 0) { + ui__error("Failure to open event '%s' on PMU '%s' which will be " + "removed.\n%s\n", + evsel__name(pos), evsel__pmu_name(pos), msg); + } + if (pos->tracking) + removed_tracking =3D true; + pos->skippable =3D true; + skipped =3D true; + } else { + pos->supported =3D true; } - - pos->supported =3D true; } =20 + if (skipped) { + struct evsel *tmp; + int idx =3D 0; + bool evlist_empty =3D true; + + /* Remove evsels that failed to open and update indices. */ + evlist__for_each_entry_safe(evlist, tmp, pos) { + if (pos->skippable) { + evlist__remove(evlist, pos); + continue; + } + + /* + * Note, dummy events may be command line parsed or + * added by the tool. We care about supporting `perf + * record -e dummy` which may be used as a permission + * check. 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Mon, 22 Sep 2025 21:18:58 -0700 (PDT) Date: Mon, 22 Sep 2025 21:18:24 -0700 In-Reply-To: <20250923041844.400164-1-irogers@google.com> Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: Mime-Version: 1.0 References: <20250923041844.400164-1-irogers@google.com> X-Mailer: git-send-email 2.51.0.534.gc79095c0ca-goog Message-ID: <20250923041844.400164-6-irogers@google.com> Subject: [PATCH v5 05/25] perf jevents: Support copying the source json files to OUTPUT From: Ian Rogers To: Peter Zijlstra , Ingo Molnar , Arnaldo Carvalho de Melo , Namhyung Kim , Mark Rutland , Alexander Shishkin , Jiri Olsa , Ian Rogers , Adrian Hunter , Kan Liang , James Clark , Xu Yang , Thomas Falcon , Andi Kleen , linux-kernel@vger.kernel.org, linux-perf-users@vger.kernel.org, bpf@vger.kernel.org, Atish Patra , Beeman Strong , Leo Yan , Vince Weaver Cc: Thomas Richter Content-Transfer-Encoding: quoted-printable Content-Type: text/plain; charset="utf-8" The jevents command expects all json files to be organized under a single directory. When generating json files from scripts (to reduce laborious copy and paste in the json) we don't want to generate the json into the source directory if there is an OUTPUT directory specified. This change adds a GEN_JSON for this case where the GEN_JSON copies the JSON files to OUTPUT, only when OUTPUT is specified. The Makefile.perf clean code is updated to clean up this directory when present. This patch is part of: https://lore.kernel.org/lkml/20240926173554.404411-12-irogers@google.com/ which was similarly adding support for generating json in scripts for the consumption of jevents.py. Tested-by: Thomas Richter Signed-off-by: Ian Rogers --- tools/perf/Makefile.perf | 21 ++++++++++++++++----- tools/perf/pmu-events/Build | 18 ++++++++++++------ 2 files changed, 28 insertions(+), 11 deletions(-) diff --git a/tools/perf/Makefile.perf b/tools/perf/Makefile.perf index e2150acc2c13..cc1635335586 100644 --- a/tools/perf/Makefile.perf +++ b/tools/perf/Makefile.perf @@ -1272,9 +1272,24 @@ endif # CONFIG_PERF_BPF_SKEL bpf-skel-clean: $(call QUIET_CLEAN, bpf-skel) $(RM) -r $(SKEL_TMP_OUT) $(SKELETONS) $(SKE= L_OUT)/vmlinux.h =20 +pmu-events-clean: +ifeq ($(OUTPUT),) + $(call QUIET_CLEAN, pmu-events) $(RM) \ + pmu-events/pmu-events.c \ + pmu-events/metric_test.log \ + pmu-events/test-empty-pmu-events.c \ + pmu-events/empty-pmu-events.log +else # When an OUTPUT directory is present, clean up the copied pmu-events= /arch directory. + $(call QUIET_CLEAN, pmu-events) $(RM) -r $(OUTPUT)pmu-events/arch \ + $(OUTPUT)pmu-events/pmu-events.c \ + $(OUTPUT)pmu-events/metric_test.log \ + $(OUTPUT)pmu-events/test-empty-pmu-events.c \ + $(OUTPUT)pmu-events/empty-pmu-events.log +endif + clean:: $(LIBAPI)-clean $(LIBBPF)-clean $(LIBSUBCMD)-clean $(LIBSYMBOL)-cl= ean $(LIBPERF)-clean \ arm64-sysreg-defs-clean fixdep-clean python-clean bpf-skel-clean \ - tests-coresight-targets-clean + tests-coresight-targets-clean pmu-events-clean $(call QUIET_CLEAN, core-objs) $(RM) $(LIBPERF_A) $(OUTPUT)perf-archive \ $(OUTPUT)perf-iostat $(LANG_BINDINGS) $(Q)find $(or $(OUTPUT),.) -name '*.o' -delete -o -name '*.a' -delete -o \ @@ -1287,10 +1302,6 @@ clean:: $(LIBAPI)-clean $(LIBBPF)-clean $(LIBSUBCMD)= -clean $(LIBSYMBOL)-clean $( $(OUTPUT)FEATURE-DUMP $(OUTPUT)util/*-bison* $(OUTPUT)util/*-flex* \ $(OUTPUT)util/intel-pt-decoder/inat-tables.c \ $(OUTPUT)tests/llvm-src-{base,kbuild,prologue,relocation}.c \ - $(OUTPUT)pmu-events/pmu-events.c \ - $(OUTPUT)pmu-events/test-empty-pmu-events.c \ - $(OUTPUT)pmu-events/empty-pmu-events.log \ - $(OUTPUT)pmu-events/metric_test.log \ $(OUTPUT)$(fadvise_advice_array) \ $(OUTPUT)$(fsconfig_arrays) \ $(OUTPUT)$(fsmount_arrays) \ diff --git a/tools/perf/pmu-events/Build b/tools/perf/pmu-events/Build index 32f387d48908..1503a16e662a 100644 --- a/tools/perf/pmu-events/Build +++ b/tools/perf/pmu-events/Build @@ -1,7 +1,6 @@ pmu-events-y +=3D pmu-events.o JDIR =3D pmu-events/arch/$(SRCARCH) -JSON =3D $(shell [ -d $(JDIR) ] && \ - find $(JDIR) -name '*.json' -o -name 'mapfile.csv') +JSON =3D $(shell find pmu-events/arch -name *.json -o -name *.csv) JDIR_TEST =3D pmu-events/arch/test JSON_TEST =3D $(shell [ -d $(JDIR_TEST) ] && \ find $(JDIR_TEST) -name '*.json') @@ -29,13 +28,20 @@ $(PMU_EVENTS_C): $(EMPTY_PMU_EVENTS_C) $(call rule_mkdir) $(Q)$(call echo-cmd,gen)cp $< $@ else +# Copy checked-in json for generation. +$(OUTPUT)pmu-events/arch/%: pmu-events/arch/% + $(call rule_mkdir) + $(Q)$(call echo-cmd,gen)cp $< $@ + +GEN_JSON =3D $(patsubst %,$(OUTPUT)%,$(JSON)) + $(METRIC_TEST_LOG): $(METRIC_TEST_PY) $(METRIC_PY) $(call rule_mkdir) $(Q)$(call echo-cmd,test)$(PYTHON) $< 2> $@ || (cat $@ && false) =20 -$(TEST_EMPTY_PMU_EVENTS_C): $(JSON) $(JSON_TEST) $(JEVENTS_PY) $(METRIC_PY= ) $(METRIC_TEST_LOG) +$(TEST_EMPTY_PMU_EVENTS_C): $(GEN_JSON) $(JSON_TEST) $(JEVENTS_PY) $(METRI= C_PY) $(METRIC_TEST_LOG) $(call rule_mkdir) - $(Q)$(call echo-cmd,gen)$(PYTHON) $(JEVENTS_PY) none none pmu-events/arch= $@ + $(Q)$(call echo-cmd,gen)$(PYTHON) $(JEVENTS_PY) none none $(OUTPUT)pmu-ev= ents/arch $@ =20 $(EMPTY_PMU_EVENTS_TEST_LOG): $(EMPTY_PMU_EVENTS_C) $(TEST_EMPTY_PMU_EVENT= S_C) $(call rule_mkdir) @@ -63,10 +69,10 @@ $(OUTPUT)%.pylint_log: % $(call rule_mkdir) $(Q)$(call echo-cmd,test)pylint "$<" > $@ || (cat $@ && rm $@ && false) =20 -$(PMU_EVENTS_C): $(JSON) $(JSON_TEST) $(JEVENTS_PY) $(METRIC_PY) $(METRIC_= TEST_LOG) \ +$(PMU_EVENTS_C): $(GEN_JSON) $(JSON_TEST) $(JEVENTS_PY) $(METRIC_PY) $(MET= RIC_TEST_LOG) \ $(EMPTY_PMU_EVENTS_TEST_LOG) $(PMU_EVENTS_MYPY_TEST_LOGS) $(PMU_EVENTS= _PYLINT_TEST_LOGS) $(call rule_mkdir) - $(Q)$(call echo-cmd,gen)$(PYTHON) $(JEVENTS_PY) $(JEVENTS_ARCH) $(JEVENTS= _MODEL) pmu-events/arch $@ + $(Q)$(call echo-cmd,gen)$(PYTHON) $(JEVENTS_PY) $(JEVENTS_ARCH) $(JEVENTS= _MODEL) $(OUTPUT)pmu-events/arch $@ endif =20 # pmu-events.c file is generated in the OUTPUT directory so it needs a --=20 2.51.0.534.gc79095c0ca-goog From nobody Thu Oct 2 03:27:35 2025 Received: from mail-pj1-f74.google.com (mail-pj1-f74.google.com [209.85.216.74]) (using TLSv1.2 with cipher ECDHE-RSA-AES128-GCM-SHA256 (128/128 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id 8BD0527FB25 for ; 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Mon, 22 Sep 2025 21:19:01 -0700 (PDT) Date: Mon, 22 Sep 2025 21:18:25 -0700 In-Reply-To: <20250923041844.400164-1-irogers@google.com> Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: Mime-Version: 1.0 References: <20250923041844.400164-1-irogers@google.com> X-Mailer: git-send-email 2.51.0.534.gc79095c0ca-goog Message-ID: <20250923041844.400164-7-irogers@google.com> Subject: [PATCH v5 06/25] perf pmu: Don't eagerly parse event terms From: Ian Rogers To: Peter Zijlstra , Ingo Molnar , Arnaldo Carvalho de Melo , Namhyung Kim , Mark Rutland , Alexander Shishkin , Jiri Olsa , Ian Rogers , Adrian Hunter , Kan Liang , James Clark , Xu Yang , Thomas Falcon , Andi Kleen , linux-kernel@vger.kernel.org, linux-perf-users@vger.kernel.org, bpf@vger.kernel.org, Atish Patra , Beeman Strong , Leo Yan , Vince Weaver Cc: Thomas Richter Content-Transfer-Encoding: quoted-printable Content-Type: text/plain; charset="utf-8" When an event/alias is created for a PMU the terms are eagerly parsed using parse_events_terms. For a command like perf stat or perf record, the particularly event/alias will be found, the terms parsed, the terms cloned for use in the event parsing, and then the terms used to configure the perf_event_attr. Events/aliases may be eagerly loaded, such as from sysfs or in perf list, in which case the aliases terms will be little or never used. To avoid redundant work, to avoid cloning, and to reduce memory overhead, hold the terms for an event as a string until they need handling as a term list. This may introduce duplicate parsing if an event is repeated in a list, but this situation is expected to be uncommon. Measuring the number of instructions before and after with a sysfs event and perf stat, there is a minor reduction in the number of instructions executed by 0.3%. Tested-by: Thomas Richter Signed-off-by: Ian Rogers --- tools/perf/tests/pmu-events.c | 24 +------ tools/perf/util/parse-events.c | 3 +- tools/perf/util/parse-events.h | 1 - tools/perf/util/pmu.c | 111 ++++++++++++++++++++------------- 4 files changed, 70 insertions(+), 69 deletions(-) diff --git a/tools/perf/tests/pmu-events.c b/tools/perf/tests/pmu-events.c index 95fd9f671a22..f40a828c9861 100644 --- a/tools/perf/tests/pmu-events.c +++ b/tools/perf/tests/pmu-events.c @@ -22,10 +22,6 @@ struct perf_pmu_test_event { /* used for matching against events from generated pmu-events.c */ struct pmu_event event; =20 - /* used for matching against event aliases */ - /* extra events for aliases */ - const char *alias_str; - /* * Note: For when PublicDescription does not exist in the JSON, we * will have no long_desc in pmu_event.long_desc, but long_desc may @@ -52,7 +48,6 @@ static const struct perf_pmu_test_event bp_l1_btb_correct= =3D { .desc =3D "L1 BTB Correction", .topic =3D "branch", }, - .alias_str =3D "event=3D0x8a", }; =20 static const struct perf_pmu_test_event bp_l2_btb_correct =3D { @@ -63,7 +58,6 @@ static const struct perf_pmu_test_event bp_l2_btb_correct= =3D { .desc =3D "L2 BTB Correction", .topic =3D "branch", }, - .alias_str =3D "event=3D0x8b", }; =20 static const struct perf_pmu_test_event segment_reg_loads_any =3D { @@ -74,7 +68,6 @@ static const struct perf_pmu_test_event segment_reg_loads= _any =3D { .desc =3D "Number of segment register loads", .topic =3D "other", }, - .alias_str =3D "event=3D0x6,period=3D0x30d40,umask=3D0x80", }; =20 static const struct perf_pmu_test_event dispatch_blocked_any =3D { @@ -85,7 +78,6 @@ static const struct perf_pmu_test_event dispatch_blocked_= any =3D { .desc =3D "Memory cluster signals to block micro-op dispatch for any rea= son", .topic =3D "other", }, - .alias_str =3D "event=3D0x9,period=3D0x30d40,umask=3D0x20", }; =20 static const struct perf_pmu_test_event eist_trans =3D { @@ -96,7 +88,6 @@ static const struct perf_pmu_test_event eist_trans =3D { .desc =3D "Number of Enhanced Intel SpeedStep(R) Technology (EIST) trans= itions", .topic =3D "other", }, - .alias_str =3D "event=3D0x3a,period=3D0x30d40", }; =20 static const struct perf_pmu_test_event l3_cache_rd =3D { @@ -108,7 +99,6 @@ static const struct perf_pmu_test_event l3_cache_rd =3D { .long_desc =3D "Attributable Level 3 cache access, read", .topic =3D "cache", }, - .alias_str =3D "event=3D0x40", .alias_long_desc =3D "Attributable Level 3 cache access, read", }; =20 @@ -130,7 +120,6 @@ static const struct perf_pmu_test_event uncore_hisi_ddr= c_flux_wcmd =3D { .topic =3D "uncore", .pmu =3D "hisi_sccl,ddrc", }, - .alias_str =3D "event=3D0x2", .matching_pmu =3D "hisi_sccl1_ddrc2", }; =20 @@ -142,7 +131,6 @@ static const struct perf_pmu_test_event unc_cbo_xsnp_re= sponse_miss_eviction =3D { .topic =3D "uncore", .pmu =3D "uncore_cbox", }, - .alias_str =3D "event=3D0x22,umask=3D0x81", .matching_pmu =3D "uncore_cbox_0", }; =20 @@ -154,7 +142,6 @@ static const struct perf_pmu_test_event uncore_hyphen = =3D { .topic =3D "uncore", .pmu =3D "uncore_cbox", }, - .alias_str =3D "event=3D0xe0", .matching_pmu =3D "uncore_cbox_0", }; =20 @@ -166,7 +153,6 @@ static const struct perf_pmu_test_event uncore_two_hyph= =3D { .topic =3D "uncore", .pmu =3D "uncore_cbox", }, - .alias_str =3D "event=3D0xc0", .matching_pmu =3D "uncore_cbox_0", }; =20 @@ -178,7 +164,6 @@ static const struct perf_pmu_test_event uncore_hisi_l3c= _rd_hit_cpipe =3D { .topic =3D "uncore", .pmu =3D "hisi_sccl,l3c", }, - .alias_str =3D "event=3D0x7", .matching_pmu =3D "hisi_sccl3_l3c7", }; =20 @@ -190,7 +175,6 @@ static const struct perf_pmu_test_event uncore_imc_free= _running_cache_miss =3D { .topic =3D "uncore", .pmu =3D "uncore_imc_free_running", }, - .alias_str =3D "event=3D0x12", .matching_pmu =3D "uncore_imc_free_running_0", }; =20 @@ -202,7 +186,6 @@ static const struct perf_pmu_test_event uncore_imc_cach= e_hits =3D { .topic =3D "uncore", .pmu =3D "uncore_imc", }, - .alias_str =3D "event=3D0x34", .matching_pmu =3D "uncore_imc_0", }; =20 @@ -226,7 +209,6 @@ static const struct perf_pmu_test_event sys_ddr_pmu_wri= te_cycles =3D { .pmu =3D "uncore_sys_ddr_pmu", .compat =3D "v8", }, - .alias_str =3D "event=3D0x2b", .matching_pmu =3D "uncore_sys_ddr_pmu0", }; =20 @@ -239,7 +221,6 @@ static const struct perf_pmu_test_event sys_ccn_pmu_rea= d_cycles =3D { .pmu =3D "uncore_sys_ccn_pmu", .compat =3D "0x01", }, - .alias_str =3D "config=3D0x2c", .matching_pmu =3D "uncore_sys_ccn_pmu4", }; =20 @@ -252,7 +233,6 @@ static const struct perf_pmu_test_event sys_cmn_pmu_hnf= _cache_miss =3D { .pmu =3D "uncore_sys_cmn_pmu", .compat =3D "(434|436|43c|43a).*", }, - .alias_str =3D "eventid=3D0x1,type=3D0x5", .matching_pmu =3D "uncore_sys_cmn_pmu0", }; =20 @@ -374,9 +354,9 @@ static int compare_alias_to_test_event(struct pmu_event= _info *alias, return -1; } =20 - if (!is_same(alias->str, test_event->alias_str)) { + if (!is_same(alias->str, test_event->event.event)) { pr_debug("testing aliases PMU %s: mismatched str, %s vs %s\n", - pmu_name, alias->str, test_event->alias_str); + pmu_name, alias->str, test_event->event.event); return -1; } =20 diff --git a/tools/perf/util/parse-events.c b/tools/perf/util/parse-events.c index d5675471afc5..9ec1738a5a64 100644 --- a/tools/perf/util/parse-events.c +++ b/tools/perf/util/parse-events.c @@ -40,6 +40,7 @@ static int get_config_terms(const struct parse_events_ter= ms *head_config, struct list_head *head_terms); static int parse_events_terms__copy(const struct parse_events_terms *src, struct parse_events_terms *dest); +static int parse_events_terms__to_strbuf(const struct parse_events_terms *= terms, struct strbuf *sb); =20 const struct event_symbol event_symbols_hw[PERF_COUNT_HW_MAX] =3D { [PERF_COUNT_HW_CPU_CYCLES] =3D { @@ -2854,7 +2855,7 @@ void parse_events_terms__delete(struct parse_events_t= erms *terms) free(terms); } =20 -int parse_events_terms__to_strbuf(const struct parse_events_terms *terms, = struct strbuf *sb) +static int parse_events_terms__to_strbuf(const struct parse_events_terms *= terms, struct strbuf *sb) { struct parse_events_term *term; bool first =3D true; diff --git a/tools/perf/util/parse-events.h b/tools/perf/util/parse-events.h index be8d2ac1e4e4..9c975bb09fe8 100644 --- a/tools/perf/util/parse-events.h +++ b/tools/perf/util/parse-events.h @@ -199,7 +199,6 @@ void parse_events_terms__delete(struct parse_events_ter= ms *terms); void parse_events_terms__init(struct parse_events_terms *terms); void parse_events_terms__exit(struct parse_events_terms *terms); int parse_events_terms(struct parse_events_terms *terms, const char *str, = FILE *input); -int parse_events_terms__to_strbuf(const struct parse_events_terms *terms, = struct strbuf *sb); =20 struct parse_events_modifier { u8 precise; /* Number of repeated 'p' for precision. */ diff --git a/tools/perf/util/pmu.c b/tools/perf/util/pmu.c index 5a291f1380ed..ddcd4918832d 100644 --- a/tools/perf/util/pmu.c +++ b/tools/perf/util/pmu.c @@ -67,8 +67,8 @@ struct perf_pmu_alias { * json events. */ char *topic; - /** @terms: Owned list of the original parsed parameters. */ - struct parse_events_terms terms; + /** @terms: Owned copy of the event terms. */ + char *terms; /** * @pmu_name: The name copied from the json struct pmu_event. This can * differ from the PMU name as it won't have suffixes. @@ -429,7 +429,7 @@ static void perf_pmu_free_alias(struct perf_pmu_alias *= alias) zfree(&alias->long_desc); zfree(&alias->topic); zfree(&alias->pmu_name); - parse_events_terms__exit(&alias->terms); + zfree(&alias->terms); free(alias); } =20 @@ -537,8 +537,8 @@ static int update_alias(const struct pmu_event *pe, assign_str(pe->name, "topic", &data->alias->topic, pe->topic); data->alias->per_pkg =3D pe->perpkg; if (pe->event) { - parse_events_terms__exit(&data->alias->terms); - ret =3D parse_events_terms(&data->alias->terms, pe->event, /*input=3D*/N= ULL); + zfree(&data->alias->terms); + data->alias->terms =3D strdup(pe->event); } if (!ret && pe->unit) { char *unit; @@ -590,7 +590,6 @@ static int perf_pmu__new_alias(struct perf_pmu *pmu, co= nst char *name, if (!alias) return -ENOMEM; =20 - parse_events_terms__init(&alias->terms); alias->scale =3D 1.0; alias->unit[0] =3D '\0'; alias->per_pkg =3D perpkg; @@ -615,11 +614,16 @@ static int perf_pmu__new_alias(struct perf_pmu *pmu, = const char *name, if (ret) return ret; =20 - ret =3D parse_events_terms(&alias->terms, val, val_fd); - if (ret) { - pr_err("Cannot parse alias %s: %d\n", val, ret); - free(alias); - return ret; + if (!val_fd) { + alias->terms =3D strdup(val); + } else { + size_t line_len; + + ret =3D getline(&alias->terms, &line_len, val_fd) < 0 ? -errno : 0; + if (ret) { + pr_err("Failed to read alias %s\n", name); + return ret; + } } =20 alias->name =3D strdup(name); @@ -767,29 +771,21 @@ static int pmu_aliases_parse_eager(struct perf_pmu *p= mu, int sysfs_fd) return ret; } =20 -static int pmu_alias_terms(struct perf_pmu_alias *alias, int err_loc, stru= ct list_head *terms) +static int pmu_alias_terms(struct perf_pmu_alias *alias, struct list_head = *terms) { - struct parse_events_term *term, *cloned; - struct parse_events_terms clone_terms; - - parse_events_terms__init(&clone_terms); - list_for_each_entry(term, &alias->terms.terms, list) { - int ret =3D parse_events_term__clone(&cloned, term); + struct parse_events_terms alias_terms; + int ret; =20 - if (ret) { - parse_events_terms__exit(&clone_terms); - return ret; - } - /* - * Weak terms don't override command line options, - * which we don't want for implicit terms in aliases. - */ - cloned->weak =3D true; - cloned->err_term =3D cloned->err_val =3D err_loc; - list_add_tail(&cloned->list, &clone_terms.terms); + parse_events_terms__init(&alias_terms); + ret =3D parse_events_terms(&alias_terms, alias->terms, /*input=3D*/NULL); + if (ret) { + pr_err("Cannot parse '%s' terms '%s': %d\n", + alias->name, alias->terms, ret); + parse_events_terms__exit(&alias_terms); + return ret; } - list_splice_init(&clone_terms.terms, terms); - parse_events_terms__exit(&clone_terms); + list_splice_init(&alias_terms.terms, terms); + parse_events_terms__exit(&alias_terms); return 0; } =20 @@ -1813,10 +1809,10 @@ int perf_pmu__check_alias(struct perf_pmu *pmu, str= uct parse_events_terms *head_ alias =3D pmu_find_alias(pmu, term); if (!alias) continue; - ret =3D pmu_alias_terms(alias, term->err_term, &term->list); + ret =3D pmu_alias_terms(alias, &term->list); if (ret) { parse_events_error__handle(err, term->err_term, - strdup("Failure to duplicate terms"), + strdup("Failed to parse terms"), NULL); return ret; } @@ -2035,18 +2031,37 @@ static int sub_non_neg(int a, int b) static char *format_alias(char *buf, int len, const struct perf_pmu *pmu, const struct perf_pmu_alias *alias, bool skip_duplicate_pmus) { + struct parse_events_terms terms; struct parse_events_term *term; + int ret, used; size_t pmu_name_len =3D pmu_deduped_name_len(pmu, pmu->name, skip_duplicate_pmus); - int used =3D snprintf(buf, len, "%.*s/%s", (int)pmu_name_len, pmu->name, = alias->name); =20 - list_for_each_entry(term, &alias->terms.terms, list) { + /* Paramemterized events have the parameters shown. */ + if (strstr(alias->terms, "=3D?")) { + /* No parameters. */ + snprintf(buf, len, "%.*s/%s/", (int)pmu_name_len, pmu->name, alias->name= ); + return buf; + } + + parse_events_terms__init(&terms); + ret =3D parse_events_terms(&terms, alias->terms, /*input=3D*/NULL); + if (ret) { + pr_err("Failure to parse '%s' terms '%s': %d\n", + alias->name, alias->terms, ret); + parse_events_terms__exit(&terms); + snprintf(buf, len, "%.*s/%s/", (int)pmu_name_len, pmu->name, alias->name= ); + return buf; + } + used =3D snprintf(buf, len, "%.*s/%s", (int)pmu_name_len, pmu->name, alia= s->name); + + list_for_each_entry(term, &terms.terms, list) { if (term->type_val =3D=3D PARSE_EVENTS__TERM_TYPE_STR) used +=3D snprintf(buf + used, sub_non_neg(len, used), ",%s=3D%s", term->config, term->val.str); } - + parse_events_terms__exit(&terms); if (sub_non_neg(len, used) > 0) { buf[used] =3D '/'; used++; @@ -2069,7 +2084,6 @@ int perf_pmu__for_each_event(struct perf_pmu *pmu, bo= ol skip_duplicate_pmus, .event_type_desc =3D "Kernel PMU event", }; int ret =3D 0; - struct strbuf sb; struct hashmap_entry *entry; size_t bkt; =20 @@ -2080,7 +2094,6 @@ int perf_pmu__for_each_event(struct perf_pmu *pmu, bo= ol skip_duplicate_pmus, if (perf_pmu__is_drm(pmu)) return drm_pmu__for_each_event(pmu, state, cb); =20 - strbuf_init(&sb, /*hint=3D*/ 0); pmu_aliases_parse(pmu); pmu_add_cpu_aliases(pmu); hashmap__for_each_entry(pmu->aliases, entry, bkt) { @@ -2115,16 +2128,14 @@ int perf_pmu__for_each_event(struct perf_pmu *pmu, = bool skip_duplicate_pmus, info.desc =3D event->desc; info.long_desc =3D event->long_desc; info.encoding_desc =3D buf + buf_used; - parse_events_terms__to_strbuf(&event->terms, &sb); buf_used +=3D snprintf(buf + buf_used, sizeof(buf) - buf_used, - "%.*s/%s/", (int)pmu_name_len, info.pmu_name, sb.buf) + 1; + "%.*s/%s/", (int)pmu_name_len, info.pmu_name, event->terms) + 1; + info.str =3D event->terms; info.topic =3D event->topic; - info.str =3D sb.buf; info.deprecated =3D event->deprecated; ret =3D cb(state, &info); if (ret) goto out; - strbuf_setlen(&sb, /*len=3D*/ 0); } if (pmu->selectable) { info.name =3D buf; @@ -2140,7 +2151,6 @@ int perf_pmu__for_each_event(struct perf_pmu *pmu, bo= ol skip_duplicate_pmus, ret =3D cb(state, &info); } out: - strbuf_release(&sb); return ret; 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Mon, 22 Sep 2025 21:19:04 -0700 (PDT) Date: Mon, 22 Sep 2025 21:18:26 -0700 In-Reply-To: <20250923041844.400164-1-irogers@google.com> Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: Mime-Version: 1.0 References: <20250923041844.400164-1-irogers@google.com> X-Mailer: git-send-email 2.51.0.534.gc79095c0ca-goog Message-ID: <20250923041844.400164-8-irogers@google.com> Subject: [PATCH v5 07/25] perf parse-events: Remove unused FILE input argument to scanner From: Ian Rogers To: Peter Zijlstra , Ingo Molnar , Arnaldo Carvalho de Melo , Namhyung Kim , Mark Rutland , Alexander Shishkin , Jiri Olsa , Ian Rogers , Adrian Hunter , Kan Liang , James Clark , Xu Yang , Thomas Falcon , Andi Kleen , linux-kernel@vger.kernel.org, linux-perf-users@vger.kernel.org, bpf@vger.kernel.org, Atish Patra , Beeman Strong , Leo Yan , Vince Weaver Cc: Thomas Richter Content-Transfer-Encoding: quoted-printable Content-Type: text/plain; charset="utf-8" Now the events file isn't directly parsed from a FILE but stored in a string prior to parsing, remove the FILE argument to the associated scanner functions as they only ever pass NULL. Tested-by: Thomas Richter Signed-off-by: Ian Rogers --- tools/perf/arch/x86/util/intel-pt.c | 2 +- tools/perf/tests/parse-events.c | 2 +- tools/perf/tests/pmu.c | 3 +-- tools/perf/util/parse-events.c | 18 ++++++------------ tools/perf/util/parse-events.h | 3 +-- tools/perf/util/pmu.c | 6 +++--- 6 files changed, 13 insertions(+), 21 deletions(-) diff --git a/tools/perf/arch/x86/util/intel-pt.c b/tools/perf/arch/x86/util= /intel-pt.c index add33cb5d1da..2d7c0dec86b0 100644 --- a/tools/perf/arch/x86/util/intel-pt.c +++ b/tools/perf/arch/x86/util/intel-pt.c @@ -72,7 +72,7 @@ static int intel_pt_parse_terms_with_default(const struct= perf_pmu *pmu, int err; =20 parse_events_terms__init(&terms); - err =3D parse_events_terms(&terms, str, /*input=3D*/ NULL); + err =3D parse_events_terms(&terms, str); if (err) goto out_free; =20 diff --git a/tools/perf/tests/parse-events.c b/tools/perf/tests/parse-event= s.c index bb8004397650..4e55b0d295bd 100644 --- a/tools/perf/tests/parse-events.c +++ b/tools/perf/tests/parse-events.c @@ -2556,7 +2556,7 @@ static int test_term(const struct terms_test *t) =20 =20 parse_events_terms__init(&terms); - ret =3D parse_events_terms(&terms, t->str, /*input=3D*/ NULL); + ret =3D parse_events_terms(&terms, t->str); if (ret) { pr_debug("failed to parse terms '%s', err %d\n", t->str , ret); diff --git a/tools/perf/tests/pmu.c b/tools/perf/tests/pmu.c index 4a9f8e090cf4..cbded2c6faa4 100644 --- a/tools/perf/tests/pmu.c +++ b/tools/perf/tests/pmu.c @@ -169,8 +169,7 @@ static int test__pmu_format(struct test_suite *test __m= aybe_unused, int subtest parse_events_terms__init(&terms); if (parse_events_terms(&terms, "krava01=3D15,krava02=3D170,krava03=3D1,krava11=3D27,krava12=3D1," - "krava13=3D2,krava21=3D119,krava22=3D11,krava23=3D2", - NULL)) { + "krava13=3D2,krava21=3D119,krava22=3D11,krava23=3D2")) { pr_err("Term parsing failed\n"); goto err_out; } diff --git a/tools/perf/util/parse-events.c b/tools/perf/util/parse-events.c index 9ec1738a5a64..c3c934da6083 100644 --- a/tools/perf/util/parse-events.c +++ b/tools/perf/util/parse-events.c @@ -1962,7 +1962,6 @@ int parse_events__set_default_name(struct list_head *= list, char *name) } =20 static int parse_events__scanner(const char *str, - FILE *input, struct parse_events_state *parse_state) { YY_BUFFER_STATE buffer; @@ -1973,10 +1972,7 @@ static int parse_events__scanner(const char *str, if (ret) return ret; =20 - if (str) - buffer =3D parse_events__scan_string(str, scanner); - else - parse_events_set_in(input, scanner); + buffer =3D parse_events__scan_string(str, scanner); =20 #ifdef PARSER_DEBUG parse_events_debug =3D 1; @@ -1984,10 +1980,8 @@ static int parse_events__scanner(const char *str, #endif ret =3D parse_events_parse(parse_state, scanner); =20 - if (str) { - parse_events__flush_buffer(buffer, scanner); - parse_events__delete_buffer(buffer, scanner); - } + parse_events__flush_buffer(buffer, scanner); + parse_events__delete_buffer(buffer, scanner); parse_events_lex_destroy(scanner); return ret; } @@ -1995,7 +1989,7 @@ static int parse_events__scanner(const char *str, /* * parse event config string, return a list of event terms. */ -int parse_events_terms(struct parse_events_terms *terms, const char *str, = FILE *input) +int parse_events_terms(struct parse_events_terms *terms, const char *str) { struct parse_events_state parse_state =3D { .terms =3D NULL, @@ -2003,7 +1997,7 @@ int parse_events_terms(struct parse_events_terms *ter= ms, const char *str, FILE * }; int ret; =20 - ret =3D parse_events__scanner(str, input, &parse_state); + ret =3D parse_events__scanner(str, &parse_state); if (!ret) list_splice(&parse_state.terms->terms, &terms->terms); =20 @@ -2307,7 +2301,7 @@ int __parse_events(struct evlist *evlist, const char = *str, const char *pmu_filte }; int ret, ret2; =20 - ret =3D parse_events__scanner(str, /*input=3D*/ NULL, &parse_state); + ret =3D parse_events__scanner(str, &parse_state); =20 if (!ret && list_empty(&parse_state.list)) { WARN_ONCE(true, "WARNING: event parser found nothing\n"); diff --git a/tools/perf/util/parse-events.h b/tools/perf/util/parse-events.h index 9c975bb09fe8..048b38e476f3 100644 --- a/tools/perf/util/parse-events.h +++ b/tools/perf/util/parse-events.h @@ -9,7 +9,6 @@ #include #include #include -#include #include #include =20 @@ -198,7 +197,7 @@ void parse_events_term__delete(struct parse_events_term= *term); void parse_events_terms__delete(struct parse_events_terms *terms); void parse_events_terms__init(struct parse_events_terms *terms); void parse_events_terms__exit(struct parse_events_terms *terms); -int parse_events_terms(struct parse_events_terms *terms, const char *str, = FILE *input); +int parse_events_terms(struct parse_events_terms *terms, const char *str); =20 struct parse_events_modifier { u8 precise; /* Number of repeated 'p' for precision. */ diff --git a/tools/perf/util/pmu.c b/tools/perf/util/pmu.c index ddcd4918832d..b44dfe4c73fc 100644 --- a/tools/perf/util/pmu.c +++ b/tools/perf/util/pmu.c @@ -777,7 +777,7 @@ static int pmu_alias_terms(struct perf_pmu_alias *alias= , struct list_head *terms int ret; =20 parse_events_terms__init(&alias_terms); - ret =3D parse_events_terms(&alias_terms, alias->terms, /*input=3D*/NULL); + ret =3D parse_events_terms(&alias_terms, alias->terms); if (ret) { pr_err("Cannot parse '%s' terms '%s': %d\n", alias->name, alias->terms, ret); @@ -2045,7 +2045,7 @@ static char *format_alias(char *buf, int len, const s= truct perf_pmu *pmu, } =20 parse_events_terms__init(&terms); - ret =3D parse_events_terms(&terms, alias->terms, /*input=3D*/NULL); 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Mon, 22 Sep 2025 21:19:05 -0700 (PDT) Date: Mon, 22 Sep 2025 21:18:27 -0700 In-Reply-To: <20250923041844.400164-1-irogers@google.com> Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: Mime-Version: 1.0 References: <20250923041844.400164-1-irogers@google.com> X-Mailer: git-send-email 2.51.0.534.gc79095c0ca-goog Message-ID: <20250923041844.400164-9-irogers@google.com> Subject: [PATCH v5 08/25] perf pmu: Use fd rather than FILE from new_alias From: Ian Rogers To: Peter Zijlstra , Ingo Molnar , Arnaldo Carvalho de Melo , Namhyung Kim , Mark Rutland , Alexander Shishkin , Jiri Olsa , Ian Rogers , Adrian Hunter , Kan Liang , James Clark , Xu Yang , Thomas Falcon , Andi Kleen , linux-kernel@vger.kernel.org, linux-perf-users@vger.kernel.org, bpf@vger.kernel.org, Atish Patra , Beeman Strong , Leo Yan , Vince Weaver Cc: Thomas Richter Content-Transfer-Encoding: quoted-printable Content-Type: text/plain; charset="utf-8" The FILE argument was necessary for the scanner but now that functionality is not being used we can switch to just using io__getline which should cut down on stdio buffer usage. Tested-by: Thomas Richter Signed-off-by: Ian Rogers --- tools/perf/util/pmu.c | 23 ++++++++++------------- 1 file changed, 10 insertions(+), 13 deletions(-) diff --git a/tools/perf/util/pmu.c b/tools/perf/util/pmu.c index b44dfe4c73fc..818be59db2c6 100644 --- a/tools/perf/util/pmu.c +++ b/tools/perf/util/pmu.c @@ -563,7 +563,7 @@ static int update_alias(const struct pmu_event *pe, } =20 static int perf_pmu__new_alias(struct perf_pmu *pmu, const char *name, - const char *desc, const char *val, FILE *val_fd, + const char *desc, const char *val, int val_fd, const struct pmu_event *pe, enum event_source src) { struct perf_pmu_alias *alias, *old_alias; @@ -614,12 +614,15 @@ static int perf_pmu__new_alias(struct perf_pmu *pmu, = const char *name, if (ret) return ret; =20 - if (!val_fd) { + if (val_fd < 0) { alias->terms =3D strdup(val); } else { + char buf[256]; + struct io io; size_t line_len; =20 - ret =3D getline(&alias->terms, &line_len, val_fd) < 0 ? -errno : 0; + io__init(&io, val_fd, buf, sizeof(buf)); + ret =3D io__getline(&io, &alias->terms, &line_len) < 0 ? -errno : 0; if (ret) { pr_err("Failed to read alias %s\n", name); return ret; @@ -698,7 +701,6 @@ static int __pmu_aliases_parse(struct perf_pmu *pmu, in= t events_dir_fd) while ((evt_ent =3D io_dir__readdir(&event_dir))) { char *name =3D evt_ent->d_name; int fd; - FILE *file; =20 if (!strcmp(name, ".") || !strcmp(name, "..")) continue; @@ -714,17 +716,12 @@ static int __pmu_aliases_parse(struct perf_pmu *pmu, = int events_dir_fd) pr_debug("Cannot open %s\n", name); continue; } - file =3D fdopen(fd, "r"); - if (!file) { - close(fd); - continue; - } =20 if (perf_pmu__new_alias(pmu, name, /*desc=3D*/ NULL, - /*val=3D*/ NULL, file, /*pe=3D*/ NULL, + /*val=3D*/ NULL, fd, /*pe=3D*/ NULL, EVENT_SRC_SYSFS) < 0) pr_debug("Cannot set up %s\n", name); - fclose(file); + close(fd); } =20 pmu->sysfs_aliases_loaded =3D true; @@ -1041,7 +1038,7 @@ static int pmu_add_cpu_aliases_map_callback(const str= uct pmu_event *pe, { struct perf_pmu *pmu =3D vdata; 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charset="utf-8" Factor existing functionality in perf_pmu__name_from_config into a helper that will be used in later patches. Tested-by: Thomas Richter Signed-off-by: Ian Rogers --- tools/perf/util/pmu.c | 33 +++++++++++++++++++-------------- 1 file changed, 19 insertions(+), 14 deletions(-) diff --git a/tools/perf/util/pmu.c b/tools/perf/util/pmu.c index 818be59db2c6..36b880bf6bbf 100644 --- a/tools/perf/util/pmu.c +++ b/tools/perf/util/pmu.c @@ -1763,6 +1763,24 @@ static int check_info_data(struct perf_pmu *pmu, return 0; } =20 +static int perf_pmu__parse_terms_to_attr(struct perf_pmu *pmu, const char = *terms_str, + struct perf_event_attr *attr) +{ + struct parse_events_terms terms; + int ret; + + parse_events_terms__init(&terms); + ret =3D parse_events_terms(&terms, terms_str); + if (ret) { + pr_debug("Failed to parse terms '%s': %d\n", terms_str, ret); + parse_events_terms__exit(&terms); + return ret; + } + ret =3D perf_pmu__config(pmu, attr, &terms, /*apply_hardcoded=3D*/true, /= *err=3D*/NULL); + parse_events_terms__exit(&terms); + return ret; +} + /* * Find alias in the terms list and replace it with the terms * defined for the alias @@ -2595,21 +2613,8 @@ const char *perf_pmu__name_from_config(struct perf_p= mu *pmu, u64 config) hashmap__for_each_entry(pmu->aliases, entry, bkt) { struct perf_pmu_alias *event =3D entry->pvalue; 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Mon, 22 Sep 2025 21:19:09 -0700 (PDT) Date: Mon, 22 Sep 2025 21:18:29 -0700 In-Reply-To: <20250923041844.400164-1-irogers@google.com> Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: Mime-Version: 1.0 References: <20250923041844.400164-1-irogers@google.com> X-Mailer: git-send-email 2.51.0.534.gc79095c0ca-goog Message-ID: <20250923041844.400164-11-irogers@google.com> Subject: [PATCH v5 10/25] perf parse-events: Add terms for legacy hardware and cache config values From: Ian Rogers To: Peter Zijlstra , Ingo Molnar , Arnaldo Carvalho de Melo , Namhyung Kim , Mark Rutland , Alexander Shishkin , Jiri Olsa , Ian Rogers , Adrian Hunter , Kan Liang , James Clark , Xu Yang , Thomas Falcon , Andi Kleen , linux-kernel@vger.kernel.org, linux-perf-users@vger.kernel.org, bpf@vger.kernel.org, Atish Patra , Beeman Strong , Leo Yan , Vince Weaver Cc: Thomas Richter X-ccpol: medium Content-Transfer-Encoding: quoted-printable Content-Type: text/plain; charset="utf-8" Add the PMU terms legacy-hardware-config and legacy-cache-config. These terms are similar to the config term in that their values are assigned to the perf_event_attr config value. They differ in that the PMU type is switched to be either PERF_TYPE_HARDWARE or PERF_TYPE_HW_CACHE, and the PMU type is moved into the extended type information of the config value. This will allow later patches to add legacy events to json. An example use of the terms is in the following: ``` $ perf stat -vv -e 'cpu/legacy-hardware-config=3D1/,cpu/legacy-cache-config= =3D0x10001/' true Using CPUID GenuineIntel-6-8D-1 Attempt to add: cpu/legacy-hardware-config=3D0x1/ ..after resolving event: cpu/legacy-hardware-config=3D0x1/ Attempt to add: cpu/legacy-cache-config=3D0x10001/ ..after resolving event: cpu/legacy-cache-config=3D0x10001/ Control descriptor is not initialized ------------------------------------------------------------ perf_event_attr: type 0 (PERF_TYPE_HARDWARE) size 136 config 0x1 (PERF_COUNT_HW_INSTRUCTIONS) sample_type IDENTIFIER read_format TOTAL_TIME_ENABLED|TOTAL_TIME_RUNNING disabled 1 inherit 1 enable_on_exec 1 ------------------------------------------------------------ sys_perf_event_open: pid 994937 cpu -1 group_fd -1 flags 0x8 =3D 3 ------------------------------------------------------------ perf_event_attr: type 3 (PERF_TYPE_HW_CACHE) size 136 config 0x10001 (PERF_COUNT_HW_CACHE_RESULT_MISS= | PERF_COUNT_HW_CACHE_OP_READ | PERF_COUNT_HW_CACHE_L1I) sample_type IDENTIFIER read_format TOTAL_TIME_ENABLED|TOTAL_TIME_RUNNING disabled 1 inherit 1 enable_on_exec 1 ------------------------------------------------------------ sys_perf_event_open: pid 994937 cpu -1 group_fd -1 flags 0x8 =3D 4 cpu/legacy-hardware-config=3D1/: -1: 1364046 414756 414756 cpu/legacy-cache-config=3D0x10001/: -1: 57453 414756 414756 cpu/legacy-hardware-config=3D1/: 1364046 414756 414756 cpu/legacy-cache-config=3D0x10001/: 57453 414756 414756 Performance counter stats for 'true': 1,364,046 cpu/legacy-hardware-config=3D1/ 57,453 cpu/legacy-cache-config=3D0x10001/ 0.001988593 seconds time elapsed 0.002194000 seconds user 0.000000000 seconds sys ``` Tested-by: Thomas Richter Signed-off-by: Ian Rogers --- tools/perf/util/parse-events.c | 70 ++++++++++++++++++++++++++++++++++ tools/perf/util/parse-events.h | 4 +- tools/perf/util/parse-events.l | 2 + tools/perf/util/pmu.c | 30 +++++++++++++++ 4 files changed, 105 insertions(+), 1 deletion(-) diff --git a/tools/perf/util/parse-events.c b/tools/perf/util/parse-events.c index c3c934da6083..f9c52eadac46 100644 --- a/tools/perf/util/parse-events.c +++ b/tools/perf/util/parse-events.c @@ -868,6 +868,8 @@ const char *parse_events__term_type_str(enum parse_even= ts__term_type term_type) [PARSE_EVENTS__TERM_TYPE_RAW] =3D "raw", [PARSE_EVENTS__TERM_TYPE_LEGACY_CACHE] =3D "legacy-cache", [PARSE_EVENTS__TERM_TYPE_HARDWARE] =3D "hardware", + [PARSE_EVENTS__TERM_TYPE_LEGACY_HARDWARE_CONFIG] =3D "legacy-hardware-co= nfig", + [PARSE_EVENTS__TERM_TYPE_LEGACY_CACHE_CONFIG] =3D "legacy-cache-config", [PARSE_EVENTS__TERM_TYPE_CPU] =3D "cpu", }; if ((unsigned int)term_type >=3D __PARSE_EVENTS__TERM_TYPE_NR) @@ -919,6 +921,8 @@ config_term_avail(enum parse_events__term_type term_typ= e, struct parse_events_er case PARSE_EVENTS__TERM_TYPE_RAW: case PARSE_EVENTS__TERM_TYPE_LEGACY_CACHE: case PARSE_EVENTS__TERM_TYPE_HARDWARE: + case PARSE_EVENTS__TERM_TYPE_LEGACY_HARDWARE_CONFIG: + case PARSE_EVENTS__TERM_TYPE_LEGACY_CACHE_CONFIG: default: if (!err) return false; @@ -1076,6 +1080,8 @@ do { \ case PARSE_EVENTS__TERM_TYPE_USER: case PARSE_EVENTS__TERM_TYPE_LEGACY_CACHE: case PARSE_EVENTS__TERM_TYPE_HARDWARE: + case PARSE_EVENTS__TERM_TYPE_LEGACY_HARDWARE_CONFIG: + case PARSE_EVENTS__TERM_TYPE_LEGACY_CACHE_CONFIG: default: parse_events_error__handle(parse_state->error, term->err_term, strdup(parse_events__term_type_str(term->type_term)), @@ -1098,10 +1104,68 @@ do { \ #undef CHECK_TYPE_VAL } =20 +static bool check_pmu_is_core(__u32 type, const struct parse_events_term *= term, + struct parse_events_error *err) +{ + struct perf_pmu *pmu =3D NULL; + + /* Avoid loading all PMUs with perf_pmus__find_by_type, just scan the cor= e ones. */ + while ((pmu =3D perf_pmus__scan_core(pmu)) !=3D NULL) { + if (pmu->type =3D=3D type) + return true; + } + parse_events_error__handle(err, term->err_val, + strdup("needs a core PMU"), + NULL); + return false; +} + static int config_term_pmu(struct perf_event_attr *attr, struct parse_events_term *term, struct parse_events_state *parse_state) { + if (term->type_term =3D=3D PARSE_EVENTS__TERM_TYPE_LEGACY_HARDWARE_CONFIG= ) { + if (check_type_val(term, parse_state->error, PARSE_EVENTS__TERM_TYPE_NUM= )) + return -EINVAL; + if (term->val.num >=3D PERF_COUNT_HW_MAX) { + parse_events_error__handle(parse_state->error, term->err_val, + strdup("too big"), + NULL); + return -EINVAL; + } + if (!check_pmu_is_core(attr->type, term, parse_state->error)) + return -EINVAL; + attr->config =3D term->val.num; + if (perf_pmus__supports_extended_type()) + attr->config |=3D (__u64)attr->type << PERF_PMU_TYPE_SHIFT; + attr->type =3D PERF_TYPE_HARDWARE; + return 0; + } + if (term->type_term =3D=3D PARSE_EVENTS__TERM_TYPE_LEGACY_CACHE_CONFIG) { + int cache_type, cache_op, cache_result; + + if (check_type_val(term, parse_state->error, PARSE_EVENTS__TERM_TYPE_NUM= )) + return -EINVAL; + cache_type =3D term->val.num & 0xFF; + cache_op =3D (term->val.num >> 8) & 0xFF; + cache_result =3D (term->val.num >> 16) & 0xFF; + if ((term->val.num & ~0xFFFFFF) || + cache_type >=3D PERF_COUNT_HW_CACHE_MAX || + cache_op >=3D PERF_COUNT_HW_CACHE_OP_MAX || + cache_result >=3D PERF_COUNT_HW_CACHE_RESULT_MAX) { + parse_events_error__handle(parse_state->error, term->err_val, + strdup("too big"), + NULL); + return -EINVAL; + } + if (!check_pmu_is_core(attr->type, term, parse_state->error)) + return -EINVAL; + attr->config =3D term->val.num; + if (perf_pmus__supports_extended_type()) + attr->config |=3D (__u64)attr->type << PERF_PMU_TYPE_SHIFT; + attr->type =3D PERF_TYPE_HW_CACHE; + return 0; + } if (term->type_term =3D=3D PARSE_EVENTS__TERM_TYPE_LEGACY_CACHE) { struct perf_pmu *pmu =3D perf_pmus__find_by_type(attr->type); =20 @@ -1188,6 +1252,8 @@ static int config_term_tracepoint(struct perf_event_a= ttr *attr, case PARSE_EVENTS__TERM_TYPE_CONFIG1: case PARSE_EVENTS__TERM_TYPE_CONFIG2: case PARSE_EVENTS__TERM_TYPE_CONFIG3: + case PARSE_EVENTS__TERM_TYPE_LEGACY_HARDWARE_CONFIG: + case PARSE_EVENTS__TERM_TYPE_LEGACY_CACHE_CONFIG: case PARSE_EVENTS__TERM_TYPE_NAME: case PARSE_EVENTS__TERM_TYPE_SAMPLE_PERIOD: case PARSE_EVENTS__TERM_TYPE_SAMPLE_FREQ: @@ -1327,6 +1393,8 @@ do { \ case PARSE_EVENTS__TERM_TYPE_CONFIG1: case PARSE_EVENTS__TERM_TYPE_CONFIG2: case PARSE_EVENTS__TERM_TYPE_CONFIG3: + case PARSE_EVENTS__TERM_TYPE_LEGACY_HARDWARE_CONFIG: + case PARSE_EVENTS__TERM_TYPE_LEGACY_CACHE_CONFIG: case PARSE_EVENTS__TERM_TYPE_NAME: case PARSE_EVENTS__TERM_TYPE_METRIC_ID: case PARSE_EVENTS__TERM_TYPE_RAW: @@ -1365,6 +1433,8 @@ static int get_config_chgs(struct perf_pmu *pmu, stru= ct parse_events_terms *head case PARSE_EVENTS__TERM_TYPE_CONFIG1: case PARSE_EVENTS__TERM_TYPE_CONFIG2: case PARSE_EVENTS__TERM_TYPE_CONFIG3: + case PARSE_EVENTS__TERM_TYPE_LEGACY_HARDWARE_CONFIG: + case PARSE_EVENTS__TERM_TYPE_LEGACY_CACHE_CONFIG: case PARSE_EVENTS__TERM_TYPE_NAME: case PARSE_EVENTS__TERM_TYPE_SAMPLE_PERIOD: case PARSE_EVENTS__TERM_TYPE_SAMPLE_FREQ: diff --git a/tools/perf/util/parse-events.h b/tools/perf/util/parse-events.h index 048b38e476f3..0db5e223e10d 100644 --- a/tools/perf/util/parse-events.h +++ b/tools/perf/util/parse-events.h @@ -82,7 +82,9 @@ enum parse_events__term_type { PARSE_EVENTS__TERM_TYPE_LEGACY_CACHE, PARSE_EVENTS__TERM_TYPE_HARDWARE, PARSE_EVENTS__TERM_TYPE_CPU, -#define __PARSE_EVENTS__TERM_TYPE_NR (PARSE_EVENTS__TERM_TYPE_CPU + 1) + PARSE_EVENTS__TERM_TYPE_LEGACY_HARDWARE_CONFIG, + PARSE_EVENTS__TERM_TYPE_LEGACY_CACHE_CONFIG, +#define __PARSE_EVENTS__TERM_TYPE_NR (PARSE_EVENTS__TERM_TYPE_LEGACY_CACHE= _CONFIG + 1) }; =20 struct parse_events_term { diff --git a/tools/perf/util/parse-events.l b/tools/perf/util/parse-events.l index 294e943bcdb4..29a8d43a47a9 100644 --- a/tools/perf/util/parse-events.l +++ b/tools/perf/util/parse-events.l @@ -337,6 +337,8 @@ aux-action { return term(yyscanner, PARSE_EVENTS__TERM= _TYPE_AUX_ACTION); } aux-sample-size { return term(yyscanner, PARSE_EVENTS__TERM_TYPE_AUX_SAMP= LE_SIZE); } metric-id { return term(yyscanner, PARSE_EVENTS__TERM_TYPE_METRIC_ID); } cpu { return term(yyscanner, PARSE_EVENTS__TERM_TYPE_CPU); } +legacy-hardware-config { return term(yyscanner, PARSE_EVENTS__TERM_TYPE_L= EGACY_HARDWARE_CONFIG); } +legacy-cache-config { return term(yyscanner, PARSE_EVENTS__TERM_TYPE_LEGAC= Y_CACHE_CONFIG); } cpu-cycles|cycles { return hw_term(yyscanner, PERF_COUNT_HW_CPU_CYCLES)= ; } stalled-cycles-frontend|idle-cycles-frontend { return hw_term(yyscanner, P= ERF_COUNT_HW_STALLED_CYCLES_FRONTEND); } stalled-cycles-backend|idle-cycles-backend { return hw_term(yyscanner, PER= F_COUNT_HW_STALLED_CYCLES_BACKEND); } diff --git a/tools/perf/util/pmu.c b/tools/perf/util/pmu.c index 36b880bf6bbf..f718eb41af88 100644 --- a/tools/perf/util/pmu.c +++ b/tools/perf/util/pmu.c @@ -1532,6 +1532,34 @@ static int pmu_config_term(const struct perf_pmu *pm= u, assert(term->type_val =3D=3D PARSE_EVENTS__TERM_TYPE_NUM); pmu_format_value(bits, term->val.num, &attr->config3, zero); break; + case PARSE_EVENTS__TERM_TYPE_LEGACY_HARDWARE_CONFIG: + assert(term->type_val =3D=3D PARSE_EVENTS__TERM_TYPE_NUM); + assert(term->val.num < PERF_COUNT_HW_MAX); + assert(pmu->is_core); + attr->config =3D term->val.num; + if (perf_pmus__supports_extended_type()) + attr->config |=3D (__u64)pmu->type << PERF_PMU_TYPE_SHIFT; + attr->type =3D PERF_TYPE_HARDWARE; + break; + case PARSE_EVENTS__TERM_TYPE_LEGACY_CACHE_CONFIG: { +#ifndef NDEBUG + int cache_type =3D term->val.num & 0xFF; + int cache_op =3D (term->val.num >> 8) & 0xFF; + int cache_result =3D (term->val.num >> 16) & 0xFF; + + assert(cache_type < PERF_COUNT_HW_CACHE_MAX); + assert(cache_op < PERF_COUNT_HW_CACHE_OP_MAX); + assert(cache_result < PERF_COUNT_HW_CACHE_RESULT_MAX); +#endif + assert(term->type_val =3D=3D PARSE_EVENTS__TERM_TYPE_NUM); + assert((term->val.num & ~0xFFFFFF) =3D=3D 0); + assert(pmu->is_core); + attr->config =3D term->val.num; + if (perf_pmus__supports_extended_type()) + attr->config |=3D (__u64)pmu->type << PERF_PMU_TYPE_SHIFT; + attr->type =3D PERF_TYPE_HW_CACHE; + break; + } case PARSE_EVENTS__TERM_TYPE_USER: /* Not hardcoded. */ return -EINVAL; case PARSE_EVENTS__TERM_TYPE_NAME ... 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charset="utf-8" Add json LegacyConfigCode and LegacyCacheCode values that translate to legacy-hardware-config and legacy-cache-config event terms respectively. Add perf_pmu__default_core_events_table as a means to find a default_core event table that will later contain legacy events. In situations like hypervisors it is more likely that tables will be NULL. Rather than testing in the calling PMU code, early exit in the pmu-event.c routines. Tested-by: Thomas Richter Signed-off-by: Ian Rogers --- tools/perf/pmu-events/empty-pmu-events.c | 26 +++++++++++++++++++ tools/perf/pmu-events/jevents.py | 32 ++++++++++++++++++++++++ tools/perf/pmu-events/pmu-events.h | 1 + 3 files changed, 59 insertions(+) diff --git a/tools/perf/pmu-events/empty-pmu-events.c b/tools/perf/pmu-even= ts/empty-pmu-events.c index 041c598b16d8..2393b3a7a4c9 100644 --- a/tools/perf/pmu-events/empty-pmu-events.c +++ b/tools/perf/pmu-events/empty-pmu-events.c @@ -461,6 +461,8 @@ int pmu_events_table__for_each_event(const struct pmu_e= vents_table *table, pmu_event_iter_fn fn, void *data) { + if (!table) + return 0; for (size_t i =3D 0; i < table->num_pmus; i++) { const struct pmu_table_entry *table_pmu =3D &table->pmus[i= ]; const char *pmu_name =3D &big_c_string[table_pmu->pmu_name= .offset]; @@ -482,6 +484,8 @@ int pmu_events_table__find_event(const struct pmu_event= s_table *table, pmu_event_iter_fn fn, void *data) { + if (!table) + return PMU_EVENTS__NOT_FOUND; for (size_t i =3D 0; i < table->num_pmus; i++) { const struct pmu_table_entry *table_pmu =3D &table->pmus[i= ]; const char *pmu_name =3D &big_c_string[table_pmu->pmu_name= .offset]; @@ -502,6 +506,8 @@ size_t pmu_events_table__num_events(const struct pmu_ev= ents_table *table, { size_t count =3D 0; =20 + if (!table) + return 0; for (size_t i =3D 0; i < table->num_pmus; i++) { const struct pmu_table_entry *table_pmu =3D &table->pmus[i= ]; const char *pmu_name =3D &big_c_string[table_pmu->pmu_name= .offset]; @@ -580,6 +586,8 @@ int pmu_metrics_table__for_each_metric(const struct pmu= _metrics_table *table, pmu_metric_iter_fn fn, void *data) { + if (!table) + return 0; for (size_t i =3D 0; i < table->num_pmus; i++) { int ret =3D pmu_metrics_table__for_each_metric_pmu(table, = &table->pmus[i], fn, data); @@ -596,6 +604,8 @@ int pmu_metrics_table__find_metric(const struct pmu_met= rics_table *table, pmu_metric_iter_fn fn, void *data) { + if (!table) + return 0; for (size_t i =3D 0; i < table->num_pmus; i++) { const struct pmu_table_entry *table_pmu =3D &table->pmus[i= ]; const char *pmu_name =3D &big_c_string[table_pmu->pmu_name= .offset]; @@ -707,6 +717,22 @@ const struct pmu_events_table *perf_pmu__find_events_t= able(struct perf_pmu *pmu) return NULL; } =20 +const struct pmu_events_table *perf_pmu__default_core_events_table(void) +{ + int i =3D 0; + + for (;;) { + const struct pmu_events_map *map =3D &pmu_events_map[i++]; + + if (!map->arch) + break; + + if (!strcmp(map->cpuid, "common")) + return &map->event_table; + } + return NULL; +} + const struct pmu_metrics_table *pmu_metrics_table__find(void) { struct perf_cpu cpu =3D {-1}; diff --git a/tools/perf/pmu-events/jevents.py b/tools/perf/pmu-events/jeven= ts.py index 168c044dd7cc..1f3917cbff87 100755 --- a/tools/perf/pmu-events/jevents.py +++ b/tools/perf/pmu-events/jevents.py @@ -325,6 +325,8 @@ class JsonEvent: eventcode |=3D int(jd['ExtSel']) << 8 configcode =3D int(jd['ConfigCode'], 0) if 'ConfigCode' in jd else None eventidcode =3D int(jd['EventidCode'], 0) if 'EventidCode' in jd else = None + legacy_hw_config =3D int(jd['LegacyConfigCode'], 0) if 'LegacyConfigCo= de' in jd else None + legacy_cache_config =3D int(jd['LegacyCacheCode'], 0) if 'LegacyCacheC= ode' in jd else None self.name =3D jd['EventName'].lower() if 'EventName' in jd else None self.topic =3D '' self.compat =3D jd.get('Compat') @@ -370,6 +372,10 @@ class JsonEvent: event =3D f'config=3D{llx(configcode)}' elif eventidcode is not None: event =3D f'eventid=3D{llx(eventidcode)}' + elif legacy_hw_config is not None: + event =3D f'legacy-hardware-config=3D{llx(legacy_hw_config)}' + elif legacy_cache_config is not None: + event =3D f'legacy-cache-config=3D{llx(legacy_cache_config)}' else: event =3D f'event=3D{llx(eventcode)}' event_fields =3D [ @@ -951,6 +957,8 @@ int pmu_events_table__for_each_event(const struct pmu_e= vents_table *table, pmu_event_iter_fn fn, void *data) { + if (!table) + return 0; for (size_t i =3D 0; i < table->num_pmus; i++) { const struct pmu_table_entry *table_pmu =3D &table->pmus[i= ]; const char *pmu_name =3D &big_c_string[table_pmu->pmu_name= .offset]; @@ -972,6 +980,8 @@ int pmu_events_table__find_event(const struct pmu_event= s_table *table, pmu_event_iter_fn fn, void *data) { + if (!table) + return PMU_EVENTS__NOT_FOUND; for (size_t i =3D 0; i < table->num_pmus; i++) { const struct pmu_table_entry *table_pmu =3D &table->pmus[i= ]; const char *pmu_name =3D &big_c_string[table_pmu->pmu_name= .offset]; @@ -992,6 +1002,8 @@ size_t pmu_events_table__num_events(const struct pmu_e= vents_table *table, { size_t count =3D 0; =20 + if (!table) + return 0; for (size_t i =3D 0; i < table->num_pmus; i++) { const struct pmu_table_entry *table_pmu =3D &table->pmus[i= ]; const char *pmu_name =3D &big_c_string[table_pmu->pmu_name= .offset]; @@ -1070,6 +1082,8 @@ int pmu_metrics_table__for_each_metric(const struct p= mu_metrics_table *table, pmu_metric_iter_fn fn, void *data) { + if (!table) + return 0; for (size_t i =3D 0; i < table->num_pmus; i++) { int ret =3D pmu_metrics_table__for_each_metric_pmu(table, = &table->pmus[i], fn, data); @@ -1086,6 +1100,8 @@ int pmu_metrics_table__find_metric(const struct pmu_m= etrics_table *table, pmu_metric_iter_fn fn, void *data) { + if (!table) + return 0; for (size_t i =3D 0; i < table->num_pmus; i++) { const struct pmu_table_entry *table_pmu =3D &table->pmus[i= ]; const char *pmu_name =3D &big_c_string[table_pmu->pmu_name= .offset]; @@ -1197,6 +1213,22 @@ const struct pmu_events_table *perf_pmu__find_events= _table(struct perf_pmu *pmu) return NULL; } =20 +const struct pmu_events_table *perf_pmu__default_core_events_table(void) +{ + int i =3D 0; + + for (;;) { + const struct pmu_events_map *map =3D &pmu_events_map[i++]; + + if (!map->arch) + break; + + if (!strcmp(map->cpuid, "common")) + return &map->event_table; + } + return NULL; +} + const struct pmu_metrics_table *pmu_metrics_table__find(void) { struct perf_cpu cpu =3D {-1}; diff --git a/tools/perf/pmu-events/pmu-events.h b/tools/perf/pmu-events/pmu= -events.h index ea022ea55087..e0535380c0b2 100644 --- a/tools/perf/pmu-events/pmu-events.h +++ b/tools/perf/pmu-events/pmu-events.h @@ -125,6 +125,7 @@ int pmu_metrics_table__find_metric(const struct pmu_met= rics_table *table, void *data); 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charset="utf-8" Add support to finding/adding events from the default_core event table. If an event already exists from sysfs/json then the default_core configuration is saved in the legacy_terms string. Lazily use the legacy_terms string to set a legacy hardware or cache event as deprecated if the core PMU doesn't support it. Use the legacy terms string to set the alternate_hw_config, avoiding the value needing to be passed from the parse_events parser. Tested-by: Thomas Richter Signed-off-by: Ian Rogers --- tools/perf/util/pmu.c | 137 ++++++++++++++++++++++++++++++++++++------ 1 file changed, 117 insertions(+), 20 deletions(-) diff --git a/tools/perf/util/pmu.c b/tools/perf/util/pmu.c index f718eb41af88..7f5bdb6688db 100644 --- a/tools/perf/util/pmu.c +++ b/tools/perf/util/pmu.c @@ -69,6 +69,11 @@ struct perf_pmu_alias { char *topic; /** @terms: Owned copy of the event terms. */ char *terms; + /** + * @legacy_terms: If the event aliases a legacy event, holds a copy + * ofthe legacy event string. + */ + char *legacy_terms; /** * @pmu_name: The name copied from the json struct pmu_event. This can * differ from the PMU name as it won't have suffixes. @@ -101,6 +106,12 @@ struct perf_pmu_alias { * default. */ bool deprecated; + /** + * @legacy_deprecated_checked: Legacy events may not be supported by the + * PMU need to be checked. If they aren't supported they are marked + * deprecated. + */ + bool legacy_deprecated_checked; /** @from_sysfs: Was the alias from sysfs or a json event? */ bool from_sysfs; /** @info_loaded: Have the scale, unit and other values been read from di= sk? */ @@ -430,6 +441,7 @@ static void perf_pmu_free_alias(struct perf_pmu_alias *= alias) zfree(&alias->topic); zfree(&alias->pmu_name); zfree(&alias->terms); + zfree(&alias->legacy_terms); free(alias); } =20 @@ -522,6 +534,7 @@ static void read_alias_info(struct perf_pmu *pmu, struc= t perf_pmu_alias *alias) struct update_alias_data { struct perf_pmu *pmu; struct perf_pmu_alias *alias; + bool legacy; }; =20 static int update_alias(const struct pmu_event *pe, @@ -537,8 +550,13 @@ static int update_alias(const struct pmu_event *pe, assign_str(pe->name, "topic", &data->alias->topic, pe->topic); data->alias->per_pkg =3D pe->perpkg; if (pe->event) { - zfree(&data->alias->terms); - data->alias->terms =3D strdup(pe->event); + if (data->legacy) { + zfree(&data->alias->legacy_terms); + data->alias->legacy_terms =3D strdup(pe->event); + } else { + zfree(&data->alias->terms); + data->alias->terms =3D strdup(pe->event); + } } if (!ret && pe->unit) { char *unit; @@ -628,7 +646,6 @@ static int perf_pmu__new_alias(struct perf_pmu *pmu, co= nst char *name, return ret; } } - alias->name =3D strdup(name); alias->desc =3D desc ? strdup(desc) : NULL; alias->long_desc =3D long_desc ? strdup(long_desc) : NULL; @@ -645,15 +662,29 @@ static int perf_pmu__new_alias(struct perf_pmu *pmu, = const char *name, default: case EVENT_SRC_SYSFS: alias->from_sysfs =3D true; - if (pmu->events_table) { + if (pmu->events_table || pmu->is_core) { /* Update an event from sysfs with json data. */ struct update_alias_data data =3D { .pmu =3D pmu, .alias =3D alias, + .legacy =3D false, }; - if (pmu_events_table__find_event(pmu->events_table, pmu, name, - update_alias, &data) =3D=3D 0) + if ((pmu_events_table__find_event(pmu->events_table, pmu, name, + update_alias, &data) =3D=3D 0)) { + /* + * Override sysfs encodings with json encodings + * specific to the cpuid. + */ pmu->cpu_common_json_aliases++; + } + if (pmu->is_core) { + /* Add in legacy encodings. */ + data.legacy =3D true; + if (pmu_events_table__find_event( + perf_pmu__default_core_events_table(), + pmu, name, update_alias, &data) =3D=3D 0) + pmu->cpu_common_json_aliases++; + } } pmu->sysfs_aliases++; break; @@ -1054,13 +1085,16 @@ void pmu_add_cpu_aliases_table(struct perf_pmu *pmu= , const struct pmu_events_tab =20 static void pmu_add_cpu_aliases(struct perf_pmu *pmu) { - if (!pmu->events_table) + if (!pmu->events_table && !pmu->is_core) return; =20 if (pmu->cpu_aliases_added) return; =20 pmu_add_cpu_aliases_table(pmu, pmu->events_table); + if (pmu->is_core) + pmu_add_cpu_aliases_table(pmu, perf_pmu__default_core_events_table()); + pmu->cpu_aliases_added =3D true; } =20 @@ -1738,10 +1772,14 @@ static struct perf_pmu_alias *pmu_find_alias(struct= perf_pmu *pmu, return alias; =20 /* Alias doesn't exist, try to get it from the json events. */ - if (pmu->events_table && - pmu_events_table__find_event(pmu->events_table, pmu, name, - pmu_add_cpu_aliases_map_callback, - pmu) =3D=3D 0) { + if ((pmu_events_table__find_event(pmu->events_table, pmu, name, + pmu_add_cpu_aliases_map_callback, + pmu) =3D=3D 0) || + (pmu->is_core && + pmu_events_table__find_event(perf_pmu__default_core_events_table(), + pmu, name, + pmu_add_cpu_aliases_map_callback, + pmu) =3D=3D 0)) { alias =3D perf_pmu__find_alias(pmu, name, /*load=3D*/ false); } return alias; @@ -1865,6 +1903,20 @@ int perf_pmu__check_alias(struct perf_pmu *pmu, stru= ct parse_events_terms *head_ if (ret) return ret; =20 + if (alias->legacy_terms) { + struct perf_event_attr attr =3D {.config =3D 0,}; + + ret =3D perf_pmu__parse_terms_to_attr(pmu, alias->legacy_terms, &attr); + if (ret) { + parse_events_error__handle(err, term->err_term, + strdup("Error evaluating legacy terms"), + NULL); + return ret; + } + if (attr.type =3D=3D PERF_TYPE_HARDWARE) + *alternate_hw_config =3D attr.config & PERF_HW_EVENT_MASK; + } + if (alias->per_pkg) info->per_pkg =3D true; =20 @@ -2033,9 +2085,13 @@ bool perf_pmu__have_event(struct perf_pmu *pmu, cons= t char *name) return drm_pmu__have_event(pmu, name); if (perf_pmu__find_alias(pmu, name, /*load=3D*/ true) !=3D NULL) return true; - if (pmu->cpu_aliases_added || !pmu->events_table) + if (pmu->cpu_aliases_added || (!pmu->events_table && !pmu->is_core)) return false; - return pmu_events_table__find_event(pmu->events_table, pmu, name, NULL, N= ULL) =3D=3D 0; + if (pmu_events_table__find_event(pmu->events_table, pmu, name, NULL, NULL= ) =3D=3D 0) + return true; + return pmu->is_core && + pmu_events_table__find_event(perf_pmu__default_core_events_table(), + pmu, name, NULL, NULL) =3D=3D 0; } =20 size_t perf_pmu__num_events(struct perf_pmu *pmu) @@ -2052,13 +2108,18 @@ size_t perf_pmu__num_events(struct perf_pmu *pmu) pmu_aliases_parse(pmu); nr =3D pmu->sysfs_aliases + pmu->sys_json_aliases; =20 - if (pmu->cpu_aliases_added) - nr +=3D pmu->cpu_json_aliases; - else if (pmu->events_table) - nr +=3D pmu_events_table__num_events(pmu->events_table, pmu) - - pmu->cpu_common_json_aliases; - else + if (pmu->cpu_aliases_added) { + nr +=3D pmu->cpu_json_aliases; + } else if (pmu->events_table || pmu->is_core) { + nr +=3D pmu_events_table__num_events(pmu->events_table, pmu); + if (pmu->is_core) { + nr +=3D pmu_events_table__num_events( + perf_pmu__default_core_events_table(), pmu); + } + nr -=3D pmu->cpu_common_json_aliases; + } else { assert(pmu->cpu_json_aliases =3D=3D 0 && pmu->cpu_common_json_aliases = =3D=3D 0); + } =20 if (perf_pmu__is_tool(pmu)) nr -=3D tool_pmu__num_skip_events(); @@ -2120,6 +2181,42 @@ static char *format_alias(char *buf, int len, const = struct perf_pmu *pmu, return buf; } =20 +static bool perf_pmu_alias__check_deprecated(struct perf_pmu *pmu, struct = perf_pmu_alias *alias) +{ + struct perf_event_attr attr =3D {.config =3D 0,}; + const char *check_terms; + bool has_legacy_config; + + if (alias->legacy_deprecated_checked) + return alias->deprecated; + + alias->legacy_deprecated_checked =3D true; + if (alias->deprecated) + return true; + + check_terms =3D alias->terms; + has_legacy_config =3D + strstr(check_terms, "legacy-hardware-config=3D") !=3D NULL || + strstr(check_terms, "legacy-cache-config=3D") !=3D NULL; + if (!has_legacy_config && alias->legacy_terms) { + check_terms =3D alias->legacy_terms; + has_legacy_config =3D + strstr(check_terms, "legacy-hardware-config=3D") !=3D NULL || + strstr(check_terms, "legacy-cache-config=3D") !=3D NULL; + } + if (!has_legacy_config) + return false; + + if (perf_pmu__parse_terms_to_attr(pmu, check_terms, &attr) !=3D 0) { + /* Parsing failed, set as deprecated. */ + alias->deprecated =3D true; + } else if (attr.type < PERF_TYPE_MAX) { + /* Flag unsupported legacy events as deprecated. */ + alias->deprecated =3D !is_event_supported(attr.type, attr.config); + } + return alias->deprecated; +} + int perf_pmu__for_each_event(struct perf_pmu *pmu, bool skip_duplicate_pmu= s, void *state, pmu_event_callback cb) { @@ -2177,7 +2274,7 @@ int perf_pmu__for_each_event(struct perf_pmu *pmu, bo= ol skip_duplicate_pmus, "%.*s/%s/", (int)pmu_name_len, info.pmu_name, event->terms) + 1; info.str =3D event->terms; info.topic =3D event->topic; - info.deprecated =3D event->deprecated; + info.deprecated =3D perf_pmu_alias__check_deprecated(pmu, event); ret =3D cb(state, &info); if (ret) goto out; --=20 2.51.0.534.gc79095c0ca-goog From nobody Thu Oct 2 03:27:35 2025 Received: from mail-pj1-f74.google.com (mail-pj1-f74.google.com [209.85.216.74]) (using TLSv1.2 with cipher ECDHE-RSA-AES128-GCM-SHA256 (128/128 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id 92F0A28B7D7 for ; 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Mon, 22 Sep 2025 21:19:16 -0700 (PDT) Date: Mon, 22 Sep 2025 21:18:32 -0700 In-Reply-To: <20250923041844.400164-1-irogers@google.com> Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: Mime-Version: 1.0 References: <20250923041844.400164-1-irogers@google.com> X-Mailer: git-send-email 2.51.0.534.gc79095c0ca-goog Message-ID: <20250923041844.400164-14-irogers@google.com> Subject: [PATCH v5 13/25] perf jevents: Add legacy-hardware and legacy-cache json From: Ian Rogers To: Peter Zijlstra , Ingo Molnar , Arnaldo Carvalho de Melo , Namhyung Kim , Mark Rutland , Alexander Shishkin , Jiri Olsa , Ian Rogers , Adrian Hunter , Kan Liang , James Clark , Xu Yang , Thomas Falcon , Andi Kleen , linux-kernel@vger.kernel.org, linux-perf-users@vger.kernel.org, bpf@vger.kernel.org, Atish Patra , Beeman Strong , Leo Yan , Vince Weaver Cc: Thomas Richter Content-Transfer-Encoding: quoted-printable Content-Type: text/plain; charset="utf-8" The legacy-hardware.json is added containing hardware events similarly to the software.json file. A difference is that for the software PMU the name is known and matches sysfs. In the legacy-hardware.json no Unit/PMU is specified for the events meaning default_core is used and the events will appear for all core PMUs. There are potentially 1216 legacy cache events, rather than list them in a json file add a make_legacy_cache.py helper to generate them. By using json for legacy hardware and cache events: descriptions of the events can be added; events can be marked as deprecated, such as those misleadingly named l2 (deprecated is also used to mark all events that weren't previously displayed in perf list); and the name lookup becomes case insensitive. The C string encoding all the perf events and metrics is increased in size by 123,499 bytes which will increase the perf binary size. Later changes will remove hard coded event parsing for legacy hardware and cache events, turning parsing overhead into a binary search during event lookup. That event descriptions are based off of those in perf_event_open man page, credit to Vince Weaver . Tested-by: Thomas Richter Signed-off-by: Ian Rogers --- tools/perf/pmu-events/Build | 8 +- .../arch/common/common/legacy-hardware.json | 72 + tools/perf/pmu-events/empty-pmu-events.c | 2745 ++++++++++++++++- tools/perf/pmu-events/make_legacy_cache.py | 129 + 4 files changed, 2814 insertions(+), 140 deletions(-) create mode 100644 tools/perf/pmu-events/arch/common/common/legacy-hardwar= e.json create mode 100755 tools/perf/pmu-events/make_legacy_cache.py diff --git a/tools/perf/pmu-events/Build b/tools/perf/pmu-events/Build index 1503a16e662a..4ebf37c14978 100644 --- a/tools/perf/pmu-events/Build +++ b/tools/perf/pmu-events/Build @@ -12,6 +12,8 @@ PMU_EVENTS_C =3D $(OUTPUT)pmu-events/pmu-events.c METRIC_TEST_LOG =3D $(OUTPUT)pmu-events/metric_test.log TEST_EMPTY_PMU_EVENTS_C =3D $(OUTPUT)pmu-events/test-empty-pmu-events.c EMPTY_PMU_EVENTS_TEST_LOG =3D $(OUTPUT)pmu-events/empty-pmu-events.log +LEGACY_CACHE_PY =3D pmu-events/make_legacy_cache.py +LEGACY_CACHE_JSON =3D $(OUTPUT)pmu-events/arch/common/common/legacy-cache.= json =20 ifeq ($(JEVENTS_ARCH),) JEVENTS_ARCH=3D$(SRCARCH) @@ -33,7 +35,11 @@ $(OUTPUT)pmu-events/arch/%: pmu-events/arch/% $(call rule_mkdir) $(Q)$(call echo-cmd,gen)cp $< $@ =20 -GEN_JSON =3D $(patsubst %,$(OUTPUT)%,$(JSON)) +$(LEGACY_CACHE_JSON): $(LEGACY_CACHE_PY) + $(call rule_mkdir) + $(Q)$(call echo-cmd,gen)$(PYTHON) $(LEGACY_CACHE_PY) > $@ + +GEN_JSON =3D $(patsubst %,$(OUTPUT)%,$(JSON)) $(LEGACY_CACHE_JSON) =20 $(METRIC_TEST_LOG): $(METRIC_TEST_PY) $(METRIC_PY) $(call rule_mkdir) diff --git a/tools/perf/pmu-events/arch/common/common/legacy-hardware.json = b/tools/perf/pmu-events/arch/common/common/legacy-hardware.json new file mode 100644 index 000000000000..71700647f19b --- /dev/null +++ b/tools/perf/pmu-events/arch/common/common/legacy-hardware.json @@ -0,0 +1,72 @@ +[ + { + "EventName": "cpu-cycles", + "BriefDescription": "Total cycles. Be wary of what happens during CPU = frequency scaling [This event is an alias of cycles].", + "LegacyConfigCode": "0" + }, + { + "EventName": "cycles", + "BriefDescription": "Total cycles. Be wary of what happens during CPU = frequency scaling [This event is an alias of cpu-cycles].", + "LegacyConfigCode": "0" + }, + { + "EventName": "instructions", + "BriefDescription": "Retired instructions. Be careful, these can be af= fected by various issues, most notably hardware interrupt counts.", + "LegacyConfigCode": "1" + }, + { + "EventName": "cache-references", + "BriefDescription": "Cache accesses. Usually this indicates Last Level= Cache accesses but this may vary depending on your CPU. This may include = prefetches and coherency messages; again this depends on the design of your= CPU.", + "LegacyConfigCode": "2" + }, + { + "EventName": "cache-misses", + "BriefDescription": "Cache misses. Usually this indicates Last Level C= ache misses; this is intended to be used in conjunction with the PERF_COUNT= _HW_CACHE_REFERENCES event to calculate cache miss rates.", + "LegacyConfigCode": "3" + }, + { + "EventName": "branches", + "BriefDescription": "Retired branch instructions [This event is an ali= as of branch-instructions].", + "LegacyConfigCode": "4" + }, + { + "EventName": "branch-instructions", + "BriefDescription": "Retired branch instructions [This event is an ali= as of branches].", + "LegacyConfigCode": "4" + }, + { + "EventName": "branch-misses", + "BriefDescription": "Mispredicted branch instructions.", + "LegacyConfigCode": "5" + }, + { + "EventName": "bus-cycles", + "BriefDescription": "Bus cycles, which can be different from total cyc= les.", + "LegacyConfigCode": "6" + }, + { + "EventName": "stalled-cycles-frontend", + "BriefDescription": "Stalled cycles during issue [This event is an ali= as of idle-cycles-frontend].", + "LegacyConfigCode": "7" + }, + { + "EventName": "idle-cycles-frontend", + "BriefDescription": "Stalled cycles during issue [This event is an ali= as of stalled-cycles-fronted].", + "LegacyConfigCode": "7" + }, + { + "EventName": "stalled-cycles-backend", + "BriefDescription": "Stalled cycles during retirement [This event is a= n alias of idle-cycles-backend].", + "LegacyConfigCode": "8" + }, + { + "EventName": "idle-cycles-backend", + "BriefDescription": "Stalled cycles during retirement [This event is a= n alias of stalled-cycles-backend].", + "LegacyConfigCode": "8" + }, + { + "EventName": "ref-cycles", + "BriefDescription": "Total cycles; not affected by CPU frequency scali= ng.", + "LegacyConfigCode": "9" + } +] diff --git a/tools/perf/pmu-events/empty-pmu-events.c b/tools/perf/pmu-even= ts/empty-pmu-events.c index 2393b3a7a4c9..336e3924ce84 100644 --- a/tools/perf/pmu-events/empty-pmu-events.c +++ b/tools/perf/pmu-events/empty-pmu-events.c @@ -19,147 +19,2614 @@ struct pmu_table_entry { }; =20 static const char *const big_c_string =3D -/* offset=3D0 */ "software\000" -/* offset=3D9 */ "cpu-clock\000software\000Per-CPU high-resolution timer b= ased event\000config=3D0\000\00000\000\000\000\000\000" -/* offset=3D87 */ "task-clock\000software\000Per-task high-resolution time= r based event\000config=3D1\000\00000\000\000\000\000\000" -/* offset=3D167 */ "faults\000software\000Number of page faults [This even= t is an alias of page-faults]\000config=3D2\000\00000\000\000\000\000\000" -/* offset=3D262 */ "page-faults\000software\000Number of page faults [This= event is an alias of faults]\000config=3D2\000\00000\000\000\000\000\000" -/* offset=3D357 */ "context-switches\000software\000Number of context swit= ches [This event is an alias of cs]\000config=3D3\000\00000\000\000\000\000= \000" -/* offset=3D458 */ "cs\000software\000Number of context switches [This eve= nt is an alias of context-switches]\000config=3D3\000\00000\000\000\000\000= \000" -/* offset=3D559 */ "cpu-migrations\000software\000Number of times a proces= s has migrated to a new CPU [This event is an alias of migrations]\000confi= g=3D4\000\00000\000\000\000\000\000" -/* offset=3D691 */ "migrations\000software\000Number of times a process ha= s migrated to a new CPU [This event is an alias of cpu-migrations]\000confi= g=3D4\000\00000\000\000\000\000\000" -/* offset=3D823 */ "minor-faults\000software\000Number of minor page fault= s. Minor faults don't require I/O to handle\000config=3D5\000\00000\000\000= \000\000\000" -/* offset=3D932 */ "major-faults\000software\000Number of major page fault= s. Major faults require I/O to handle\000config=3D6\000\00000\000\000\000\0= 00\000" -/* offset=3D1035 */ "alignment-faults\000software\000Number of kernel hand= led memory alignment faults\000config=3D7\000\00000\000\000\000\000\000" -/* offset=3D1127 */ "emulation-faults\000software\000Number of kernel hand= led unimplemented instruction faults handled through emulation\000config=3D= 8\000\00000\000\000\000\000\000" -/* offset=3D1254 */ "dummy\000software\000A placeholder event that doesn't= count anything\000config=3D9\000\00000\000\000\000\000\000" -/* offset=3D1334 */ "bpf-output\000software\000An event used by BPF progra= ms to write to the perf ring buffer\000config=3D0xa\000\00000\000\000\000\0= 00\000" -/* offset=3D1436 */ "cgroup-switches\000software\000Number of context swit= ches to a task in a different cgroup\000config=3D0xb\000\00000\000\000\000\= 000\000" -/* offset=3D1539 */ "tool\000" -/* offset=3D1544 */ "duration_time\000tool\000Wall clock interval time in = nanoseconds\000config=3D1\000\00000\000\000\000\000\000" -/* offset=3D1620 */ "user_time\000tool\000User (non-kernel) time in nanose= conds\000config=3D2\000\00000\000\000\000\000\000" -/* offset=3D1690 */ "system_time\000tool\000System/kernel time in nanoseco= nds\000config=3D3\000\00000\000\000\000\000\000" -/* offset=3D1758 */ "has_pmem\000tool\0001 if persistent memory installed = otherwise 0\000config=3D4\000\00000\000\000\000\000\000" -/* offset=3D1834 */ "num_cores\000tool\000Number of cores. A core consists= of 1 or more thread, with each thread being associated with a logical Linu= x CPU\000config=3D5\000\00000\000\000\000\000\000" -/* offset=3D1979 */ "num_cpus\000tool\000Number of logical Linux CPUs. The= re may be multiple such CPUs on a core\000config=3D6\000\00000\000\000\000\= 000\000" -/* offset=3D2082 */ "num_cpus_online\000tool\000Number of online logical L= inux CPUs. There may be multiple such CPUs on a core\000config=3D7\000\0000= 0\000\000\000\000\000" -/* offset=3D2199 */ "num_dies\000tool\000Number of dies. Each die has 1 or= more cores\000config=3D8\000\00000\000\000\000\000\000" -/* offset=3D2275 */ "num_packages\000tool\000Number of packages. Each pack= age has 1 or more die\000config=3D9\000\00000\000\000\000\000\000" -/* offset=3D2361 */ "slots\000tool\000Number of functional units that in p= arallel can execute parts of an instruction\000config=3D0xa\000\00000\000\0= 00\000\000\000" -/* offset=3D2471 */ "smt_on\000tool\0001 if simultaneous multithreading (a= ka hyperthreading) is enable otherwise 0\000config=3D0xb\000\00000\000\000\= 000\000\000" -/* offset=3D2578 */ "system_tsc_freq\000tool\000The amount a Time Stamp Co= unter (TSC) increases per second\000config=3D0xc\000\00000\000\000\000\000\= 000" -/* offset=3D2677 */ "default_core\000" -/* offset=3D2690 */ "bp_l1_btb_correct\000branch\000L1 BTB Correction\000e= vent=3D0x8a\000\00000\000\000\000\000\000" -/* offset=3D2752 */ "bp_l2_btb_correct\000branch\000L2 BTB Correction\000e= vent=3D0x8b\000\00000\000\000\000\000\000" -/* offset=3D2814 */ "l3_cache_rd\000cache\000L3 cache access, read\000even= t=3D0x40\000\00000\000\000\000\000Attributable Level 3 cache access, read\0= 00" -/* offset=3D2912 */ "segment_reg_loads.any\000other\000Number of segment r= egister loads\000event=3D6,period=3D200000,umask=3D0x80\000\00000\000\000\0= 00\000\000" -/* offset=3D3014 */ "dispatch_blocked.any\000other\000Memory cluster signa= ls to block micro-op dispatch for any reason\000event=3D9,period=3D200000,u= mask=3D0x20\000\00000\000\000\000\000\000" -/* offset=3D3147 */ "eist_trans\000other\000Number of Enhanced Intel Speed= Step(R) Technology (EIST) transitions\000event=3D0x3a,period=3D200000\000\0= 0000\000\000\000\000\000" -/* offset=3D3265 */ "hisi_sccl,ddrc\000" -/* offset=3D3280 */ "uncore_hisi_ddrc.flux_wcmd\000uncore\000DDRC write co= mmands\000event=3D2\000\00000\000\000\000\000\000" -/* offset=3D3350 */ "uncore_cbox\000" -/* offset=3D3362 */ "unc_cbo_xsnp_response.miss_eviction\000uncore\000A cr= oss-core snoop resulted from L3 Eviction which misses in some processor cor= e\000event=3D0x22,umask=3D0x81\000\00000\000\000\000\000\000" -/* offset=3D3516 */ "event-hyphen\000uncore\000UNC_CBO_HYPHEN\000event=3D0= xe0\000\00000\000\000\000\000\000" -/* offset=3D3570 */ "event-two-hyph\000uncore\000UNC_CBO_TWO_HYPH\000event= =3D0xc0\000\00000\000\000\000\000\000" -/* offset=3D3628 */ "hisi_sccl,l3c\000" -/* offset=3D3642 */ "uncore_hisi_l3c.rd_hit_cpipe\000uncore\000Total read = hits\000event=3D7\000\00000\000\000\000\000\000" -/* offset=3D3710 */ "uncore_imc_free_running\000" -/* offset=3D3734 */ "uncore_imc_free_running.cache_miss\000uncore\000Total= cache misses\000event=3D0x12\000\00000\000\000\000\000\000" -/* offset=3D3814 */ "uncore_imc\000" -/* offset=3D3825 */ "uncore_imc.cache_hits\000uncore\000Total cache hits\0= 00event=3D0x34\000\00000\000\000\000\000\000" -/* offset=3D3890 */ "uncore_sys_ddr_pmu\000" -/* offset=3D3909 */ "sys_ddr_pmu.write_cycles\000uncore\000ddr write-cycle= s event\000event=3D0x2b\000v8\00000\000\000\000\000\000" -/* offset=3D3985 */ "uncore_sys_ccn_pmu\000" -/* offset=3D4004 */ "sys_ccn_pmu.read_cycles\000uncore\000ccn read-cycles = event\000config=3D0x2c\0000x01\00000\000\000\000\000\000" -/* offset=3D4081 */ "uncore_sys_cmn_pmu\000" -/* offset=3D4100 */ "sys_cmn_pmu.hnf_cache_miss\000uncore\000Counts total = cache misses in first lookup result (high priority)\000eventid=3D1,type=3D5= \000(434|436|43c|43a).*\00000\000\000\000\000\000" -/* offset=3D4243 */ "CPI\000\0001 / IPC\000\000\000\000\000\000\000\00000" -/* offset=3D4265 */ "IPC\000group1\000inst_retired.any / cpu_clk_unhalted.= thread\000\000\000\000\000\000\000\00000" -/* offset=3D4328 */ "Frontend_Bound_SMT\000\000idq_uops_not_delivered.core= / (4 * (cpu_clk_unhalted.thread / 2 * (1 + cpu_clk_unhalted.one_thread_act= ive / cpu_clk_unhalted.ref_xclk)))\000\000\000\000\000\000\000\00000" -/* offset=3D4494 */ "dcache_miss_cpi\000\000l1d\\-loads\\-misses / inst_re= tired.any\000\000\000\000\000\000\000\00000" -/* offset=3D4558 */ "icache_miss_cycles\000\000l1i\\-loads\\-misses / inst= _retired.any\000\000\000\000\000\000\000\00000" -/* offset=3D4625 */ "cache_miss_cycles\000group1\000dcache_miss_cpi + icac= he_miss_cycles\000\000\000\000\000\000\000\00000" -/* offset=3D4696 */ "DCache_L2_All_Hits\000\000l2_rqsts.demand_data_rd_hit= + l2_rqsts.pf_hit + l2_rqsts.rfo_hit\000\000\000\000\000\000\000\00000" -/* offset=3D4790 */ "DCache_L2_All_Miss\000\000max(l2_rqsts.all_demand_dat= a_rd - l2_rqsts.demand_data_rd_hit, 0) + l2_rqsts.pf_miss + l2_rqsts.rfo_mi= ss\000\000\000\000\000\000\000\00000" -/* offset=3D4924 */ "DCache_L2_All\000\000DCache_L2_All_Hits + DCache_L2_A= ll_Miss\000\000\000\000\000\000\000\00000" -/* offset=3D4988 */ "DCache_L2_Hits\000\000d_ratio(DCache_L2_All_Hits, DCa= che_L2_All)\000\000\000\000\000\000\000\00000" -/* offset=3D5056 */ "DCache_L2_Misses\000\000d_ratio(DCache_L2_All_Miss, D= Cache_L2_All)\000\000\000\000\000\000\000\00000" -/* offset=3D5126 */ "M1\000\000ipc + M2\000\000\000\000\000\000\000\00000" -/* offset=3D5148 */ "M2\000\000ipc + M1\000\000\000\000\000\000\000\00000" -/* offset=3D5170 */ "M3\000\0001 / M3\000\000\000\000\000\000\000\00000" -/* offset=3D5190 */ "L1D_Cache_Fill_BW\000\00064 * l1d.replacement / 1e9 /= duration_time\000\000\000\000\000\000\000\00000" +/* offset=3D0 */ "default_core\000" +/* offset=3D13 */ "l1-dcache\000legacy cache\000Level 1 data cache read ac= cesses\000legacy-cache-config=3D0\000\00010\000\000\000\000\000" +/* offset=3D99 */ "l1-dcache-load\000legacy cache\000Level 1 data cache re= ad accesses\000legacy-cache-config=3D0\000\00010\000\000\000\000\000" +/* offset=3D190 */ "l1-dcache-load-refs\000legacy cache\000Level 1 data ca= che read accesses\000legacy-cache-config=3D0\000\00010\000\000\000\000\000" +/* offset=3D286 */ "l1-dcache-load-reference\000legacy cache\000Level 1 da= ta cache read accesses\000legacy-cache-config=3D0\000\00010\000\000\000\000= \000" +/* offset=3D387 */ "l1-dcache-load-ops\000legacy cache\000Level 1 data cac= he read accesses\000legacy-cache-config=3D0\000\00010\000\000\000\000\000" +/* offset=3D482 */ "l1-dcache-load-access\000legacy cache\000Level 1 data = cache read accesses\000legacy-cache-config=3D0\000\00010\000\000\000\000\00= 0" +/* offset=3D580 */ "l1-dcache-load-misses\000legacy cache\000Level 1 data = cache read misses\000legacy-cache-config=3D0x10000\000\00000\000\000\000\00= 0\000" +/* offset=3D682 */ "l1-dcache-load-miss\000legacy cache\000Level 1 data ca= che read misses\000legacy-cache-config=3D0x10000\000\00010\000\000\000\000\= 000" +/* offset=3D782 */ "l1-dcache-loads\000legacy cache\000Level 1 data cache = read accesses\000legacy-cache-config=3D0\000\00000\000\000\000\000\000" +/* offset=3D874 */ "l1-dcache-loads-refs\000legacy cache\000Level 1 data c= ache read accesses\000legacy-cache-config=3D0\000\00010\000\000\000\000\000" +/* offset=3D971 */ "l1-dcache-loads-reference\000legacy cache\000Level 1 d= ata cache read accesses\000legacy-cache-config=3D0\000\00010\000\000\000\00= 0\000" +/* offset=3D1073 */ "l1-dcache-loads-ops\000legacy cache\000Level 1 data c= ache read accesses\000legacy-cache-config=3D0\000\00010\000\000\000\000\000" +/* offset=3D1169 */ "l1-dcache-loads-access\000legacy cache\000Level 1 dat= a cache read accesses\000legacy-cache-config=3D0\000\00010\000\000\000\000\= 000" +/* offset=3D1268 */ "l1-dcache-loads-misses\000legacy cache\000Level 1 dat= a cache read misses\000legacy-cache-config=3D0x10000\000\00010\000\000\000\= 000\000" +/* offset=3D1371 */ "l1-dcache-loads-miss\000legacy cache\000Level 1 data = cache read misses\000legacy-cache-config=3D0x10000\000\00010\000\000\000\00= 0\000" +/* offset=3D1472 */ "l1-dcache-read\000legacy cache\000Level 1 data cache = read accesses\000legacy-cache-config=3D0\000\00010\000\000\000\000\000" +/* offset=3D1563 */ "l1-dcache-read-refs\000legacy cache\000Level 1 data c= ache read accesses\000legacy-cache-config=3D0\000\00010\000\000\000\000\000" +/* offset=3D1659 */ "l1-dcache-read-reference\000legacy cache\000Level 1 d= ata cache read accesses\000legacy-cache-config=3D0\000\00010\000\000\000\00= 0\000" +/* offset=3D1760 */ "l1-dcache-read-ops\000legacy cache\000Level 1 data ca= che read accesses\000legacy-cache-config=3D0\000\00010\000\000\000\000\000" +/* offset=3D1855 */ "l1-dcache-read-access\000legacy cache\000Level 1 data= cache read accesses\000legacy-cache-config=3D0\000\00010\000\000\000\000\0= 00" +/* offset=3D1953 */ "l1-dcache-read-misses\000legacy cache\000Level 1 data= cache read misses\000legacy-cache-config=3D0x10000\000\00010\000\000\000\0= 00\000" +/* offset=3D2055 */ "l1-dcache-read-miss\000legacy cache\000Level 1 data c= ache read misses\000legacy-cache-config=3D0x10000\000\00010\000\000\000\000= \000" +/* offset=3D2155 */ "l1-dcache-store\000legacy cache\000Level 1 data cache= write accesses\000legacy-cache-config=3D0x100\000\00010\000\000\000\000\00= 0" +/* offset=3D2252 */ "l1-dcache-store-refs\000legacy cache\000Level 1 data = cache write accesses\000legacy-cache-config=3D0x100\000\00010\000\000\000\0= 00\000" +/* offset=3D2354 */ "l1-dcache-store-reference\000legacy cache\000Level 1 = data cache write accesses\000legacy-cache-config=3D0x100\000\00010\000\000\= 000\000\000" +/* offset=3D2461 */ "l1-dcache-store-ops\000legacy cache\000Level 1 data c= ache write accesses\000legacy-cache-config=3D0x100\000\00010\000\000\000\00= 0\000" +/* offset=3D2562 */ "l1-dcache-store-access\000legacy cache\000Level 1 dat= a cache write accesses\000legacy-cache-config=3D0x100\000\00010\000\000\000= \000\000" +/* offset=3D2666 */ "l1-dcache-store-misses\000legacy cache\000Level 1 dat= a cache write misses\000legacy-cache-config=3D0x10100\000\00000\000\000\000= \000\000" +/* offset=3D2770 */ "l1-dcache-store-miss\000legacy cache\000Level 1 data = cache write misses\000legacy-cache-config=3D0x10100\000\00010\000\000\000\0= 00\000" +/* offset=3D2872 */ "l1-dcache-stores\000legacy cache\000Level 1 data cach= e write accesses\000legacy-cache-config=3D0x100\000\00000\000\000\000\000\0= 00" +/* offset=3D2970 */ "l1-dcache-stores-refs\000legacy cache\000Level 1 data= cache write accesses\000legacy-cache-config=3D0x100\000\00010\000\000\000\= 000\000" +/* offset=3D3073 */ "l1-dcache-stores-reference\000legacy cache\000Level 1= data cache write accesses\000legacy-cache-config=3D0x100\000\00010\000\000= \000\000\000" +/* offset=3D3181 */ "l1-dcache-stores-ops\000legacy cache\000Level 1 data = cache write accesses\000legacy-cache-config=3D0x100\000\00010\000\000\000\0= 00\000" +/* offset=3D3283 */ "l1-dcache-stores-access\000legacy cache\000Level 1 da= ta cache write accesses\000legacy-cache-config=3D0x100\000\00010\000\000\00= 0\000\000" +/* offset=3D3388 */ "l1-dcache-stores-misses\000legacy cache\000Level 1 da= ta cache write misses\000legacy-cache-config=3D0x10100\000\00010\000\000\00= 0\000\000" +/* offset=3D3493 */ "l1-dcache-stores-miss\000legacy cache\000Level 1 data= cache write misses\000legacy-cache-config=3D0x10100\000\00010\000\000\000\= 000\000" +/* offset=3D3596 */ "l1-dcache-write\000legacy cache\000Level 1 data cache= write accesses\000legacy-cache-config=3D0x100\000\00010\000\000\000\000\00= 0" +/* offset=3D3693 */ "l1-dcache-write-refs\000legacy cache\000Level 1 data = cache write accesses\000legacy-cache-config=3D0x100\000\00010\000\000\000\0= 00\000" +/* offset=3D3795 */ "l1-dcache-write-reference\000legacy cache\000Level 1 = data cache write accesses\000legacy-cache-config=3D0x100\000\00010\000\000\= 000\000\000" +/* offset=3D3902 */ "l1-dcache-write-ops\000legacy cache\000Level 1 data c= ache write accesses\000legacy-cache-config=3D0x100\000\00010\000\000\000\00= 0\000" +/* offset=3D4003 */ "l1-dcache-write-access\000legacy cache\000Level 1 dat= a cache write accesses\000legacy-cache-config=3D0x100\000\00010\000\000\000= \000\000" +/* offset=3D4107 */ "l1-dcache-write-misses\000legacy cache\000Level 1 dat= a cache write misses\000legacy-cache-config=3D0x10100\000\00010\000\000\000= \000\000" +/* offset=3D4211 */ "l1-dcache-write-miss\000legacy cache\000Level 1 data = cache write misses\000legacy-cache-config=3D0x10100\000\00010\000\000\000\0= 00\000" +/* offset=3D4313 */ "l1-dcache-prefetch\000legacy cache\000Level 1 data ca= che prefetch accesses\000legacy-cache-config=3D0x200\000\00010\000\000\000\= 000\000" +/* offset=3D4416 */ "l1-dcache-prefetch-refs\000legacy cache\000Level 1 da= ta cache prefetch accesses\000legacy-cache-config=3D0x200\000\00010\000\000= \000\000\000" +/* offset=3D4524 */ "l1-dcache-prefetch-reference\000legacy cache\000Level= 1 data cache prefetch accesses\000legacy-cache-config=3D0x200\000\00010\00= 0\000\000\000\000" +/* offset=3D4637 */ "l1-dcache-prefetch-ops\000legacy cache\000Level 1 dat= a cache prefetch accesses\000legacy-cache-config=3D0x200\000\00010\000\000\= 000\000\000" +/* offset=3D4744 */ "l1-dcache-prefetch-access\000legacy cache\000Level 1 = data cache prefetch accesses\000legacy-cache-config=3D0x200\000\00010\000\0= 00\000\000\000" +/* offset=3D4854 */ "l1-dcache-prefetch-misses\000legacy cache\000Level 1 = data cache prefetch misses\000legacy-cache-config=3D0x10200\000\00000\000\0= 00\000\000\000" +/* offset=3D4964 */ "l1-dcache-prefetch-miss\000legacy cache\000Level 1 da= ta cache prefetch misses\000legacy-cache-config=3D0x10200\000\00010\000\000= \000\000\000" +/* offset=3D5072 */ "l1-dcache-prefetches\000legacy cache\000Level 1 data = cache prefetch accesses\000legacy-cache-config=3D0x200\000\00000\000\000\00= 0\000\000" +/* offset=3D5177 */ "l1-dcache-prefetches-refs\000legacy cache\000Level 1 = data cache prefetch accesses\000legacy-cache-config=3D0x200\000\00010\000\0= 00\000\000\000" +/* offset=3D5287 */ "l1-dcache-prefetches-reference\000legacy cache\000Lev= el 1 data cache prefetch accesses\000legacy-cache-config=3D0x200\000\00010\= 000\000\000\000\000" +/* offset=3D5402 */ "l1-dcache-prefetches-ops\000legacy cache\000Level 1 d= ata cache prefetch accesses\000legacy-cache-config=3D0x200\000\00010\000\00= 0\000\000\000" +/* offset=3D5511 */ "l1-dcache-prefetches-access\000legacy cache\000Level = 1 data cache prefetch accesses\000legacy-cache-config=3D0x200\000\00010\000= \000\000\000\000" +/* offset=3D5623 */ "l1-dcache-prefetches-misses\000legacy cache\000Level = 1 data cache prefetch misses\000legacy-cache-config=3D0x10200\000\00010\000= \000\000\000\000" +/* offset=3D5735 */ "l1-dcache-prefetches-miss\000legacy cache\000Level 1 = data cache prefetch misses\000legacy-cache-config=3D0x10200\000\00010\000\0= 00\000\000\000" +/* offset=3D5845 */ "l1-dcache-speculative-read\000legacy cache\000Level 1= data cache prefetch accesses\000legacy-cache-config=3D0x200\000\00010\000\= 000\000\000\000" +/* offset=3D5956 */ "l1-dcache-speculative-read-refs\000legacy cache\000Le= vel 1 data cache prefetch accesses\000legacy-cache-config=3D0x200\000\00010= \000\000\000\000\000" +/* offset=3D6072 */ "l1-dcache-speculative-read-reference\000legacy cache\= 000Level 1 data cache prefetch accesses\000legacy-cache-config=3D0x200\000\= 00010\000\000\000\000\000" +/* offset=3D6193 */ "l1-dcache-speculative-read-ops\000legacy cache\000Lev= el 1 data cache prefetch accesses\000legacy-cache-config=3D0x200\000\00010\= 000\000\000\000\000" +/* offset=3D6308 */ "l1-dcache-speculative-read-access\000legacy cache\000= Level 1 data cache prefetch accesses\000legacy-cache-config=3D0x200\000\000= 10\000\000\000\000\000" +/* offset=3D6426 */ "l1-dcache-speculative-read-misses\000legacy cache\000= Level 1 data cache prefetch misses\000legacy-cache-config=3D0x10200\000\000= 10\000\000\000\000\000" +/* offset=3D6544 */ "l1-dcache-speculative-read-miss\000legacy cache\000Le= vel 1 data cache prefetch misses\000legacy-cache-config=3D0x10200\000\00010= \000\000\000\000\000" +/* offset=3D6660 */ "l1-dcache-speculative-load\000legacy cache\000Level 1= data cache prefetch accesses\000legacy-cache-config=3D0x200\000\00010\000\= 000\000\000\000" +/* offset=3D6771 */ "l1-dcache-speculative-load-refs\000legacy cache\000Le= vel 1 data cache prefetch accesses\000legacy-cache-config=3D0x200\000\00010= \000\000\000\000\000" +/* offset=3D6887 */ "l1-dcache-speculative-load-reference\000legacy cache\= 000Level 1 data cache prefetch accesses\000legacy-cache-config=3D0x200\000\= 00010\000\000\000\000\000" +/* offset=3D7008 */ "l1-dcache-speculative-load-ops\000legacy cache\000Lev= el 1 data cache prefetch accesses\000legacy-cache-config=3D0x200\000\00010\= 000\000\000\000\000" +/* offset=3D7123 */ "l1-dcache-speculative-load-access\000legacy cache\000= Level 1 data cache prefetch accesses\000legacy-cache-config=3D0x200\000\000= 10\000\000\000\000\000" +/* offset=3D7241 */ "l1-dcache-speculative-load-misses\000legacy cache\000= Level 1 data cache prefetch misses\000legacy-cache-config=3D0x10200\000\000= 10\000\000\000\000\000" +/* offset=3D7359 */ "l1-dcache-speculative-load-miss\000legacy cache\000Le= vel 1 data cache prefetch misses\000legacy-cache-config=3D0x10200\000\00010= \000\000\000\000\000" +/* offset=3D7475 */ "l1-dcache-refs\000legacy cache\000Level 1 data cache = read accesses\000legacy-cache-config=3D0\000\00010\000\000\000\000\000" +/* offset=3D7566 */ "l1-dcache-reference\000legacy cache\000Level 1 data c= ache read accesses\000legacy-cache-config=3D0\000\00010\000\000\000\000\000" +/* offset=3D7662 */ "l1-dcache-ops\000legacy cache\000Level 1 data cache r= ead accesses\000legacy-cache-config=3D0\000\00010\000\000\000\000\000" +/* offset=3D7752 */ "l1-dcache-access\000legacy cache\000Level 1 data cach= e read accesses\000legacy-cache-config=3D0\000\00010\000\000\000\000\000" +/* offset=3D7845 */ "l1-dcache-misses\000legacy cache\000Level 1 data cach= e read misses\000legacy-cache-config=3D0x10000\000\00010\000\000\000\000\00= 0" +/* offset=3D7942 */ "l1-dcache-miss\000legacy cache\000Level 1 data cache = read misses\000legacy-cache-config=3D0x10000\000\00010\000\000\000\000\000" +/* offset=3D8037 */ "l1-d\000legacy cache\000Level 1 data cache read acces= ses\000legacy-cache-config=3D0\000\00010\000\000\000\000\000" +/* offset=3D8118 */ "l1-d-load\000legacy cache\000Level 1 data cache read = accesses\000legacy-cache-config=3D0\000\00010\000\000\000\000\000" +/* offset=3D8204 */ "l1-d-load-refs\000legacy cache\000Level 1 data cache = read accesses\000legacy-cache-config=3D0\000\00010\000\000\000\000\000" +/* offset=3D8295 */ "l1-d-load-reference\000legacy cache\000Level 1 data c= ache read accesses\000legacy-cache-config=3D0\000\00010\000\000\000\000\000" +/* offset=3D8391 */ "l1-d-load-ops\000legacy cache\000Level 1 data cache r= ead accesses\000legacy-cache-config=3D0\000\00010\000\000\000\000\000" +/* offset=3D8481 */ "l1-d-load-access\000legacy cache\000Level 1 data cach= e read accesses\000legacy-cache-config=3D0\000\00010\000\000\000\000\000" +/* offset=3D8574 */ "l1-d-load-misses\000legacy cache\000Level 1 data cach= e read misses\000legacy-cache-config=3D0x10000\000\00010\000\000\000\000\00= 0" +/* offset=3D8671 */ "l1-d-load-miss\000legacy cache\000Level 1 data cache = read misses\000legacy-cache-config=3D0x10000\000\00010\000\000\000\000\000" +/* offset=3D8766 */ "l1-d-loads\000legacy cache\000Level 1 data cache read= accesses\000legacy-cache-config=3D0\000\00010\000\000\000\000\000" +/* offset=3D8853 */ "l1-d-loads-refs\000legacy cache\000Level 1 data cache= read accesses\000legacy-cache-config=3D0\000\00010\000\000\000\000\000" +/* offset=3D8945 */ "l1-d-loads-reference\000legacy cache\000Level 1 data = cache read accesses\000legacy-cache-config=3D0\000\00010\000\000\000\000\00= 0" +/* offset=3D9042 */ "l1-d-loads-ops\000legacy cache\000Level 1 data cache = read accesses\000legacy-cache-config=3D0\000\00010\000\000\000\000\000" +/* offset=3D9133 */ "l1-d-loads-access\000legacy cache\000Level 1 data cac= he read accesses\000legacy-cache-config=3D0\000\00010\000\000\000\000\000" +/* offset=3D9227 */ "l1-d-loads-misses\000legacy cache\000Level 1 data cac= he read misses\000legacy-cache-config=3D0x10000\000\00010\000\000\000\000\0= 00" +/* offset=3D9325 */ "l1-d-loads-miss\000legacy cache\000Level 1 data cache= read misses\000legacy-cache-config=3D0x10000\000\00010\000\000\000\000\000" +/* offset=3D9421 */ "l1-d-read\000legacy cache\000Level 1 data cache read = accesses\000legacy-cache-config=3D0\000\00010\000\000\000\000\000" +/* offset=3D9507 */ "l1-d-read-refs\000legacy cache\000Level 1 data cache = read accesses\000legacy-cache-config=3D0\000\00010\000\000\000\000\000" +/* offset=3D9598 */ "l1-d-read-reference\000legacy cache\000Level 1 data c= ache read accesses\000legacy-cache-config=3D0\000\00010\000\000\000\000\000" +/* offset=3D9694 */ "l1-d-read-ops\000legacy cache\000Level 1 data cache r= ead accesses\000legacy-cache-config=3D0\000\00010\000\000\000\000\000" +/* offset=3D9784 */ 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accesses\000legacy-cache-config=3D0x100\000\00010\000\000\000\000\00= 0" +/* offset=3D10456 */ "l1-d-store-access\000legacy cache\000Level 1 data ca= che write accesses\000legacy-cache-config=3D0x100\000\00010\000\000\000\000= \000" +/* offset=3D10555 */ "l1-d-store-misses\000legacy cache\000Level 1 data ca= che write misses\000legacy-cache-config=3D0x10100\000\00010\000\000\000\000= \000" +/* offset=3D10654 */ "l1-d-store-miss\000legacy cache\000Level 1 data cach= e write misses\000legacy-cache-config=3D0x10100\000\00010\000\000\000\000\0= 00" +/* offset=3D10751 */ "l1-d-stores\000legacy cache\000Level 1 data cache wr= ite accesses\000legacy-cache-config=3D0x100\000\00010\000\000\000\000\000" +/* offset=3D10844 */ "l1-d-stores-refs\000legacy cache\000Level 1 data cac= he write accesses\000legacy-cache-config=3D0x100\000\00010\000\000\000\000\= 000" +/* offset=3D10942 */ "l1-d-stores-reference\000legacy cache\000Level 1 dat= a cache write accesses\000legacy-cache-config=3D0x100\000\00010\000\000\000= \000\000" +/* offset=3D11045 */ "l1-d-stores-ops\000legacy cache\000Level 1 data cach= e write accesses\000legacy-cache-config=3D0x100\000\00010\000\000\000\000\0= 00" +/* offset=3D11142 */ "l1-d-stores-access\000legacy cache\000Level 1 data c= ache write accesses\000legacy-cache-config=3D0x100\000\00010\000\000\000\00= 0\000" +/* offset=3D11242 */ "l1-d-stores-misses\000legacy cache\000Level 1 data c= ache write misses\000legacy-cache-config=3D0x10100\000\00010\000\000\000\00= 0\000" +/* offset=3D11342 */ "l1-d-stores-miss\000legacy cache\000Level 1 data cac= he write misses\000legacy-cache-config=3D0x10100\000\00010\000\000\000\000\= 000" +/* offset=3D11440 */ "l1-d-write\000legacy cache\000Level 1 data cache wri= te accesses\000legacy-cache-config=3D0x100\000\00010\000\000\000\000\000" +/* offset=3D11532 */ "l1-d-write-refs\000legacy cache\000Level 1 data cach= e write accesses\000legacy-cache-config=3D0x100\000\00010\000\000\000\000\0= 00" +/* offset=3D11629 */ "l1-d-write-reference\000legacy cache\000Level 1 data= cache write accesses\000legacy-cache-config=3D0x100\000\00010\000\000\000\= 000\000" +/* offset=3D11731 */ "l1-d-write-ops\000legacy cache\000Level 1 data cache= write accesses\000legacy-cache-config=3D0x100\000\00010\000\000\000\000\00= 0" +/* offset=3D11827 */ "l1-d-write-access\000legacy cache\000Level 1 data ca= che write accesses\000legacy-cache-config=3D0x100\000\00010\000\000\000\000= \000" +/* offset=3D11926 */ "l1-d-write-misses\000legacy cache\000Level 1 data ca= che write misses\000legacy-cache-config=3D0x10100\000\00010\000\000\000\000= \000" +/* offset=3D12025 */ "l1-d-write-miss\000legacy cache\000Level 1 data cach= e write misses\000legacy-cache-config=3D0x10100\000\00010\000\000\000\000\0= 00" +/* offset=3D12122 */ "l1-d-prefetch\000legacy cache\000Level 1 data cache = prefetch accesses\000legacy-cache-config=3D0x200\000\00010\000\000\000\000\= 000" +/* offset=3D12220 */ "l1-d-prefetch-refs\000legacy cache\000Level 1 data c= ache prefetch accesses\000legacy-cache-config=3D0x200\000\00010\000\000\000= \000\000" +/* offset=3D12323 */ "l1-d-prefetch-reference\000legacy cache\000Level 1 d= ata cache prefetch accesses\000legacy-cache-config=3D0x200\000\00010\000\00= 0\000\000\000" +/* offset=3D12431 */ "l1-d-prefetch-ops\000legacy cache\000Level 1 data ca= che prefetch accesses\000legacy-cache-config=3D0x200\000\00010\000\000\000\= 000\000" +/* offset=3D12533 */ "l1-d-prefetch-access\000legacy cache\000Level 1 data= cache prefetch accesses\000legacy-cache-config=3D0x200\000\00010\000\000\0= 00\000\000" +/* offset=3D12638 */ "l1-d-prefetch-misses\000legacy cache\000Level 1 data= cache prefetch misses\000legacy-cache-config=3D0x10200\000\00010\000\000\0= 00\000\000" +/* offset=3D12743 */ "l1-d-prefetch-miss\000legacy cache\000Level 1 data c= ache prefetch misses\000legacy-cache-config=3D0x10200\000\00010\000\000\000= \000\000" +/* offset=3D12846 */ "l1-d-prefetches\000legacy cache\000Level 1 data cach= e prefetch accesses\000legacy-cache-config=3D0x200\000\00010\000\000\000\00= 0\000" +/* offset=3D12946 */ "l1-d-prefetches-refs\000legacy cache\000Level 1 data= cache prefetch accesses\000legacy-cache-config=3D0x200\000\00010\000\000\0= 00\000\000" +/* offset=3D13051 */ "l1-d-prefetches-reference\000legacy cache\000Level 1= data cache prefetch accesses\000legacy-cache-config=3D0x200\000\00010\000\= 000\000\000\000" +/* offset=3D13161 */ "l1-d-prefetches-ops\000legacy cache\000Level 1 data = cache prefetch accesses\000legacy-cache-config=3D0x200\000\00010\000\000\00= 0\000\000" +/* offset=3D13265 */ "l1-d-prefetches-access\000legacy cache\000Level 1 da= ta cache prefetch accesses\000legacy-cache-config=3D0x200\000\00010\000\000= \000\000\000" +/* offset=3D13372 */ "l1-d-prefetches-misses\000legacy cache\000Level 1 da= ta cache prefetch misses\000legacy-cache-config=3D0x10200\000\00010\000\000= \000\000\000" +/* offset=3D13479 */ "l1-d-prefetches-miss\000legacy cache\000Level 1 data= cache prefetch misses\000legacy-cache-config=3D0x10200\000\00010\000\000\0= 00\000\000" +/* offset=3D13584 */ "l1-d-speculative-read\000legacy cache\000Level 1 dat= a cache prefetch accesses\000legacy-cache-config=3D0x200\000\00010\000\000\= 000\000\000" +/* offset=3D13690 */ "l1-d-speculative-read-refs\000legacy cache\000Level = 1 data cache prefetch accesses\000legacy-cache-config=3D0x200\000\00010\000= \000\000\000\000" +/* offset=3D13801 */ "l1-d-speculative-read-reference\000legacy cache\000L= evel 1 data cache prefetch accesses\000legacy-cache-config=3D0x200\000\0001= 0\000\000\000\000\000" +/* offset=3D13917 */ "l1-d-speculative-read-ops\000legacy cache\000Level 1= data cache prefetch accesses\000legacy-cache-config=3D0x200\000\00010\000\= 000\000\000\000" +/* offset=3D14027 */ "l1-d-speculative-read-access\000legacy cache\000Leve= l 1 data cache prefetch accesses\000legacy-cache-config=3D0x200\000\00010\0= 00\000\000\000\000" +/* offset=3D14140 */ "l1-d-speculative-read-misses\000legacy cache\000Leve= l 1 data cache prefetch misses\000legacy-cache-config=3D0x10200\000\00010\0= 00\000\000\000\000" +/* offset=3D14253 */ "l1-d-speculative-read-miss\000legacy cache\000Level = 1 data cache prefetch misses\000legacy-cache-config=3D0x10200\000\00010\000= \000\000\000\000" +/* offset=3D14364 */ "l1-d-speculative-load\000legacy cache\000Level 1 dat= a cache prefetch accesses\000legacy-cache-config=3D0x200\000\00010\000\000\= 000\000\000" +/* offset=3D14470 */ "l1-d-speculative-load-refs\000legacy cache\000Level = 1 data cache prefetch accesses\000legacy-cache-config=3D0x200\000\00010\000= \000\000\000\000" +/* offset=3D14581 */ "l1-d-speculative-load-reference\000legacy cache\000L= evel 1 data cache prefetch accesses\000legacy-cache-config=3D0x200\000\0001= 0\000\000\000\000\000" +/* offset=3D14697 */ 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"l1-d-ops\000legacy cache\000Level 1 data cache read = accesses\000legacy-cache-config=3D0\000\00010\000\000\000\000\000" +/* offset=3D15406 */ "l1-d-access\000legacy cache\000Level 1 data cache re= ad accesses\000legacy-cache-config=3D0\000\00010\000\000\000\000\000" +/* offset=3D15494 */ "l1-d-misses\000legacy cache\000Level 1 data cache re= ad misses\000legacy-cache-config=3D0x10000\000\00010\000\000\000\000\000" +/* offset=3D15586 */ "l1-d-miss\000legacy cache\000Level 1 data cache read= misses\000legacy-cache-config=3D0x10000\000\00010\000\000\000\000\000" +/* offset=3D15676 */ "l1d\000legacy cache\000Level 1 data cache read acces= ses\000legacy-cache-config=3D0\000\00010\000\000\000\000\000" +/* offset=3D15756 */ "l1d-load\000legacy cache\000Level 1 data cache read = accesses\000legacy-cache-config=3D0\000\00010\000\000\000\000\000" +/* offset=3D15841 */ "l1d-load-refs\000legacy cache\000Level 1 data cache = read accesses\000legacy-cache-config=3D0\000\00010\000\000\000\000\000" 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accesses\000legacy-cache-config=3D0\000\00010\000\000\000\000\000" +/* offset=3D16574 */ "l1d-loads-reference\000legacy cache\000Level 1 data = cache read accesses\000legacy-cache-config=3D0\000\00010\000\000\000\000\00= 0" +/* offset=3D16670 */ "l1d-loads-ops\000legacy cache\000Level 1 data cache = read accesses\000legacy-cache-config=3D0\000\00010\000\000\000\000\000" +/* offset=3D16760 */ "l1d-loads-access\000legacy cache\000Level 1 data cac= he read accesses\000legacy-cache-config=3D0\000\00010\000\000\000\000\000" +/* offset=3D16853 */ "l1d-loads-misses\000legacy cache\000Level 1 data cac= he read misses\000legacy-cache-config=3D0x10000\000\00010\000\000\000\000\0= 00" +/* offset=3D16950 */ "l1d-loads-miss\000legacy cache\000Level 1 data cache= read misses\000legacy-cache-config=3D0x10000\000\00010\000\000\000\000\000" +/* offset=3D17045 */ "l1d-read\000legacy cache\000Level 1 data cache read = accesses\000legacy-cache-config=3D0\000\00010\000\000\000\000\000" +/* offset=3D17130 */ "l1d-read-refs\000legacy cache\000Level 1 data cache = read accesses\000legacy-cache-config=3D0\000\00010\000\000\000\000\000" +/* offset=3D17220 */ "l1d-read-reference\000legacy cache\000Level 1 data c= ache read accesses\000legacy-cache-config=3D0\000\00010\000\000\000\000\000" +/* offset=3D17315 */ "l1d-read-ops\000legacy cache\000Level 1 data cache r= ead accesses\000legacy-cache-config=3D0\000\00010\000\000\000\000\000" +/* offset=3D17404 */ "l1d-read-access\000legacy cache\000Level 1 data cach= e read accesses\000legacy-cache-config=3D0\000\00010\000\000\000\000\000" +/* offset=3D17496 */ "l1d-read-misses\000legacy cache\000Level 1 data cach= e read misses\000legacy-cache-config=3D0x10000\000\00010\000\000\000\000\00= 0" +/* offset=3D17592 */ "l1d-read-miss\000legacy cache\000Level 1 data cache = read misses\000legacy-cache-config=3D0x10000\000\00010\000\000\000\000\000" +/* offset=3D17686 */ "l1d-store\000legacy cache\000Level 1 data cache writ= e accesses\000legacy-cache-config=3D0x100\000\00010\000\000\000\000\000" +/* offset=3D17777 */ "l1d-store-refs\000legacy cache\000Level 1 data cache= write accesses\000legacy-cache-config=3D0x100\000\00010\000\000\000\000\00= 0" +/* offset=3D17873 */ "l1d-store-reference\000legacy cache\000Level 1 data = cache write accesses\000legacy-cache-config=3D0x100\000\00010\000\000\000\0= 00\000" +/* offset=3D17974 */ "l1d-store-ops\000legacy cache\000Level 1 data cache = write accesses\000legacy-cache-config=3D0x100\000\00010\000\000\000\000\000" +/* offset=3D18069 */ "l1d-store-access\000legacy cache\000Level 1 data cac= he write accesses\000legacy-cache-config=3D0x100\000\00010\000\000\000\000\= 000" +/* offset=3D18167 */ "l1d-store-misses\000legacy cache\000Level 1 data cac= he write misses\000legacy-cache-config=3D0x10100\000\00010\000\000\000\000\= 000" +/* offset=3D18265 */ "l1d-store-miss\000legacy cache\000Level 1 data cache= write misses\000legacy-cache-config=3D0x10100\000\00010\000\000\000\000\00= 0" +/* offset=3D18361 */ "l1d-stores\000legacy cache\000Level 1 data cache wri= te accesses\000legacy-cache-config=3D0x100\000\00010\000\000\000\000\000" +/* offset=3D18453 */ "l1d-stores-refs\000legacy cache\000Level 1 data cach= e write accesses\000legacy-cache-config=3D0x100\000\00010\000\000\000\000\0= 00" +/* offset=3D18550 */ "l1d-stores-reference\000legacy cache\000Level 1 data= cache write accesses\000legacy-cache-config=3D0x100\000\00010\000\000\000\= 000\000" +/* offset=3D18652 */ "l1d-stores-ops\000legacy cache\000Level 1 data cache= write accesses\000legacy-cache-config=3D0x100\000\00010\000\000\000\000\00= 0" +/* offset=3D18748 */ "l1d-stores-access\000legacy cache\000Level 1 data ca= che write accesses\000legacy-cache-config=3D0x100\000\00010\000\000\000\000= \000" +/* offset=3D18847 */ "l1d-stores-misses\000legacy cache\000Level 1 data ca= che write misses\000legacy-cache-config=3D0x10100\000\00010\000\000\000\000= \000" +/* offset=3D18946 */ "l1d-stores-miss\000legacy cache\000Level 1 data cach= e write misses\000legacy-cache-config=3D0x10100\000\00010\000\000\000\000\0= 00" +/* offset=3D19043 */ "l1d-write\000legacy cache\000Level 1 data cache writ= e accesses\000legacy-cache-config=3D0x100\000\00010\000\000\000\000\000" +/* offset=3D19134 */ "l1d-write-refs\000legacy cache\000Level 1 data cache= write accesses\000legacy-cache-config=3D0x100\000\00010\000\000\000\000\00= 0" +/* offset=3D19230 */ "l1d-write-reference\000legacy cache\000Level 1 data = cache write accesses\000legacy-cache-config=3D0x100\000\00010\000\000\000\0= 00\000" +/* offset=3D19331 */ "l1d-write-ops\000legacy cache\000Level 1 data cache = write accesses\000legacy-cache-config=3D0x100\000\00010\000\000\000\000\000" +/* offset=3D19426 */ "l1d-write-access\000legacy cache\000Level 1 data cac= he write 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accesses\000legacy-cache-config=3D0x200\000\00010\000\000\000\0= 00\000" +/* offset=3D20125 */ "l1d-prefetch-access\000legacy cache\000Level 1 data = cache prefetch accesses\000legacy-cache-config=3D0x200\000\00010\000\000\00= 0\000\000" +/* offset=3D20229 */ "l1d-prefetch-misses\000legacy cache\000Level 1 data = cache prefetch misses\000legacy-cache-config=3D0x10200\000\00010\000\000\00= 0\000\000" +/* offset=3D20333 */ "l1d-prefetch-miss\000legacy cache\000Level 1 data ca= che prefetch misses\000legacy-cache-config=3D0x10200\000\00010\000\000\000\= 000\000" +/* offset=3D20435 */ "l1d-prefetches\000legacy cache\000Level 1 data cache= prefetch accesses\000legacy-cache-config=3D0x200\000\00010\000\000\000\000= \000" +/* offset=3D20534 */ "l1d-prefetches-refs\000legacy cache\000Level 1 data = cache prefetch accesses\000legacy-cache-config=3D0x200\000\00010\000\000\00= 0\000\000" +/* offset=3D20638 */ "l1d-prefetches-reference\000legacy cache\000Level 1 = data cache prefetch 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*/ "l1-i-miss\000legacy cache\000Level 1 instruction cac= he read misses\000legacy-cache-config=3D0x10001\000\00010\000\000\000\000\0= 00" +/* offset=3D43344 */ "l1i\000legacy cache\000Level 1 instruction cache rea= d accesses\000legacy-cache-config=3D1\000\00010\000\000\000\000\000" +/* offset=3D43431 */ "l1i-load\000legacy cache\000Level 1 instruction cach= e read accesses\000legacy-cache-config=3D1\000\00010\000\000\000\000\000" +/* offset=3D43523 */ "l1i-load-refs\000legacy cache\000Level 1 instruction= cache read accesses\000legacy-cache-config=3D1\000\00010\000\000\000\000\0= 00" +/* offset=3D43620 */ "l1i-load-reference\000legacy cache\000Level 1 instru= ction cache read accesses\000legacy-cache-config=3D1\000\00010\000\000\000\= 000\000" +/* offset=3D43722 */ "l1i-load-ops\000legacy cache\000Level 1 instruction = cache read accesses\000legacy-cache-config=3D1\000\00010\000\000\000\000\00= 0" +/* offset=3D43818 */ "l1i-load-access\000legacy cache\000Level 1 instructi= on cache read accesses\000legacy-cache-config=3D1\000\00010\000\000\000\000= \000" +/* offset=3D43917 */ "l1i-load-misses\000legacy cache\000Level 1 instructi= on cache read misses\000legacy-cache-config=3D0x10001\000\00010\000\000\000= \000\000" +/* offset=3D44020 */ "l1i-load-miss\000legacy cache\000Level 1 instruction= cache read misses\000legacy-cache-config=3D0x10001\000\00010\000\000\000\0= 00\000" +/* offset=3D44121 */ "l1i-loads\000legacy cache\000Level 1 instruction cac= he read accesses\000legacy-cache-config=3D1\000\00010\000\000\000\000\000" +/* offset=3D44214 */ "l1i-loads-refs\000legacy cache\000Level 1 instructio= n cache read accesses\000legacy-cache-config=3D1\000\00010\000\000\000\000\= 000" +/* offset=3D44312 */ "l1i-loads-reference\000legacy cache\000Level 1 instr= uction cache read accesses\000legacy-cache-config=3D1\000\00010\000\000\000= \000\000" +/* offset=3D44415 */ "l1i-loads-ops\000legacy cache\000Level 1 instruction= cache read accesses\000legacy-cache-config=3D1\000\00010\000\000\000\000\0= 00" +/* offset=3D44512 */ "l1i-loads-access\000legacy cache\000Level 1 instruct= ion cache read accesses\000legacy-cache-config=3D1\000\00010\000\000\000\00= 0\000" +/* offset=3D44612 */ "l1i-loads-misses\000legacy cache\000Level 1 instruct= ion cache read misses\000legacy-cache-config=3D0x10001\000\00010\000\000\00= 0\000\000" +/* offset=3D44716 */ "l1i-loads-miss\000legacy cache\000Level 1 instructio= n cache read misses\000legacy-cache-config=3D0x10001\000\00010\000\000\000\= 000\000" +/* offset=3D44818 */ "l1i-read\000legacy cache\000Level 1 instruction cach= e read accesses\000legacy-cache-config=3D1\000\00010\000\000\000\000\000" +/* offset=3D44910 */ "l1i-read-refs\000legacy cache\000Level 1 instruction= cache read accesses\000legacy-cache-config=3D1\000\00010\000\000\000\000\0= 00" +/* offset=3D45007 */ "l1i-read-reference\000legacy cache\000Level 1 instru= ction cache read accesses\000legacy-cache-config=3D1\000\00010\000\000\000\= 000\000" +/* offset=3D45109 */ "l1i-read-ops\000legacy cache\000Level 1 instruction = cache read accesses\000legacy-cache-config=3D1\000\00010\000\000\000\000\00= 0" +/* offset=3D45205 */ "l1i-read-access\000legacy cache\000Level 1 instructi= on cache read accesses\000legacy-cache-config=3D1\000\00010\000\000\000\000= \000" +/* offset=3D45304 */ "l1i-read-misses\000legacy cache\000Level 1 instructi= on cache read misses\000legacy-cache-config=3D0x10001\000\00010\000\000\000= \000\000" +/* offset=3D45407 */ "l1i-read-miss\000legacy cache\000Level 1 instruction= cache read misses\000legacy-cache-config=3D0x10001\000\00010\000\000\000\0= 00\000" +/* offset=3D45508 */ "l1i-prefetch\000legacy cache\000Level 1 instruction = cache prefetch accesses\000legacy-cache-config=3D0x201\000\00010\000\000\00= 0\000\000" +/* offset=3D45612 */ "l1i-prefetch-refs\000legacy cache\000Level 1 instruc= tion cache prefetch accesses\000legacy-cache-config=3D0x201\000\00010\000\0= 00\000\000\000" +/* offset=3D45721 */ "l1i-prefetch-reference\000legacy cache\000Level 1 in= struction cache prefetch accesses\000legacy-cache-config=3D0x201\000\00010\= 000\000\000\000\000" +/* offset=3D45835 */ "l1i-prefetch-ops\000legacy cache\000Level 1 instruct= ion cache prefetch accesses\000legacy-cache-config=3D0x201\000\00010\000\00= 0\000\000\000" +/* offset=3D45943 */ "l1i-prefetch-access\000legacy cache\000Level 1 instr= uction cache prefetch accesses\000legacy-cache-config=3D0x201\000\00010\000= \000\000\000\000" +/* offset=3D46054 */ "l1i-prefetch-misses\000legacy cache\000Level 1 instr= uction cache prefetch misses\000legacy-cache-config=3D0x10201\000\00010\000= \000\000\000\000" +/* offset=3D46165 */ "l1i-prefetch-miss\000legacy cache\000Level 1 instruc= tion cache prefetch misses\000legacy-cache-config=3D0x10201\000\00010\000\0= 00\000\000\000" +/* offset=3D46274 */ "l1i-prefetches\000legacy cache\000Level 1 instructio= n cache prefetch accesses\000legacy-cache-config=3D0x201\000\00010\000\000\= 000\000\000" +/* offset=3D46380 */ "l1i-prefetches-refs\000legacy cache\000Level 1 instr= uction cache prefetch accesses\000legacy-cache-config=3D0x201\000\00010\000= \000\000\000\000" +/* offset=3D46491 */ "l1i-prefetches-reference\000legacy cache\000Level 1 = instruction cache prefetch accesses\000legacy-cache-config=3D0x201\000\0001= 0\000\000\000\000\000" +/* offset=3D46607 */ "l1i-prefetches-ops\000legacy cache\000Level 1 instru= ction cache prefetch accesses\000legacy-cache-config=3D0x201\000\00010\000\= 000\000\000\000" +/* offset=3D46717 */ "l1i-prefetches-access\000legacy cache\000Level 1 ins= truction cache prefetch accesses\000legacy-cache-config=3D0x201\000\00010\0= 00\000\000\000\000" +/* offset=3D46830 */ "l1i-prefetches-misses\000legacy cache\000Level 1 ins= truction cache prefetch misses\000legacy-cache-config=3D0x10201\000\00010\0= 00\000\000\000\000" +/* offset=3D46943 */ "l1i-prefetches-miss\000legacy cache\000Level 1 instr= uction cache prefetch misses\000legacy-cache-config=3D0x10201\000\00010\000= \000\000\000\000" +/* offset=3D47054 */ "l1i-speculative-read\000legacy cache\000Level 1 inst= ruction cache prefetch accesses\000legacy-cache-config=3D0x201\000\00010\00= 0\000\000\000\000" +/* offset=3D47166 */ "l1i-speculative-read-refs\000legacy cache\000Level 1= instruction cache prefetch accesses\000legacy-cache-config=3D0x201\000\000= 10\000\000\000\000\000" +/* offset=3D47283 */ "l1i-speculative-read-reference\000legacy cache\000Le= vel 1 instruction cache prefetch accesses\000legacy-cache-config=3D0x201\00= 0\00010\000\000\000\000\000" +/* offset=3D47405 */ "l1i-speculative-read-ops\000legacy cache\000Level 1 = instruction cache prefetch accesses\000legacy-cache-config=3D0x201\000\0001= 0\000\000\000\000\000" +/* offset=3D47521 */ "l1i-speculative-read-access\000legacy cache\000Level= 1 instruction cache prefetch accesses\000legacy-cache-config=3D0x201\000\0= 0010\000\000\000\000\000" +/* offset=3D47640 */ "l1i-speculative-read-misses\000legacy cache\000Level= 1 instruction cache prefetch misses\000legacy-cache-config=3D0x10201\000\0= 0010\000\000\000\000\000" +/* offset=3D47759 */ "l1i-speculative-read-miss\000legacy cache\000Level 1= instruction cache prefetch misses\000legacy-cache-config=3D0x10201\000\000= 10\000\000\000\000\000" +/* offset=3D47876 */ "l1i-speculative-load\000legacy cache\000Level 1 inst= ruction cache prefetch accesses\000legacy-cache-config=3D0x201\000\00010\00= 0\000\000\000\000" +/* offset=3D47988 */ "l1i-speculative-load-refs\000legacy cache\000Level 1= instruction cache prefetch accesses\000legacy-cache-config=3D0x201\000\000= 10\000\000\000\000\000" +/* offset=3D48105 */ "l1i-speculative-load-reference\000legacy cache\000Le= vel 1 instruction cache prefetch accesses\000legacy-cache-config=3D0x201\00= 0\00010\000\000\000\000\000" +/* offset=3D48227 */ "l1i-speculative-load-ops\000legacy cache\000Level 1 = instruction cache prefetch accesses\000legacy-cache-config=3D0x201\000\0001= 0\000\000\000\000\000" +/* offset=3D48343 */ "l1i-speculative-load-access\000legacy cache\000Level= 1 instruction cache prefetch accesses\000legacy-cache-config=3D0x201\000\0= 0010\000\000\000\000\000" +/* offset=3D48462 */ "l1i-speculative-load-misses\000legacy cache\000Level= 1 instruction cache prefetch misses\000legacy-cache-config=3D0x10201\000\0= 0010\000\000\000\000\000" +/* offset=3D48581 */ "l1i-speculative-load-miss\000legacy cache\000Level 1= instruction cache prefetch misses\000legacy-cache-config=3D0x10201\000\000= 10\000\000\000\000\000" +/* offset=3D48698 */ "l1i-refs\000legacy cache\000Level 1 instruction cach= e read accesses\000legacy-cache-config=3D1\000\00010\000\000\000\000\000" +/* offset=3D48790 */ "l1i-reference\000legacy cache\000Level 1 instruction= cache read accesses\000legacy-cache-config=3D1\000\00010\000\000\000\000\0= 00" +/* offset=3D48887 */ "l1i-ops\000legacy cache\000Level 1 instruction cache= read accesses\000legacy-cache-config=3D1\000\00010\000\000\000\000\000" +/* offset=3D48978 */ "l1i-access\000legacy cache\000Level 1 instruction ca= che read accesses\000legacy-cache-config=3D1\000\00010\000\000\000\000\000" +/* offset=3D49072 */ "l1i-misses\000legacy cache\000Level 1 instruction ca= che read misses\000legacy-cache-config=3D0x10001\000\00010\000\000\000\000\= 000" +/* offset=3D49170 */ "l1i-miss\000legacy cache\000Level 1 instruction cach= e read misses\000legacy-cache-config=3D0x10001\000\00010\000\000\000\000\00= 0" +/* offset=3D49266 */ "l1-instruction\000legacy cache\000Level 1 instructio= n cache read accesses\000legacy-cache-config=3D1\000\00010\000\000\000\000\= 000" +/* offset=3D49364 */ "l1-instruction-load\000legacy cache\000Level 1 instr= uction cache read accesses\000legacy-cache-config=3D1\000\00010\000\000\000= \000\000" +/* offset=3D49467 */ "l1-instruction-load-refs\000legacy cache\000Level 1 = instruction cache read accesses\000legacy-cache-config=3D1\000\00010\000\00= 0\000\000\000" +/* offset=3D49575 */ "l1-instruction-load-reference\000legacy cache\000Lev= el 1 instruction cache read accesses\000legacy-cache-config=3D1\000\00010\0= 00\000\000\000\000" +/* offset=3D49688 */ "l1-instruction-load-ops\000legacy cache\000Level 1 i= nstruction cache read accesses\000legacy-cache-config=3D1\000\00010\000\000= \000\000\000" +/* offset=3D49795 */ "l1-instruction-load-access\000legacy cache\000Level = 1 instruction cache read accesses\000legacy-cache-config=3D1\000\00010\000\= 000\000\000\000" +/* offset=3D49905 */ "l1-instruction-load-misses\000legacy cache\000Level = 1 instruction cache read misses\000legacy-cache-config=3D0x10001\000\00010\= 000\000\000\000\000" +/* offset=3D50019 */ "l1-instruction-load-miss\000legacy cache\000Level 1 = instruction cache read misses\000legacy-cache-config=3D0x10001\000\00010\00= 0\000\000\000\000" +/* offset=3D50131 */ "l1-instruction-loads\000legacy cache\000Level 1 inst= ruction cache read accesses\000legacy-cache-config=3D1\000\00010\000\000\00= 0\000\000" +/* offset=3D50235 */ "l1-instruction-loads-refs\000legacy cache\000Level 1= instruction cache read accesses\000legacy-cache-config=3D1\000\00010\000\0= 00\000\000\000" +/* offset=3D50344 */ "l1-instruction-loads-reference\000legacy cache\000Le= vel 1 instruction cache read accesses\000legacy-cache-config=3D1\000\00010\= 000\000\000\000\000" +/* offset=3D50458 */ "l1-instruction-loads-ops\000legacy cache\000Level 1 = instruction cache read accesses\000legacy-cache-config=3D1\000\00010\000\00= 0\000\000\000" +/* offset=3D50566 */ "l1-instruction-loads-access\000legacy cache\000Level= 1 instruction cache read accesses\000legacy-cache-config=3D1\000\00010\000= \000\000\000\000" +/* offset=3D50677 */ "l1-instruction-loads-misses\000legacy cache\000Level= 1 instruction cache read misses\000legacy-cache-config=3D0x10001\000\00010= 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accesses\000legacy-cache-config=3D1\000\00010\000\= 000\000\000\000" +/* offset=3D51446 */ "l1-instruction-read-misses\000legacy cache\000Level = 1 instruction cache read misses\000legacy-cache-config=3D0x10001\000\00010\= 000\000\000\000\000" +/* offset=3D51560 */ "l1-instruction-read-miss\000legacy cache\000Level 1 = instruction cache read misses\000legacy-cache-config=3D0x10001\000\00010\00= 0\000\000\000\000" +/* offset=3D51672 */ "l1-instruction-prefetch\000legacy cache\000Level 1 i= nstruction cache prefetch accesses\000legacy-cache-config=3D0x201\000\00010= \000\000\000\000\000" +/* offset=3D51787 */ "l1-instruction-prefetch-refs\000legacy cache\000Leve= l 1 instruction cache prefetch accesses\000legacy-cache-config=3D0x201\000\= 00010\000\000\000\000\000" +/* offset=3D51907 */ "l1-instruction-prefetch-reference\000legacy cache\00= 0Level 1 instruction cache prefetch accesses\000legacy-cache-config=3D0x201= \000\00010\000\000\000\000\000" +/* offset=3D52032 */ "l1-instruction-prefetch-ops\000legacy cache\000Level= 1 instruction cache prefetch accesses\000legacy-cache-config=3D0x201\000\0= 0010\000\000\000\000\000" +/* offset=3D52151 */ "l1-instruction-prefetch-access\000legacy cache\000Le= vel 1 instruction cache prefetch accesses\000legacy-cache-config=3D0x201\00= 0\00010\000\000\000\000\000" +/* offset=3D52273 */ "l1-instruction-prefetch-misses\000legacy cache\000Le= vel 1 instruction cache prefetch misses\000legacy-cache-config=3D0x10201\00= 0\00010\000\000\000\000\000" +/* offset=3D52395 */ "l1-instruction-prefetch-miss\000legacy cache\000Leve= l 1 instruction cache prefetch misses\000legacy-cache-config=3D0x10201\000\= 00010\000\000\000\000\000" +/* offset=3D52515 */ "l1-instruction-prefetches\000legacy cache\000Level 1= instruction cache prefetch accesses\000legacy-cache-config=3D0x201\000\000= 10\000\000\000\000\000" +/* offset=3D52632 */ "l1-instruction-prefetches-refs\000legacy cache\000Le= vel 1 instruction cache prefetch accesses\000legacy-cache-config=3D0x201\00= 0\00010\000\000\000\000\000" +/* offset=3D52754 */ "l1-instruction-prefetches-reference\000legacy cache\= 000Level 1 instruction cache prefetch accesses\000legacy-cache-config=3D0x2= 01\000\00010\000\000\000\000\000" +/* offset=3D52881 */ "l1-instruction-prefetches-ops\000legacy cache\000Lev= el 1 instruction cache prefetch accesses\000legacy-cache-config=3D0x201\000= \00010\000\000\000\000\000" +/* offset=3D53002 */ "l1-instruction-prefetches-access\000legacy cache\000= Level 1 instruction cache prefetch accesses\000legacy-cache-config=3D0x201\= 000\00010\000\000\000\000\000" +/* offset=3D53126 */ "l1-instruction-prefetches-misses\000legacy cache\000= Level 1 instruction cache prefetch misses\000legacy-cache-config=3D0x10201\= 000\00010\000\000\000\000\000" +/* offset=3D53250 */ "l1-instruction-prefetches-miss\000legacy cache\000Le= vel 1 instruction cache prefetch misses\000legacy-cache-config=3D0x10201\00= 0\00010\000\000\000\000\000" +/* offset=3D53372 */ "l1-instruction-speculative-read\000legacy cache\000L= evel 1 instruction cache prefetch accesses\000legacy-cache-config=3D0x201\0= 00\00010\000\000\000\000\000" +/* offset=3D53495 */ "l1-instruction-speculative-read-refs\000legacy cache= \000Level 1 instruction cache prefetch accesses\000legacy-cache-config=3D0x= 201\000\00010\000\000\000\000\000" +/* offset=3D53623 */ "l1-instruction-speculative-read-reference\000legacy = cache\000Level 1 instruction cache prefetch accesses\000legacy-cache-config= =3D0x201\000\00010\000\000\000\000\000" +/* offset=3D53756 */ "l1-instruction-speculative-read-ops\000legacy cache\= 000Level 1 instruction cache prefetch accesses\000legacy-cache-config=3D0x2= 01\000\00010\000\000\000\000\000" +/* offset=3D53883 */ "l1-instruction-speculative-read-access\000legacy cac= he\000Level 1 instruction cache prefetch accesses\000legacy-cache-config=3D= 0x201\000\00010\000\000\000\000\000" +/* offset=3D54013 */ "l1-instruction-speculative-read-misses\000legacy cac= he\000Level 1 instruction cache prefetch misses\000legacy-cache-config=3D0x= 10201\000\00010\000\000\000\000\000" +/* offset=3D54143 */ "l1-instruction-speculative-read-miss\000legacy cache= \000Level 1 instruction cache prefetch misses\000legacy-cache-config=3D0x10= 201\000\00010\000\000\000\000\000" +/* offset=3D54271 */ "l1-instruction-speculative-load\000legacy cache\000L= evel 1 instruction cache prefetch accesses\000legacy-cache-config=3D0x201\0= 00\00010\000\000\000\000\000" +/* offset=3D54394 */ "l1-instruction-speculative-load-refs\000legacy cache= \000Level 1 instruction cache prefetch accesses\000legacy-cache-config=3D0x= 201\000\00010\000\000\000\000\000" +/* offset=3D54522 */ "l1-instruction-speculative-load-reference\000legacy = cache\000Level 1 instruction cache prefetch accesses\000legacy-cache-config= =3D0x201\000\00010\000\000\000\000\000" +/* offset=3D54655 */ "l1-instruction-speculative-load-ops\000legacy cache\= 000Level 1 instruction cache prefetch accesses\000legacy-cache-config=3D0x2= 01\000\00010\000\000\000\000\000" +/* offset=3D54782 */ "l1-instruction-speculative-load-access\000legacy cac= he\000Level 1 instruction cache prefetch accesses\000legacy-cache-config=3D= 0x201\000\00010\000\000\000\000\000" +/* offset=3D54912 */ "l1-instruction-speculative-load-misses\000legacy cac= he\000Level 1 instruction cache prefetch misses\000legacy-cache-config=3D0x= 10201\000\00010\000\000\000\000\000" +/* offset=3D55042 */ "l1-instruction-speculative-load-miss\000legacy cache= \000Level 1 instruction cache prefetch misses\000legacy-cache-config=3D0x10= 201\000\00010\000\000\000\000\000" +/* offset=3D55170 */ "l1-instruction-refs\000legacy cache\000Level 1 instr= uction cache read accesses\000legacy-cache-config=3D1\000\00010\000\000\000= \000\000" +/* offset=3D55273 */ "l1-instruction-reference\000legacy cache\000Level 1 = instruction cache read accesses\000legacy-cache-config=3D1\000\00010\000\00= 0\000\000\000" +/* offset=3D55381 */ "l1-instruction-ops\000legacy cache\000Level 1 instru= ction cache read accesses\000legacy-cache-config=3D1\000\00010\000\000\000\= 000\000" +/* offset=3D55483 */ "l1-instruction-access\000legacy cache\000Level 1 ins= truction cache read accesses\000legacy-cache-config=3D1\000\00010\000\000\0= 00\000\000" +/* offset=3D55588 */ "l1-instruction-misses\000legacy cache\000Level 1 ins= truction cache read misses\000legacy-cache-config=3D0x10001\000\00010\000\0= 00\000\000\000" +/* offset=3D55697 */ "l1-instruction-miss\000legacy cache\000Level 1 instr= uction cache read misses\000legacy-cache-config=3D0x10001\000\00010\000\000= \000\000\000" +/* offset=3D55804 */ "llc\000legacy cache\000Last level cache read accesse= s\000legacy-cache-config=3D2\000\00010\000\000\000\000\000" +/* offset=3D55882 */ "llc-load\000legacy cache\000Last level cache read ac= cesses\000legacy-cache-config=3D2\000\00010\000\000\000\000\000" +/* offset=3D55965 */ "llc-load-refs\000legacy cache\000Last level cache re= ad accesses\000legacy-cache-config=3D2\000\00010\000\000\000\000\000" +/* offset=3D56053 */ "llc-load-reference\000legacy cache\000Last level cac= he read accesses\000legacy-cache-config=3D2\000\00010\000\000\000\000\000" +/* offset=3D56146 */ "llc-load-ops\000legacy cache\000Last level cache rea= d accesses\000legacy-cache-config=3D2\000\00010\000\000\000\000\000" +/* offset=3D56233 */ "llc-load-access\000legacy cache\000Last level cache = read accesses\000legacy-cache-config=3D2\000\00010\000\000\000\000\000" +/* offset=3D56323 */ "llc-load-misses\000legacy cache\000Last level cache = read misses\000legacy-cache-config=3D0x10002\000\00000\000\000\000\000\000" +/* offset=3D56417 */ "llc-load-miss\000legacy cache\000Last level cache re= ad misses\000legacy-cache-config=3D0x10002\000\00010\000\000\000\000\000" +/* offset=3D56509 */ "llc-loads\000legacy cache\000Last level cache read a= ccesses\000legacy-cache-config=3D2\000\00000\000\000\000\000\000" +/* offset=3D56593 */ "llc-loads-refs\000legacy cache\000Last level cache r= ead accesses\000legacy-cache-config=3D2\000\00010\000\000\000\000\000" +/* offset=3D56682 */ "llc-loads-reference\000legacy cache\000Last level ca= che read accesses\000legacy-cache-config=3D2\000\00010\000\000\000\000\000" +/* offset=3D56776 */ "llc-loads-ops\000legacy cache\000Last level cache re= ad accesses\000legacy-cache-config=3D2\000\00010\000\000\000\000\000" +/* offset=3D56864 */ "llc-loads-access\000legacy cache\000Last level cache= read accesses\000legacy-cache-config=3D2\000\00010\000\000\000\000\000" +/* offset=3D56955 */ "llc-loads-misses\000legacy cache\000Last level cache= read misses\000legacy-cache-config=3D0x10002\000\00010\000\000\000\000\000" +/* offset=3D57050 */ "llc-loads-miss\000legacy cache\000Last level cache r= ead misses\000legacy-cache-config=3D0x10002\000\00010\000\000\000\000\000" +/* offset=3D57143 */ "llc-read\000legacy cache\000Last level cache read ac= cesses\000legacy-cache-config=3D2\000\00010\000\000\000\000\000" +/* offset=3D57226 */ "llc-read-refs\000legacy cache\000Last level cache re= ad accesses\000legacy-cache-config=3D2\000\00010\000\000\000\000\000" +/* offset=3D57314 */ "llc-read-reference\000legacy cache\000Last level cac= he read accesses\000legacy-cache-config=3D2\000\00010\000\000\000\000\000" +/* offset=3D57407 */ "llc-read-ops\000legacy cache\000Last level cache rea= d accesses\000legacy-cache-config=3D2\000\00010\000\000\000\000\000" +/* offset=3D57494 */ "llc-read-access\000legacy cache\000Last level cache = read accesses\000legacy-cache-config=3D2\000\00010\000\000\000\000\000" +/* offset=3D57584 */ "llc-read-misses\000legacy cache\000Last level cache = read misses\000legacy-cache-config=3D0x10002\000\00010\000\000\000\000\000" +/* offset=3D57678 */ "llc-read-miss\000legacy cache\000Last level cache re= ad misses\000legacy-cache-config=3D0x10002\000\00010\000\000\000\000\000" +/* offset=3D57770 */ "llc-store\000legacy cache\000Last level cache write = accesses\000legacy-cache-config=3D0x102\000\00010\000\000\000\000\000" +/* offset=3D57859 */ "llc-store-refs\000legacy cache\000Last level cache w= rite accesses\000legacy-cache-config=3D0x102\000\00010\000\000\000\000\000" +/* offset=3D57953 */ "llc-store-reference\000legacy cache\000Last level ca= che write accesses\000legacy-cache-config=3D0x102\000\00010\000\000\000\000= \000" +/* offset=3D58052 */ "llc-store-ops\000legacy cache\000Last level cache wr= ite accesses\000legacy-cache-config=3D0x102\000\00010\000\000\000\000\000" +/* offset=3D58145 */ "llc-store-access\000legacy cache\000Last level cache= write accesses\000legacy-cache-config=3D0x102\000\00010\000\000\000\000\00= 0" +/* offset=3D58241 */ "llc-store-misses\000legacy cache\000Last level cache= write misses\000legacy-cache-config=3D0x10102\000\00000\000\000\000\000\00= 0" +/* offset=3D58337 */ "llc-store-miss\000legacy cache\000Last level cache w= rite misses\000legacy-cache-config=3D0x10102\000\00010\000\000\000\000\000" +/* offset=3D58431 */ "llc-stores\000legacy cache\000Last level cache write= accesses\000legacy-cache-config=3D0x102\000\00000\000\000\000\000\000" +/* offset=3D58521 */ "llc-stores-refs\000legacy cache\000Last level cache = write accesses\000legacy-cache-config=3D0x102\000\00010\000\000\000\000\000" +/* offset=3D58616 */ "llc-stores-reference\000legacy cache\000Last level c= ache write accesses\000legacy-cache-config=3D0x102\000\00010\000\000\000\00= 0\000" +/* offset=3D58716 */ "llc-stores-ops\000legacy cache\000Last level cache w= rite accesses\000legacy-cache-config=3D0x102\000\00010\000\000\000\000\000" +/* offset=3D58810 */ "llc-stores-access\000legacy cache\000Last level cach= e write accesses\000legacy-cache-config=3D0x102\000\00010\000\000\000\000\0= 00" +/* offset=3D58907 */ "llc-stores-misses\000legacy cache\000Last level cach= e write misses\000legacy-cache-config=3D0x10102\000\00010\000\000\000\000\0= 00" +/* offset=3D59004 */ "llc-stores-miss\000legacy cache\000Last level cache = write misses\000legacy-cache-config=3D0x10102\000\00010\000\000\000\000\000" +/* offset=3D59099 */ "llc-write\000legacy cache\000Last level cache write = accesses\000legacy-cache-config=3D0x102\000\00010\000\000\000\000\000" +/* offset=3D59188 */ "llc-write-refs\000legacy cache\000Last level cache w= rite accesses\000legacy-cache-config=3D0x102\000\00010\000\000\000\000\000" +/* offset=3D59282 */ "llc-write-reference\000legacy cache\000Last level ca= che write accesses\000legacy-cache-config=3D0x102\000\00010\000\000\000\000= \000" +/* offset=3D59381 */ "llc-write-ops\000legacy cache\000Last level cache wr= ite accesses\000legacy-cache-config=3D0x102\000\00010\000\000\000\000\000" +/* offset=3D59474 */ "llc-write-access\000legacy cache\000Last level cache= write accesses\000legacy-cache-config=3D0x102\000\00010\000\000\000\000\00= 0" +/* offset=3D59570 */ "llc-write-misses\000legacy cache\000Last level cache= write misses\000legacy-cache-config=3D0x10102\000\00010\000\000\000\000\00= 0" +/* offset=3D59666 */ "llc-write-miss\000legacy cache\000Last level cache w= rite misses\000legacy-cache-config=3D0x10102\000\00010\000\000\000\000\000" +/* offset=3D59760 */ "llc-prefetch\000legacy cache\000Last level cache pre= fetch accesses\000legacy-cache-config=3D0x202\000\00010\000\000\000\000\000" +/* offset=3D59855 */ "llc-prefetch-refs\000legacy cache\000Last level cach= e prefetch accesses\000legacy-cache-config=3D0x202\000\00010\000\000\000\00= 0\000" +/* offset=3D59955 */ "llc-prefetch-reference\000legacy cache\000Last level= cache prefetch accesses\000legacy-cache-config=3D0x202\000\00010\000\000\0= 00\000\000" +/* offset=3D60060 */ "llc-prefetch-ops\000legacy cache\000Last level cache= prefetch accesses\000legacy-cache-config=3D0x202\000\00010\000\000\000\000= \000" +/* offset=3D60159 */ "llc-prefetch-access\000legacy cache\000Last level ca= che prefetch accesses\000legacy-cache-config=3D0x202\000\00010\000\000\000\= 000\000" +/* offset=3D60261 */ "llc-prefetch-misses\000legacy cache\000Last level ca= che prefetch misses\000legacy-cache-config=3D0x10202\000\00000\000\000\000\= 000\000" +/* offset=3D60363 */ "llc-prefetch-miss\000legacy cache\000Last level cach= e prefetch misses\000legacy-cache-config=3D0x10202\000\00010\000\000\000\00= 0\000" +/* offset=3D60463 */ "llc-prefetches\000legacy cache\000Last level cache p= refetch accesses\000legacy-cache-config=3D0x202\000\00000\000\000\000\000\0= 00" +/* offset=3D60560 */ "llc-prefetches-refs\000legacy cache\000Last level ca= che prefetch accesses\000legacy-cache-config=3D0x202\000\00010\000\000\000\= 000\000" +/* offset=3D60662 */ "llc-prefetches-reference\000legacy cache\000Last lev= el cache prefetch accesses\000legacy-cache-config=3D0x202\000\00010\000\000= \000\000\000" +/* offset=3D60769 */ "llc-prefetches-ops\000legacy cache\000Last level cac= he prefetch accesses\000legacy-cache-config=3D0x202\000\00010\000\000\000\0= 00\000" +/* offset=3D60870 */ "llc-prefetches-access\000legacy cache\000Last level = cache prefetch accesses\000legacy-cache-config=3D0x202\000\00010\000\000\00= 0\000\000" +/* offset=3D60974 */ "llc-prefetches-misses\000legacy cache\000Last level = cache prefetch misses\000legacy-cache-config=3D0x10202\000\00010\000\000\00= 0\000\000" +/* offset=3D61078 */ "llc-prefetches-miss\000legacy cache\000Last level ca= che prefetch misses\000legacy-cache-config=3D0x10202\000\00010\000\000\000\= 000\000" +/* offset=3D61180 */ "llc-speculative-read\000legacy cache\000Last level c= ache prefetch accesses\000legacy-cache-config=3D0x202\000\00010\000\000\000= \000\000" +/* offset=3D61283 */ "llc-speculative-read-refs\000legacy cache\000Last le= vel cache prefetch accesses\000legacy-cache-config=3D0x202\000\00010\000\00= 0\000\000\000" +/* offset=3D61391 */ "llc-speculative-read-reference\000legacy cache\000La= st level cache prefetch accesses\000legacy-cache-config=3D0x202\000\00010\0= 00\000\000\000\000" +/* offset=3D61504 */ "llc-speculative-read-ops\000legacy cache\000Last lev= el cache prefetch accesses\000legacy-cache-config=3D0x202\000\00010\000\000= \000\000\000" +/* offset=3D61611 */ "llc-speculative-read-access\000legacy cache\000Last = level cache prefetch accesses\000legacy-cache-config=3D0x202\000\00010\000\= 000\000\000\000" +/* offset=3D61721 */ "llc-speculative-read-misses\000legacy cache\000Last = level cache prefetch misses\000legacy-cache-config=3D0x10202\000\00010\000\= 000\000\000\000" +/* offset=3D61831 */ "llc-speculative-read-miss\000legacy cache\000Last le= vel cache prefetch misses\000legacy-cache-config=3D0x10202\000\00010\000\00= 0\000\000\000" +/* offset=3D61939 */ "llc-speculative-load\000legacy cache\000Last level c= ache prefetch accesses\000legacy-cache-config=3D0x202\000\00010\000\000\000= \000\000" +/* offset=3D62042 */ "llc-speculative-load-refs\000legacy cache\000Last le= vel cache prefetch accesses\000legacy-cache-config=3D0x202\000\00010\000\00= 0\000\000\000" +/* offset=3D62150 */ "llc-speculative-load-reference\000legacy cache\000La= st level cache prefetch accesses\000legacy-cache-config=3D0x202\000\00010\0= 00\000\000\000\000" +/* offset=3D62263 */ "llc-speculative-load-ops\000legacy cache\000Last lev= el cache prefetch accesses\000legacy-cache-config=3D0x202\000\00010\000\000= \000\000\000" +/* offset=3D62370 */ "llc-speculative-load-access\000legacy cache\000Last = level cache prefetch accesses\000legacy-cache-config=3D0x202\000\00010\000\= 000\000\000\000" +/* offset=3D62480 */ "llc-speculative-load-misses\000legacy cache\000Last = level cache prefetch misses\000legacy-cache-config=3D0x10202\000\00010\000\= 000\000\000\000" +/* offset=3D62590 */ "llc-speculative-load-miss\000legacy cache\000Last le= vel cache prefetch misses\000legacy-cache-config=3D0x10202\000\00010\000\00= 0\000\000\000" +/* offset=3D62698 */ "llc-refs\000legacy cache\000Last level cache read ac= cesses\000legacy-cache-config=3D2\000\00010\000\000\000\000\000" +/* offset=3D62781 */ "llc-reference\000legacy cache\000Last level cache re= ad accesses\000legacy-cache-config=3D2\000\00010\000\000\000\000\000" +/* offset=3D62869 */ "llc-ops\000legacy cache\000Last level cache read acc= esses\000legacy-cache-config=3D2\000\00010\000\000\000\000\000" +/* offset=3D62951 */ "llc-access\000legacy cache\000Last level cache read = accesses\000legacy-cache-config=3D2\000\00010\000\000\000\000\000" +/* offset=3D63036 */ "llc-misses\000legacy cache\000Last level cache read = misses\000legacy-cache-config=3D0x10002\000\00010\000\000\000\000\000" +/* offset=3D63125 */ "llc-miss\000legacy cache\000Last level cache read mi= sses\000legacy-cache-config=3D0x10002\000\00010\000\000\000\000\000" +/* offset=3D63212 */ "l2\000legacy cache\000Level 2 (or higher) last level= cache read accesses\000legacy-cache-config=3D2\000\00010\000\000\000\000\0= 00" +/* offset=3D63309 */ "l2-load\000legacy cache\000Level 2 (or higher) last = level cache read accesses\000legacy-cache-config=3D2\000\00010\000\000\000\= 000\000" +/* offset=3D63411 */ "l2-load-refs\000legacy cache\000Level 2 (or higher) = last level cache read accesses\000legacy-cache-config=3D2\000\00010\000\000= \000\000\000" +/* offset=3D63518 */ "l2-load-reference\000legacy cache\000Level 2 (or hig= her) last level cache read accesses\000legacy-cache-config=3D2\000\00010\00= 0\000\000\000\000" +/* offset=3D63630 */ "l2-load-ops\000legacy cache\000Level 2 (or higher) l= ast level cache read accesses\000legacy-cache-config=3D2\000\00010\000\000\= 000\000\000" +/* offset=3D63736 */ "l2-load-access\000legacy cache\000Level 2 (or higher= ) last level cache read accesses\000legacy-cache-config=3D2\000\00010\000\0= 00\000\000\000" +/* offset=3D63845 */ "l2-load-misses\000legacy cache\000Level 2 (or higher= ) last level cache read misses\000legacy-cache-config=3D0x10002\000\00010\0= 00\000\000\000\000" +/* offset=3D63958 */ "l2-load-miss\000legacy cache\000Level 2 (or higher) = last level cache read misses\000legacy-cache-config=3D0x10002\000\00010\000= \000\000\000\000" +/* offset=3D64069 */ "l2-loads\000legacy cache\000Level 2 (or higher) last= level cache read accesses\000legacy-cache-config=3D2\000\00010\000\000\000= \000\000" +/* offset=3D64172 */ "l2-loads-refs\000legacy cache\000Level 2 (or higher)= last level cache read accesses\000legacy-cache-config=3D2\000\00010\000\00= 0\000\000\000" +/* offset=3D64280 */ "l2-loads-reference\000legacy cache\000Level 2 (or hi= gher) last level cache read accesses\000legacy-cache-config=3D2\000\00010\0= 00\000\000\000\000" +/* offset=3D64393 */ "l2-loads-ops\000legacy cache\000Level 2 (or higher) = last level cache read accesses\000legacy-cache-config=3D2\000\00010\000\000= \000\000\000" +/* offset=3D64500 */ "l2-loads-access\000legacy cache\000Level 2 (or highe= r) last level cache read accesses\000legacy-cache-config=3D2\000\00010\000\= 000\000\000\000" +/* offset=3D64610 */ "l2-loads-misses\000legacy cache\000Level 2 (or highe= r) last level cache read misses\000legacy-cache-config=3D0x10002\000\00010\= 000\000\000\000\000" +/* offset=3D64724 */ "l2-loads-miss\000legacy cache\000Level 2 (or higher)= last level cache read misses\000legacy-cache-config=3D0x10002\000\00010\00= 0\000\000\000\000" +/* offset=3D64836 */ "l2-read\000legacy cache\000Level 2 (or higher) last = level cache read accesses\000legacy-cache-config=3D2\000\00010\000\000\000\= 000\000" +/* offset=3D64938 */ "l2-read-refs\000legacy cache\000Level 2 (or higher) = last level cache read accesses\000legacy-cache-config=3D2\000\00010\000\000= \000\000\000" +/* offset=3D65045 */ "l2-read-reference\000legacy cache\000Level 2 (or hig= her) last level cache read accesses\000legacy-cache-config=3D2\000\00010\00= 0\000\000\000\000" +/* offset=3D65157 */ "l2-read-ops\000legacy cache\000Level 2 (or higher) l= ast level cache read accesses\000legacy-cache-config=3D2\000\00010\000\000\= 000\000\000" +/* offset=3D65263 */ "l2-read-access\000legacy cache\000Level 2 (or higher= ) last level cache read accesses\000legacy-cache-config=3D2\000\00010\000\0= 00\000\000\000" +/* offset=3D65372 */ "l2-read-misses\000legacy cache\000Level 2 (or higher= ) last level cache read misses\000legacy-cache-config=3D0x10002\000\00010\0= 00\000\000\000\000" +/* offset=3D65485 */ "l2-read-miss\000legacy cache\000Level 2 (or higher) = last level cache read misses\000legacy-cache-config=3D0x10002\000\00010\000= \000\000\000\000" +/* offset=3D65596 */ "l2-store\000legacy cache\000Level 2 (or higher) last= level cache write accesses\000legacy-cache-config=3D0x102\000\00010\000\00= 0\000\000\000" +/* offset=3D65704 */ "l2-store-refs\000legacy cache\000Level 2 (or higher)= last level cache write accesses\000legacy-cache-config=3D0x102\000\00010\0= 00\000\000\000\000" +/* offset=3D65817 */ "l2-store-reference\000legacy cache\000Level 2 (or hi= gher) last level cache write accesses\000legacy-cache-config=3D0x102\000\00= 010\000\000\000\000\000" +/* offset=3D65935 */ "l2-store-ops\000legacy cache\000Level 2 (or higher) = last level cache write accesses\000legacy-cache-config=3D0x102\000\00010\00= 0\000\000\000\000" +/* offset=3D66047 */ "l2-store-access\000legacy cache\000Level 2 (or highe= r) last level cache write accesses\000legacy-cache-config=3D0x102\000\00010= \000\000\000\000\000" +/* offset=3D66162 */ "l2-store-misses\000legacy cache\000Level 2 (or highe= r) last level cache write misses\000legacy-cache-config=3D0x10102\000\00010= \000\000\000\000\000" +/* offset=3D66277 */ "l2-store-miss\000legacy cache\000Level 2 (or higher)= last level cache write misses\000legacy-cache-config=3D0x10102\000\00010\0= 00\000\000\000\000" +/* offset=3D66390 */ "l2-stores\000legacy cache\000Level 2 (or higher) las= t level cache write accesses\000legacy-cache-config=3D0x102\000\00010\000\0= 00\000\000\000" +/* offset=3D66499 */ "l2-stores-refs\000legacy cache\000Level 2 (or higher= ) last level cache write accesses\000legacy-cache-config=3D0x102\000\00010\= 000\000\000\000\000" +/* offset=3D66613 */ "l2-stores-reference\000legacy cache\000Level 2 (or h= igher) last level cache write accesses\000legacy-cache-config=3D0x102\000\0= 0010\000\000\000\000\000" +/* offset=3D66732 */ "l2-stores-ops\000legacy cache\000Level 2 (or higher)= last level cache write accesses\000legacy-cache-config=3D0x102\000\00010\0= 00\000\000\000\000" +/* offset=3D66845 */ "l2-stores-access\000legacy cache\000Level 2 (or high= er) last level cache write accesses\000legacy-cache-config=3D0x102\000\0001= 0\000\000\000\000\000" +/* offset=3D66961 */ "l2-stores-misses\000legacy cache\000Level 2 (or high= er) last level cache write misses\000legacy-cache-config=3D0x10102\000\0001= 0\000\000\000\000\000" +/* offset=3D67077 */ "l2-stores-miss\000legacy cache\000Level 2 (or higher= ) last level cache write misses\000legacy-cache-config=3D0x10102\000\00010\= 000\000\000\000\000" +/* offset=3D67191 */ "l2-write\000legacy cache\000Level 2 (or higher) last= level cache write accesses\000legacy-cache-config=3D0x102\000\00010\000\00= 0\000\000\000" +/* offset=3D67299 */ "l2-write-refs\000legacy cache\000Level 2 (or higher)= last level cache write accesses\000legacy-cache-config=3D0x102\000\00010\0= 00\000\000\000\000" +/* offset=3D67412 */ "l2-write-reference\000legacy cache\000Level 2 (or hi= gher) last level cache write accesses\000legacy-cache-config=3D0x102\000\00= 010\000\000\000\000\000" +/* offset=3D67530 */ "l2-write-ops\000legacy cache\000Level 2 (or higher) = last level cache write accesses\000legacy-cache-config=3D0x102\000\00010\00= 0\000\000\000\000" +/* offset=3D67642 */ "l2-write-access\000legacy cache\000Level 2 (or highe= r) last level cache write accesses\000legacy-cache-config=3D0x102\000\00010= \000\000\000\000\000" +/* offset=3D67757 */ "l2-write-misses\000legacy cache\000Level 2 (or highe= r) last level cache write misses\000legacy-cache-config=3D0x10102\000\00010= \000\000\000\000\000" +/* offset=3D67872 */ "l2-write-miss\000legacy cache\000Level 2 (or higher)= last level cache write misses\000legacy-cache-config=3D0x10102\000\00010\0= 00\000\000\000\000" +/* offset=3D67985 */ "l2-prefetch\000legacy cache\000Level 2 (or higher) l= ast level cache prefetch accesses\000legacy-cache-config=3D0x202\000\00010\= 000\000\000\000\000" +/* offset=3D68099 */ "l2-prefetch-refs\000legacy cache\000Level 2 (or high= er) last level cache prefetch accesses\000legacy-cache-config=3D0x202\000\0= 0010\000\000\000\000\000" +/* offset=3D68218 */ "l2-prefetch-reference\000legacy cache\000Level 2 (or= higher) last level cache prefetch accesses\000legacy-cache-config=3D0x202\= 000\00010\000\000\000\000\000" +/* offset=3D68342 */ "l2-prefetch-ops\000legacy cache\000Level 2 (or highe= r) last level cache prefetch accesses\000legacy-cache-config=3D0x202\000\00= 010\000\000\000\000\000" +/* offset=3D68460 */ "l2-prefetch-access\000legacy cache\000Level 2 (or hi= gher) last level cache prefetch accesses\000legacy-cache-config=3D0x202\000= \00010\000\000\000\000\000" +/* offset=3D68581 */ "l2-prefetch-misses\000legacy cache\000Level 2 (or hi= gher) last level cache prefetch misses\000legacy-cache-config=3D0x10202\000= \00010\000\000\000\000\000" +/* offset=3D68702 */ "l2-prefetch-miss\000legacy cache\000Level 2 (or high= er) last level cache prefetch misses\000legacy-cache-config=3D0x10202\000\0= 0010\000\000\000\000\000" +/* offset=3D68821 */ "l2-prefetches\000legacy cache\000Level 2 (or higher)= last level cache prefetch accesses\000legacy-cache-config=3D0x202\000\0001= 0\000\000\000\000\000" +/* offset=3D68937 */ "l2-prefetches-refs\000legacy cache\000Level 2 (or hi= gher) last level cache prefetch accesses\000legacy-cache-config=3D0x202\000= \00010\000\000\000\000\000" +/* offset=3D69058 */ "l2-prefetches-reference\000legacy cache\000Level 2 (= or higher) last level cache prefetch accesses\000legacy-cache-config=3D0x20= 2\000\00010\000\000\000\000\000" +/* offset=3D69184 */ "l2-prefetches-ops\000legacy cache\000Level 2 (or hig= her) last level cache prefetch accesses\000legacy-cache-config=3D0x202\000\= 00010\000\000\000\000\000" +/* offset=3D69304 */ "l2-prefetches-access\000legacy cache\000Level 2 (or = higher) last level cache prefetch accesses\000legacy-cache-config=3D0x202\0= 00\00010\000\000\000\000\000" +/* offset=3D69427 */ "l2-prefetches-misses\000legacy cache\000Level 2 (or = higher) last level cache prefetch misses\000legacy-cache-config=3D0x10202\0= 00\00010\000\000\000\000\000" +/* offset=3D69550 */ "l2-prefetches-miss\000legacy cache\000Level 2 (or hi= gher) last level cache prefetch misses\000legacy-cache-config=3D0x10202\000= \00010\000\000\000\000\000" +/* offset=3D69671 */ "l2-speculative-read\000legacy cache\000Level 2 (or h= igher) last level cache prefetch accesses\000legacy-cache-config=3D0x202\00= 0\00010\000\000\000\000\000" +/* offset=3D69793 */ "l2-speculative-read-refs\000legacy cache\000Level 2 = (or higher) last level cache prefetch accesses\000legacy-cache-config=3D0x2= 02\000\00010\000\000\000\000\000" +/* offset=3D69920 */ "l2-speculative-read-reference\000legacy cache\000Lev= el 2 (or higher) last level cache prefetch accesses\000legacy-cache-config= =3D0x202\000\00010\000\000\000\000\000" +/* offset=3D70052 */ "l2-speculative-read-ops\000legacy cache\000Level 2 (= or higher) last level cache prefetch accesses\000legacy-cache-config=3D0x20= 2\000\00010\000\000\000\000\000" +/* offset=3D70178 */ "l2-speculative-read-access\000legacy cache\000Level = 2 (or higher) last level cache prefetch accesses\000legacy-cache-config=3D0= x202\000\00010\000\000\000\000\000" +/* offset=3D70307 */ "l2-speculative-read-misses\000legacy cache\000Level = 2 (or higher) last level cache prefetch misses\000legacy-cache-config=3D0x1= 0202\000\00010\000\000\000\000\000" +/* offset=3D70436 */ "l2-speculative-read-miss\000legacy cache\000Level 2 = (or higher) last level cache prefetch misses\000legacy-cache-config=3D0x102= 02\000\00010\000\000\000\000\000" +/* offset=3D70563 */ "l2-speculative-load\000legacy cache\000Level 2 (or h= igher) last level cache prefetch accesses\000legacy-cache-config=3D0x202\00= 0\00010\000\000\000\000\000" +/* offset=3D70685 */ "l2-speculative-load-refs\000legacy cache\000Level 2 = (or higher) last level cache prefetch accesses\000legacy-cache-config=3D0x2= 02\000\00010\000\000\000\000\000" +/* offset=3D70812 */ "l2-speculative-load-reference\000legacy cache\000Lev= el 2 (or higher) last level cache prefetch accesses\000legacy-cache-config= =3D0x202\000\00010\000\000\000\000\000" +/* offset=3D70944 */ "l2-speculative-load-ops\000legacy cache\000Level 2 (= or higher) last level cache prefetch accesses\000legacy-cache-config=3D0x20= 2\000\00010\000\000\000\000\000" +/* offset=3D71070 */ "l2-speculative-load-access\000legacy cache\000Level = 2 (or higher) last level cache prefetch accesses\000legacy-cache-config=3D0= x202\000\00010\000\000\000\000\000" +/* offset=3D71199 */ "l2-speculative-load-misses\000legacy cache\000Level = 2 (or higher) last level cache prefetch misses\000legacy-cache-config=3D0x1= 0202\000\00010\000\000\000\000\000" +/* offset=3D71328 */ "l2-speculative-load-miss\000legacy cache\000Level 2 = (or higher) last level cache prefetch misses\000legacy-cache-config=3D0x102= 02\000\00010\000\000\000\000\000" +/* offset=3D71455 */ "l2-refs\000legacy cache\000Level 2 (or higher) last = level cache read accesses\000legacy-cache-config=3D2\000\00010\000\000\000\= 000\000" +/* offset=3D71557 */ "l2-reference\000legacy cache\000Level 2 (or higher) = last level cache read accesses\000legacy-cache-config=3D2\000\00010\000\000= \000\000\000" +/* offset=3D71664 */ "l2-ops\000legacy cache\000Level 2 (or higher) last l= evel cache read accesses\000legacy-cache-config=3D2\000\00010\000\000\000\0= 00\000" +/* offset=3D71765 */ "l2-access\000legacy cache\000Level 2 (or higher) las= t level cache read accesses\000legacy-cache-config=3D2\000\00010\000\000\00= 0\000\000" +/* offset=3D71869 */ "l2-misses\000legacy cache\000Level 2 (or higher) las= t level cache read misses\000legacy-cache-config=3D0x10002\000\00010\000\00= 0\000\000\000" +/* offset=3D71977 */ "l2-miss\000legacy cache\000Level 2 (or higher) last = level cache read misses\000legacy-cache-config=3D0x10002\000\00010\000\000\= 000\000\000" +/* offset=3D72083 */ "dtlb\000legacy cache\000Data TLB read accesses\000le= gacy-cache-config=3D3\000\00010\000\000\000\000\000" +/* offset=3D72154 */ "dtlb-load\000legacy cache\000Data TLB read accesses\= 000legacy-cache-config=3D3\000\00010\000\000\000\000\000" +/* offset=3D72230 */ "dtlb-load-refs\000legacy cache\000Data TLB read acce= sses\000legacy-cache-config=3D3\000\00010\000\000\000\000\000" +/* offset=3D72311 */ "dtlb-load-reference\000legacy cache\000Data TLB read= accesses\000legacy-cache-config=3D3\000\00010\000\000\000\000\000" +/* offset=3D72397 */ "dtlb-load-ops\000legacy cache\000Data TLB read acces= ses\000legacy-cache-config=3D3\000\00010\000\000\000\000\000" +/* offset=3D72477 */ "dtlb-load-access\000legacy cache\000Data TLB read ac= cesses\000legacy-cache-config=3D3\000\00010\000\000\000\000\000" +/* offset=3D72560 */ "dtlb-load-misses\000legacy cache\000Data TLB read mi= sses\000legacy-cache-config=3D0x10003\000\00000\000\000\000\000\000" +/* offset=3D72647 */ "dtlb-load-miss\000legacy cache\000Data TLB read miss= es\000legacy-cache-config=3D0x10003\000\00010\000\000\000\000\000" +/* offset=3D72732 */ "dtlb-loads\000legacy cache\000Data TLB read accesses= \000legacy-cache-config=3D3\000\00000\000\000\000\000\000" +/* offset=3D72809 */ "dtlb-loads-refs\000legacy cache\000Data TLB read acc= esses\000legacy-cache-config=3D3\000\00010\000\000\000\000\000" +/* offset=3D72891 */ "dtlb-loads-reference\000legacy cache\000Data TLB rea= d accesses\000legacy-cache-config=3D3\000\00010\000\000\000\000\000" +/* offset=3D72978 */ "dtlb-loads-ops\000legacy cache\000Data TLB read acce= sses\000legacy-cache-config=3D3\000\00010\000\000\000\000\000" +/* offset=3D73059 */ "dtlb-loads-access\000legacy cache\000Data TLB read a= ccesses\000legacy-cache-config=3D3\000\00010\000\000\000\000\000" +/* offset=3D73143 */ "dtlb-loads-misses\000legacy cache\000Data TLB read m= isses\000legacy-cache-config=3D0x10003\000\00010\000\000\000\000\000" +/* offset=3D73231 */ "dtlb-loads-miss\000legacy cache\000Data TLB read mis= ses\000legacy-cache-config=3D0x10003\000\00010\000\000\000\000\000" +/* offset=3D73317 */ "dtlb-read\000legacy cache\000Data TLB read accesses\= 000legacy-cache-config=3D3\000\00010\000\000\000\000\000" +/* offset=3D73393 */ "dtlb-read-refs\000legacy cache\000Data TLB read acce= sses\000legacy-cache-config=3D3\000\00010\000\000\000\000\000" +/* offset=3D73474 */ "dtlb-read-reference\000legacy cache\000Data TLB read= accesses\000legacy-cache-config=3D3\000\00010\000\000\000\000\000" +/* offset=3D73560 */ "dtlb-read-ops\000legacy cache\000Data TLB read acces= ses\000legacy-cache-config=3D3\000\00010\000\000\000\000\000" +/* offset=3D73640 */ "dtlb-read-access\000legacy cache\000Data TLB read ac= cesses\000legacy-cache-config=3D3\000\00010\000\000\000\000\000" +/* offset=3D73723 */ "dtlb-read-misses\000legacy cache\000Data TLB read mi= sses\000legacy-cache-config=3D0x10003\000\00010\000\000\000\000\000" +/* offset=3D73810 */ "dtlb-read-miss\000legacy cache\000Data TLB read miss= es\000legacy-cache-config=3D0x10003\000\00010\000\000\000\000\000" +/* offset=3D73895 */ "dtlb-store\000legacy cache\000Data TLB write accesse= s\000legacy-cache-config=3D0x103\000\00010\000\000\000\000\000" +/* offset=3D73977 */ "dtlb-store-refs\000legacy cache\000Data TLB write ac= cesses\000legacy-cache-config=3D0x103\000\00010\000\000\000\000\000" +/* offset=3D74064 */ "dtlb-store-reference\000legacy cache\000Data TLB wri= te accesses\000legacy-cache-config=3D0x103\000\00010\000\000\000\000\000" +/* offset=3D74156 */ "dtlb-store-ops\000legacy cache\000Data TLB write acc= esses\000legacy-cache-config=3D0x103\000\00010\000\000\000\000\000" +/* offset=3D74242 */ "dtlb-store-access\000legacy cache\000Data TLB write = accesses\000legacy-cache-config=3D0x103\000\00010\000\000\000\000\000" +/* offset=3D74331 */ "dtlb-store-misses\000legacy cache\000Data TLB write = misses\000legacy-cache-config=3D0x10103\000\00000\000\000\000\000\000" +/* offset=3D74420 */ "dtlb-store-miss\000legacy cache\000Data TLB write mi= sses\000legacy-cache-config=3D0x10103\000\00010\000\000\000\000\000" +/* offset=3D74507 */ "dtlb-stores\000legacy cache\000Data TLB write access= es\000legacy-cache-config=3D0x103\000\00000\000\000\000\000\000" +/* offset=3D74590 */ "dtlb-stores-refs\000legacy cache\000Data TLB write a= ccesses\000legacy-cache-config=3D0x103\000\00010\000\000\000\000\000" +/* offset=3D74678 */ "dtlb-stores-reference\000legacy cache\000Data TLB wr= ite accesses\000legacy-cache-config=3D0x103\000\00010\000\000\000\000\000" +/* offset=3D74771 */ "dtlb-stores-ops\000legacy cache\000Data TLB write ac= cesses\000legacy-cache-config=3D0x103\000\00010\000\000\000\000\000" +/* offset=3D74858 */ "dtlb-stores-access\000legacy cache\000Data TLB write= accesses\000legacy-cache-config=3D0x103\000\00010\000\000\000\000\000" +/* offset=3D74948 */ "dtlb-stores-misses\000legacy cache\000Data TLB write= misses\000legacy-cache-config=3D0x10103\000\00010\000\000\000\000\000" +/* offset=3D75038 */ "dtlb-stores-miss\000legacy cache\000Data TLB write m= isses\000legacy-cache-config=3D0x10103\000\00010\000\000\000\000\000" +/* offset=3D75126 */ "dtlb-write\000legacy cache\000Data TLB write accesse= s\000legacy-cache-config=3D0x103\000\00010\000\000\000\000\000" +/* offset=3D75208 */ "dtlb-write-refs\000legacy cache\000Data TLB write ac= cesses\000legacy-cache-config=3D0x103\000\00010\000\000\000\000\000" +/* offset=3D75295 */ "dtlb-write-reference\000legacy cache\000Data TLB wri= te accesses\000legacy-cache-config=3D0x103\000\00010\000\000\000\000\000" +/* offset=3D75387 */ "dtlb-write-ops\000legacy cache\000Data TLB write acc= esses\000legacy-cache-config=3D0x103\000\00010\000\000\000\000\000" +/* offset=3D75473 */ "dtlb-write-access\000legacy cache\000Data TLB write = accesses\000legacy-cache-config=3D0x103\000\00010\000\000\000\000\000" +/* offset=3D75562 */ "dtlb-write-misses\000legacy cache\000Data TLB write = misses\000legacy-cache-config=3D0x10103\000\00010\000\000\000\000\000" +/* offset=3D75651 */ "dtlb-write-miss\000legacy cache\000Data TLB write mi= sses\000legacy-cache-config=3D0x10103\000\00010\000\000\000\000\000" +/* offset=3D75738 */ "dtlb-prefetch\000legacy cache\000Data TLB prefetch a= ccesses\000legacy-cache-config=3D0x203\000\00010\000\000\000\000\000" +/* offset=3D75826 */ "dtlb-prefetch-refs\000legacy cache\000Data TLB prefe= tch accesses\000legacy-cache-config=3D0x203\000\00010\000\000\000\000\000" +/* offset=3D75919 */ "dtlb-prefetch-reference\000legacy cache\000Data TLB = prefetch accesses\000legacy-cache-config=3D0x203\000\00010\000\000\000\000\= 000" +/* offset=3D76017 */ "dtlb-prefetch-ops\000legacy cache\000Data TLB prefet= ch accesses\000legacy-cache-config=3D0x203\000\00010\000\000\000\000\000" +/* offset=3D76109 */ "dtlb-prefetch-access\000legacy cache\000Data TLB pre= fetch accesses\000legacy-cache-config=3D0x203\000\00010\000\000\000\000\000" +/* offset=3D76204 */ "dtlb-prefetch-misses\000legacy cache\000Data TLB pre= fetch misses\000legacy-cache-config=3D0x10203\000\00000\000\000\000\000\000" +/* offset=3D76299 */ "dtlb-prefetch-miss\000legacy cache\000Data TLB prefe= tch misses\000legacy-cache-config=3D0x10203\000\00010\000\000\000\000\000" +/* offset=3D76392 */ "dtlb-prefetches\000legacy cache\000Data TLB prefetch= accesses\000legacy-cache-config=3D0x203\000\00000\000\000\000\000\000" +/* offset=3D76482 */ "dtlb-prefetches-refs\000legacy cache\000Data TLB pre= fetch accesses\000legacy-cache-config=3D0x203\000\00010\000\000\000\000\000" +/* offset=3D76577 */ "dtlb-prefetches-reference\000legacy cache\000Data TL= B prefetch accesses\000legacy-cache-config=3D0x203\000\00010\000\000\000\00= 0\000" +/* offset=3D76677 */ "dtlb-prefetches-ops\000legacy cache\000Data TLB pref= etch accesses\000legacy-cache-config=3D0x203\000\00010\000\000\000\000\000" +/* offset=3D76771 */ "dtlb-prefetches-access\000legacy cache\000Data TLB p= refetch accesses\000legacy-cache-config=3D0x203\000\00010\000\000\000\000\0= 00" +/* offset=3D76868 */ "dtlb-prefetches-misses\000legacy cache\000Data TLB p= refetch misses\000legacy-cache-config=3D0x10203\000\00010\000\000\000\000\0= 00" +/* offset=3D76965 */ "dtlb-prefetches-miss\000legacy cache\000Data TLB pre= fetch misses\000legacy-cache-config=3D0x10203\000\00010\000\000\000\000\000" +/* offset=3D77060 */ "dtlb-speculative-read\000legacy cache\000Data TLB pr= efetch accesses\000legacy-cache-config=3D0x203\000\00010\000\000\000\000\00= 0" +/* offset=3D77156 */ "dtlb-speculative-read-refs\000legacy cache\000Data T= LB prefetch accesses\000legacy-cache-config=3D0x203\000\00010\000\000\000\0= 00\000" +/* offset=3D77257 */ "dtlb-speculative-read-reference\000legacy cache\000D= ata TLB prefetch accesses\000legacy-cache-config=3D0x203\000\00010\000\000\= 000\000\000" +/* offset=3D77363 */ "dtlb-speculative-read-ops\000legacy cache\000Data TL= B prefetch accesses\000legacy-cache-config=3D0x203\000\00010\000\000\000\00= 0\000" +/* offset=3D77463 */ "dtlb-speculative-read-access\000legacy cache\000Data= TLB prefetch accesses\000legacy-cache-config=3D0x203\000\00010\000\000\000= \000\000" +/* offset=3D77566 */ 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s\000legacy-cache-config=3D3\000\00010\000\000\000\000\000" +/* offset=3D78790 */ "dtlb-misses\000legacy cache\000Data TLB read misses\= 000legacy-cache-config=3D0x10003\000\00010\000\000\000\000\000" +/* offset=3D78872 */ "dtlb-miss\000legacy cache\000Data TLB read misses\00= 0legacy-cache-config=3D0x10003\000\00010\000\000\000\000\000" +/* offset=3D78952 */ "d-tlb\000legacy cache\000Data TLB read accesses\000l= egacy-cache-config=3D3\000\00010\000\000\000\000\000" +/* offset=3D79024 */ "d-tlb-load\000legacy cache\000Data TLB read accesses= \000legacy-cache-config=3D3\000\00010\000\000\000\000\000" +/* offset=3D79101 */ "d-tlb-load-refs\000legacy cache\000Data TLB read acc= esses\000legacy-cache-config=3D3\000\00010\000\000\000\000\000" +/* offset=3D79183 */ "d-tlb-load-reference\000legacy cache\000Data TLB rea= d accesses\000legacy-cache-config=3D3\000\00010\000\000\000\000\000" +/* offset=3D79270 */ "d-tlb-load-ops\000legacy cache\000Data TLB read acce= sses\000legacy-cache-config=3D3\000\00010\000\000\000\000\000" +/* offset=3D79351 */ "d-tlb-load-access\000legacy cache\000Data TLB read a= ccesses\000legacy-cache-config=3D3\000\00010\000\000\000\000\000" +/* offset=3D79435 */ "d-tlb-load-misses\000legacy cache\000Data TLB read m= isses\000legacy-cache-config=3D0x10003\000\00010\000\000\000\000\000" +/* offset=3D79523 */ "d-tlb-load-miss\000legacy cache\000Data TLB read mis= ses\000legacy-cache-config=3D0x10003\000\00010\000\000\000\000\000" +/* offset=3D79609 */ "d-tlb-loads\000legacy cache\000Data TLB read accesse= s\000legacy-cache-config=3D3\000\00010\000\000\000\000\000" +/* offset=3D79687 */ "d-tlb-loads-refs\000legacy cache\000Data TLB read ac= cesses\000legacy-cache-config=3D3\000\00010\000\000\000\000\000" +/* offset=3D79770 */ "d-tlb-loads-reference\000legacy cache\000Data TLB re= ad accesses\000legacy-cache-config=3D3\000\00010\000\000\000\000\000" +/* offset=3D79858 */ "d-tlb-loads-ops\000legacy cache\000Data TLB read acc= esses\000legacy-cache-config=3D3\000\00010\000\000\000\000\000" +/* offset=3D79940 */ "d-tlb-loads-access\000legacy cache\000Data TLB read = accesses\000legacy-cache-config=3D3\000\00010\000\000\000\000\000" +/* offset=3D80025 */ "d-tlb-loads-misses\000legacy cache\000Data TLB read = misses\000legacy-cache-config=3D0x10003\000\00010\000\000\000\000\000" +/* offset=3D80114 */ "d-tlb-loads-miss\000legacy cache\000Data TLB read mi= sses\000legacy-cache-config=3D0x10003\000\00010\000\000\000\000\000" +/* offset=3D80201 */ "d-tlb-read\000legacy cache\000Data TLB read accesses= \000legacy-cache-config=3D3\000\00010\000\000\000\000\000" +/* offset=3D80278 */ "d-tlb-read-refs\000legacy cache\000Data TLB read acc= esses\000legacy-cache-config=3D3\000\00010\000\000\000\000\000" +/* offset=3D80360 */ "d-tlb-read-reference\000legacy cache\000Data TLB rea= d accesses\000legacy-cache-config=3D3\000\00010\000\000\000\000\000" +/* offset=3D80447 */ "d-tlb-read-ops\000legacy cache\000Data TLB read acce= sses\000legacy-cache-config=3D3\000\00010\000\000\000\000\000" +/* offset=3D80528 */ "d-tlb-read-access\000legacy cache\000Data TLB read a= ccesses\000legacy-cache-config=3D3\000\00010\000\000\000\000\000" +/* offset=3D80612 */ "d-tlb-read-misses\000legacy cache\000Data TLB read m= isses\000legacy-cache-config=3D0x10003\000\00010\000\000\000\000\000" +/* offset=3D80700 */ "d-tlb-read-miss\000legacy cache\000Data TLB read mis= ses\000legacy-cache-config=3D0x10003\000\00010\000\000\000\000\000" +/* offset=3D80786 */ "d-tlb-store\000legacy cache\000Data TLB write access= es\000legacy-cache-config=3D0x103\000\00010\000\000\000\000\000" +/* offset=3D80869 */ "d-tlb-store-refs\000legacy cache\000Data TLB write a= ccesses\000legacy-cache-config=3D0x103\000\00010\000\000\000\000\000" +/* offset=3D80957 */ "d-tlb-store-reference\000legacy cache\000Data TLB wr= ite accesses\000legacy-cache-config=3D0x103\000\00010\000\000\000\000\000" +/* offset=3D81050 */ "d-tlb-store-ops\000legacy cache\000Data TLB write ac= cesses\000legacy-cache-config=3D0x103\000\00010\000\000\000\000\000" +/* offset=3D81137 */ "d-tlb-store-access\000legacy cache\000Data TLB write= accesses\000legacy-cache-config=3D0x103\000\00010\000\000\000\000\000" +/* offset=3D81227 */ "d-tlb-store-misses\000legacy cache\000Data TLB write= misses\000legacy-cache-config=3D0x10103\000\00010\000\000\000\000\000" +/* offset=3D81317 */ "d-tlb-store-miss\000legacy cache\000Data TLB write m= isses\000legacy-cache-config=3D0x10103\000\00010\000\000\000\000\000" +/* offset=3D81405 */ "d-tlb-stores\000legacy cache\000Data TLB write acces= ses\000legacy-cache-config=3D0x103\000\00010\000\000\000\000\000" +/* offset=3D81489 */ "d-tlb-stores-refs\000legacy cache\000Data TLB write = accesses\000legacy-cache-config=3D0x103\000\00010\000\000\000\000\000" +/* offset=3D81578 */ "d-tlb-stores-reference\000legacy cache\000Data TLB w= rite accesses\000legacy-cache-config=3D0x103\000\00010\000\000\000\000\000" +/* offset=3D81672 */ "d-tlb-stores-ops\000legacy cache\000Data TLB write a= ccesses\000legacy-cache-config=3D0x103\000\00010\000\000\000\000\000" +/* offset=3D81760 */ "d-tlb-stores-access\000legacy cache\000Data TLB writ= e accesses\000legacy-cache-config=3D0x103\000\00010\000\000\000\000\000" +/* offset=3D81851 */ "d-tlb-stores-misses\000legacy cache\000Data TLB writ= e misses\000legacy-cache-config=3D0x10103\000\00010\000\000\000\000\000" +/* offset=3D81942 */ "d-tlb-stores-miss\000legacy cache\000Data TLB write = misses\000legacy-cache-config=3D0x10103\000\00010\000\000\000\000\000" +/* offset=3D82031 */ "d-tlb-write\000legacy cache\000Data TLB write access= es\000legacy-cache-config=3D0x103\000\00010\000\000\000\000\000" +/* offset=3D82114 */ "d-tlb-write-refs\000legacy cache\000Data TLB write a= ccesses\000legacy-cache-config=3D0x103\000\00010\000\000\000\000\000" +/* offset=3D82202 */ "d-tlb-write-reference\000legacy cache\000Data TLB wr= ite accesses\000legacy-cache-config=3D0x103\000\00010\000\000\000\000\000" +/* offset=3D82295 */ "d-tlb-write-ops\000legacy cache\000Data TLB write ac= cesses\000legacy-cache-config=3D0x103\000\00010\000\000\000\000\000" +/* offset=3D82382 */ "d-tlb-write-access\000legacy cache\000Data TLB write= accesses\000legacy-cache-config=3D0x103\000\00010\000\000\000\000\000" +/* offset=3D82472 */ "d-tlb-write-misses\000legacy cache\000Data TLB write= misses\000legacy-cache-config=3D0x10103\000\00010\000\000\000\000\000" +/* offset=3D82562 */ "d-tlb-write-miss\000legacy cache\000Data TLB write m= isses\000legacy-cache-config=3D0x10103\000\00010\000\000\000\000\000" +/* offset=3D82650 */ "d-tlb-prefetch\000legacy cache\000Data TLB prefetch = accesses\000legacy-cache-config=3D0x203\000\00010\000\000\000\000\000" +/* offset=3D82739 */ "d-tlb-prefetch-refs\000legacy cache\000Data TLB pref= etch accesses\000legacy-cache-config=3D0x203\000\00010\000\000\000\000\000" +/* offset=3D82833 */ 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accesses\000legacy-cache-config=3D0x203\000\00010\000\000\000\000\00= 0" +/* offset=3D83498 */ "d-tlb-prefetches-reference\000legacy cache\000Data T= LB prefetch accesses\000legacy-cache-config=3D0x203\000\00010\000\000\000\0= 00\000" +/* offset=3D83599 */ "d-tlb-prefetches-ops\000legacy cache\000Data TLB pre= fetch accesses\000legacy-cache-config=3D0x203\000\00010\000\000\000\000\000" +/* offset=3D83694 */ "d-tlb-prefetches-access\000legacy cache\000Data TLB = prefetch accesses\000legacy-cache-config=3D0x203\000\00010\000\000\000\000\= 000" +/* offset=3D83792 */ "d-tlb-prefetches-misses\000legacy cache\000Data TLB = prefetch misses\000legacy-cache-config=3D0x10203\000\00010\000\000\000\000\= 000" +/* offset=3D83890 */ "d-tlb-prefetches-miss\000legacy cache\000Data TLB pr= efetch misses\000legacy-cache-config=3D0x10203\000\00010\000\000\000\000\00= 0" +/* offset=3D83986 */ "d-tlb-speculative-read\000legacy cache\000Data TLB p= refetch accesses\000legacy-cache-config=3D0x203\000\00010\000\000\000\000\0= 00" +/* offset=3D84083 */ "d-tlb-speculative-read-refs\000legacy cache\000Data = TLB prefetch accesses\000legacy-cache-config=3D0x203\000\00010\000\000\000\= 000\000" +/* offset=3D84185 */ "d-tlb-speculative-read-reference\000legacy cache\000= Data TLB prefetch accesses\000legacy-cache-config=3D0x203\000\00010\000\000= \000\000\000" +/* offset=3D84292 */ "d-tlb-speculative-read-ops\000legacy cache\000Data T= LB prefetch accesses\000legacy-cache-config=3D0x203\000\00010\000\000\000\0= 00\000" +/* offset=3D84393 */ "d-tlb-speculative-read-access\000legacy cache\000Dat= a TLB prefetch accesses\000legacy-cache-config=3D0x203\000\00010\000\000\00= 0\000\000" +/* offset=3D84497 */ "d-tlb-speculative-read-misses\000legacy cache\000Dat= a TLB prefetch misses\000legacy-cache-config=3D0x10203\000\00010\000\000\00= 0\000\000" +/* offset=3D84601 */ "d-tlb-speculative-read-miss\000legacy cache\000Data = TLB prefetch misses\000legacy-cache-config=3D0x10203\000\00010\000\000\000\= 000\000" +/* offset=3D84703 */ "d-tlb-speculative-load\000legacy cache\000Data TLB p= refetch accesses\000legacy-cache-config=3D0x203\000\00010\000\000\000\000\0= 00" +/* offset=3D84800 */ "d-tlb-speculative-load-refs\000legacy cache\000Data = TLB prefetch accesses\000legacy-cache-config=3D0x203\000\00010\000\000\000\= 000\000" +/* offset=3D84902 */ "d-tlb-speculative-load-reference\000legacy cache\000= Data TLB prefetch accesses\000legacy-cache-config=3D0x203\000\00010\000\000= \000\000\000" +/* offset=3D85009 */ "d-tlb-speculative-load-ops\000legacy cache\000Data T= LB prefetch accesses\000legacy-cache-config=3D0x203\000\00010\000\000\000\0= 00\000" +/* offset=3D85110 */ "d-tlb-speculative-load-access\000legacy cache\000Dat= a TLB prefetch accesses\000legacy-cache-config=3D0x203\000\00010\000\000\00= 0\000\000" +/* offset=3D85214 */ "d-tlb-speculative-load-misses\000legacy cache\000Dat= a TLB prefetch misses\000legacy-cache-config=3D0x10203\000\00010\000\000\00= 0\000\000" +/* offset=3D85318 */ "d-tlb-speculative-load-miss\000legacy cache\000Data = TLB prefetch misses\000legacy-cache-config=3D0x10203\000\00010\000\000\000\= 000\000" +/* offset=3D85420 */ "d-tlb-refs\000legacy cache\000Data TLB read accesses= \000legacy-cache-config=3D3\000\00010\000\000\000\000\000" +/* offset=3D85497 */ "d-tlb-reference\000legacy cache\000Data TLB read acc= esses\000legacy-cache-config=3D3\000\00010\000\000\000\000\000" +/* offset=3D85579 */ "d-tlb-ops\000legacy cache\000Data TLB read accesses\= 000legacy-cache-config=3D3\000\00010\000\000\000\000\000" +/* offset=3D85655 */ "d-tlb-access\000legacy cache\000Data TLB read access= es\000legacy-cache-config=3D3\000\00010\000\000\000\000\000" +/* offset=3D85734 */ "d-tlb-misses\000legacy cache\000Data TLB read misses= \000legacy-cache-config=3D0x10003\000\00010\000\000\000\000\000" +/* offset=3D85817 */ "d-tlb-miss\000legacy cache\000Data TLB read misses\0= 00legacy-cache-config=3D0x10003\000\00010\000\000\000\000\000" +/* offset=3D85898 */ "data-tlb\000legacy cache\000Data TLB read accesses\0= 00legacy-cache-config=3D3\000\00010\000\000\000\000\000" +/* offset=3D85973 */ "data-tlb-load\000legacy cache\000Data TLB read acces= ses\000legacy-cache-config=3D3\000\00010\000\000\000\000\000" +/* offset=3D86053 */ "data-tlb-load-refs\000legacy cache\000Data TLB read = accesses\000legacy-cache-config=3D3\000\00010\000\000\000\000\000" +/* offset=3D86138 */ "data-tlb-load-reference\000legacy cache\000Data TLB = read accesses\000legacy-cache-config=3D3\000\00010\000\000\000\000\000" +/* offset=3D86228 */ "data-tlb-load-ops\000legacy cache\000Data TLB read a= ccesses\000legacy-cache-config=3D3\000\00010\000\000\000\000\000" +/* offset=3D86312 */ "data-tlb-load-access\000legacy cache\000Data TLB rea= d accesses\000legacy-cache-config=3D3\000\00010\000\000\000\000\000" +/* offset=3D86399 */ "data-tlb-load-misses\000legacy cache\000Data TLB rea= d misses\000legacy-cache-config=3D0x10003\000\00010\000\000\000\000\000" +/* offset=3D86490 */ "data-tlb-load-miss\000legacy cache\000Data TLB read = misses\000legacy-cache-config=3D0x10003\000\00010\000\000\000\000\000" +/* offset=3D86579 */ "data-tlb-loads\000legacy cache\000Data TLB read acce= sses\000legacy-cache-config=3D3\000\00010\000\000\000\000\000" +/* offset=3D86660 */ "data-tlb-loads-refs\000legacy cache\000Data TLB read= accesses\000legacy-cache-config=3D3\000\00010\000\000\000\000\000" +/* offset=3D86746 */ "data-tlb-loads-reference\000legacy cache\000Data TLB= read accesses\000legacy-cache-config=3D3\000\00010\000\000\000\000\000" +/* offset=3D86837 */ "data-tlb-loads-ops\000legacy cache\000Data TLB read = accesses\000legacy-cache-config=3D3\000\00010\000\000\000\000\000" +/* offset=3D86922 */ "data-tlb-loads-access\000legacy cache\000Data TLB re= ad accesses\000legacy-cache-config=3D3\000\00010\000\000\000\000\000" +/* offset=3D87010 */ "data-tlb-loads-misses\000legacy cache\000Data TLB re= ad misses\000legacy-cache-config=3D0x10003\000\00010\000\000\000\000\000" +/* offset=3D87102 */ "data-tlb-loads-miss\000legacy cache\000Data TLB read= misses\000legacy-cache-config=3D0x10003\000\00010\000\000\000\000\000" +/* offset=3D87192 */ "data-tlb-read\000legacy cache\000Data TLB read acces= ses\000legacy-cache-config=3D3\000\00010\000\000\000\000\000" +/* offset=3D87272 */ "data-tlb-read-refs\000legacy cache\000Data TLB read = accesses\000legacy-cache-config=3D3\000\00010\000\000\000\000\000" +/* offset=3D87357 */ "data-tlb-read-reference\000legacy cache\000Data TLB = read accesses\000legacy-cache-config=3D3\000\00010\000\000\000\000\000" +/* offset=3D87447 */ "data-tlb-read-ops\000legacy cache\000Data TLB read a= ccesses\000legacy-cache-config=3D3\000\00010\000\000\000\000\000" +/* offset=3D87531 */ "data-tlb-read-access\000legacy cache\000Data TLB rea= d accesses\000legacy-cache-config=3D3\000\00010\000\000\000\000\000" +/* offset=3D87618 */ "data-tlb-read-misses\000legacy cache\000Data TLB rea= d misses\000legacy-cache-config=3D0x10003\000\00010\000\000\000\000\000" +/* offset=3D87709 */ "data-tlb-read-miss\000legacy cache\000Data TLB read = misses\000legacy-cache-config=3D0x10003\000\00010\000\000\000\000\000" +/* offset=3D87798 */ "data-tlb-store\000legacy cache\000Data TLB write acc= esses\000legacy-cache-config=3D0x103\000\00010\000\000\000\000\000" +/* offset=3D87884 */ "data-tlb-store-refs\000legacy cache\000Data TLB writ= e accesses\000legacy-cache-config=3D0x103\000\00010\000\000\000\000\000" +/* offset=3D87975 */ "data-tlb-store-reference\000legacy cache\000Data TLB= write accesses\000legacy-cache-config=3D0x103\000\00010\000\000\000\000\00= 0" +/* offset=3D88071 */ "data-tlb-store-ops\000legacy cache\000Data TLB write= accesses\000legacy-cache-config=3D0x103\000\00010\000\000\000\000\000" +/* offset=3D88161 */ "data-tlb-store-access\000legacy cache\000Data TLB wr= ite accesses\000legacy-cache-config=3D0x103\000\00010\000\000\000\000\000" +/* offset=3D88254 */ "data-tlb-store-misses\000legacy cache\000Data TLB wr= ite misses\000legacy-cache-config=3D0x10103\000\00010\000\000\000\000\000" +/* offset=3D88347 */ "data-tlb-store-miss\000legacy cache\000Data TLB writ= e misses\000legacy-cache-config=3D0x10103\000\00010\000\000\000\000\000" +/* offset=3D88438 */ "data-tlb-stores\000legacy cache\000Data TLB write ac= cesses\000legacy-cache-config=3D0x103\000\00010\000\000\000\000\000" +/* offset=3D88525 */ "data-tlb-stores-refs\000legacy cache\000Data TLB wri= te accesses\000legacy-cache-config=3D0x103\000\00010\000\000\000\000\000" +/* offset=3D88617 */ "data-tlb-stores-reference\000legacy cache\000Data TL= B write accesses\000legacy-cache-config=3D0x103\000\00010\000\000\000\000\0= 00" +/* offset=3D88714 */ "data-tlb-stores-ops\000legacy cache\000Data TLB writ= e accesses\000legacy-cache-config=3D0x103\000\00010\000\000\000\000\000" +/* offset=3D88805 */ "data-tlb-stores-access\000legacy cache\000Data TLB w= rite accesses\000legacy-cache-config=3D0x103\000\00010\000\000\000\000\000" +/* offset=3D88899 */ "data-tlb-stores-misses\000legacy cache\000Data TLB w= rite misses\000legacy-cache-config=3D0x10103\000\00010\000\000\000\000\000" +/* offset=3D88993 */ "data-tlb-stores-miss\000legacy cache\000Data TLB wri= te misses\000legacy-cache-config=3D0x10103\000\00010\000\000\000\000\000" +/* offset=3D89085 */ "data-tlb-write\000legacy cache\000Data TLB write acc= esses\000legacy-cache-config=3D0x103\000\00010\000\000\000\000\000" +/* offset=3D89171 */ "data-tlb-write-refs\000legacy cache\000Data TLB writ= e accesses\000legacy-cache-config=3D0x103\000\00010\000\000\000\000\000" +/* offset=3D89262 */ "data-tlb-write-reference\000legacy cache\000Data TLB= write accesses\000legacy-cache-config=3D0x103\000\00010\000\000\000\000\00= 0" +/* offset=3D89358 */ "data-tlb-write-ops\000legacy cache\000Data TLB write= accesses\000legacy-cache-config=3D0x103\000\00010\000\000\000\000\000" +/* offset=3D89448 */ "data-tlb-write-access\000legacy cache\000Data TLB wr= ite accesses\000legacy-cache-config=3D0x103\000\00010\000\000\000\000\000" +/* offset=3D89541 */ "data-tlb-write-misses\000legacy cache\000Data TLB wr= ite misses\000legacy-cache-config=3D0x10103\000\00010\000\000\000\000\000" +/* offset=3D89634 */ "data-tlb-write-miss\000legacy cache\000Data TLB writ= e misses\000legacy-cache-config=3D0x10103\000\00010\000\000\000\000\000" +/* offset=3D89725 */ "data-tlb-prefetch\000legacy cache\000Data TLB prefet= ch accesses\000legacy-cache-config=3D0x203\000\00010\000\000\000\000\000" +/* offset=3D89817 */ "data-tlb-prefetch-refs\000legacy cache\000Data TLB p= refetch accesses\000legacy-cache-config=3D0x203\000\00010\000\000\000\000\0= 00" +/* offset=3D89914 */ "data-tlb-prefetch-reference\000legacy cache\000Data = TLB prefetch accesses\000legacy-cache-config=3D0x203\000\00010\000\000\000\= 000\000" +/* offset=3D90016 */ "data-tlb-prefetch-ops\000legacy cache\000Data TLB pr= efetch accesses\000legacy-cache-config=3D0x203\000\00010\000\000\000\000\00= 0" +/* offset=3D90112 */ "data-tlb-prefetch-access\000legacy cache\000Data TLB= prefetch accesses\000legacy-cache-config=3D0x203\000\00010\000\000\000\000= \000" +/* offset=3D90211 */ "data-tlb-prefetch-misses\000legacy cache\000Data TLB= prefetch misses\000legacy-cache-config=3D0x10203\000\00010\000\000\000\000= \000" +/* offset=3D90310 */ "data-tlb-prefetch-miss\000legacy cache\000Data TLB p= refetch misses\000legacy-cache-config=3D0x10203\000\00010\000\000\000\000\0= 00" +/* offset=3D90407 */ "data-tlb-prefetches\000legacy cache\000Data TLB pref= etch accesses\000legacy-cache-config=3D0x203\000\00010\000\000\000\000\000" +/* offset=3D90501 */ "data-tlb-prefetches-refs\000legacy cache\000Data TLB= prefetch accesses\000legacy-cache-config=3D0x203\000\00010\000\000\000\000= \000" +/* offset=3D90600 */ "data-tlb-prefetches-reference\000legacy cache\000Dat= a TLB prefetch accesses\000legacy-cache-config=3D0x203\000\00010\000\000\00= 0\000\000" +/* offset=3D90704 */ "data-tlb-prefetches-ops\000legacy cache\000Data TLB = prefetch accesses\000legacy-cache-config=3D0x203\000\00010\000\000\000\000\= 000" +/* offset=3D90802 */ "data-tlb-prefetches-access\000legacy cache\000Data T= LB prefetch accesses\000legacy-cache-config=3D0x203\000\00010\000\000\000\0= 00\000" +/* offset=3D90903 */ "data-tlb-prefetches-misses\000legacy cache\000Data T= LB prefetch misses\000legacy-cache-config=3D0x10203\000\00010\000\000\000\0= 00\000" +/* offset=3D91004 */ "data-tlb-prefetches-miss\000legacy cache\000Data TLB= prefetch misses\000legacy-cache-config=3D0x10203\000\00010\000\000\000\000= \000" +/* offset=3D91103 */ "data-tlb-speculative-read\000legacy cache\000Data TL= B prefetch accesses\000legacy-cache-config=3D0x203\000\00010\000\000\000\00= 0\000" +/* offset=3D91203 */ "data-tlb-speculative-read-refs\000legacy cache\000Da= ta TLB prefetch accesses\000legacy-cache-config=3D0x203\000\00010\000\000\0= 00\000\000" +/* offset=3D91308 */ "data-tlb-speculative-read-reference\000legacy cache\= 000Data TLB prefetch accesses\000legacy-cache-config=3D0x203\000\00010\000\= 000\000\000\000" +/* offset=3D91418 */ "data-tlb-speculative-read-ops\000legacy cache\000Dat= a TLB prefetch accesses\000legacy-cache-config=3D0x203\000\00010\000\000\00= 0\000\000" +/* offset=3D91522 */ "data-tlb-speculative-read-access\000legacy cache\000= Data TLB prefetch accesses\000legacy-cache-config=3D0x203\000\00010\000\000= \000\000\000" +/* offset=3D91629 */ "data-tlb-speculative-read-misses\000legacy cache\000= Data TLB prefetch misses\000legacy-cache-config=3D0x10203\000\00010\000\000= \000\000\000" +/* offset=3D91736 */ "data-tlb-speculative-read-miss\000legacy cache\000Da= ta TLB prefetch misses\000legacy-cache-config=3D0x10203\000\00010\000\000\0= 00\000\000" +/* offset=3D91841 */ "data-tlb-speculative-load\000legacy cache\000Data TL= B prefetch accesses\000legacy-cache-config=3D0x203\000\00010\000\000\000\00= 0\000" +/* offset=3D91941 */ "data-tlb-speculative-load-refs\000legacy cache\000Da= ta TLB prefetch accesses\000legacy-cache-config=3D0x203\000\00010\000\000\0= 00\000\000" +/* offset=3D92046 */ "data-tlb-speculative-load-reference\000legacy cache\= 000Data TLB prefetch accesses\000legacy-cache-config=3D0x203\000\00010\000\= 000\000\000\000" +/* offset=3D92156 */ "data-tlb-speculative-load-ops\000legacy cache\000Dat= a TLB prefetch accesses\000legacy-cache-config=3D0x203\000\00010\000\000\00= 0\000\000" +/* offset=3D92260 */ "data-tlb-speculative-load-access\000legacy cache\000= Data TLB prefetch accesses\000legacy-cache-config=3D0x203\000\00010\000\000= \000\000\000" +/* offset=3D92367 */ "data-tlb-speculative-load-misses\000legacy cache\000= Data TLB prefetch misses\000legacy-cache-config=3D0x10203\000\00010\000\000= \000\000\000" +/* offset=3D92474 */ "data-tlb-speculative-load-miss\000legacy cache\000Da= ta TLB prefetch misses\000legacy-cache-config=3D0x10203\000\00010\000\000\0= 00\000\000" +/* offset=3D92579 */ "data-tlb-refs\000legacy cache\000Data TLB read acces= ses\000legacy-cache-config=3D3\000\00010\000\000\000\000\000" +/* offset=3D92659 */ "data-tlb-reference\000legacy cache\000Data TLB read = accesses\000legacy-cache-config=3D3\000\00010\000\000\000\000\000" +/* offset=3D92744 */ "data-tlb-ops\000legacy cache\000Data TLB read access= es\000legacy-cache-config=3D3\000\00010\000\000\000\000\000" +/* offset=3D92823 */ "data-tlb-access\000legacy cache\000Data TLB read acc= esses\000legacy-cache-config=3D3\000\00010\000\000\000\000\000" +/* offset=3D92905 */ "data-tlb-misses\000legacy cache\000Data TLB read mis= ses\000legacy-cache-config=3D0x10003\000\00010\000\000\000\000\000" +/* offset=3D92991 */ "data-tlb-miss\000legacy cache\000Data TLB read misse= s\000legacy-cache-config=3D0x10003\000\00010\000\000\000\000\000" +/* offset=3D93075 */ "itlb\000legacy cache\000Instruction TLB read accesse= s\000legacy-cache-config=3D4\000\00010\000\000\000\000\000" +/* offset=3D93153 */ "itlb-load\000legacy cache\000Instruction TLB read ac= cesses\000legacy-cache-config=3D4\000\00010\000\000\000\000\000" +/* offset=3D93236 */ "itlb-load-refs\000legacy cache\000Instruction TLB re= ad accesses\000legacy-cache-config=3D4\000\00010\000\000\000\000\000" +/* offset=3D93324 */ "itlb-load-reference\000legacy cache\000Instruction T= LB read accesses\000legacy-cache-config=3D4\000\00010\000\000\000\000\000" +/* offset=3D93417 */ "itlb-load-ops\000legacy cache\000Instruction TLB rea= d accesses\000legacy-cache-config=3D4\000\00010\000\000\000\000\000" +/* offset=3D93504 */ "itlb-load-access\000legacy cache\000Instruction TLB = read accesses\000legacy-cache-config=3D4\000\00010\000\000\000\000\000" +/* offset=3D93594 */ "itlb-load-misses\000legacy cache\000Instruction TLB = read misses\000legacy-cache-config=3D0x10004\000\00000\000\000\000\000\000" +/* offset=3D93688 */ "itlb-load-miss\000legacy cache\000Instruction TLB re= ad misses\000legacy-cache-config=3D0x10004\000\00010\000\000\000\000\000" +/* offset=3D93780 */ "itlb-loads\000legacy cache\000Instruction TLB read a= ccesses\000legacy-cache-config=3D4\000\00000\000\000\000\000\000" +/* offset=3D93864 */ "itlb-loads-refs\000legacy cache\000Instruction TLB r= ead accesses\000legacy-cache-config=3D4\000\00010\000\000\000\000\000" +/* offset=3D93953 */ "itlb-loads-reference\000legacy cache\000Instruction = TLB read accesses\000legacy-cache-config=3D4\000\00010\000\000\000\000\000" +/* offset=3D94047 */ "itlb-loads-ops\000legacy cache\000Instruction TLB re= ad accesses\000legacy-cache-config=3D4\000\00010\000\000\000\000\000" +/* offset=3D94135 */ "itlb-loads-access\000legacy cache\000Instruction TLB= read accesses\000legacy-cache-config=3D4\000\00010\000\000\000\000\000" +/* offset=3D94226 */ "itlb-loads-misses\000legacy cache\000Instruction TLB= read misses\000legacy-cache-config=3D0x10004\000\00010\000\000\000\000\000" +/* offset=3D94321 */ "itlb-loads-miss\000legacy cache\000Instruction TLB r= ead misses\000legacy-cache-config=3D0x10004\000\00010\000\000\000\000\000" +/* offset=3D94414 */ "itlb-read\000legacy cache\000Instruction TLB read ac= cesses\000legacy-cache-config=3D4\000\00010\000\000\000\000\000" +/* offset=3D94497 */ "itlb-read-refs\000legacy cache\000Instruction TLB re= ad accesses\000legacy-cache-config=3D4\000\00010\000\000\000\000\000" +/* offset=3D94585 */ "itlb-read-reference\000legacy cache\000Instruction T= LB read accesses\000legacy-cache-config=3D4\000\00010\000\000\000\000\000" +/* offset=3D94678 */ "itlb-read-ops\000legacy cache\000Instruction TLB rea= d accesses\000legacy-cache-config=3D4\000\00010\000\000\000\000\000" +/* offset=3D94765 */ "itlb-read-access\000legacy cache\000Instruction TLB = read accesses\000legacy-cache-config=3D4\000\00010\000\000\000\000\000" +/* offset=3D94855 */ "itlb-read-misses\000legacy cache\000Instruction TLB = read misses\000legacy-cache-config=3D0x10004\000\00010\000\000\000\000\000" +/* offset=3D94949 */ "itlb-read-miss\000legacy cache\000Instruction TLB re= ad misses\000legacy-cache-config=3D0x10004\000\00010\000\000\000\000\000" +/* offset=3D95041 */ "itlb-refs\000legacy cache\000Instruction TLB read ac= cesses\000legacy-cache-config=3D4\000\00010\000\000\000\000\000" +/* offset=3D95124 */ "itlb-reference\000legacy cache\000Instruction TLB re= ad accesses\000legacy-cache-config=3D4\000\00010\000\000\000\000\000" +/* offset=3D95212 */ "itlb-ops\000legacy cache\000Instruction TLB read acc= esses\000legacy-cache-config=3D4\000\00010\000\000\000\000\000" +/* offset=3D95294 */ "itlb-access\000legacy cache\000Instruction TLB read = accesses\000legacy-cache-config=3D4\000\00010\000\000\000\000\000" +/* offset=3D95379 */ "itlb-misses\000legacy cache\000Instruction TLB read = misses\000legacy-cache-config=3D0x10004\000\00010\000\000\000\000\000" +/* offset=3D95468 */ "itlb-miss\000legacy cache\000Instruction TLB read mi= sses\000legacy-cache-config=3D0x10004\000\00010\000\000\000\000\000" +/* offset=3D95555 */ "i-tlb\000legacy cache\000Instruction TLB read access= es\000legacy-cache-config=3D4\000\00010\000\000\000\000\000" +/* offset=3D95634 */ "i-tlb-load\000legacy cache\000Instruction TLB read a= ccesses\000legacy-cache-config=3D4\000\00010\000\000\000\000\000" +/* offset=3D95718 */ "i-tlb-load-refs\000legacy cache\000Instruction TLB r= ead accesses\000legacy-cache-config=3D4\000\00010\000\000\000\000\000" +/* offset=3D95807 */ "i-tlb-load-reference\000legacy cache\000Instruction = TLB read accesses\000legacy-cache-config=3D4\000\00010\000\000\000\000\000" +/* offset=3D95901 */ "i-tlb-load-ops\000legacy cache\000Instruction TLB re= ad accesses\000legacy-cache-config=3D4\000\00010\000\000\000\000\000" +/* offset=3D95989 */ "i-tlb-load-access\000legacy cache\000Instruction TLB= read accesses\000legacy-cache-config=3D4\000\00010\000\000\000\000\000" +/* offset=3D96080 */ "i-tlb-load-misses\000legacy cache\000Instruction TLB= read misses\000legacy-cache-config=3D0x10004\000\00010\000\000\000\000\000" +/* offset=3D96175 */ "i-tlb-load-miss\000legacy cache\000Instruction TLB r= ead misses\000legacy-cache-config=3D0x10004\000\00010\000\000\000\000\000" +/* offset=3D96268 */ "i-tlb-loads\000legacy cache\000Instruction TLB read = accesses\000legacy-cache-config=3D4\000\00010\000\000\000\000\000" +/* offset=3D96353 */ "i-tlb-loads-refs\000legacy cache\000Instruction TLB = read accesses\000legacy-cache-config=3D4\000\00010\000\000\000\000\000" +/* offset=3D96443 */ "i-tlb-loads-reference\000legacy cache\000Instruction= TLB read accesses\000legacy-cache-config=3D4\000\00010\000\000\000\000\000" +/* offset=3D96538 */ "i-tlb-loads-ops\000legacy cache\000Instruction TLB r= ead accesses\000legacy-cache-config=3D4\000\00010\000\000\000\000\000" +/* offset=3D96627 */ "i-tlb-loads-access\000legacy cache\000Instruction TL= B read accesses\000legacy-cache-config=3D4\000\00010\000\000\000\000\000" +/* offset=3D96719 */ "i-tlb-loads-misses\000legacy cache\000Instruction TL= B read misses\000legacy-cache-config=3D0x10004\000\00010\000\000\000\000\00= 0" +/* offset=3D96815 */ "i-tlb-loads-miss\000legacy cache\000Instruction TLB = read misses\000legacy-cache-config=3D0x10004\000\00010\000\000\000\000\000" +/* offset=3D96909 */ "i-tlb-read\000legacy cache\000Instruction TLB read a= ccesses\000legacy-cache-config=3D4\000\00010\000\000\000\000\000" +/* offset=3D96993 */ "i-tlb-read-refs\000legacy cache\000Instruction TLB r= ead accesses\000legacy-cache-config=3D4\000\00010\000\000\000\000\000" +/* offset=3D97082 */ "i-tlb-read-reference\000legacy cache\000Instruction = TLB read accesses\000legacy-cache-config=3D4\000\00010\000\000\000\000\000" +/* offset=3D97176 */ "i-tlb-read-ops\000legacy cache\000Instruction TLB re= ad accesses\000legacy-cache-config=3D4\000\00010\000\000\000\000\000" +/* offset=3D97264 */ "i-tlb-read-access\000legacy cache\000Instruction TLB= read accesses\000legacy-cache-config=3D4\000\00010\000\000\000\000\000" +/* offset=3D97355 */ "i-tlb-read-misses\000legacy cache\000Instruction TLB= read misses\000legacy-cache-config=3D0x10004\000\00010\000\000\000\000\000" +/* offset=3D97450 */ "i-tlb-read-miss\000legacy cache\000Instruction TLB r= ead misses\000legacy-cache-config=3D0x10004\000\00010\000\000\000\000\000" +/* offset=3D97543 */ "i-tlb-refs\000legacy cache\000Instruction TLB read a= ccesses\000legacy-cache-config=3D4\000\00010\000\000\000\000\000" +/* offset=3D97627 */ "i-tlb-reference\000legacy cache\000Instruction TLB r= ead accesses\000legacy-cache-config=3D4\000\00010\000\000\000\000\000" +/* offset=3D97716 */ "i-tlb-ops\000legacy cache\000Instruction TLB read ac= cesses\000legacy-cache-config=3D4\000\00010\000\000\000\000\000" +/* offset=3D97799 */ "i-tlb-access\000legacy cache\000Instruction TLB read= accesses\000legacy-cache-config=3D4\000\00010\000\000\000\000\000" +/* offset=3D97885 */ "i-tlb-misses\000legacy cache\000Instruction TLB read= misses\000legacy-cache-config=3D0x10004\000\00010\000\000\000\000\000" +/* offset=3D97975 */ "i-tlb-miss\000legacy cache\000Instruction TLB read m= isses\000legacy-cache-config=3D0x10004\000\00010\000\000\000\000\000" +/* offset=3D98063 */ "instruction-tlb\000legacy cache\000Instruction TLB r= ead accesses\000legacy-cache-config=3D4\000\00010\000\000\000\000\000" +/* offset=3D98152 */ "instruction-tlb-load\000legacy cache\000Instruction = TLB read accesses\000legacy-cache-config=3D4\000\00010\000\000\000\000\000" +/* offset=3D98246 */ "instruction-tlb-load-refs\000legacy cache\000Instruc= tion TLB read accesses\000legacy-cache-config=3D4\000\00010\000\000\000\000= \000" +/* offset=3D98345 */ "instruction-tlb-load-reference\000legacy cache\000In= struction TLB read accesses\000legacy-cache-config=3D4\000\00010\000\000\00= 0\000\000" +/* offset=3D98449 */ "instruction-tlb-load-ops\000legacy cache\000Instruct= ion TLB read accesses\000legacy-cache-config=3D4\000\00010\000\000\000\000\= 000" +/* offset=3D98547 */ "instruction-tlb-load-access\000legacy cache\000Instr= uction TLB read accesses\000legacy-cache-config=3D4\000\00010\000\000\000\0= 00\000" +/* offset=3D98648 */ "instruction-tlb-load-misses\000legacy cache\000Instr= uction TLB read misses\000legacy-cache-config=3D0x10004\000\00010\000\000\0= 00\000\000" +/* offset=3D98753 */ "instruction-tlb-load-miss\000legacy cache\000Instruc= tion TLB read misses\000legacy-cache-config=3D0x10004\000\00010\000\000\000= \000\000" +/* offset=3D98856 */ "instruction-tlb-loads\000legacy cache\000Instruction= TLB read accesses\000legacy-cache-config=3D4\000\00010\000\000\000\000\000" +/* offset=3D98951 */ "instruction-tlb-loads-refs\000legacy cache\000Instru= ction TLB read accesses\000legacy-cache-config=3D4\000\00010\000\000\000\00= 0\000" +/* offset=3D99051 */ "instruction-tlb-loads-reference\000legacy cache\000I= nstruction TLB read accesses\000legacy-cache-config=3D4\000\00010\000\000\0= 00\000\000" +/* offset=3D99156 */ "instruction-tlb-loads-ops\000legacy cache\000Instruc= tion TLB read accesses\000legacy-cache-config=3D4\000\00010\000\000\000\000= \000" +/* offset=3D99255 */ "instruction-tlb-loads-access\000legacy cache\000Inst= ruction TLB read accesses\000legacy-cache-config=3D4\000\00010\000\000\000\= 000\000" +/* offset=3D99357 */ "instruction-tlb-loads-misses\000legacy cache\000Inst= ruction TLB read misses\000legacy-cache-config=3D0x10004\000\00010\000\000\= 000\000\000" +/* offset=3D99463 */ "instruction-tlb-loads-miss\000legacy cache\000Instru= ction TLB read misses\000legacy-cache-config=3D0x10004\000\00010\000\000\00= 0\000\000" +/* offset=3D99567 */ "instruction-tlb-read\000legacy cache\000Instruction = TLB read accesses\000legacy-cache-config=3D4\000\00010\000\000\000\000\000" +/* offset=3D99661 */ "instruction-tlb-read-refs\000legacy cache\000Instruc= tion TLB read accesses\000legacy-cache-config=3D4\000\00010\000\000\000\000= \000" +/* offset=3D99760 */ "instruction-tlb-read-reference\000legacy cache\000In= struction TLB read accesses\000legacy-cache-config=3D4\000\00010\000\000\00= 0\000\000" +/* offset=3D99864 */ "instruction-tlb-read-ops\000legacy cache\000Instruct= ion TLB read accesses\000legacy-cache-config=3D4\000\00010\000\000\000\000\= 000" +/* offset=3D99962 */ "instruction-tlb-read-access\000legacy cache\000Instr= uction TLB read accesses\000legacy-cache-config=3D4\000\00010\000\000\000\0= 00\000" +/* offset=3D100063 */ "instruction-tlb-read-misses\000legacy cache\000Inst= ruction TLB read misses\000legacy-cache-config=3D0x10004\000\00010\000\000\= 000\000\000" +/* offset=3D100168 */ "instruction-tlb-read-miss\000legacy cache\000Instru= ction TLB read misses\000legacy-cache-config=3D0x10004\000\00010\000\000\00= 0\000\000" +/* offset=3D100271 */ "instruction-tlb-refs\000legacy cache\000Instruction= TLB read accesses\000legacy-cache-config=3D4\000\00010\000\000\000\000\000" +/* offset=3D100365 */ "instruction-tlb-reference\000legacy cache\000Instru= ction TLB read accesses\000legacy-cache-config=3D4\000\00010\000\000\000\00= 0\000" +/* offset=3D100464 */ "instruction-tlb-ops\000legacy cache\000Instruction = TLB read accesses\000legacy-cache-config=3D4\000\00010\000\000\000\000\000" +/* offset=3D100557 */ "instruction-tlb-access\000legacy cache\000Instructi= on TLB read accesses\000legacy-cache-config=3D4\000\00010\000\000\000\000\0= 00" +/* offset=3D100653 */ "instruction-tlb-misses\000legacy cache\000Instructi= on TLB read misses\000legacy-cache-config=3D0x10004\000\00010\000\000\000\0= 00\000" +/* offset=3D100753 */ "instruction-tlb-miss\000legacy cache\000Instruction= TLB read misses\000legacy-cache-config=3D0x10004\000\00010\000\000\000\000= \000" +/* offset=3D100851 */ "branch\000legacy cache\000Branch prediction unit re= ad accesses\000legacy-cache-config=3D5\000\00010\000\000\000\000\000" +/* offset=3D100938 */ "branch-load\000legacy cache\000Branch prediction un= it read accesses\000legacy-cache-config=3D5\000\00010\000\000\000\000\000" +/* offset=3D101030 */ "branch-load-refs\000legacy cache\000Branch predicti= on unit read accesses\000legacy-cache-config=3D5\000\00010\000\000\000\000\= 000" +/* offset=3D101127 */ "branch-load-reference\000legacy cache\000Branch pre= diction unit read accesses\000legacy-cache-config=3D5\000\00010\000\000\000= \000\000" +/* offset=3D101229 */ "branch-load-ops\000legacy cache\000Branch predictio= n unit read accesses\000legacy-cache-config=3D5\000\00010\000\000\000\000\0= 00" +/* offset=3D101325 */ "branch-load-access\000legacy cache\000Branch predic= tion unit read accesses\000legacy-cache-config=3D5\000\00010\000\000\000\00= 0\000" +/* offset=3D101424 */ "branch-load-misses\000legacy cache\000Branch predic= tion unit read misses\000legacy-cache-config=3D0x10005\000\00000\000\000\00= 0\000\000" +/* offset=3D101527 */ "branch-load-miss\000legacy cache\000Branch predicti= on unit read misses\000legacy-cache-config=3D0x10005\000\00010\000\000\000\= 000\000" +/* offset=3D101628 */ "branch-loads\000legacy cache\000Branch prediction u= nit read accesses\000legacy-cache-config=3D5\000\00000\000\000\000\000\000" +/* offset=3D101721 */ "branch-loads-refs\000legacy cache\000Branch predict= ion unit read accesses\000legacy-cache-config=3D5\000\00010\000\000\000\000= \000" +/* offset=3D101819 */ "branch-loads-reference\000legacy cache\000Branch pr= ediction unit read accesses\000legacy-cache-config=3D5\000\00010\000\000\00= 0\000\000" +/* offset=3D101922 */ "branch-loads-ops\000legacy cache\000Branch predicti= on unit read accesses\000legacy-cache-config=3D5\000\00010\000\000\000\000\= 000" +/* offset=3D102019 */ "branch-loads-access\000legacy cache\000Branch predi= ction unit read accesses\000legacy-cache-config=3D5\000\00010\000\000\000\0= 00\000" +/* offset=3D102119 */ "branch-loads-misses\000legacy cache\000Branch predi= ction unit read misses\000legacy-cache-config=3D0x10005\000\00010\000\000\0= 00\000\000" +/* offset=3D102223 */ "branch-loads-miss\000legacy cache\000Branch predict= ion unit read misses\000legacy-cache-config=3D0x10005\000\00010\000\000\000= \000\000" +/* offset=3D102325 */ "branch-read\000legacy cache\000Branch prediction un= it read accesses\000legacy-cache-config=3D5\000\00010\000\000\000\000\000" +/* offset=3D102417 */ "branch-read-refs\000legacy cache\000Branch predicti= on unit read accesses\000legacy-cache-config=3D5\000\00010\000\000\000\000\= 000" +/* offset=3D102514 */ "branch-read-reference\000legacy cache\000Branch pre= diction unit read accesses\000legacy-cache-config=3D5\000\00010\000\000\000= \000\000" +/* offset=3D102616 */ "branch-read-ops\000legacy cache\000Branch predictio= n unit read accesses\000legacy-cache-config=3D5\000\00010\000\000\000\000\0= 00" +/* offset=3D102712 */ "branch-read-access\000legacy cache\000Branch predic= tion unit read accesses\000legacy-cache-config=3D5\000\00010\000\000\000\00= 0\000" +/* offset=3D102811 */ "branch-read-misses\000legacy cache\000Branch predic= tion unit read misses\000legacy-cache-config=3D0x10005\000\00010\000\000\00= 0\000\000" +/* offset=3D102914 */ "branch-read-miss\000legacy cache\000Branch predicti= on unit read misses\000legacy-cache-config=3D0x10005\000\00010\000\000\000\= 000\000" +/* offset=3D103015 */ "branch-refs\000legacy cache\000Branch prediction un= it read accesses\000legacy-cache-config=3D5\000\00010\000\000\000\000\000" +/* offset=3D103107 */ "branch-reference\000legacy cache\000Branch predicti= on unit read accesses\000legacy-cache-config=3D5\000\00010\000\000\000\000\= 000" +/* offset=3D103204 */ "branch-ops\000legacy cache\000Branch prediction uni= t read accesses\000legacy-cache-config=3D5\000\00010\000\000\000\000\000" +/* offset=3D103295 */ "branch-access\000legacy cache\000Branch prediction = unit read accesses\000legacy-cache-config=3D5\000\00010\000\000\000\000\000" +/* offset=3D103389 */ "branch-miss\000legacy cache\000Branch prediction un= it read misses\000legacy-cache-config=3D0x10005\000\00010\000\000\000\000\0= 00" +/* offset=3D103485 */ "branches-load\000legacy cache\000Branch prediction = unit read accesses\000legacy-cache-config=3D5\000\00010\000\000\000\000\000" +/* offset=3D103579 */ "branches-load-refs\000legacy cache\000Branch predic= tion unit read accesses\000legacy-cache-config=3D5\000\00010\000\000\000\00= 0\000" +/* offset=3D103678 */ "branches-load-reference\000legacy cache\000Branch p= rediction unit read accesses\000legacy-cache-config=3D5\000\00010\000\000\0= 00\000\000" +/* offset=3D103782 */ "branches-load-ops\000legacy cache\000Branch predict= ion unit read accesses\000legacy-cache-config=3D5\000\00010\000\000\000\000= \000" +/* offset=3D103880 */ "branches-load-access\000legacy cache\000Branch pred= iction unit read accesses\000legacy-cache-config=3D5\000\00010\000\000\000\= 000\000" +/* offset=3D103981 */ "branches-load-misses\000legacy cache\000Branch pred= iction unit read misses\000legacy-cache-config=3D0x10005\000\00010\000\000\= 000\000\000" +/* offset=3D104086 */ "branches-load-miss\000legacy cache\000Branch predic= tion unit read misses\000legacy-cache-config=3D0x10005\000\00010\000\000\00= 0\000\000" +/* offset=3D104189 */ "branches-loads\000legacy cache\000Branch prediction= unit read accesses\000legacy-cache-config=3D5\000\00010\000\000\000\000\00= 0" +/* offset=3D104284 */ "branches-loads-refs\000legacy cache\000Branch predi= ction unit read accesses\000legacy-cache-config=3D5\000\00010\000\000\000\0= 00\000" +/* offset=3D104384 */ "branches-loads-reference\000legacy cache\000Branch = prediction unit read accesses\000legacy-cache-config=3D5\000\00010\000\000\= 000\000\000" +/* offset=3D104489 */ "branches-loads-ops\000legacy cache\000Branch predic= tion unit read accesses\000legacy-cache-config=3D5\000\00010\000\000\000\00= 0\000" +/* offset=3D104588 */ "branches-loads-access\000legacy cache\000Branch pre= diction unit read accesses\000legacy-cache-config=3D5\000\00010\000\000\000= \000\000" +/* offset=3D104690 */ "branches-loads-misses\000legacy cache\000Branch pre= diction unit read misses\000legacy-cache-config=3D0x10005\000\00010\000\000= \000\000\000" +/* offset=3D104796 */ "branches-loads-miss\000legacy cache\000Branch predi= ction unit read misses\000legacy-cache-config=3D0x10005\000\00010\000\000\0= 00\000\000" +/* offset=3D104900 */ "branches-read\000legacy cache\000Branch prediction = unit read accesses\000legacy-cache-config=3D5\000\00010\000\000\000\000\000" +/* offset=3D104994 */ "branches-read-refs\000legacy cache\000Branch predic= tion unit read accesses\000legacy-cache-config=3D5\000\00010\000\000\000\00= 0\000" +/* offset=3D105093 */ "branches-read-reference\000legacy cache\000Branch p= rediction unit read accesses\000legacy-cache-config=3D5\000\00010\000\000\0= 00\000\000" +/* offset=3D105197 */ "branches-read-ops\000legacy cache\000Branch predict= ion unit read accesses\000legacy-cache-config=3D5\000\00010\000\000\000\000= \000" +/* offset=3D105295 */ "branches-read-access\000legacy cache\000Branch pred= iction unit read accesses\000legacy-cache-config=3D5\000\00010\000\000\000\= 000\000" +/* offset=3D105396 */ "branches-read-misses\000legacy cache\000Branch pred= iction unit read misses\000legacy-cache-config=3D0x10005\000\00010\000\000\= 000\000\000" +/* offset=3D105501 */ "branches-read-miss\000legacy cache\000Branch predic= tion unit read misses\000legacy-cache-config=3D0x10005\000\00010\000\000\00= 0\000\000" +/* offset=3D105604 */ "branches-refs\000legacy cache\000Branch prediction = unit read accesses\000legacy-cache-config=3D5\000\00010\000\000\000\000\000" +/* offset=3D105698 */ "branches-reference\000legacy cache\000Branch predic= tion unit read accesses\000legacy-cache-config=3D5\000\00010\000\000\000\00= 0\000" +/* offset=3D105797 */ "branches-ops\000legacy cache\000Branch prediction u= nit read accesses\000legacy-cache-config=3D5\000\00010\000\000\000\000\000" +/* offset=3D105890 */ "branches-access\000legacy cache\000Branch predictio= n unit read accesses\000legacy-cache-config=3D5\000\00010\000\000\000\000\0= 00" +/* offset=3D105986 */ "branches-misses\000legacy cache\000Branch predictio= n unit read misses\000legacy-cache-config=3D0x10005\000\00010\000\000\000\0= 00\000" +/* offset=3D106086 */ "branches-miss\000legacy cache\000Branch prediction = unit read misses\000legacy-cache-config=3D0x10005\000\00010\000\000\000\000= \000" +/* offset=3D106184 */ "bpu\000legacy cache\000Branch prediction unit read = accesses\000legacy-cache-config=3D5\000\00010\000\000\000\000\000" +/* offset=3D106268 */ "bpu-load\000legacy cache\000Branch prediction unit = read accesses\000legacy-cache-config=3D5\000\00010\000\000\000\000\000" +/* offset=3D106357 */ "bpu-load-refs\000legacy cache\000Branch prediction = unit read accesses\000legacy-cache-config=3D5\000\00010\000\000\000\000\000" +/* offset=3D106451 */ "bpu-load-reference\000legacy cache\000Branch predic= tion unit read accesses\000legacy-cache-config=3D5\000\00010\000\000\000\00= 0\000" +/* offset=3D106550 */ "bpu-load-ops\000legacy cache\000Branch prediction u= nit read accesses\000legacy-cache-config=3D5\000\00010\000\000\000\000\000" +/* offset=3D106643 */ "bpu-load-access\000legacy cache\000Branch predictio= n unit read accesses\000legacy-cache-config=3D5\000\00010\000\000\000\000\0= 00" +/* offset=3D106739 */ "bpu-load-misses\000legacy cache\000Branch predictio= n unit read misses\000legacy-cache-config=3D0x10005\000\00010\000\000\000\0= 00\000" +/* offset=3D106839 */ "bpu-load-miss\000legacy cache\000Branch prediction = unit read misses\000legacy-cache-config=3D0x10005\000\00010\000\000\000\000= \000" +/* offset=3D106937 */ "bpu-loads\000legacy cache\000Branch prediction unit= read accesses\000legacy-cache-config=3D5\000\00010\000\000\000\000\000" +/* offset=3D107027 */ "bpu-loads-refs\000legacy cache\000Branch prediction= unit read accesses\000legacy-cache-config=3D5\000\00010\000\000\000\000\00= 0" +/* offset=3D107122 */ "bpu-loads-reference\000legacy cache\000Branch predi= ction unit read accesses\000legacy-cache-config=3D5\000\00010\000\000\000\0= 00\000" +/* offset=3D107222 */ "bpu-loads-ops\000legacy cache\000Branch prediction = unit read accesses\000legacy-cache-config=3D5\000\00010\000\000\000\000\000" +/* offset=3D107316 */ "bpu-loads-access\000legacy cache\000Branch predicti= on unit read accesses\000legacy-cache-config=3D5\000\00010\000\000\000\000\= 000" +/* offset=3D107413 */ "bpu-loads-misses\000legacy cache\000Branch predicti= on unit read misses\000legacy-cache-config=3D0x10005\000\00010\000\000\000\= 000\000" +/* offset=3D107514 */ "bpu-loads-miss\000legacy cache\000Branch prediction= unit read misses\000legacy-cache-config=3D0x10005\000\00010\000\000\000\00= 0\000" +/* offset=3D107613 */ "bpu-read\000legacy cache\000Branch prediction unit = read accesses\000legacy-cache-config=3D5\000\00010\000\000\000\000\000" +/* offset=3D107702 */ "bpu-read-refs\000legacy cache\000Branch prediction = unit read accesses\000legacy-cache-config=3D5\000\00010\000\000\000\000\000" +/* offset=3D107796 */ "bpu-read-reference\000legacy cache\000Branch predic= tion unit read accesses\000legacy-cache-config=3D5\000\00010\000\000\000\00= 0\000" +/* offset=3D107895 */ "bpu-read-ops\000legacy cache\000Branch prediction u= nit read accesses\000legacy-cache-config=3D5\000\00010\000\000\000\000\000" +/* offset=3D107988 */ "bpu-read-access\000legacy cache\000Branch predictio= n unit read accesses\000legacy-cache-config=3D5\000\00010\000\000\000\000\0= 00" +/* offset=3D108084 */ "bpu-read-misses\000legacy cache\000Branch predictio= n unit read misses\000legacy-cache-config=3D0x10005\000\00010\000\000\000\0= 00\000" +/* offset=3D108184 */ "bpu-read-miss\000legacy cache\000Branch prediction = unit read misses\000legacy-cache-config=3D0x10005\000\00010\000\000\000\000= \000" +/* offset=3D108282 */ "bpu-refs\000legacy cache\000Branch prediction unit = read accesses\000legacy-cache-config=3D5\000\00010\000\000\000\000\000" +/* offset=3D108371 */ "bpu-reference\000legacy cache\000Branch prediction = unit read accesses\000legacy-cache-config=3D5\000\00010\000\000\000\000\000" +/* offset=3D108465 */ "bpu-ops\000legacy cache\000Branch prediction unit r= ead accesses\000legacy-cache-config=3D5\000\00010\000\000\000\000\000" +/* offset=3D108553 */ "bpu-access\000legacy cache\000Branch prediction uni= t read accesses\000legacy-cache-config=3D5\000\00010\000\000\000\000\000" +/* offset=3D108644 */ "bpu-misses\000legacy cache\000Branch prediction uni= t read misses\000legacy-cache-config=3D0x10005\000\00010\000\000\000\000\00= 0" +/* offset=3D108739 */ "bpu-miss\000legacy cache\000Branch prediction unit = read misses\000legacy-cache-config=3D0x10005\000\00010\000\000\000\000\000" +/* offset=3D108832 */ "btb\000legacy cache\000Branch prediction unit read = accesses\000legacy-cache-config=3D5\000\00010\000\000\000\000\000" +/* offset=3D108916 */ "btb-load\000legacy cache\000Branch prediction unit = read accesses\000legacy-cache-config=3D5\000\00010\000\000\000\000\000" +/* offset=3D109005 */ "btb-load-refs\000legacy cache\000Branch prediction = unit read accesses\000legacy-cache-config=3D5\000\00010\000\000\000\000\000" +/* offset=3D109099 */ "btb-load-reference\000legacy cache\000Branch predic= tion unit read accesses\000legacy-cache-config=3D5\000\00010\000\000\000\00= 0\000" +/* offset=3D109198 */ "btb-load-ops\000legacy cache\000Branch prediction u= nit read accesses\000legacy-cache-config=3D5\000\00010\000\000\000\000\000" +/* offset=3D109291 */ "btb-load-access\000legacy cache\000Branch predictio= n unit read accesses\000legacy-cache-config=3D5\000\00010\000\000\000\000\0= 00" +/* offset=3D109387 */ "btb-load-misses\000legacy cache\000Branch predictio= n unit read misses\000legacy-cache-config=3D0x10005\000\00010\000\000\000\0= 00\000" +/* offset=3D109487 */ "btb-load-miss\000legacy cache\000Branch prediction = unit read misses\000legacy-cache-config=3D0x10005\000\00010\000\000\000\000= \000" +/* offset=3D109585 */ "btb-loads\000legacy cache\000Branch prediction unit= read accesses\000legacy-cache-config=3D5\000\00010\000\000\000\000\000" +/* offset=3D109675 */ "btb-loads-refs\000legacy cache\000Branch prediction= unit read accesses\000legacy-cache-config=3D5\000\00010\000\000\000\000\00= 0" +/* offset=3D109770 */ "btb-loads-reference\000legacy cache\000Branch predi= ction unit read accesses\000legacy-cache-config=3D5\000\00010\000\000\000\0= 00\000" +/* offset=3D109870 */ "btb-loads-ops\000legacy cache\000Branch prediction = unit read accesses\000legacy-cache-config=3D5\000\00010\000\000\000\000\000" +/* offset=3D109964 */ "btb-loads-access\000legacy cache\000Branch predicti= on unit read accesses\000legacy-cache-config=3D5\000\00010\000\000\000\000\= 000" +/* offset=3D110061 */ "btb-loads-misses\000legacy cache\000Branch predicti= on unit read misses\000legacy-cache-config=3D0x10005\000\00010\000\000\000\= 000\000" +/* offset=3D110162 */ "btb-loads-miss\000legacy cache\000Branch prediction= unit read misses\000legacy-cache-config=3D0x10005\000\00010\000\000\000\00= 0\000" +/* offset=3D110261 */ "btb-read\000legacy cache\000Branch prediction unit = read accesses\000legacy-cache-config=3D5\000\00010\000\000\000\000\000" +/* offset=3D110350 */ "btb-read-refs\000legacy cache\000Branch prediction = unit read accesses\000legacy-cache-config=3D5\000\00010\000\000\000\000\000" +/* offset=3D110444 */ "btb-read-reference\000legacy cache\000Branch predic= tion unit read accesses\000legacy-cache-config=3D5\000\00010\000\000\000\00= 0\000" +/* offset=3D110543 */ "btb-read-ops\000legacy cache\000Branch prediction u= nit read accesses\000legacy-cache-config=3D5\000\00010\000\000\000\000\000" +/* offset=3D110636 */ "btb-read-access\000legacy cache\000Branch predictio= n unit read accesses\000legacy-cache-config=3D5\000\00010\000\000\000\000\0= 00" +/* offset=3D110732 */ "btb-read-misses\000legacy cache\000Branch predictio= n unit read misses\000legacy-cache-config=3D0x10005\000\00010\000\000\000\0= 00\000" +/* offset=3D110832 */ "btb-read-miss\000legacy cache\000Branch prediction = unit read misses\000legacy-cache-config=3D0x10005\000\00010\000\000\000\000= \000" +/* offset=3D110930 */ "btb-refs\000legacy cache\000Branch prediction unit = read accesses\000legacy-cache-config=3D5\000\00010\000\000\000\000\000" +/* offset=3D111019 */ "btb-reference\000legacy cache\000Branch prediction = unit read accesses\000legacy-cache-config=3D5\000\00010\000\000\000\000\000" +/* offset=3D111113 */ "btb-ops\000legacy cache\000Branch prediction unit r= ead accesses\000legacy-cache-config=3D5\000\00010\000\000\000\000\000" +/* offset=3D111201 */ "btb-access\000legacy cache\000Branch prediction uni= t read accesses\000legacy-cache-config=3D5\000\00010\000\000\000\000\000" +/* offset=3D111292 */ "btb-misses\000legacy cache\000Branch prediction uni= t read misses\000legacy-cache-config=3D0x10005\000\00010\000\000\000\000\00= 0" +/* offset=3D111387 */ "btb-miss\000legacy cache\000Branch prediction unit = read misses\000legacy-cache-config=3D0x10005\000\00010\000\000\000\000\000" +/* offset=3D111480 */ "bpc\000legacy cache\000Branch prediction unit read = accesses\000legacy-cache-config=3D5\000\00010\000\000\000\000\000" +/* offset=3D111564 */ "bpc-load\000legacy cache\000Branch prediction unit = read accesses\000legacy-cache-config=3D5\000\00010\000\000\000\000\000" +/* offset=3D111653 */ "bpc-load-refs\000legacy cache\000Branch prediction = unit read accesses\000legacy-cache-config=3D5\000\00010\000\000\000\000\000" +/* offset=3D111747 */ "bpc-load-reference\000legacy cache\000Branch predic= tion unit read accesses\000legacy-cache-config=3D5\000\00010\000\000\000\00= 0\000" +/* offset=3D111846 */ "bpc-load-ops\000legacy cache\000Branch prediction u= nit read accesses\000legacy-cache-config=3D5\000\00010\000\000\000\000\000" +/* offset=3D111939 */ "bpc-load-access\000legacy cache\000Branch predictio= n unit read accesses\000legacy-cache-config=3D5\000\00010\000\000\000\000\0= 00" +/* offset=3D112035 */ "bpc-load-misses\000legacy cache\000Branch predictio= n unit read misses\000legacy-cache-config=3D0x10005\000\00010\000\000\000\0= 00\000" +/* offset=3D112135 */ "bpc-load-miss\000legacy cache\000Branch prediction = unit read misses\000legacy-cache-config=3D0x10005\000\00010\000\000\000\000= \000" +/* offset=3D112233 */ "bpc-loads\000legacy cache\000Branch prediction unit= read accesses\000legacy-cache-config=3D5\000\00010\000\000\000\000\000" +/* offset=3D112323 */ "bpc-loads-refs\000legacy cache\000Branch prediction= unit read accesses\000legacy-cache-config=3D5\000\00010\000\000\000\000\00= 0" +/* offset=3D112418 */ "bpc-loads-reference\000legacy cache\000Branch predi= ction unit read accesses\000legacy-cache-config=3D5\000\00010\000\000\000\0= 00\000" +/* offset=3D112518 */ "bpc-loads-ops\000legacy cache\000Branch prediction = unit read accesses\000legacy-cache-config=3D5\000\00010\000\000\000\000\000" +/* offset=3D112612 */ "bpc-loads-access\000legacy cache\000Branch predicti= on unit read accesses\000legacy-cache-config=3D5\000\00010\000\000\000\000\= 000" +/* offset=3D112709 */ "bpc-loads-misses\000legacy cache\000Branch predicti= on unit read misses\000legacy-cache-config=3D0x10005\000\00010\000\000\000\= 000\000" +/* offset=3D112810 */ "bpc-loads-miss\000legacy cache\000Branch prediction= unit read misses\000legacy-cache-config=3D0x10005\000\00010\000\000\000\00= 0\000" +/* offset=3D112909 */ "bpc-read\000legacy cache\000Branch prediction unit = read accesses\000legacy-cache-config=3D5\000\00010\000\000\000\000\000" +/* offset=3D112998 */ "bpc-read-refs\000legacy cache\000Branch prediction = unit read accesses\000legacy-cache-config=3D5\000\00010\000\000\000\000\000" +/* offset=3D113092 */ "bpc-read-reference\000legacy cache\000Branch predic= tion unit read accesses\000legacy-cache-config=3D5\000\00010\000\000\000\00= 0\000" +/* offset=3D113191 */ "bpc-read-ops\000legacy cache\000Branch prediction u= nit read accesses\000legacy-cache-config=3D5\000\00010\000\000\000\000\000" +/* offset=3D113284 */ "bpc-read-access\000legacy cache\000Branch predictio= n unit read accesses\000legacy-cache-config=3D5\000\00010\000\000\000\000\0= 00" +/* offset=3D113380 */ "bpc-read-misses\000legacy cache\000Branch predictio= n unit read misses\000legacy-cache-config=3D0x10005\000\00010\000\000\000\0= 00\000" +/* offset=3D113480 */ "bpc-read-miss\000legacy cache\000Branch prediction = unit read misses\000legacy-cache-config=3D0x10005\000\00010\000\000\000\000= \000" +/* offset=3D113578 */ "bpc-refs\000legacy cache\000Branch prediction unit = read accesses\000legacy-cache-config=3D5\000\00010\000\000\000\000\000" +/* offset=3D113667 */ "bpc-reference\000legacy cache\000Branch prediction = unit read accesses\000legacy-cache-config=3D5\000\00010\000\000\000\000\000" +/* offset=3D113761 */ "bpc-ops\000legacy cache\000Branch prediction unit r= ead accesses\000legacy-cache-config=3D5\000\00010\000\000\000\000\000" +/* offset=3D113849 */ "bpc-access\000legacy cache\000Branch prediction uni= t read accesses\000legacy-cache-config=3D5\000\00010\000\000\000\000\000" +/* offset=3D113940 */ "bpc-misses\000legacy cache\000Branch prediction uni= t read misses\000legacy-cache-config=3D0x10005\000\00010\000\000\000\000\00= 0" +/* offset=3D114035 */ "bpc-miss\000legacy cache\000Branch prediction unit = read misses\000legacy-cache-config=3D0x10005\000\00010\000\000\000\000\000" +/* offset=3D114128 */ "node\000legacy cache\000Local memory read accesses\= 000legacy-cache-config=3D6\000\00010\000\000\000\000\000" +/* offset=3D114203 */ "node-load\000legacy cache\000Local memory read acce= sses\000legacy-cache-config=3D6\000\00010\000\000\000\000\000" +/* offset=3D114283 */ "node-load-refs\000legacy cache\000Local memory read= accesses\000legacy-cache-config=3D6\000\00010\000\000\000\000\000" +/* offset=3D114368 */ "node-load-reference\000legacy cache\000Local memory= read accesses\000legacy-cache-config=3D6\000\00010\000\000\000\000\000" +/* offset=3D114458 */ "node-load-ops\000legacy cache\000Local memory read = accesses\000legacy-cache-config=3D6\000\00010\000\000\000\000\000" +/* offset=3D114542 */ "node-load-access\000legacy cache\000Local memory re= ad accesses\000legacy-cache-config=3D6\000\00010\000\000\000\000\000" +/* offset=3D114629 */ "node-load-misses\000legacy cache\000Local memory re= ad misses\000legacy-cache-config=3D0x10006\000\00000\000\000\000\000\000" +/* offset=3D114720 */ "node-load-miss\000legacy cache\000Local memory read= misses\000legacy-cache-config=3D0x10006\000\00010\000\000\000\000\000" +/* offset=3D114809 */ "node-loads\000legacy cache\000Local memory read acc= esses\000legacy-cache-config=3D6\000\00000\000\000\000\000\000" +/* offset=3D114890 */ "node-loads-refs\000legacy cache\000Local memory rea= d accesses\000legacy-cache-config=3D6\000\00010\000\000\000\000\000" +/* offset=3D114976 */ "node-loads-reference\000legacy cache\000Local memor= y read accesses\000legacy-cache-config=3D6\000\00010\000\000\000\000\000" +/* offset=3D115067 */ "node-loads-ops\000legacy cache\000Local memory read= accesses\000legacy-cache-config=3D6\000\00010\000\000\000\000\000" +/* offset=3D115152 */ "node-loads-access\000legacy cache\000Local memory r= ead accesses\000legacy-cache-config=3D6\000\00010\000\000\000\000\000" +/* offset=3D115240 */ "node-loads-misses\000legacy cache\000Local memory r= ead misses\000legacy-cache-config=3D0x10006\000\00010\000\000\000\000\000" +/* offset=3D115332 */ "node-loads-miss\000legacy cache\000Local memory rea= d misses\000legacy-cache-config=3D0x10006\000\00010\000\000\000\000\000" +/* offset=3D115422 */ "node-read\000legacy cache\000Local memory read acce= sses\000legacy-cache-config=3D6\000\00010\000\000\000\000\000" +/* offset=3D115502 */ "node-read-refs\000legacy cache\000Local memory read= accesses\000legacy-cache-config=3D6\000\00010\000\000\000\000\000" +/* offset=3D115587 */ "node-read-reference\000legacy cache\000Local memory= read accesses\000legacy-cache-config=3D6\000\00010\000\000\000\000\000" +/* offset=3D115677 */ "node-read-ops\000legacy cache\000Local memory read = accesses\000legacy-cache-config=3D6\000\00010\000\000\000\000\000" +/* offset=3D115761 */ "node-read-access\000legacy cache\000Local memory re= ad accesses\000legacy-cache-config=3D6\000\00010\000\000\000\000\000" +/* offset=3D115848 */ "node-read-misses\000legacy cache\000Local memory re= ad misses\000legacy-cache-config=3D0x10006\000\00010\000\000\000\000\000" +/* offset=3D115939 */ "node-read-miss\000legacy cache\000Local memory read= misses\000legacy-cache-config=3D0x10006\000\00010\000\000\000\000\000" +/* offset=3D116028 */ "node-store\000legacy cache\000Local memory write ac= cesses\000legacy-cache-config=3D0x106\000\00010\000\000\000\000\000" +/* offset=3D116114 */ "node-store-refs\000legacy cache\000Local memory wri= te accesses\000legacy-cache-config=3D0x106\000\00010\000\000\000\000\000" +/* offset=3D116205 */ "node-store-reference\000legacy cache\000Local memor= y write accesses\000legacy-cache-config=3D0x106\000\00010\000\000\000\000\0= 00" +/* offset=3D116301 */ "node-store-ops\000legacy cache\000Local memory writ= e accesses\000legacy-cache-config=3D0x106\000\00010\000\000\000\000\000" +/* offset=3D116391 */ "node-store-access\000legacy cache\000Local memory w= rite accesses\000legacy-cache-config=3D0x106\000\00010\000\000\000\000\000" +/* offset=3D116484 */ "node-store-misses\000legacy cache\000Local memory w= rite misses\000legacy-cache-config=3D0x10106\000\00000\000\000\000\000\000" +/* offset=3D116577 */ "node-store-miss\000legacy cache\000Local memory wri= te misses\000legacy-cache-config=3D0x10106\000\00010\000\000\000\000\000" +/* offset=3D116668 */ "node-stores\000legacy cache\000Local memory write a= ccesses\000legacy-cache-config=3D0x106\000\00000\000\000\000\000\000" +/* offset=3D116755 */ "node-stores-refs\000legacy cache\000Local memory wr= ite accesses\000legacy-cache-config=3D0x106\000\00010\000\000\000\000\000" +/* offset=3D116847 */ "node-stores-reference\000legacy cache\000Local memo= ry write accesses\000legacy-cache-config=3D0x106\000\00010\000\000\000\000\= 000" +/* offset=3D116944 */ "node-stores-ops\000legacy cache\000Local memory wri= te accesses\000legacy-cache-config=3D0x106\000\00010\000\000\000\000\000" +/* offset=3D117035 */ "node-stores-access\000legacy cache\000Local memory = write accesses\000legacy-cache-config=3D0x106\000\00010\000\000\000\000\000" +/* offset=3D117129 */ "node-stores-misses\000legacy cache\000Local memory = write misses\000legacy-cache-config=3D0x10106\000\00010\000\000\000\000\000" +/* offset=3D117223 */ "node-stores-miss\000legacy cache\000Local memory wr= ite misses\000legacy-cache-config=3D0x10106\000\00010\000\000\000\000\000" +/* offset=3D117315 */ "node-write\000legacy cache\000Local memory write ac= cesses\000legacy-cache-config=3D0x106\000\00010\000\000\000\000\000" +/* offset=3D117401 */ "node-write-refs\000legacy cache\000Local memory wri= te accesses\000legacy-cache-config=3D0x106\000\00010\000\000\000\000\000" +/* offset=3D117492 */ "node-write-reference\000legacy cache\000Local memor= y write accesses\000legacy-cache-config=3D0x106\000\00010\000\000\000\000\0= 00" +/* offset=3D117588 */ "node-write-ops\000legacy cache\000Local memory writ= e accesses\000legacy-cache-config=3D0x106\000\00010\000\000\000\000\000" +/* offset=3D117678 */ "node-write-access\000legacy cache\000Local memory w= rite accesses\000legacy-cache-config=3D0x106\000\00010\000\000\000\000\000" +/* offset=3D117771 */ "node-write-misses\000legacy cache\000Local memory w= rite misses\000legacy-cache-config=3D0x10106\000\00010\000\000\000\000\000" +/* offset=3D117864 */ "node-write-miss\000legacy cache\000Local memory wri= te misses\000legacy-cache-config=3D0x10106\000\00010\000\000\000\000\000" +/* offset=3D117955 */ "node-prefetch\000legacy cache\000Local memory prefe= tch accesses\000legacy-cache-config=3D0x206\000\00010\000\000\000\000\000" +/* offset=3D118047 */ "node-prefetch-refs\000legacy cache\000Local memory = prefetch accesses\000legacy-cache-config=3D0x206\000\00010\000\000\000\000\= 000" +/* offset=3D118144 */ "node-prefetch-reference\000legacy cache\000Local me= mory prefetch accesses\000legacy-cache-config=3D0x206\000\00010\000\000\000= \000\000" +/* offset=3D118246 */ "node-prefetch-ops\000legacy cache\000Local memory p= refetch accesses\000legacy-cache-config=3D0x206\000\00010\000\000\000\000\0= 00" +/* offset=3D118342 */ "node-prefetch-access\000legacy cache\000Local memor= y prefetch accesses\000legacy-cache-config=3D0x206\000\00010\000\000\000\00= 0\000" +/* offset=3D118441 */ "node-prefetch-misses\000legacy cache\000Local memor= y prefetch misses\000legacy-cache-config=3D0x10206\000\00000\000\000\000\00= 0\000" +/* offset=3D118540 */ "node-prefetch-miss\000legacy cache\000Local memory = prefetch misses\000legacy-cache-config=3D0x10206\000\00010\000\000\000\000\= 000" +/* offset=3D118637 */ "node-prefetches\000legacy cache\000Local memory pre= fetch accesses\000legacy-cache-config=3D0x206\000\00000\000\000\000\000\000" +/* offset=3D118731 */ "node-prefetches-refs\000legacy cache\000Local memor= y prefetch accesses\000legacy-cache-config=3D0x206\000\00010\000\000\000\00= 0\000" +/* offset=3D118830 */ "node-prefetches-reference\000legacy cache\000Local = memory prefetch accesses\000legacy-cache-config=3D0x206\000\00010\000\000\0= 00\000\000" +/* offset=3D118934 */ "node-prefetches-ops\000legacy cache\000Local memory= prefetch accesses\000legacy-cache-config=3D0x206\000\00010\000\000\000\000= \000" +/* offset=3D119032 */ "node-prefetches-access\000legacy cache\000Local mem= ory prefetch accesses\000legacy-cache-config=3D0x206\000\00010\000\000\000\= 000\000" +/* offset=3D119133 */ "node-prefetches-misses\000legacy cache\000Local mem= ory prefetch misses\000legacy-cache-config=3D0x10206\000\00010\000\000\000\= 000\000" +/* offset=3D119234 */ "node-prefetches-miss\000legacy cache\000Local memor= y prefetch misses\000legacy-cache-config=3D0x10206\000\00010\000\000\000\00= 0\000" +/* offset=3D119333 */ "node-speculative-read\000legacy cache\000Local memo= ry prefetch accesses\000legacy-cache-config=3D0x206\000\00010\000\000\000\0= 00\000" +/* offset=3D119433 */ "node-speculative-read-refs\000legacy cache\000Local= memory prefetch accesses\000legacy-cache-config=3D0x206\000\00010\000\000\= 000\000\000" +/* offset=3D119538 */ "node-speculative-read-reference\000legacy cache\000= Local memory prefetch accesses\000legacy-cache-config=3D0x206\000\00010\000= \000\000\000\000" +/* offset=3D119648 */ "node-speculative-read-ops\000legacy cache\000Local = memory prefetch accesses\000legacy-cache-config=3D0x206\000\00010\000\000\0= 00\000\000" +/* offset=3D119752 */ "node-speculative-read-access\000legacy cache\000Loc= al memory prefetch accesses\000legacy-cache-config=3D0x206\000\00010\000\00= 0\000\000\000" +/* offset=3D119859 */ "node-speculative-read-misses\000legacy cache\000Loc= al memory prefetch misses\000legacy-cache-config=3D0x10206\000\00010\000\00= 0\000\000\000" +/* offset=3D119966 */ "node-speculative-read-miss\000legacy cache\000Local= memory prefetch misses\000legacy-cache-config=3D0x10206\000\00010\000\000\= 000\000\000" +/* offset=3D120071 */ "node-speculative-load\000legacy cache\000Local memo= ry prefetch accesses\000legacy-cache-config=3D0x206\000\00010\000\000\000\0= 00\000" +/* offset=3D120171 */ "node-speculative-load-refs\000legacy cache\000Local= memory prefetch accesses\000legacy-cache-config=3D0x206\000\00010\000\000\= 000\000\000" +/* offset=3D120276 */ "node-speculative-load-reference\000legacy cache\000= Local memory prefetch accesses\000legacy-cache-config=3D0x206\000\00010\000= \000\000\000\000" +/* offset=3D120386 */ "node-speculative-load-ops\000legacy cache\000Local = memory prefetch accesses\000legacy-cache-config=3D0x206\000\00010\000\000\0= 00\000\000" +/* offset=3D120490 */ "node-speculative-load-access\000legacy cache\000Loc= al memory prefetch accesses\000legacy-cache-config=3D0x206\000\00010\000\00= 0\000\000\000" +/* offset=3D120597 */ "node-speculative-load-misses\000legacy cache\000Loc= al memory prefetch misses\000legacy-cache-config=3D0x10206\000\00010\000\00= 0\000\000\000" +/* offset=3D120704 */ "node-speculative-load-miss\000legacy cache\000Local= memory prefetch misses\000legacy-cache-config=3D0x10206\000\00010\000\000\= 000\000\000" +/* offset=3D120809 */ "node-refs\000legacy cache\000Local memory read acce= sses\000legacy-cache-config=3D6\000\00010\000\000\000\000\000" +/* offset=3D120889 */ "node-reference\000legacy cache\000Local memory read= accesses\000legacy-cache-config=3D6\000\00010\000\000\000\000\000" +/* offset=3D120974 */ "node-ops\000legacy cache\000Local memory read acces= ses\000legacy-cache-config=3D6\000\00010\000\000\000\000\000" +/* offset=3D121053 */ "node-access\000legacy cache\000Local memory read ac= cesses\000legacy-cache-config=3D6\000\00010\000\000\000\000\000" +/* offset=3D121135 */ "node-misses\000legacy cache\000Local memory read mi= sses\000legacy-cache-config=3D0x10006\000\00010\000\000\000\000\000" +/* offset=3D121221 */ "node-miss\000legacy cache\000Local memory read miss= es\000legacy-cache-config=3D0x10006\000\00010\000\000\000\000\000" +/* offset=3D121305 */ "cpu-cycles\000legacy hardware\000Total cycles. Be w= ary of what happens during CPU frequency scaling [This event is an alias of= cycles]\000legacy-hardware-config=3D0\000\00000\000\000\000\000\000" +/* offset=3D121467 */ "cycles\000legacy hardware\000Total cycles. Be wary = of what happens during CPU frequency scaling [This event is an alias of cpu= -cycles]\000legacy-hardware-config=3D0\000\00000\000\000\000\000\000" +/* offset=3D121629 */ "instructions\000legacy hardware\000Retired instruct= ions. Be careful, these can be affected by various issues, most notably har= dware interrupt counts\000legacy-hardware-config=3D1\000\00000\000\000\000\= 000\000" +/* offset=3D121805 */ "cache-references\000legacy hardware\000Cache access= es. Usually this indicates Last Level Cache accesses but this may vary depe= nding on your CPU. This may include prefetches and coherency messages; aga= in this depends on the design of your CPU\000legacy-hardware-config=3D2\000= \00000\000\000\000\000\000" +/* offset=3D122075 */ "cache-misses\000legacy hardware\000Cache misses. Us= ually this indicates Last Level Cache misses; this is intended to be used i= n conjunction with the PERF_COUNT_HW_CACHE_REFERENCES event to calculate ca= che miss rates\000legacy-hardware-config=3D3\000\00000\000\000\000\000\000" +/* offset=3D122318 */ "branches\000legacy hardware\000Retired branch instr= uctions [This event is an alias of branch-instructions]\000legacy-hardware-= config=3D4\000\00000\000\000\000\000\000" +/* offset=3D122452 */ "branch-instructions\000legacy hardware\000Retired b= ranch instructions [This event is an alias of branches]\000legacy-hardware-= config=3D4\000\00000\000\000\000\000\000" +/* offset=3D122586 */ "branch-misses\000legacy hardware\000Mispredicted br= anch instructions\000legacy-hardware-config=3D5\000\00000\000\000\000\000\0= 00" +/* offset=3D122682 */ "bus-cycles\000legacy hardware\000Bus cycles, which = can be different from total cycles\000legacy-hardware-config=3D6\000\00000\= 000\000\000\000\000" +/* offset=3D122795 */ "stalled-cycles-frontend\000legacy hardware\000Stall= ed cycles during issue [This event is an alias of idle-cycles-frontend]\000= legacy-hardware-config=3D7\000\00000\000\000\000\000\000" +/* offset=3D122945 */ "idle-cycles-frontend\000legacy hardware\000Stalled = cycles during issue [This event is an alias of stalled-cycles-fronted]\000l= egacy-hardware-config=3D7\000\00000\000\000\000\000\000" +/* offset=3D123094 */ "stalled-cycles-backend\000legacy hardware\000Stalle= d cycles during retirement [This event is an alias of idle-cycles-backend]\= 000legacy-hardware-config=3D8\000\00000\000\000\000\000\000" +/* offset=3D123247 */ "idle-cycles-backend\000legacy hardware\000Stalled c= ycles during retirement [This event is an alias of stalled-cycles-backend]\= 000legacy-hardware-config=3D8\000\00000\000\000\000\000\000" +/* offset=3D123400 */ "ref-cycles\000legacy hardware\000Total cycles; not = affected by CPU frequency scaling\000legacy-hardware-config=3D9\000\00000\0= 00\000\000\000\000" +/* offset=3D123512 */ "software\000" +/* offset=3D123521 */ "cpu-clock\000software\000Per-CPU high-resolution ti= mer based event\000config=3D0\000\00000\000\000\000\000\000" +/* offset=3D123599 */ "task-clock\000software\000Per-task high-resolution = timer based event\000config=3D1\000\00000\000\000\000\000\000" +/* offset=3D123679 */ "faults\000software\000Number of page faults [This e= vent is an alias of page-faults]\000config=3D2\000\00000\000\000\000\000\00= 0" +/* offset=3D123774 */ "page-faults\000software\000Number of page faults [T= his event is an alias of faults]\000config=3D2\000\00000\000\000\000\000\00= 0" +/* offset=3D123869 */ "context-switches\000software\000Number of context s= witches [This event is an alias of cs]\000config=3D3\000\00000\000\000\000\= 000\000" +/* offset=3D123970 */ "cs\000software\000Number of context switches [This = event is an alias of context-switches]\000config=3D3\000\00000\000\000\000\= 000\000" +/* offset=3D124071 */ "cpu-migrations\000software\000Number of times a pro= cess has migrated to a new CPU [This event is an alias of migrations]\000co= nfig=3D4\000\00000\000\000\000\000\000" +/* offset=3D124203 */ "migrations\000software\000Number of times a process= has migrated to a new CPU [This event is an alias of cpu-migrations]\000co= nfig=3D4\000\00000\000\000\000\000\000" +/* offset=3D124335 */ "minor-faults\000software\000Number of minor page fa= ults. Minor faults don't require I/O to handle\000config=3D5\000\00000\000\= 000\000\000\000" +/* offset=3D124444 */ "major-faults\000software\000Number of major page fa= ults. Major faults require I/O to handle\000config=3D6\000\00000\000\000\00= 0\000\000" +/* offset=3D124547 */ "alignment-faults\000software\000Number of kernel ha= ndled memory alignment faults\000config=3D7\000\00000\000\000\000\000\000" +/* offset=3D124639 */ "emulation-faults\000software\000Number of kernel ha= ndled unimplemented instruction faults handled through emulation\000config= =3D8\000\00000\000\000\000\000\000" +/* offset=3D124766 */ "dummy\000software\000A placeholder event that doesn= 't count anything\000config=3D9\000\00000\000\000\000\000\000" +/* offset=3D124846 */ "bpf-output\000software\000An event used by BPF prog= rams to write to the perf ring buffer\000config=3D0xa\000\00000\000\000\000= \000\000" +/* offset=3D124948 */ "cgroup-switches\000software\000Number of context sw= itches to a task in a different cgroup\000config=3D0xb\000\00000\000\000\00= 0\000\000" +/* offset=3D125051 */ "tool\000" +/* offset=3D125056 */ "duration_time\000tool\000Wall clock interval time i= n nanoseconds\000config=3D1\000\00000\000\000\000\000\000" +/* offset=3D125132 */ "user_time\000tool\000User (non-kernel) time in nano= seconds\000config=3D2\000\00000\000\000\000\000\000" +/* offset=3D125202 */ "system_time\000tool\000System/kernel time in nanose= conds\000config=3D3\000\00000\000\000\000\000\000" +/* offset=3D125270 */ "has_pmem\000tool\0001 if persistent memory installe= d otherwise 0\000config=3D4\000\00000\000\000\000\000\000" +/* offset=3D125346 */ "num_cores\000tool\000Number of cores. A core consis= ts of 1 or more thread, with each thread being associated with a logical Li= nux CPU\000config=3D5\000\00000\000\000\000\000\000" +/* offset=3D125491 */ "num_cpus\000tool\000Number of logical Linux CPUs. T= here may be multiple such CPUs on a core\000config=3D6\000\00000\000\000\00= 0\000\000" +/* offset=3D125594 */ "num_cpus_online\000tool\000Number of online logical= Linux CPUs. There may be multiple such CPUs on a core\000config=3D7\000\00= 000\000\000\000\000\000" +/* offset=3D125711 */ "num_dies\000tool\000Number of dies. Each die has 1 = or more cores\000config=3D8\000\00000\000\000\000\000\000" +/* offset=3D125787 */ "num_packages\000tool\000Number of packages. Each pa= ckage has 1 or more die\000config=3D9\000\00000\000\000\000\000\000" +/* offset=3D125873 */ "slots\000tool\000Number of functional units that in= parallel can execute parts of an instruction\000config=3D0xa\000\00000\000= \000\000\000\000" +/* offset=3D125983 */ "smt_on\000tool\0001 if simultaneous multithreading = (aka hyperthreading) is enable otherwise 0\000config=3D0xb\000\00000\000\00= 0\000\000\000" +/* offset=3D126090 */ "system_tsc_freq\000tool\000The amount a Time Stamp = Counter (TSC) increases per second\000config=3D0xc\000\00000\000\000\000\00= 0\000" +/* offset=3D126189 */ "bp_l1_btb_correct\000branch\000L1 BTB Correction\00= 0event=3D0x8a\000\00000\000\000\000\000\000" +/* offset=3D126251 */ "bp_l2_btb_correct\000branch\000L2 BTB Correction\00= 0event=3D0x8b\000\00000\000\000\000\000\000" +/* offset=3D126313 */ "l3_cache_rd\000cache\000L3 cache access, read\000ev= ent=3D0x40\000\00000\000\000\000\000Attributable Level 3 cache access, read= \000" +/* offset=3D126411 */ "segment_reg_loads.any\000other\000Number of segment= register loads\000event=3D6,period=3D200000,umask=3D0x80\000\00000\000\000= \000\000\000" +/* offset=3D126513 */ "dispatch_blocked.any\000other\000Memory cluster sig= nals to block micro-op dispatch for any reason\000event=3D9,period=3D200000= ,umask=3D0x20\000\00000\000\000\000\000\000" +/* offset=3D126646 */ "eist_trans\000other\000Number of Enhanced Intel Spe= edStep(R) Technology (EIST) transitions\000event=3D0x3a,period=3D200000\000= \00000\000\000\000\000\000" +/* offset=3D126764 */ "hisi_sccl,ddrc\000" +/* offset=3D126779 */ "uncore_hisi_ddrc.flux_wcmd\000uncore\000DDRC write = commands\000event=3D2\000\00000\000\000\000\000\000" +/* offset=3D126849 */ "uncore_cbox\000" +/* offset=3D126861 */ "unc_cbo_xsnp_response.miss_eviction\000uncore\000A = cross-core snoop resulted from L3 Eviction which misses in some processor c= ore\000event=3D0x22,umask=3D0x81\000\00000\000\000\000\000\000" +/* offset=3D127015 */ "event-hyphen\000uncore\000UNC_CBO_HYPHEN\000event= =3D0xe0\000\00000\000\000\000\000\000" +/* offset=3D127069 */ "event-two-hyph\000uncore\000UNC_CBO_TWO_HYPH\000eve= nt=3D0xc0\000\00000\000\000\000\000\000" +/* offset=3D127127 */ "hisi_sccl,l3c\000" +/* offset=3D127141 */ "uncore_hisi_l3c.rd_hit_cpipe\000uncore\000Total rea= d hits\000event=3D7\000\00000\000\000\000\000\000" +/* offset=3D127209 */ "uncore_imc_free_running\000" +/* offset=3D127233 */ "uncore_imc_free_running.cache_miss\000uncore\000Tot= al cache misses\000event=3D0x12\000\00000\000\000\000\000\000" +/* offset=3D127313 */ "uncore_imc\000" +/* offset=3D127324 */ "uncore_imc.cache_hits\000uncore\000Total cache hits= \000event=3D0x34\000\00000\000\000\000\000\000" +/* offset=3D127389 */ "uncore_sys_ddr_pmu\000" +/* offset=3D127408 */ "sys_ddr_pmu.write_cycles\000uncore\000ddr write-cyc= les event\000event=3D0x2b\000v8\00000\000\000\000\000\000" +/* offset=3D127484 */ "uncore_sys_ccn_pmu\000" +/* offset=3D127503 */ "sys_ccn_pmu.read_cycles\000uncore\000ccn read-cycle= s event\000config=3D0x2c\0000x01\00000\000\000\000\000\000" +/* offset=3D127580 */ "uncore_sys_cmn_pmu\000" +/* offset=3D127599 */ "sys_cmn_pmu.hnf_cache_miss\000uncore\000Counts tota= l cache misses in first lookup result (high priority)\000eventid=3D1,type= =3D5\000(434|436|43c|43a).*\00000\000\000\000\000\000" +/* offset=3D127742 */ "CPI\000\0001 / IPC\000\000\000\000\000\000\000\0000= 0" +/* offset=3D127764 */ "IPC\000group1\000inst_retired.any / cpu_clk_unhalte= d.thread\000\000\000\000\000\000\000\00000" +/* offset=3D127827 */ "Frontend_Bound_SMT\000\000idq_uops_not_delivered.co= re / (4 * (cpu_clk_unhalted.thread / 2 * (1 + cpu_clk_unhalted.one_thread_a= ctive / cpu_clk_unhalted.ref_xclk)))\000\000\000\000\000\000\000\00000" +/* offset=3D127993 */ "dcache_miss_cpi\000\000l1d\\-loads\\-misses / inst_= retired.any\000\000\000\000\000\000\000\00000" +/* offset=3D128057 */ "icache_miss_cycles\000\000l1i\\-loads\\-misses / in= st_retired.any\000\000\000\000\000\000\000\00000" +/* offset=3D128124 */ "cache_miss_cycles\000group1\000dcache_miss_cpi + ic= ache_miss_cycles\000\000\000\000\000\000\000\00000" +/* offset=3D128195 */ "DCache_L2_All_Hits\000\000l2_rqsts.demand_data_rd_h= it + l2_rqsts.pf_hit + l2_rqsts.rfo_hit\000\000\000\000\000\000\000\00000" +/* offset=3D128289 */ "DCache_L2_All_Miss\000\000max(l2_rqsts.all_demand_d= ata_rd - l2_rqsts.demand_data_rd_hit, 0) + l2_rqsts.pf_miss + l2_rqsts.rfo_= miss\000\000\000\000\000\000\000\00000" +/* offset=3D128423 */ "DCache_L2_All\000\000DCache_L2_All_Hits + DCache_L2= _All_Miss\000\000\000\000\000\000\000\00000" +/* offset=3D128487 */ "DCache_L2_Hits\000\000d_ratio(DCache_L2_All_Hits, D= Cache_L2_All)\000\000\000\000\000\000\000\00000" +/* offset=3D128555 */ "DCache_L2_Misses\000\000d_ratio(DCache_L2_All_Miss,= DCache_L2_All)\000\000\000\000\000\000\000\00000" +/* offset=3D128625 */ "M1\000\000ipc + M2\000\000\000\000\000\000\000\0000= 0" +/* offset=3D128647 */ "M2\000\000ipc + M1\000\000\000\000\000\000\000\0000= 0" +/* offset=3D128669 */ "M3\000\0001 / M3\000\000\000\000\000\000\000\00000" +/* offset=3D128689 */ "L1D_Cache_Fill_BW\000\00064 * l1d.replacement / 1e9= / duration_time\000\000\000\000\000\000\000\00000" ; =20 +static const struct compact_pmu_event pmu_events__common_default_core[] = =3D { +{ 111480 }, /* bpc\000legacy cache\000Branch prediction unit read accesses= \000legacy-cache-config=3D5\000\00010\000\000\000\000\000 */ +{ 113849 }, /* bpc-access\000legacy cache\000Branch prediction unit read a= ccesses\000legacy-cache-config=3D5\000\00010\000\000\000\000\000 */ +{ 111564 }, /* bpc-load\000legacy cache\000Branch prediction unit read acc= esses\000legacy-cache-config=3D5\000\00010\000\000\000\000\000 */ +{ 111939 }, /* bpc-load-access\000legacy cache\000Branch prediction unit r= ead accesses\000legacy-cache-config=3D5\000\00010\000\000\000\000\000 */ +{ 112135 }, /* bpc-load-miss\000legacy cache\000Branch prediction unit rea= d misses\000legacy-cache-config=3D0x10005\000\00010\000\000\000\000\000 */ +{ 112035 }, /* bpc-load-misses\000legacy cache\000Branch prediction unit r= ead misses\000legacy-cache-config=3D0x10005\000\00010\000\000\000\000\000 */ +{ 111846 }, /* bpc-load-ops\000legacy cache\000Branch prediction unit read= accesses\000legacy-cache-config=3D5\000\00010\000\000\000\000\000 */ +{ 111747 }, /* bpc-load-reference\000legacy cache\000Branch prediction uni= t read accesses\000legacy-cache-config=3D5\000\00010\000\000\000\000\000 */ +{ 111653 }, /* bpc-load-refs\000legacy cache\000Branch prediction unit rea= d accesses\000legacy-cache-config=3D5\000\00010\000\000\000\000\000 */ +{ 112233 }, /* bpc-loads\000legacy cache\000Branch prediction unit read ac= cesses\000legacy-cache-config=3D5\000\00010\000\000\000\000\000 */ +{ 112612 }, /* bpc-loads-access\000legacy cache\000Branch prediction unit = read accesses\000legacy-cache-config=3D5\000\00010\000\000\000\000\000 */ +{ 112810 }, /* bpc-loads-miss\000legacy cache\000Branch prediction unit re= ad misses\000legacy-cache-config=3D0x10005\000\00010\000\000\000\000\000 */ +{ 112709 }, /* bpc-loads-misses\000legacy cache\000Branch prediction unit = read misses\000legacy-cache-config=3D0x10005\000\00010\000\000\000\000\000 = */ +{ 112518 }, /* bpc-loads-ops\000legacy cache\000Branch prediction unit rea= d accesses\000legacy-cache-config=3D5\000\00010\000\000\000\000\000 */ +{ 112418 }, /* bpc-loads-reference\000legacy cache\000Branch prediction un= it read accesses\000legacy-cache-config=3D5\000\00010\000\000\000\000\000 */ +{ 112323 }, /* bpc-loads-refs\000legacy cache\000Branch prediction unit re= ad accesses\000legacy-cache-config=3D5\000\00010\000\000\000\000\000 */ +{ 114035 }, /* bpc-miss\000legacy cache\000Branch prediction unit read mis= ses\000legacy-cache-config=3D0x10005\000\00010\000\000\000\000\000 */ +{ 113940 }, /* bpc-misses\000legacy cache\000Branch prediction unit read m= isses\000legacy-cache-config=3D0x10005\000\00010\000\000\000\000\000 */ +{ 113761 }, /* bpc-ops\000legacy cache\000Branch prediction unit read acce= sses\000legacy-cache-config=3D5\000\00010\000\000\000\000\000 */ +{ 112909 }, /* bpc-read\000legacy cache\000Branch prediction unit read acc= esses\000legacy-cache-config=3D5\000\00010\000\000\000\000\000 */ +{ 113284 }, /* bpc-read-access\000legacy cache\000Branch prediction unit r= ead accesses\000legacy-cache-config=3D5\000\00010\000\000\000\000\000 */ +{ 113480 }, /* bpc-read-miss\000legacy cache\000Branch prediction unit rea= d misses\000legacy-cache-config=3D0x10005\000\00010\000\000\000\000\000 */ +{ 113380 }, /* bpc-read-misses\000legacy cache\000Branch prediction unit r= ead misses\000legacy-cache-config=3D0x10005\000\00010\000\000\000\000\000 */ +{ 113191 }, /* bpc-read-ops\000legacy cache\000Branch prediction unit read= accesses\000legacy-cache-config=3D5\000\00010\000\000\000\000\000 */ +{ 113092 }, /* bpc-read-reference\000legacy cache\000Branch prediction uni= t read accesses\000legacy-cache-config=3D5\000\00010\000\000\000\000\000 */ +{ 112998 }, /* bpc-read-refs\000legacy cache\000Branch prediction unit rea= d accesses\000legacy-cache-config=3D5\000\00010\000\000\000\000\000 */ +{ 113667 }, /* bpc-reference\000legacy cache\000Branch prediction unit rea= d accesses\000legacy-cache-config=3D5\000\00010\000\000\000\000\000 */ +{ 113578 }, /* bpc-refs\000legacy cache\000Branch prediction unit read acc= esses\000legacy-cache-config=3D5\000\00010\000\000\000\000\000 */ +{ 106184 }, /* bpu\000legacy cache\000Branch prediction unit read accesses= \000legacy-cache-config=3D5\000\00010\000\000\000\000\000 */ +{ 108553 }, /* bpu-access\000legacy cache\000Branch prediction unit read a= ccesses\000legacy-cache-config=3D5\000\00010\000\000\000\000\000 */ +{ 106268 }, /* bpu-load\000legacy cache\000Branch prediction unit read acc= esses\000legacy-cache-config=3D5\000\00010\000\000\000\000\000 */ +{ 106643 }, /* bpu-load-access\000legacy cache\000Branch prediction unit r= ead accesses\000legacy-cache-config=3D5\000\00010\000\000\000\000\000 */ +{ 106839 }, /* bpu-load-miss\000legacy cache\000Branch prediction unit rea= d misses\000legacy-cache-config=3D0x10005\000\00010\000\000\000\000\000 */ +{ 106739 }, /* bpu-load-misses\000legacy cache\000Branch prediction unit r= ead misses\000legacy-cache-config=3D0x10005\000\00010\000\000\000\000\000 */ +{ 106550 }, /* bpu-load-ops\000legacy cache\000Branch prediction unit read= accesses\000legacy-cache-config=3D5\000\00010\000\000\000\000\000 */ +{ 106451 }, /* bpu-load-reference\000legacy cache\000Branch prediction uni= t read accesses\000legacy-cache-config=3D5\000\00010\000\000\000\000\000 */ +{ 106357 }, /* bpu-load-refs\000legacy cache\000Branch prediction unit rea= d accesses\000legacy-cache-config=3D5\000\00010\000\000\000\000\000 */ +{ 106937 }, /* bpu-loads\000legacy cache\000Branch prediction unit read ac= cesses\000legacy-cache-config=3D5\000\00010\000\000\000\000\000 */ +{ 107316 }, /* bpu-loads-access\000legacy cache\000Branch prediction unit = read accesses\000legacy-cache-config=3D5\000\00010\000\000\000\000\000 */ +{ 107514 }, /* bpu-loads-miss\000legacy cache\000Branch prediction unit re= ad misses\000legacy-cache-config=3D0x10005\000\00010\000\000\000\000\000 */ +{ 107413 }, /* bpu-loads-misses\000legacy cache\000Branch prediction unit = read misses\000legacy-cache-config=3D0x10005\000\00010\000\000\000\000\000 = */ +{ 107222 }, /* bpu-loads-ops\000legacy cache\000Branch prediction unit rea= d accesses\000legacy-cache-config=3D5\000\00010\000\000\000\000\000 */ +{ 107122 }, /* bpu-loads-reference\000legacy cache\000Branch prediction un= it read accesses\000legacy-cache-config=3D5\000\00010\000\000\000\000\000 */ +{ 107027 }, /* bpu-loads-refs\000legacy cache\000Branch prediction unit re= ad accesses\000legacy-cache-config=3D5\000\00010\000\000\000\000\000 */ +{ 108739 }, /* bpu-miss\000legacy cache\000Branch prediction unit read mis= ses\000legacy-cache-config=3D0x10005\000\00010\000\000\000\000\000 */ +{ 108644 }, /* bpu-misses\000legacy cache\000Branch prediction unit read m= isses\000legacy-cache-config=3D0x10005\000\00010\000\000\000\000\000 */ +{ 108465 }, /* bpu-ops\000legacy cache\000Branch prediction unit read acce= sses\000legacy-cache-config=3D5\000\00010\000\000\000\000\000 */ +{ 107613 }, /* bpu-read\000legacy cache\000Branch prediction unit read acc= esses\000legacy-cache-config=3D5\000\00010\000\000\000\000\000 */ +{ 107988 }, /* bpu-read-access\000legacy cache\000Branch prediction unit r= ead accesses\000legacy-cache-config=3D5\000\00010\000\000\000\000\000 */ +{ 108184 }, /* bpu-read-miss\000legacy cache\000Branch prediction unit rea= d misses\000legacy-cache-config=3D0x10005\000\00010\000\000\000\000\000 */ +{ 108084 }, /* bpu-read-misses\000legacy cache\000Branch prediction unit r= ead misses\000legacy-cache-config=3D0x10005\000\00010\000\000\000\000\000 */ +{ 107895 }, /* bpu-read-ops\000legacy cache\000Branch prediction unit read= accesses\000legacy-cache-config=3D5\000\00010\000\000\000\000\000 */ +{ 107796 }, /* bpu-read-reference\000legacy cache\000Branch prediction uni= t read accesses\000legacy-cache-config=3D5\000\00010\000\000\000\000\000 */ +{ 107702 }, /* bpu-read-refs\000legacy cache\000Branch prediction unit rea= d accesses\000legacy-cache-config=3D5\000\00010\000\000\000\000\000 */ +{ 108371 }, /* bpu-reference\000legacy cache\000Branch prediction unit rea= d accesses\000legacy-cache-config=3D5\000\00010\000\000\000\000\000 */ +{ 108282 }, /* bpu-refs\000legacy cache\000Branch prediction unit read acc= esses\000legacy-cache-config=3D5\000\00010\000\000\000\000\000 */ +{ 100851 }, /* branch\000legacy cache\000Branch prediction unit read acces= ses\000legacy-cache-config=3D5\000\00010\000\000\000\000\000 */ +{ 103295 }, /* branch-access\000legacy cache\000Branch prediction unit rea= d accesses\000legacy-cache-config=3D5\000\00010\000\000\000\000\000 */ +{ 122452 }, /* branch-instructions\000legacy hardware\000Retired branch in= structions [This event is an alias of branches]\000legacy-hardware-config= =3D4\000\00000\000\000\000\000\000 */ +{ 100938 }, /* branch-load\000legacy cache\000Branch prediction unit read = accesses\000legacy-cache-config=3D5\000\00010\000\000\000\000\000 */ +{ 101325 }, /* branch-load-access\000legacy cache\000Branch prediction uni= t read accesses\000legacy-cache-config=3D5\000\00010\000\000\000\000\000 */ +{ 101527 }, /* branch-load-miss\000legacy cache\000Branch prediction unit = read misses\000legacy-cache-config=3D0x10005\000\00010\000\000\000\000\000 = */ +{ 101424 }, /* branch-load-misses\000legacy cache\000Branch prediction uni= t read misses\000legacy-cache-config=3D0x10005\000\00000\000\000\000\000\00= 0 */ +{ 101229 }, /* branch-load-ops\000legacy cache\000Branch prediction unit r= ead accesses\000legacy-cache-config=3D5\000\00010\000\000\000\000\000 */ +{ 101127 }, /* branch-load-reference\000legacy cache\000Branch prediction = unit read accesses\000legacy-cache-config=3D5\000\00010\000\000\000\000\000= */ +{ 101030 }, /* branch-load-refs\000legacy cache\000Branch prediction unit = read accesses\000legacy-cache-config=3D5\000\00010\000\000\000\000\000 */ +{ 101628 }, /* branch-loads\000legacy cache\000Branch prediction unit read= accesses\000legacy-cache-config=3D5\000\00000\000\000\000\000\000 */ +{ 102019 }, /* branch-loads-access\000legacy cache\000Branch prediction un= it read accesses\000legacy-cache-config=3D5\000\00010\000\000\000\000\000 */ +{ 102223 }, /* branch-loads-miss\000legacy cache\000Branch prediction unit= read misses\000legacy-cache-config=3D0x10005\000\00010\000\000\000\000\000= */ +{ 102119 }, /* branch-loads-misses\000legacy cache\000Branch prediction un= it read misses\000legacy-cache-config=3D0x10005\000\00010\000\000\000\000\0= 00 */ +{ 101922 }, /* branch-loads-ops\000legacy cache\000Branch prediction unit = read accesses\000legacy-cache-config=3D5\000\00010\000\000\000\000\000 */ +{ 101819 }, /* branch-loads-reference\000legacy cache\000Branch prediction= unit read accesses\000legacy-cache-config=3D5\000\00010\000\000\000\000\00= 0 */ +{ 101721 }, /* branch-loads-refs\000legacy cache\000Branch prediction unit= read accesses\000legacy-cache-config=3D5\000\00010\000\000\000\000\000 */ +{ 103389 }, /* branch-miss\000legacy cache\000Branch prediction unit read = misses\000legacy-cache-config=3D0x10005\000\00010\000\000\000\000\000 */ +{ 122586 }, /* branch-misses\000legacy hardware\000Mispredicted branch ins= tructions\000legacy-hardware-config=3D5\000\00000\000\000\000\000\000 */ +{ 103204 }, /* branch-ops\000legacy cache\000Branch prediction unit read a= ccesses\000legacy-cache-config=3D5\000\00010\000\000\000\000\000 */ +{ 102325 }, /* branch-read\000legacy cache\000Branch prediction unit read = accesses\000legacy-cache-config=3D5\000\00010\000\000\000\000\000 */ +{ 102712 }, /* branch-read-access\000legacy cache\000Branch prediction uni= t read accesses\000legacy-cache-config=3D5\000\00010\000\000\000\000\000 */ +{ 102914 }, /* branch-read-miss\000legacy cache\000Branch prediction unit = read misses\000legacy-cache-config=3D0x10005\000\00010\000\000\000\000\000 = */ +{ 102811 }, /* branch-read-misses\000legacy cache\000Branch prediction uni= t read misses\000legacy-cache-config=3D0x10005\000\00010\000\000\000\000\00= 0 */ +{ 102616 }, /* branch-read-ops\000legacy cache\000Branch prediction unit r= ead accesses\000legacy-cache-config=3D5\000\00010\000\000\000\000\000 */ +{ 102514 }, /* branch-read-reference\000legacy cache\000Branch prediction = unit read accesses\000legacy-cache-config=3D5\000\00010\000\000\000\000\000= */ +{ 102417 }, /* branch-read-refs\000legacy cache\000Branch prediction unit = read accesses\000legacy-cache-config=3D5\000\00010\000\000\000\000\000 */ +{ 103107 }, /* branch-reference\000legacy cache\000Branch prediction unit = read accesses\000legacy-cache-config=3D5\000\00010\000\000\000\000\000 */ +{ 103015 }, /* branch-refs\000legacy cache\000Branch prediction unit read = accesses\000legacy-cache-config=3D5\000\00010\000\000\000\000\000 */ +{ 122318 }, /* branches\000legacy hardware\000Retired branch instructions = [This event is an alias of branch-instructions]\000legacy-hardware-config= =3D4\000\00000\000\000\000\000\000 */ +{ 105890 }, /* branches-access\000legacy cache\000Branch prediction unit r= ead accesses\000legacy-cache-config=3D5\000\00010\000\000\000\000\000 */ +{ 103485 }, /* branches-load\000legacy cache\000Branch prediction unit rea= d accesses\000legacy-cache-config=3D5\000\00010\000\000\000\000\000 */ +{ 103880 }, /* branches-load-access\000legacy cache\000Branch prediction u= nit read accesses\000legacy-cache-config=3D5\000\00010\000\000\000\000\000 = */ +{ 104086 }, /* branches-load-miss\000legacy cache\000Branch prediction uni= t read misses\000legacy-cache-config=3D0x10005\000\00010\000\000\000\000\00= 0 */ +{ 103981 }, /* branches-load-misses\000legacy cache\000Branch prediction u= nit read misses\000legacy-cache-config=3D0x10005\000\00010\000\000\000\000\= 000 */ +{ 103782 }, /* branches-load-ops\000legacy cache\000Branch prediction unit= read accesses\000legacy-cache-config=3D5\000\00010\000\000\000\000\000 */ +{ 103678 }, /* branches-load-reference\000legacy cache\000Branch predictio= n unit read accesses\000legacy-cache-config=3D5\000\00010\000\000\000\000\0= 00 */ +{ 103579 }, /* branches-load-refs\000legacy cache\000Branch prediction uni= t read accesses\000legacy-cache-config=3D5\000\00010\000\000\000\000\000 */ +{ 104189 }, /* branches-loads\000legacy cache\000Branch prediction unit re= ad accesses\000legacy-cache-config=3D5\000\00010\000\000\000\000\000 */ +{ 104588 }, /* branches-loads-access\000legacy cache\000Branch prediction = unit read accesses\000legacy-cache-config=3D5\000\00010\000\000\000\000\000= */ +{ 104796 }, /* branches-loads-miss\000legacy cache\000Branch prediction un= it read misses\000legacy-cache-config=3D0x10005\000\00010\000\000\000\000\0= 00 */ +{ 104690 }, /* branches-loads-misses\000legacy cache\000Branch prediction = unit read misses\000legacy-cache-config=3D0x10005\000\00010\000\000\000\000= \000 */ +{ 104489 }, /* branches-loads-ops\000legacy cache\000Branch prediction uni= t read accesses\000legacy-cache-config=3D5\000\00010\000\000\000\000\000 */ +{ 104384 }, /* branches-loads-reference\000legacy cache\000Branch predicti= on unit read accesses\000legacy-cache-config=3D5\000\00010\000\000\000\000\= 000 */ +{ 104284 }, /* branches-loads-refs\000legacy cache\000Branch prediction un= it read accesses\000legacy-cache-config=3D5\000\00010\000\000\000\000\000 */ +{ 106086 }, /* branches-miss\000legacy cache\000Branch prediction unit rea= d misses\000legacy-cache-config=3D0x10005\000\00010\000\000\000\000\000 */ +{ 105986 }, /* branches-misses\000legacy cache\000Branch prediction unit r= ead misses\000legacy-cache-config=3D0x10005\000\00010\000\000\000\000\000 */ +{ 105797 }, /* branches-ops\000legacy cache\000Branch prediction unit read= accesses\000legacy-cache-config=3D5\000\00010\000\000\000\000\000 */ +{ 104900 }, /* branches-read\000legacy cache\000Branch prediction unit rea= d accesses\000legacy-cache-config=3D5\000\00010\000\000\000\000\000 */ +{ 105295 }, /* branches-read-access\000legacy cache\000Branch prediction u= nit read accesses\000legacy-cache-config=3D5\000\00010\000\000\000\000\000 = */ +{ 105501 }, /* branches-read-miss\000legacy cache\000Branch prediction uni= t read misses\000legacy-cache-config=3D0x10005\000\00010\000\000\000\000\00= 0 */ +{ 105396 }, /* branches-read-misses\000legacy cache\000Branch prediction u= nit read misses\000legacy-cache-config=3D0x10005\000\00010\000\000\000\000\= 000 */ +{ 105197 }, /* branches-read-ops\000legacy cache\000Branch prediction unit= read accesses\000legacy-cache-config=3D5\000\00010\000\000\000\000\000 */ +{ 105093 }, /* branches-read-reference\000legacy cache\000Branch predictio= n unit read accesses\000legacy-cache-config=3D5\000\00010\000\000\000\000\0= 00 */ +{ 104994 }, /* branches-read-refs\000legacy cache\000Branch prediction uni= t read accesses\000legacy-cache-config=3D5\000\00010\000\000\000\000\000 */ +{ 105698 }, /* branches-reference\000legacy cache\000Branch prediction uni= t read accesses\000legacy-cache-config=3D5\000\00010\000\000\000\000\000 */ +{ 105604 }, /* branches-refs\000legacy cache\000Branch prediction unit rea= d accesses\000legacy-cache-config=3D5\000\00010\000\000\000\000\000 */ +{ 108832 }, /* btb\000legacy cache\000Branch prediction unit read accesses= \000legacy-cache-config=3D5\000\00010\000\000\000\000\000 */ +{ 111201 }, /* btb-access\000legacy cache\000Branch prediction unit read a= ccesses\000legacy-cache-config=3D5\000\00010\000\000\000\000\000 */ +{ 108916 }, /* btb-load\000legacy cache\000Branch prediction unit read acc= esses\000legacy-cache-config=3D5\000\00010\000\000\000\000\000 */ +{ 109291 }, /* btb-load-access\000legacy cache\000Branch prediction unit r= ead accesses\000legacy-cache-config=3D5\000\00010\000\000\000\000\000 */ +{ 109487 }, /* btb-load-miss\000legacy cache\000Branch prediction unit rea= d misses\000legacy-cache-config=3D0x10005\000\00010\000\000\000\000\000 */ +{ 109387 }, /* btb-load-misses\000legacy cache\000Branch prediction unit r= ead misses\000legacy-cache-config=3D0x10005\000\00010\000\000\000\000\000 */ +{ 109198 }, /* btb-load-ops\000legacy cache\000Branch prediction unit read= accesses\000legacy-cache-config=3D5\000\00010\000\000\000\000\000 */ +{ 109099 }, /* btb-load-reference\000legacy cache\000Branch prediction uni= t read accesses\000legacy-cache-config=3D5\000\00010\000\000\000\000\000 */ +{ 109005 }, /* btb-load-refs\000legacy cache\000Branch prediction unit rea= d accesses\000legacy-cache-config=3D5\000\00010\000\000\000\000\000 */ +{ 109585 }, /* btb-loads\000legacy cache\000Branch prediction unit read ac= cesses\000legacy-cache-config=3D5\000\00010\000\000\000\000\000 */ +{ 109964 }, /* btb-loads-access\000legacy cache\000Branch prediction unit = read accesses\000legacy-cache-config=3D5\000\00010\000\000\000\000\000 */ +{ 110162 }, /* btb-loads-miss\000legacy cache\000Branch prediction unit re= ad misses\000legacy-cache-config=3D0x10005\000\00010\000\000\000\000\000 */ +{ 110061 }, /* btb-loads-misses\000legacy cache\000Branch prediction unit = read misses\000legacy-cache-config=3D0x10005\000\00010\000\000\000\000\000 = */ +{ 109870 }, /* btb-loads-ops\000legacy cache\000Branch prediction unit rea= d accesses\000legacy-cache-config=3D5\000\00010\000\000\000\000\000 */ +{ 109770 }, /* btb-loads-reference\000legacy cache\000Branch prediction un= it read accesses\000legacy-cache-config=3D5\000\00010\000\000\000\000\000 */ +{ 109675 }, /* btb-loads-refs\000legacy cache\000Branch prediction unit re= ad accesses\000legacy-cache-config=3D5\000\00010\000\000\000\000\000 */ +{ 111387 }, /* btb-miss\000legacy cache\000Branch prediction unit read mis= ses\000legacy-cache-config=3D0x10005\000\00010\000\000\000\000\000 */ +{ 111292 }, /* btb-misses\000legacy cache\000Branch prediction unit read m= isses\000legacy-cache-config=3D0x10005\000\00010\000\000\000\000\000 */ +{ 111113 }, /* btb-ops\000legacy cache\000Branch prediction unit read acce= sses\000legacy-cache-config=3D5\000\00010\000\000\000\000\000 */ +{ 110261 }, /* btb-read\000legacy cache\000Branch prediction unit read acc= esses\000legacy-cache-config=3D5\000\00010\000\000\000\000\000 */ +{ 110636 }, /* btb-read-access\000legacy cache\000Branch prediction unit r= ead accesses\000legacy-cache-config=3D5\000\00010\000\000\000\000\000 */ +{ 110832 }, /* btb-read-miss\000legacy cache\000Branch prediction unit rea= d misses\000legacy-cache-config=3D0x10005\000\00010\000\000\000\000\000 */ +{ 110732 }, /* btb-read-misses\000legacy cache\000Branch prediction unit r= ead misses\000legacy-cache-config=3D0x10005\000\00010\000\000\000\000\000 */ +{ 110543 }, /* btb-read-ops\000legacy cache\000Branch prediction unit read= accesses\000legacy-cache-config=3D5\000\00010\000\000\000\000\000 */ +{ 110444 }, /* btb-read-reference\000legacy cache\000Branch prediction uni= t read accesses\000legacy-cache-config=3D5\000\00010\000\000\000\000\000 */ +{ 110350 }, /* btb-read-refs\000legacy cache\000Branch prediction unit rea= d accesses\000legacy-cache-config=3D5\000\00010\000\000\000\000\000 */ +{ 111019 }, /* btb-reference\000legacy cache\000Branch prediction unit rea= d accesses\000legacy-cache-config=3D5\000\00010\000\000\000\000\000 */ +{ 110930 }, /* btb-refs\000legacy cache\000Branch prediction unit read acc= esses\000legacy-cache-config=3D5\000\00010\000\000\000\000\000 */ +{ 122682 }, /* bus-cycles\000legacy hardware\000Bus cycles, which can be d= ifferent from total cycles\000legacy-hardware-config=3D6\000\00000\000\000\= 000\000\000 */ +{ 122075 }, /* cache-misses\000legacy hardware\000Cache misses. Usually th= is indicates Last Level Cache misses; this is intended to be used in conjun= ction with the PERF_COUNT_HW_CACHE_REFERENCES event to calculate cache miss= rates\000legacy-hardware-config=3D3\000\00000\000\000\000\000\000 */ +{ 121805 }, /* cache-references\000legacy hardware\000Cache accesses. Usua= lly this indicates Last Level Cache accesses but this may vary depending on= your CPU. This may include prefetches and coherency messages; again this = depends on the design of your CPU\000legacy-hardware-config=3D2\000\00000\0= 00\000\000\000\000 */ +{ 121305 }, /* cpu-cycles\000legacy hardware\000Total cycles. Be wary of w= hat happens during CPU frequency scaling [This event is an alias of cycles]= \000legacy-hardware-config=3D0\000\00000\000\000\000\000\000 */ +{ 121467 }, /* cycles\000legacy hardware\000Total cycles. Be wary of what = happens during CPU frequency scaling [This event is an alias of cpu-cycles]= \000legacy-hardware-config=3D0\000\00000\000\000\000\000\000 */ +{ 78952 }, /* d-tlb\000legacy cache\000Data TLB read accesses\000legacy-ca= che-config=3D3\000\00010\000\000\000\000\000 */ +{ 85655 }, /* d-tlb-access\000legacy cache\000Data TLB read accesses\000le= gacy-cache-config=3D3\000\00010\000\000\000\000\000 */ +{ 79024 }, /* d-tlb-load\000legacy cache\000Data TLB read accesses\000lega= cy-cache-config=3D3\000\00010\000\000\000\000\000 */ +{ 79351 }, /* d-tlb-load-access\000legacy cache\000Data TLB read accesses\= 000legacy-cache-config=3D3\000\00010\000\000\000\000\000 */ +{ 79523 }, /* d-tlb-load-miss\000legacy cache\000Data TLB read misses\000l= egacy-cache-config=3D0x10003\000\00010\000\000\000\000\000 */ +{ 79435 }, /* d-tlb-load-misses\000legacy cache\000Data TLB read misses\00= 0legacy-cache-config=3D0x10003\000\00010\000\000\000\000\000 */ +{ 79270 }, /* d-tlb-load-ops\000legacy cache\000Data TLB read accesses\000= legacy-cache-config=3D3\000\00010\000\000\000\000\000 */ +{ 79183 }, /* d-tlb-load-reference\000legacy cache\000Data TLB read access= es\000legacy-cache-config=3D3\000\00010\000\000\000\000\000 */ +{ 79101 }, /* d-tlb-load-refs\000legacy cache\000Data TLB read accesses\00= 0legacy-cache-config=3D3\000\00010\000\000\000\000\000 */ +{ 79609 }, /* d-tlb-loads\000legacy cache\000Data TLB read accesses\000leg= acy-cache-config=3D3\000\00010\000\000\000\000\000 */ +{ 79940 }, /* d-tlb-loads-access\000legacy cache\000Data TLB read accesses= \000legacy-cache-config=3D3\000\00010\000\000\000\000\000 */ +{ 80114 }, /* d-tlb-loads-miss\000legacy cache\000Data TLB read misses\000= legacy-cache-config=3D0x10003\000\00010\000\000\000\000\000 */ +{ 80025 }, /* d-tlb-loads-misses\000legacy cache\000Data TLB read misses\0= 00legacy-cache-config=3D0x10003\000\00010\000\000\000\000\000 */ +{ 79858 }, /* d-tlb-loads-ops\000legacy cache\000Data TLB read accesses\00= 0legacy-cache-config=3D3\000\00010\000\000\000\000\000 */ +{ 79770 }, /* d-tlb-loads-reference\000legacy cache\000Data TLB read acces= ses\000legacy-cache-config=3D3\000\00010\000\000\000\000\000 */ +{ 79687 }, /* d-tlb-loads-refs\000legacy cache\000Data TLB read accesses\0= 00legacy-cache-config=3D3\000\00010\000\000\000\000\000 */ +{ 85817 }, /* d-tlb-miss\000legacy cache\000Data TLB read misses\000legacy= -cache-config=3D0x10003\000\00010\000\000\000\000\000 */ +{ 85734 }, /* d-tlb-misses\000legacy cache\000Data TLB read misses\000lega= cy-cache-config=3D0x10003\000\00010\000\000\000\000\000 */ +{ 85579 }, /* d-tlb-ops\000legacy cache\000Data TLB read accesses\000legac= y-cache-config=3D3\000\00010\000\000\000\000\000 */ +{ 82650 }, /* d-tlb-prefetch\000legacy cache\000Data TLB prefetch accesses= \000legacy-cache-config=3D0x203\000\00010\000\000\000\000\000 */ +{ 83025 }, /* d-tlb-prefetch-access\000legacy cache\000Data TLB prefetch a= ccesses\000legacy-cache-config=3D0x203\000\00010\000\000\000\000\000 */ +{ 83217 }, /* d-tlb-prefetch-miss\000legacy cache\000Data TLB prefetch mis= ses\000legacy-cache-config=3D0x10203\000\00010\000\000\000\000\000 */ +{ 83121 }, /* d-tlb-prefetch-misses\000legacy cache\000Data TLB prefetch m= isses\000legacy-cache-config=3D0x10203\000\00010\000\000\000\000\000 */ +{ 82932 }, /* d-tlb-prefetch-ops\000legacy cache\000Data TLB prefetch acce= sses\000legacy-cache-config=3D0x203\000\00010\000\000\000\000\000 */ +{ 82833 }, /* d-tlb-prefetch-reference\000legacy cache\000Data TLB prefetc= h accesses\000legacy-cache-config=3D0x203\000\00010\000\000\000\000\000 */ +{ 82739 }, /* d-tlb-prefetch-refs\000legacy cache\000Data TLB prefetch acc= esses\000legacy-cache-config=3D0x203\000\00010\000\000\000\000\000 */ +{ 83311 }, /* d-tlb-prefetches\000legacy cache\000Data TLB prefetch access= es\000legacy-cache-config=3D0x203\000\00010\000\000\000\000\000 */ +{ 83694 }, /* d-tlb-prefetches-access\000legacy cache\000Data TLB prefetch= accesses\000legacy-cache-config=3D0x203\000\00010\000\000\000\000\000 */ +{ 83890 }, /* d-tlb-prefetches-miss\000legacy cache\000Data TLB prefetch m= isses\000legacy-cache-config=3D0x10203\000\00010\000\000\000\000\000 */ +{ 83792 }, /* d-tlb-prefetches-misses\000legacy cache\000Data TLB prefetch= misses\000legacy-cache-config=3D0x10203\000\00010\000\000\000\000\000 */ +{ 83599 }, /* d-tlb-prefetches-ops\000legacy cache\000Data TLB prefetch ac= cesses\000legacy-cache-config=3D0x203\000\00010\000\000\000\000\000 */ +{ 83498 }, /* d-tlb-prefetches-reference\000legacy cache\000Data TLB prefe= tch accesses\000legacy-cache-config=3D0x203\000\00010\000\000\000\000\000 */ +{ 83402 }, /* d-tlb-prefetches-refs\000legacy cache\000Data TLB prefetch a= ccesses\000legacy-cache-config=3D0x203\000\00010\000\000\000\000\000 */ +{ 80201 }, /* d-tlb-read\000legacy cache\000Data TLB read accesses\000lega= cy-cache-config=3D3\000\00010\000\000\000\000\000 */ +{ 80528 }, /* d-tlb-read-access\000legacy cache\000Data TLB read accesses\= 000legacy-cache-config=3D3\000\00010\000\000\000\000\000 */ +{ 80700 }, /* d-tlb-read-miss\000legacy cache\000Data TLB read misses\000l= egacy-cache-config=3D0x10003\000\00010\000\000\000\000\000 */ +{ 80612 }, /* d-tlb-read-misses\000legacy cache\000Data TLB read misses\00= 0legacy-cache-config=3D0x10003\000\00010\000\000\000\000\000 */ +{ 80447 }, /* d-tlb-read-ops\000legacy cache\000Data TLB read accesses\000= legacy-cache-config=3D3\000\00010\000\000\000\000\000 */ +{ 80360 }, /* d-tlb-read-reference\000legacy cache\000Data TLB read access= es\000legacy-cache-config=3D3\000\00010\000\000\000\000\000 */ +{ 80278 }, /* d-tlb-read-refs\000legacy cache\000Data TLB read accesses\00= 0legacy-cache-config=3D3\000\00010\000\000\000\000\000 */ +{ 85497 }, /* d-tlb-reference\000legacy cache\000Data TLB read accesses\00= 0legacy-cache-config=3D3\000\00010\000\000\000\000\000 */ +{ 85420 }, /* d-tlb-refs\000legacy cache\000Data TLB read accesses\000lega= cy-cache-config=3D3\000\00010\000\000\000\000\000 */ +{ 84703 }, /* d-tlb-speculative-load\000legacy cache\000Data TLB prefetch = accesses\000legacy-cache-config=3D0x203\000\00010\000\000\000\000\000 */ +{ 85110 }, /* d-tlb-speculative-load-access\000legacy cache\000Data TLB pr= efetch accesses\000legacy-cache-config=3D0x203\000\00010\000\000\000\000\00= 0 */ +{ 85318 }, /* d-tlb-speculative-load-miss\000legacy cache\000Data TLB pref= etch misses\000legacy-cache-config=3D0x10203\000\00010\000\000\000\000\000 = */ +{ 85214 }, /* d-tlb-speculative-load-misses\000legacy cache\000Data TLB pr= efetch misses\000legacy-cache-config=3D0x10203\000\00010\000\000\000\000\00= 0 */ +{ 85009 }, /* d-tlb-speculative-load-ops\000legacy cache\000Data TLB prefe= tch accesses\000legacy-cache-config=3D0x203\000\00010\000\000\000\000\000 */ +{ 84902 }, /* d-tlb-speculative-load-reference\000legacy cache\000Data TLB= prefetch accesses\000legacy-cache-config=3D0x203\000\00010\000\000\000\000= \000 */ +{ 84800 }, /* d-tlb-speculative-load-refs\000legacy cache\000Data TLB pref= etch accesses\000legacy-cache-config=3D0x203\000\00010\000\000\000\000\000 = */ +{ 83986 }, /* d-tlb-speculative-read\000legacy cache\000Data TLB prefetch = accesses\000legacy-cache-config=3D0x203\000\00010\000\000\000\000\000 */ +{ 84393 }, /* d-tlb-speculative-read-access\000legacy cache\000Data TLB pr= efetch accesses\000legacy-cache-config=3D0x203\000\00010\000\000\000\000\00= 0 */ +{ 84601 }, /* d-tlb-speculative-read-miss\000legacy cache\000Data TLB pref= etch misses\000legacy-cache-config=3D0x10203\000\00010\000\000\000\000\000 = */ +{ 84497 }, /* d-tlb-speculative-read-misses\000legacy cache\000Data TLB pr= efetch misses\000legacy-cache-config=3D0x10203\000\00010\000\000\000\000\00= 0 */ +{ 84292 }, /* d-tlb-speculative-read-ops\000legacy cache\000Data TLB prefe= tch accesses\000legacy-cache-config=3D0x203\000\00010\000\000\000\000\000 */ +{ 84185 }, /* d-tlb-speculative-read-reference\000legacy cache\000Data TLB= prefetch accesses\000legacy-cache-config=3D0x203\000\00010\000\000\000\000= \000 */ +{ 84083 }, /* d-tlb-speculative-read-refs\000legacy cache\000Data TLB pref= etch accesses\000legacy-cache-config=3D0x203\000\00010\000\000\000\000\000 = */ +{ 80786 }, /* d-tlb-store\000legacy cache\000Data TLB write accesses\000le= gacy-cache-config=3D0x103\000\00010\000\000\000\000\000 */ +{ 81137 }, /* d-tlb-store-access\000legacy cache\000Data TLB write accesse= s\000legacy-cache-config=3D0x103\000\00010\000\000\000\000\000 */ +{ 81317 }, /* d-tlb-store-miss\000legacy cache\000Data TLB write misses\00= 0legacy-cache-config=3D0x10103\000\00010\000\000\000\000\000 */ +{ 81227 }, /* d-tlb-store-misses\000legacy cache\000Data TLB write misses\= 000legacy-cache-config=3D0x10103\000\00010\000\000\000\000\000 */ +{ 81050 }, /* d-tlb-store-ops\000legacy cache\000Data TLB write accesses\0= 00legacy-cache-config=3D0x103\000\00010\000\000\000\000\000 */ +{ 80957 }, /* d-tlb-store-reference\000legacy cache\000Data TLB write acce= sses\000legacy-cache-config=3D0x103\000\00010\000\000\000\000\000 */ +{ 80869 }, /* d-tlb-store-refs\000legacy cache\000Data TLB write accesses\= 000legacy-cache-config=3D0x103\000\00010\000\000\000\000\000 */ +{ 81405 }, /* d-tlb-stores\000legacy cache\000Data TLB write accesses\000l= egacy-cache-config=3D0x103\000\00010\000\000\000\000\000 */ +{ 81760 }, /* d-tlb-stores-access\000legacy cache\000Data TLB write access= es\000legacy-cache-config=3D0x103\000\00010\000\000\000\000\000 */ +{ 81942 }, /* d-tlb-stores-miss\000legacy cache\000Data TLB write misses\0= 00legacy-cache-config=3D0x10103\000\00010\000\000\000\000\000 */ +{ 81851 }, /* d-tlb-stores-misses\000legacy cache\000Data TLB write misses= \000legacy-cache-config=3D0x10103\000\00010\000\000\000\000\000 */ +{ 81672 }, /* d-tlb-stores-ops\000legacy cache\000Data TLB write accesses\= 000legacy-cache-config=3D0x103\000\00010\000\000\000\000\000 */ +{ 81578 }, /* d-tlb-stores-reference\000legacy cache\000Data TLB write acc= esses\000legacy-cache-config=3D0x103\000\00010\000\000\000\000\000 */ +{ 81489 }, /* d-tlb-stores-refs\000legacy cache\000Data TLB write accesses= \000legacy-cache-config=3D0x103\000\00010\000\000\000\000\000 */ +{ 82031 }, /* d-tlb-write\000legacy cache\000Data TLB write accesses\000le= gacy-cache-config=3D0x103\000\00010\000\000\000\000\000 */ +{ 82382 }, /* d-tlb-write-access\000legacy cache\000Data TLB write accesse= s\000legacy-cache-config=3D0x103\000\00010\000\000\000\000\000 */ +{ 82562 }, /* d-tlb-write-miss\000legacy cache\000Data TLB write misses\00= 0legacy-cache-config=3D0x10103\000\00010\000\000\000\000\000 */ +{ 82472 }, /* d-tlb-write-misses\000legacy cache\000Data TLB write misses\= 000legacy-cache-config=3D0x10103\000\00010\000\000\000\000\000 */ +{ 82295 }, /* d-tlb-write-ops\000legacy cache\000Data TLB write accesses\0= 00legacy-cache-config=3D0x103\000\00010\000\000\000\000\000 */ +{ 82202 }, /* d-tlb-write-reference\000legacy cache\000Data TLB write acce= sses\000legacy-cache-config=3D0x103\000\00010\000\000\000\000\000 */ +{ 82114 }, /* d-tlb-write-refs\000legacy cache\000Data TLB write accesses\= 000legacy-cache-config=3D0x103\000\00010\000\000\000\000\000 */ +{ 85898 }, /* data-tlb\000legacy cache\000Data TLB read accesses\000legacy= -cache-config=3D3\000\00010\000\000\000\000\000 */ +{ 92823 }, /* data-tlb-access\000legacy cache\000Data TLB read accesses\00= 0legacy-cache-config=3D3\000\00010\000\000\000\000\000 */ +{ 85973 }, /* data-tlb-load\000legacy cache\000Data TLB read accesses\000l= egacy-cache-config=3D3\000\00010\000\000\000\000\000 */ +{ 86312 }, /* data-tlb-load-access\000legacy cache\000Data TLB read access= es\000legacy-cache-config=3D3\000\00010\000\000\000\000\000 */ +{ 86490 }, /* data-tlb-load-miss\000legacy cache\000Data TLB read misses\0= 00legacy-cache-config=3D0x10003\000\00010\000\000\000\000\000 */ +{ 86399 }, /* data-tlb-load-misses\000legacy cache\000Data TLB read misses= \000legacy-cache-config=3D0x10003\000\00010\000\000\000\000\000 */ +{ 86228 }, /* data-tlb-load-ops\000legacy cache\000Data TLB read accesses\= 000legacy-cache-config=3D3\000\00010\000\000\000\000\000 */ +{ 86138 }, /* data-tlb-load-reference\000legacy cache\000Data TLB read acc= esses\000legacy-cache-config=3D3\000\00010\000\000\000\000\000 */ +{ 86053 }, /* data-tlb-load-refs\000legacy cache\000Data TLB read accesses= \000legacy-cache-config=3D3\000\00010\000\000\000\000\000 */ +{ 86579 }, /* data-tlb-loads\000legacy cache\000Data TLB read accesses\000= legacy-cache-config=3D3\000\00010\000\000\000\000\000 */ +{ 86922 }, /* data-tlb-loads-access\000legacy cache\000Data TLB read acces= ses\000legacy-cache-config=3D3\000\00010\000\000\000\000\000 */ +{ 87102 }, /* data-tlb-loads-miss\000legacy cache\000Data TLB read misses\= 000legacy-cache-config=3D0x10003\000\00010\000\000\000\000\000 */ +{ 87010 }, /* data-tlb-loads-misses\000legacy cache\000Data TLB read misse= s\000legacy-cache-config=3D0x10003\000\00010\000\000\000\000\000 */ +{ 86837 }, /* data-tlb-loads-ops\000legacy cache\000Data TLB read accesses= \000legacy-cache-config=3D3\000\00010\000\000\000\000\000 */ +{ 86746 }, /* data-tlb-loads-reference\000legacy cache\000Data TLB read ac= cesses\000legacy-cache-config=3D3\000\00010\000\000\000\000\000 */ +{ 86660 }, /* data-tlb-loads-refs\000legacy cache\000Data TLB read accesse= s\000legacy-cache-config=3D3\000\00010\000\000\000\000\000 */ +{ 92991 }, /* data-tlb-miss\000legacy cache\000Data TLB read misses\000leg= acy-cache-config=3D0x10003\000\00010\000\000\000\000\000 */ +{ 92905 }, /* data-tlb-misses\000legacy cache\000Data TLB read misses\000l= egacy-cache-config=3D0x10003\000\00010\000\000\000\000\000 */ +{ 92744 }, /* data-tlb-ops\000legacy cache\000Data TLB read accesses\000le= gacy-cache-config=3D3\000\00010\000\000\000\000\000 */ +{ 89725 }, /* data-tlb-prefetch\000legacy cache\000Data TLB prefetch acces= ses\000legacy-cache-config=3D0x203\000\00010\000\000\000\000\000 */ +{ 90112 }, /* data-tlb-prefetch-access\000legacy cache\000Data TLB prefetc= h accesses\000legacy-cache-config=3D0x203\000\00010\000\000\000\000\000 */ +{ 90310 }, /* data-tlb-prefetch-miss\000legacy cache\000Data TLB prefetch = misses\000legacy-cache-config=3D0x10203\000\00010\000\000\000\000\000 */ +{ 90211 }, /* data-tlb-prefetch-misses\000legacy cache\000Data TLB prefetc= h misses\000legacy-cache-config=3D0x10203\000\00010\000\000\000\000\000 */ +{ 90016 }, /* data-tlb-prefetch-ops\000legacy cache\000Data TLB prefetch a= ccesses\000legacy-cache-config=3D0x203\000\00010\000\000\000\000\000 */ +{ 89914 }, /* data-tlb-prefetch-reference\000legacy cache\000Data TLB pref= etch accesses\000legacy-cache-config=3D0x203\000\00010\000\000\000\000\000 = */ +{ 89817 }, /* data-tlb-prefetch-refs\000legacy cache\000Data TLB prefetch = accesses\000legacy-cache-config=3D0x203\000\00010\000\000\000\000\000 */ +{ 90407 }, /* data-tlb-prefetches\000legacy cache\000Data TLB prefetch acc= esses\000legacy-cache-config=3D0x203\000\00010\000\000\000\000\000 */ +{ 90802 }, /* data-tlb-prefetches-access\000legacy cache\000Data TLB prefe= tch accesses\000legacy-cache-config=3D0x203\000\00010\000\000\000\000\000 */ +{ 91004 }, /* data-tlb-prefetches-miss\000legacy cache\000Data TLB prefetc= h misses\000legacy-cache-config=3D0x10203\000\00010\000\000\000\000\000 */ +{ 90903 }, /* data-tlb-prefetches-misses\000legacy cache\000Data TLB prefe= tch misses\000legacy-cache-config=3D0x10203\000\00010\000\000\000\000\000 */ +{ 90704 }, /* data-tlb-prefetches-ops\000legacy cache\000Data TLB prefetch= accesses\000legacy-cache-config=3D0x203\000\00010\000\000\000\000\000 */ +{ 90600 }, /* data-tlb-prefetches-reference\000legacy cache\000Data TLB pr= efetch accesses\000legacy-cache-config=3D0x203\000\00010\000\000\000\000\00= 0 */ +{ 90501 }, /* data-tlb-prefetches-refs\000legacy cache\000Data TLB prefetc= h accesses\000legacy-cache-config=3D0x203\000\00010\000\000\000\000\000 */ +{ 87192 }, /* data-tlb-read\000legacy cache\000Data TLB read accesses\000l= egacy-cache-config=3D3\000\00010\000\000\000\000\000 */ +{ 87531 }, /* data-tlb-read-access\000legacy cache\000Data TLB read access= es\000legacy-cache-config=3D3\000\00010\000\000\000\000\000 */ +{ 87709 }, /* data-tlb-read-miss\000legacy cache\000Data TLB read misses\0= 00legacy-cache-config=3D0x10003\000\00010\000\000\000\000\000 */ +{ 87618 }, /* data-tlb-read-misses\000legacy cache\000Data TLB read misses= \000legacy-cache-config=3D0x10003\000\00010\000\000\000\000\000 */ +{ 87447 }, /* data-tlb-read-ops\000legacy cache\000Data TLB read accesses\= 000legacy-cache-config=3D3\000\00010\000\000\000\000\000 */ +{ 87357 }, /* data-tlb-read-reference\000legacy cache\000Data TLB read acc= esses\000legacy-cache-config=3D3\000\00010\000\000\000\000\000 */ +{ 87272 }, /* data-tlb-read-refs\000legacy cache\000Data TLB read accesses= \000legacy-cache-config=3D3\000\00010\000\000\000\000\000 */ +{ 92659 }, /* data-tlb-reference\000legacy cache\000Data TLB read accesses= \000legacy-cache-config=3D3\000\00010\000\000\000\000\000 */ +{ 92579 }, /* data-tlb-refs\000legacy cache\000Data TLB read accesses\000l= egacy-cache-config=3D3\000\00010\000\000\000\000\000 */ +{ 91841 }, /* data-tlb-speculative-load\000legacy cache\000Data TLB prefet= ch accesses\000legacy-cache-config=3D0x203\000\00010\000\000\000\000\000 */ +{ 92260 }, /* data-tlb-speculative-load-access\000legacy cache\000Data TLB= prefetch accesses\000legacy-cache-config=3D0x203\000\00010\000\000\000\000= \000 */ +{ 92474 }, /* data-tlb-speculative-load-miss\000legacy cache\000Data TLB p= refetch misses\000legacy-cache-config=3D0x10203\000\00010\000\000\000\000\0= 00 */ +{ 92367 }, /* data-tlb-speculative-load-misses\000legacy cache\000Data TLB= prefetch misses\000legacy-cache-config=3D0x10203\000\00010\000\000\000\000= \000 */ +{ 92156 }, /* data-tlb-speculative-load-ops\000legacy cache\000Data TLB pr= efetch accesses\000legacy-cache-config=3D0x203\000\00010\000\000\000\000\00= 0 */ +{ 92046 }, /* data-tlb-speculative-load-reference\000legacy cache\000Data = TLB prefetch accesses\000legacy-cache-config=3D0x203\000\00010\000\000\000\= 000\000 */ +{ 91941 }, /* data-tlb-speculative-load-refs\000legacy cache\000Data TLB p= refetch accesses\000legacy-cache-config=3D0x203\000\00010\000\000\000\000\0= 00 */ +{ 91103 }, /* data-tlb-speculative-read\000legacy cache\000Data TLB prefet= ch accesses\000legacy-cache-config=3D0x203\000\00010\000\000\000\000\000 */ +{ 91522 }, /* data-tlb-speculative-read-access\000legacy cache\000Data TLB= prefetch accesses\000legacy-cache-config=3D0x203\000\00010\000\000\000\000= \000 */ +{ 91736 }, /* data-tlb-speculative-read-miss\000legacy cache\000Data TLB p= refetch misses\000legacy-cache-config=3D0x10203\000\00010\000\000\000\000\0= 00 */ +{ 91629 }, /* data-tlb-speculative-read-misses\000legacy cache\000Data TLB= prefetch misses\000legacy-cache-config=3D0x10203\000\00010\000\000\000\000= \000 */ +{ 91418 }, /* data-tlb-speculative-read-ops\000legacy cache\000Data TLB pr= efetch accesses\000legacy-cache-config=3D0x203\000\00010\000\000\000\000\00= 0 */ +{ 91308 }, /* data-tlb-speculative-read-reference\000legacy cache\000Data = TLB prefetch accesses\000legacy-cache-config=3D0x203\000\00010\000\000\000\= 000\000 */ +{ 91203 }, /* data-tlb-speculative-read-refs\000legacy cache\000Data TLB p= refetch accesses\000legacy-cache-config=3D0x203\000\00010\000\000\000\000\0= 00 */ +{ 87798 }, /* data-tlb-store\000legacy cache\000Data TLB write accesses\00= 0legacy-cache-config=3D0x103\000\00010\000\000\000\000\000 */ +{ 88161 }, /* data-tlb-store-access\000legacy cache\000Data TLB write acce= sses\000legacy-cache-config=3D0x103\000\00010\000\000\000\000\000 */ +{ 88347 }, /* data-tlb-store-miss\000legacy cache\000Data TLB write misses= \000legacy-cache-config=3D0x10103\000\00010\000\000\000\000\000 */ +{ 88254 }, /* data-tlb-store-misses\000legacy cache\000Data TLB write miss= es\000legacy-cache-config=3D0x10103\000\00010\000\000\000\000\000 */ +{ 88071 }, /* data-tlb-store-ops\000legacy cache\000Data TLB write accesse= s\000legacy-cache-config=3D0x103\000\00010\000\000\000\000\000 */ +{ 87975 }, /* data-tlb-store-reference\000legacy cache\000Data TLB write a= ccesses\000legacy-cache-config=3D0x103\000\00010\000\000\000\000\000 */ +{ 87884 }, /* data-tlb-store-refs\000legacy cache\000Data TLB write access= es\000legacy-cache-config=3D0x103\000\00010\000\000\000\000\000 */ +{ 88438 }, /* data-tlb-stores\000legacy cache\000Data TLB write accesses\0= 00legacy-cache-config=3D0x103\000\00010\000\000\000\000\000 */ +{ 88805 }, /* data-tlb-stores-access\000legacy cache\000Data TLB write acc= esses\000legacy-cache-config=3D0x103\000\00010\000\000\000\000\000 */ +{ 88993 }, /* data-tlb-stores-miss\000legacy cache\000Data TLB write misse= s\000legacy-cache-config=3D0x10103\000\00010\000\000\000\000\000 */ +{ 88899 }, /* data-tlb-stores-misses\000legacy cache\000Data TLB write mis= ses\000legacy-cache-config=3D0x10103\000\00010\000\000\000\000\000 */ +{ 88714 }, /* data-tlb-stores-ops\000legacy cache\000Data TLB write access= es\000legacy-cache-config=3D0x103\000\00010\000\000\000\000\000 */ +{ 88617 }, /* data-tlb-stores-reference\000legacy cache\000Data TLB write = accesses\000legacy-cache-config=3D0x103\000\00010\000\000\000\000\000 */ +{ 88525 }, /* data-tlb-stores-refs\000legacy cache\000Data TLB write acces= ses\000legacy-cache-config=3D0x103\000\00010\000\000\000\000\000 */ +{ 89085 }, /* data-tlb-write\000legacy cache\000Data TLB write accesses\00= 0legacy-cache-config=3D0x103\000\00010\000\000\000\000\000 */ +{ 89448 }, /* data-tlb-write-access\000legacy cache\000Data TLB write acce= sses\000legacy-cache-config=3D0x103\000\00010\000\000\000\000\000 */ +{ 89634 }, /* data-tlb-write-miss\000legacy cache\000Data TLB write misses= \000legacy-cache-config=3D0x10103\000\00010\000\000\000\000\000 */ +{ 89541 }, /* data-tlb-write-misses\000legacy cache\000Data TLB write miss= es\000legacy-cache-config=3D0x10103\000\00010\000\000\000\000\000 */ +{ 89358 }, /* data-tlb-write-ops\000legacy cache\000Data TLB write accesse= s\000legacy-cache-config=3D0x103\000\00010\000\000\000\000\000 */ +{ 89262 }, /* data-tlb-write-reference\000legacy cache\000Data TLB write a= ccesses\000legacy-cache-config=3D0x103\000\00010\000\000\000\000\000 */ +{ 89171 }, /* data-tlb-write-refs\000legacy cache\000Data TLB write access= es\000legacy-cache-config=3D0x103\000\00010\000\000\000\000\000 */ +{ 72083 }, /* dtlb\000legacy cache\000Data TLB read accesses\000legacy-cac= he-config=3D3\000\00010\000\000\000\000\000 */ +{ 78712 }, /* dtlb-access\000legacy cache\000Data TLB read accesses\000leg= acy-cache-config=3D3\000\00010\000\000\000\000\000 */ +{ 72154 }, /* dtlb-load\000legacy cache\000Data TLB read accesses\000legac= y-cache-config=3D3\000\00010\000\000\000\000\000 */ +{ 72477 }, /* dtlb-load-access\000legacy cache\000Data TLB read accesses\0= 00legacy-cache-config=3D3\000\00010\000\000\000\000\000 */ +{ 72647 }, /* dtlb-load-miss\000legacy cache\000Data TLB read misses\000le= gacy-cache-config=3D0x10003\000\00010\000\000\000\000\000 */ +{ 72560 }, /* dtlb-load-misses\000legacy cache\000Data TLB read misses\000= legacy-cache-config=3D0x10003\000\00000\000\000\000\000\000 */ +{ 72397 }, /* dtlb-load-ops\000legacy cache\000Data TLB read accesses\000l= egacy-cache-config=3D3\000\00010\000\000\000\000\000 */ +{ 72311 }, /* dtlb-load-reference\000legacy cache\000Data TLB read accesse= s\000legacy-cache-config=3D3\000\00010\000\000\000\000\000 */ +{ 72230 }, /* dtlb-load-refs\000legacy cache\000Data TLB read accesses\000= legacy-cache-config=3D3\000\00010\000\000\000\000\000 */ +{ 72732 }, /* dtlb-loads\000legacy cache\000Data TLB read accesses\000lega= cy-cache-config=3D3\000\00000\000\000\000\000\000 */ +{ 73059 }, /* dtlb-loads-access\000legacy cache\000Data TLB read accesses\= 000legacy-cache-config=3D3\000\00010\000\000\000\000\000 */ +{ 73231 }, /* dtlb-loads-miss\000legacy cache\000Data TLB read misses\000l= egacy-cache-config=3D0x10003\000\00010\000\000\000\000\000 */ +{ 73143 }, /* dtlb-loads-misses\000legacy cache\000Data TLB read misses\00= 0legacy-cache-config=3D0x10003\000\00010\000\000\000\000\000 */ +{ 72978 }, /* dtlb-loads-ops\000legacy cache\000Data TLB read accesses\000= legacy-cache-config=3D3\000\00010\000\000\000\000\000 */ +{ 72891 }, /* dtlb-loads-reference\000legacy cache\000Data TLB read access= es\000legacy-cache-config=3D3\000\00010\000\000\000\000\000 */ +{ 72809 }, /* dtlb-loads-refs\000legacy cache\000Data TLB read accesses\00= 0legacy-cache-config=3D3\000\00010\000\000\000\000\000 */ +{ 78872 }, /* dtlb-miss\000legacy cache\000Data TLB read misses\000legacy-= cache-config=3D0x10003\000\00010\000\000\000\000\000 */ +{ 78790 }, /* dtlb-misses\000legacy cache\000Data TLB read misses\000legac= y-cache-config=3D0x10003\000\00010\000\000\000\000\000 */ +{ 78637 }, /* dtlb-ops\000legacy cache\000Data TLB read accesses\000legacy= -cache-config=3D3\000\00010\000\000\000\000\000 */ +{ 75738 }, /* dtlb-prefetch\000legacy cache\000Data TLB prefetch accesses\= 000legacy-cache-config=3D0x203\000\00010\000\000\000\000\000 */ +{ 76109 }, /* dtlb-prefetch-access\000legacy cache\000Data TLB prefetch ac= cesses\000legacy-cache-config=3D0x203\000\00010\000\000\000\000\000 */ +{ 76299 }, /* dtlb-prefetch-miss\000legacy cache\000Data TLB prefetch miss= es\000legacy-cache-config=3D0x10203\000\00010\000\000\000\000\000 */ +{ 76204 }, /* dtlb-prefetch-misses\000legacy cache\000Data TLB prefetch mi= sses\000legacy-cache-config=3D0x10203\000\00000\000\000\000\000\000 */ +{ 76017 }, /* dtlb-prefetch-ops\000legacy cache\000Data TLB prefetch acces= ses\000legacy-cache-config=3D0x203\000\00010\000\000\000\000\000 */ +{ 75919 }, /* dtlb-prefetch-reference\000legacy cache\000Data TLB prefetch= accesses\000legacy-cache-config=3D0x203\000\00010\000\000\000\000\000 */ +{ 75826 }, /* dtlb-prefetch-refs\000legacy cache\000Data TLB prefetch acce= sses\000legacy-cache-config=3D0x203\000\00010\000\000\000\000\000 */ +{ 76392 }, /* dtlb-prefetches\000legacy cache\000Data TLB prefetch accesse= s\000legacy-cache-config=3D0x203\000\00000\000\000\000\000\000 */ +{ 76771 }, /* dtlb-prefetches-access\000legacy cache\000Data TLB prefetch = accesses\000legacy-cache-config=3D0x203\000\00010\000\000\000\000\000 */ +{ 76965 }, /* dtlb-prefetches-miss\000legacy cache\000Data TLB prefetch mi= sses\000legacy-cache-config=3D0x10203\000\00010\000\000\000\000\000 */ +{ 76868 }, /* dtlb-prefetches-misses\000legacy cache\000Data TLB prefetch = misses\000legacy-cache-config=3D0x10203\000\00010\000\000\000\000\000 */ +{ 76677 }, /* dtlb-prefetches-ops\000legacy cache\000Data TLB prefetch acc= esses\000legacy-cache-config=3D0x203\000\00010\000\000\000\000\000 */ +{ 76577 }, /* dtlb-prefetches-reference\000legacy cache\000Data TLB prefet= ch accesses\000legacy-cache-config=3D0x203\000\00010\000\000\000\000\000 */ +{ 76482 }, /* dtlb-prefetches-refs\000legacy cache\000Data TLB prefetch ac= cesses\000legacy-cache-config=3D0x203\000\00010\000\000\000\000\000 */ +{ 73317 }, /* dtlb-read\000legacy cache\000Data TLB read accesses\000legac= y-cache-config=3D3\000\00010\000\000\000\000\000 */ +{ 73640 }, /* dtlb-read-access\000legacy cache\000Data TLB read accesses\0= 00legacy-cache-config=3D3\000\00010\000\000\000\000\000 */ +{ 73810 }, /* dtlb-read-miss\000legacy cache\000Data TLB read misses\000le= gacy-cache-config=3D0x10003\000\00010\000\000\000\000\000 */ +{ 73723 }, /* dtlb-read-misses\000legacy cache\000Data TLB read misses\000= legacy-cache-config=3D0x10003\000\00010\000\000\000\000\000 */ +{ 73560 }, /* dtlb-read-ops\000legacy cache\000Data TLB read accesses\000l= egacy-cache-config=3D3\000\00010\000\000\000\000\000 */ +{ 73474 }, /* dtlb-read-reference\000legacy cache\000Data TLB read accesse= s\000legacy-cache-config=3D3\000\00010\000\000\000\000\000 */ +{ 73393 }, /* dtlb-read-refs\000legacy cache\000Data TLB read accesses\000= legacy-cache-config=3D3\000\00010\000\000\000\000\000 */ +{ 78556 }, /* dtlb-reference\000legacy cache\000Data TLB read accesses\000= legacy-cache-config=3D3\000\00010\000\000\000\000\000 */ +{ 78480 }, /* dtlb-refs\000legacy cache\000Data TLB read accesses\000legac= y-cache-config=3D3\000\00010\000\000\000\000\000 */ +{ 77770 }, /* dtlb-speculative-load\000legacy cache\000Data TLB prefetch a= ccesses\000legacy-cache-config=3D0x203\000\00010\000\000\000\000\000 */ +{ 78173 }, /* dtlb-speculative-load-access\000legacy cache\000Data TLB pre= fetch accesses\000legacy-cache-config=3D0x203\000\00010\000\000\000\000\000= */ +{ 78379 }, /* dtlb-speculative-load-miss\000legacy cache\000Data TLB prefe= tch misses\000legacy-cache-config=3D0x10203\000\00010\000\000\000\000\000 */ +{ 78276 }, /* dtlb-speculative-load-misses\000legacy cache\000Data TLB pre= fetch misses\000legacy-cache-config=3D0x10203\000\00010\000\000\000\000\000= */ +{ 78073 }, /* dtlb-speculative-load-ops\000legacy cache\000Data TLB prefet= ch accesses\000legacy-cache-config=3D0x203\000\00010\000\000\000\000\000 */ +{ 77967 }, /* dtlb-speculative-load-reference\000legacy cache\000Data TLB = prefetch accesses\000legacy-cache-config=3D0x203\000\00010\000\000\000\000\= 000 */ +{ 77866 }, /* dtlb-speculative-load-refs\000legacy cache\000Data TLB prefe= tch accesses\000legacy-cache-config=3D0x203\000\00010\000\000\000\000\000 */ +{ 77060 }, /* dtlb-speculative-read\000legacy cache\000Data TLB prefetch a= ccesses\000legacy-cache-config=3D0x203\000\00010\000\000\000\000\000 */ +{ 77463 }, /* dtlb-speculative-read-access\000legacy cache\000Data TLB pre= fetch accesses\000legacy-cache-config=3D0x203\000\00010\000\000\000\000\000= */ +{ 77669 }, /* dtlb-speculative-read-miss\000legacy cache\000Data TLB prefe= tch misses\000legacy-cache-config=3D0x10203\000\00010\000\000\000\000\000 */ +{ 77566 }, /* dtlb-speculative-read-misses\000legacy cache\000Data TLB pre= fetch misses\000legacy-cache-config=3D0x10203\000\00010\000\000\000\000\000= */ +{ 77363 }, /* dtlb-speculative-read-ops\000legacy cache\000Data TLB prefet= ch accesses\000legacy-cache-config=3D0x203\000\00010\000\000\000\000\000 */ +{ 77257 }, /* dtlb-speculative-read-reference\000legacy cache\000Data TLB = prefetch accesses\000legacy-cache-config=3D0x203\000\00010\000\000\000\000\= 000 */ +{ 77156 }, /* dtlb-speculative-read-refs\000legacy cache\000Data TLB prefe= tch accesses\000legacy-cache-config=3D0x203\000\00010\000\000\000\000\000 */ +{ 73895 }, /* dtlb-store\000legacy cache\000Data TLB write accesses\000leg= acy-cache-config=3D0x103\000\00010\000\000\000\000\000 */ +{ 74242 }, /* dtlb-store-access\000legacy cache\000Data TLB write accesses= \000legacy-cache-config=3D0x103\000\00010\000\000\000\000\000 */ +{ 74420 }, /* dtlb-store-miss\000legacy cache\000Data TLB write misses\000= legacy-cache-config=3D0x10103\000\00010\000\000\000\000\000 */ +{ 74331 }, /* dtlb-store-misses\000legacy cache\000Data TLB write misses\0= 00legacy-cache-config=3D0x10103\000\00000\000\000\000\000\000 */ +{ 74156 }, /* dtlb-store-ops\000legacy cache\000Data TLB write accesses\00= 0legacy-cache-config=3D0x103\000\00010\000\000\000\000\000 */ +{ 74064 }, /* dtlb-store-reference\000legacy cache\000Data TLB write acces= ses\000legacy-cache-config=3D0x103\000\00010\000\000\000\000\000 */ +{ 73977 }, /* dtlb-store-refs\000legacy cache\000Data TLB write accesses\0= 00legacy-cache-config=3D0x103\000\00010\000\000\000\000\000 */ +{ 74507 }, /* dtlb-stores\000legacy cache\000Data TLB write accesses\000le= gacy-cache-config=3D0x103\000\00000\000\000\000\000\000 */ +{ 74858 }, /* dtlb-stores-access\000legacy cache\000Data TLB write accesse= s\000legacy-cache-config=3D0x103\000\00010\000\000\000\000\000 */ +{ 75038 }, /* dtlb-stores-miss\000legacy cache\000Data TLB write misses\00= 0legacy-cache-config=3D0x10103\000\00010\000\000\000\000\000 */ +{ 74948 }, /* dtlb-stores-misses\000legacy cache\000Data TLB write misses\= 000legacy-cache-config=3D0x10103\000\00010\000\000\000\000\000 */ +{ 74771 }, /* dtlb-stores-ops\000legacy cache\000Data TLB write accesses\0= 00legacy-cache-config=3D0x103\000\00010\000\000\000\000\000 */ +{ 74678 }, /* dtlb-stores-reference\000legacy cache\000Data TLB write acce= sses\000legacy-cache-config=3D0x103\000\00010\000\000\000\000\000 */ +{ 74590 }, /* dtlb-stores-refs\000legacy cache\000Data TLB write accesses\= 000legacy-cache-config=3D0x103\000\00010\000\000\000\000\000 */ +{ 75126 }, /* dtlb-write\000legacy cache\000Data TLB write accesses\000leg= acy-cache-config=3D0x103\000\00010\000\000\000\000\000 */ +{ 75473 }, /* dtlb-write-access\000legacy cache\000Data TLB write accesses= \000legacy-cache-config=3D0x103\000\00010\000\000\000\000\000 */ +{ 75651 }, /* dtlb-write-miss\000legacy cache\000Data TLB write misses\000= legacy-cache-config=3D0x10103\000\00010\000\000\000\000\000 */ +{ 75562 }, /* dtlb-write-misses\000legacy cache\000Data TLB write misses\0= 00legacy-cache-config=3D0x10103\000\00010\000\000\000\000\000 */ +{ 75387 }, /* dtlb-write-ops\000legacy cache\000Data TLB write accesses\00= 0legacy-cache-config=3D0x103\000\00010\000\000\000\000\000 */ +{ 75295 }, /* dtlb-write-reference\000legacy cache\000Data TLB write acces= ses\000legacy-cache-config=3D0x103\000\00010\000\000\000\000\000 */ +{ 75208 }, /* dtlb-write-refs\000legacy cache\000Data TLB write accesses\0= 00legacy-cache-config=3D0x103\000\00010\000\000\000\000\000 */ +{ 95555 }, /* i-tlb\000legacy cache\000Instruction TLB read accesses\000le= gacy-cache-config=3D4\000\00010\000\000\000\000\000 */ +{ 97799 }, /* i-tlb-access\000legacy cache\000Instruction TLB read accesse= s\000legacy-cache-config=3D4\000\00010\000\000\000\000\000 */ +{ 95634 }, /* i-tlb-load\000legacy cache\000Instruction TLB read accesses\= 000legacy-cache-config=3D4\000\00010\000\000\000\000\000 */ +{ 95989 }, /* i-tlb-load-access\000legacy cache\000Instruction TLB read ac= cesses\000legacy-cache-config=3D4\000\00010\000\000\000\000\000 */ +{ 96175 }, /* i-tlb-load-miss\000legacy cache\000Instruction TLB read miss= es\000legacy-cache-config=3D0x10004\000\00010\000\000\000\000\000 */ +{ 96080 }, /* i-tlb-load-misses\000legacy cache\000Instruction TLB read mi= sses\000legacy-cache-config=3D0x10004\000\00010\000\000\000\000\000 */ +{ 95901 }, /* i-tlb-load-ops\000legacy cache\000Instruction TLB read acces= ses\000legacy-cache-config=3D4\000\00010\000\000\000\000\000 */ +{ 95807 }, /* i-tlb-load-reference\000legacy cache\000Instruction TLB read= accesses\000legacy-cache-config=3D4\000\00010\000\000\000\000\000 */ +{ 95718 }, /* i-tlb-load-refs\000legacy cache\000Instruction TLB read acce= sses\000legacy-cache-config=3D4\000\00010\000\000\000\000\000 */ +{ 96268 }, /* i-tlb-loads\000legacy cache\000Instruction TLB read accesses= \000legacy-cache-config=3D4\000\00010\000\000\000\000\000 */ +{ 96627 }, /* i-tlb-loads-access\000legacy cache\000Instruction TLB read a= ccesses\000legacy-cache-config=3D4\000\00010\000\000\000\000\000 */ +{ 96815 }, /* i-tlb-loads-miss\000legacy cache\000Instruction TLB read mis= ses\000legacy-cache-config=3D0x10004\000\00010\000\000\000\000\000 */ +{ 96719 }, /* i-tlb-loads-misses\000legacy cache\000Instruction TLB read m= isses\000legacy-cache-config=3D0x10004\000\00010\000\000\000\000\000 */ +{ 96538 }, /* i-tlb-loads-ops\000legacy cache\000Instruction TLB read acce= sses\000legacy-cache-config=3D4\000\00010\000\000\000\000\000 */ +{ 96443 }, /* i-tlb-loads-reference\000legacy cache\000Instruction TLB rea= d accesses\000legacy-cache-config=3D4\000\00010\000\000\000\000\000 */ +{ 96353 }, /* i-tlb-loads-refs\000legacy cache\000Instruction TLB read acc= esses\000legacy-cache-config=3D4\000\00010\000\000\000\000\000 */ +{ 97975 }, /* i-tlb-miss\000legacy cache\000Instruction TLB read misses\00= 0legacy-cache-config=3D0x10004\000\00010\000\000\000\000\000 */ +{ 97885 }, /* i-tlb-misses\000legacy cache\000Instruction TLB read misses\= 000legacy-cache-config=3D0x10004\000\00010\000\000\000\000\000 */ +{ 97716 }, /* i-tlb-ops\000legacy cache\000Instruction TLB read accesses\0= 00legacy-cache-config=3D4\000\00010\000\000\000\000\000 */ +{ 96909 }, /* i-tlb-read\000legacy cache\000Instruction TLB read accesses\= 000legacy-cache-config=3D4\000\00010\000\000\000\000\000 */ +{ 97264 }, /* i-tlb-read-access\000legacy cache\000Instruction TLB read ac= cesses\000legacy-cache-config=3D4\000\00010\000\000\000\000\000 */ +{ 97450 }, /* i-tlb-read-miss\000legacy cache\000Instruction TLB read miss= es\000legacy-cache-config=3D0x10004\000\00010\000\000\000\000\000 */ +{ 97355 }, /* i-tlb-read-misses\000legacy cache\000Instruction TLB read mi= sses\000legacy-cache-config=3D0x10004\000\00010\000\000\000\000\000 */ +{ 97176 }, /* i-tlb-read-ops\000legacy cache\000Instruction TLB read acces= ses\000legacy-cache-config=3D4\000\00010\000\000\000\000\000 */ +{ 97082 }, /* i-tlb-read-reference\000legacy cache\000Instruction TLB read= accesses\000legacy-cache-config=3D4\000\00010\000\000\000\000\000 */ +{ 96993 }, /* i-tlb-read-refs\000legacy cache\000Instruction TLB read acce= sses\000legacy-cache-config=3D4\000\00010\000\000\000\000\000 */ +{ 97627 }, /* i-tlb-reference\000legacy cache\000Instruction TLB read acce= sses\000legacy-cache-config=3D4\000\00010\000\000\000\000\000 */ +{ 97543 }, /* i-tlb-refs\000legacy cache\000Instruction TLB read accesses\= 000legacy-cache-config=3D4\000\00010\000\000\000\000\000 */ +{ 123247 }, /* idle-cycles-backend\000legacy hardware\000Stalled cycles du= ring retirement [This event is an alias of stalled-cycles-backend]\000legac= y-hardware-config=3D8\000\00000\000\000\000\000\000 */ +{ 122945 }, /* idle-cycles-frontend\000legacy hardware\000Stalled cycles d= uring issue [This event is an alias of stalled-cycles-fronted]\000legacy-ha= rdware-config=3D7\000\00000\000\000\000\000\000 */ +{ 98063 }, /* instruction-tlb\000legacy cache\000Instruction TLB read acce= sses\000legacy-cache-config=3D4\000\00010\000\000\000\000\000 */ +{ 100557 }, /* instruction-tlb-access\000legacy cache\000Instruction TLB r= ead accesses\000legacy-cache-config=3D4\000\00010\000\000\000\000\000 */ +{ 98152 }, /* instruction-tlb-load\000legacy cache\000Instruction TLB read= accesses\000legacy-cache-config=3D4\000\00010\000\000\000\000\000 */ +{ 98547 }, /* instruction-tlb-load-access\000legacy cache\000Instruction T= LB read accesses\000legacy-cache-config=3D4\000\00010\000\000\000\000\000 */ +{ 98753 }, /* instruction-tlb-load-miss\000legacy cache\000Instruction TLB= read misses\000legacy-cache-config=3D0x10004\000\00010\000\000\000\000\000= */ +{ 98648 }, /* instruction-tlb-load-misses\000legacy cache\000Instruction T= LB read misses\000legacy-cache-config=3D0x10004\000\00010\000\000\000\000\0= 00 */ +{ 98449 }, /* instruction-tlb-load-ops\000legacy cache\000Instruction TLB = read accesses\000legacy-cache-config=3D4\000\00010\000\000\000\000\000 */ +{ 98345 }, /* instruction-tlb-load-reference\000legacy cache\000Instructio= n TLB read accesses\000legacy-cache-config=3D4\000\00010\000\000\000\000\00= 0 */ +{ 98246 }, /* instruction-tlb-load-refs\000legacy cache\000Instruction TLB= read accesses\000legacy-cache-config=3D4\000\00010\000\000\000\000\000 */ +{ 98856 }, /* instruction-tlb-loads\000legacy cache\000Instruction TLB rea= d accesses\000legacy-cache-config=3D4\000\00010\000\000\000\000\000 */ +{ 99255 }, /* instruction-tlb-loads-access\000legacy cache\000Instruction = TLB read accesses\000legacy-cache-config=3D4\000\00010\000\000\000\000\000 = */ +{ 99463 }, /* instruction-tlb-loads-miss\000legacy cache\000Instruction TL= B read misses\000legacy-cache-config=3D0x10004\000\00010\000\000\000\000\00= 0 */ +{ 99357 }, /* instruction-tlb-loads-misses\000legacy cache\000Instruction = TLB read misses\000legacy-cache-config=3D0x10004\000\00010\000\000\000\000\= 000 */ +{ 99156 }, /* instruction-tlb-loads-ops\000legacy cache\000Instruction TLB= read accesses\000legacy-cache-config=3D4\000\00010\000\000\000\000\000 */ +{ 99051 }, /* instruction-tlb-loads-reference\000legacy cache\000Instructi= on TLB read accesses\000legacy-cache-config=3D4\000\00010\000\000\000\000\0= 00 */ +{ 98951 }, /* instruction-tlb-loads-refs\000legacy cache\000Instruction TL= B read accesses\000legacy-cache-config=3D4\000\00010\000\000\000\000\000 */ +{ 100753 }, /* instruction-tlb-miss\000legacy cache\000Instruction TLB rea= d misses\000legacy-cache-config=3D0x10004\000\00010\000\000\000\000\000 */ +{ 100653 }, /* instruction-tlb-misses\000legacy cache\000Instruction TLB r= ead misses\000legacy-cache-config=3D0x10004\000\00010\000\000\000\000\000 */ +{ 100464 }, /* instruction-tlb-ops\000legacy cache\000Instruction TLB read= accesses\000legacy-cache-config=3D4\000\00010\000\000\000\000\000 */ +{ 99567 }, /* instruction-tlb-read\000legacy cache\000Instruction TLB read= accesses\000legacy-cache-config=3D4\000\00010\000\000\000\000\000 */ +{ 99962 }, /* instruction-tlb-read-access\000legacy cache\000Instruction T= LB read accesses\000legacy-cache-config=3D4\000\00010\000\000\000\000\000 */ +{ 100168 }, /* instruction-tlb-read-miss\000legacy cache\000Instruction TL= B read misses\000legacy-cache-config=3D0x10004\000\00010\000\000\000\000\00= 0 */ +{ 100063 }, /* instruction-tlb-read-misses\000legacy cache\000Instruction = TLB read misses\000legacy-cache-config=3D0x10004\000\00010\000\000\000\000\= 000 */ +{ 99864 }, /* instruction-tlb-read-ops\000legacy cache\000Instruction TLB = read accesses\000legacy-cache-config=3D4\000\00010\000\000\000\000\000 */ +{ 99760 }, /* instruction-tlb-read-reference\000legacy cache\000Instructio= n TLB read accesses\000legacy-cache-config=3D4\000\00010\000\000\000\000\00= 0 */ +{ 99661 }, /* instruction-tlb-read-refs\000legacy cache\000Instruction TLB= read accesses\000legacy-cache-config=3D4\000\00010\000\000\000\000\000 */ +{ 100365 }, /* instruction-tlb-reference\000legacy cache\000Instruction TL= B read accesses\000legacy-cache-config=3D4\000\00010\000\000\000\000\000 */ +{ 100271 }, /* instruction-tlb-refs\000legacy cache\000Instruction TLB rea= d accesses\000legacy-cache-config=3D4\000\00010\000\000\000\000\000 */ +{ 121629 }, /* instructions\000legacy hardware\000Retired instructions. Be= careful, these can be affected by various issues, most notably hardware in= terrupt counts\000legacy-hardware-config=3D1\000\00000\000\000\000\000\000 = */ +{ 93075 }, /* itlb\000legacy cache\000Instruction TLB read accesses\000leg= acy-cache-config=3D4\000\00010\000\000\000\000\000 */ +{ 95294 }, /* itlb-access\000legacy cache\000Instruction TLB read accesses= \000legacy-cache-config=3D4\000\00010\000\000\000\000\000 */ +{ 93153 }, /* itlb-load\000legacy cache\000Instruction TLB read accesses\0= 00legacy-cache-config=3D4\000\00010\000\000\000\000\000 */ +{ 93504 }, /* itlb-load-access\000legacy cache\000Instruction TLB read acc= esses\000legacy-cache-config=3D4\000\00010\000\000\000\000\000 */ +{ 93688 }, /* itlb-load-miss\000legacy cache\000Instruction TLB read misse= s\000legacy-cache-config=3D0x10004\000\00010\000\000\000\000\000 */ +{ 93594 }, /* itlb-load-misses\000legacy cache\000Instruction TLB read mis= ses\000legacy-cache-config=3D0x10004\000\00000\000\000\000\000\000 */ +{ 93417 }, /* itlb-load-ops\000legacy cache\000Instruction TLB read access= es\000legacy-cache-config=3D4\000\00010\000\000\000\000\000 */ +{ 93324 }, /* itlb-load-reference\000legacy cache\000Instruction TLB read = accesses\000legacy-cache-config=3D4\000\00010\000\000\000\000\000 */ +{ 93236 }, /* itlb-load-refs\000legacy cache\000Instruction TLB read acces= ses\000legacy-cache-config=3D4\000\00010\000\000\000\000\000 */ +{ 93780 }, /* itlb-loads\000legacy cache\000Instruction TLB read accesses\= 000legacy-cache-config=3D4\000\00000\000\000\000\000\000 */ +{ 94135 }, /* itlb-loads-access\000legacy cache\000Instruction TLB read ac= cesses\000legacy-cache-config=3D4\000\00010\000\000\000\000\000 */ +{ 94321 }, /* itlb-loads-miss\000legacy cache\000Instruction TLB read miss= es\000legacy-cache-config=3D0x10004\000\00010\000\000\000\000\000 */ +{ 94226 }, /* itlb-loads-misses\000legacy cache\000Instruction TLB read mi= sses\000legacy-cache-config=3D0x10004\000\00010\000\000\000\000\000 */ +{ 94047 }, /* itlb-loads-ops\000legacy cache\000Instruction TLB read acces= ses\000legacy-cache-config=3D4\000\00010\000\000\000\000\000 */ +{ 93953 }, /* itlb-loads-reference\000legacy cache\000Instruction TLB read= accesses\000legacy-cache-config=3D4\000\00010\000\000\000\000\000 */ +{ 93864 }, /* itlb-loads-refs\000legacy cache\000Instruction TLB read acce= sses\000legacy-cache-config=3D4\000\00010\000\000\000\000\000 */ +{ 95468 }, /* itlb-miss\000legacy cache\000Instruction TLB read misses\000= legacy-cache-config=3D0x10004\000\00010\000\000\000\000\000 */ +{ 95379 }, /* itlb-misses\000legacy cache\000Instruction TLB read misses\0= 00legacy-cache-config=3D0x10004\000\00010\000\000\000\000\000 */ +{ 95212 }, /* itlb-ops\000legacy cache\000Instruction TLB read accesses\00= 0legacy-cache-config=3D4\000\00010\000\000\000\000\000 */ +{ 94414 }, /* itlb-read\000legacy cache\000Instruction TLB read accesses\0= 00legacy-cache-config=3D4\000\00010\000\000\000\000\000 */ +{ 94765 }, /* itlb-read-access\000legacy cache\000Instruction TLB read acc= esses\000legacy-cache-config=3D4\000\00010\000\000\000\000\000 */ +{ 94949 }, /* itlb-read-miss\000legacy cache\000Instruction TLB read misse= s\000legacy-cache-config=3D0x10004\000\00010\000\000\000\000\000 */ +{ 94855 }, /* itlb-read-misses\000legacy cache\000Instruction TLB read mis= ses\000legacy-cache-config=3D0x10004\000\00010\000\000\000\000\000 */ +{ 94678 }, /* itlb-read-ops\000legacy cache\000Instruction TLB read access= es\000legacy-cache-config=3D4\000\00010\000\000\000\000\000 */ +{ 94585 }, /* itlb-read-reference\000legacy cache\000Instruction TLB read = accesses\000legacy-cache-config=3D4\000\00010\000\000\000\000\000 */ +{ 94497 }, /* itlb-read-refs\000legacy cache\000Instruction TLB read acces= ses\000legacy-cache-config=3D4\000\00010\000\000\000\000\000 */ +{ 95124 }, /* itlb-reference\000legacy cache\000Instruction TLB read acces= ses\000legacy-cache-config=3D4\000\00010\000\000\000\000\000 */ +{ 95041 }, /* itlb-refs\000legacy cache\000Instruction TLB read accesses\0= 00legacy-cache-config=3D4\000\00010\000\000\000\000\000 */ +{ 8037 }, /* l1-d\000legacy cache\000Level 1 data cache read accesses\000l= egacy-cache-config=3D0\000\00010\000\000\000\000\000 */ +{ 15406 }, /* l1-d-access\000legacy cache\000Level 1 data cache read acces= ses\000legacy-cache-config=3D0\000\00010\000\000\000\000\000 */ +{ 8118 }, /* l1-d-load\000legacy cache\000Level 1 data cache read accesses= \000legacy-cache-config=3D0\000\00010\000\000\000\000\000 */ +{ 8481 }, /* l1-d-load-access\000legacy cache\000Level 1 data cache read a= ccesses\000legacy-cache-config=3D0\000\00010\000\000\000\000\000 */ +{ 8671 }, /* l1-d-load-miss\000legacy cache\000Level 1 data cache read mis= ses\000legacy-cache-config=3D0x10000\000\00010\000\000\000\000\000 */ +{ 8574 }, /* l1-d-load-misses\000legacy cache\000Level 1 data cache read m= isses\000legacy-cache-config=3D0x10000\000\00010\000\000\000\000\000 */ +{ 8391 }, /* l1-d-load-ops\000legacy cache\000Level 1 data cache read acce= sses\000legacy-cache-config=3D0\000\00010\000\000\000\000\000 */ +{ 8295 }, /* l1-d-load-reference\000legacy cache\000Level 1 data cache rea= d accesses\000legacy-cache-config=3D0\000\00010\000\000\000\000\000 */ +{ 8204 }, /* l1-d-load-refs\000legacy cache\000Level 1 data cache read acc= esses\000legacy-cache-config=3D0\000\00010\000\000\000\000\000 */ +{ 8766 }, /* l1-d-loads\000legacy cache\000Level 1 data cache read accesse= s\000legacy-cache-config=3D0\000\00010\000\000\000\000\000 */ +{ 9133 }, /* l1-d-loads-access\000legacy cache\000Level 1 data cache read = accesses\000legacy-cache-config=3D0\000\00010\000\000\000\000\000 */ +{ 9325 }, /* l1-d-loads-miss\000legacy cache\000Level 1 data cache read mi= sses\000legacy-cache-config=3D0x10000\000\00010\000\000\000\000\000 */ +{ 9227 }, /* l1-d-loads-misses\000legacy cache\000Level 1 data cache read = misses\000legacy-cache-config=3D0x10000\000\00010\000\000\000\000\000 */ +{ 9042 }, /* l1-d-loads-ops\000legacy cache\000Level 1 data cache read acc= esses\000legacy-cache-config=3D0\000\00010\000\000\000\000\000 */ +{ 8945 }, /* l1-d-loads-reference\000legacy cache\000Level 1 data cache re= ad accesses\000legacy-cache-config=3D0\000\00010\000\000\000\000\000 */ +{ 8853 }, /* l1-d-loads-refs\000legacy cache\000Level 1 data cache read ac= cesses\000legacy-cache-config=3D0\000\00010\000\000\000\000\000 */ +{ 15586 }, /* l1-d-miss\000legacy cache\000Level 1 data cache read misses\= 000legacy-cache-config=3D0x10000\000\00010\000\000\000\000\000 */ +{ 15494 }, /* l1-d-misses\000legacy cache\000Level 1 data cache read misse= s\000legacy-cache-config=3D0x10000\000\00010\000\000\000\000\000 */ +{ 15321 }, /* l1-d-ops\000legacy cache\000Level 1 data cache read accesses= \000legacy-cache-config=3D0\000\00010\000\000\000\000\000 */ +{ 12122 }, /* l1-d-prefetch\000legacy cache\000Level 1 data cache prefetch= accesses\000legacy-cache-config=3D0x200\000\00010\000\000\000\000\000 */ +{ 12533 }, /* l1-d-prefetch-access\000legacy cache\000Level 1 data cache p= refetch accesses\000legacy-cache-config=3D0x200\000\00010\000\000\000\000\0= 00 */ +{ 12743 }, /* l1-d-prefetch-miss\000legacy cache\000Level 1 data cache pre= fetch misses\000legacy-cache-config=3D0x10200\000\00010\000\000\000\000\000= */ +{ 12638 }, /* l1-d-prefetch-misses\000legacy cache\000Level 1 data cache p= refetch misses\000legacy-cache-config=3D0x10200\000\00010\000\000\000\000\0= 00 */ +{ 12431 }, /* l1-d-prefetch-ops\000legacy cache\000Level 1 data cache pref= etch accesses\000legacy-cache-config=3D0x200\000\00010\000\000\000\000\000 = */ +{ 12323 }, /* l1-d-prefetch-reference\000legacy cache\000Level 1 data cach= e prefetch accesses\000legacy-cache-config=3D0x200\000\00010\000\000\000\00= 0\000 */ +{ 12220 }, /* l1-d-prefetch-refs\000legacy cache\000Level 1 data cache pre= fetch accesses\000legacy-cache-config=3D0x200\000\00010\000\000\000\000\000= */ +{ 12846 }, /* l1-d-prefetches\000legacy cache\000Level 1 data cache prefet= ch accesses\000legacy-cache-config=3D0x200\000\00010\000\000\000\000\000 */ +{ 13265 }, /* l1-d-prefetches-access\000legacy cache\000Level 1 data cache= prefetch accesses\000legacy-cache-config=3D0x200\000\00010\000\000\000\000= \000 */ +{ 13479 }, /* l1-d-prefetches-miss\000legacy cache\000Level 1 data cache p= refetch misses\000legacy-cache-config=3D0x10200\000\00010\000\000\000\000\0= 00 */ +{ 13372 }, /* l1-d-prefetches-misses\000legacy cache\000Level 1 data cache= prefetch misses\000legacy-cache-config=3D0x10200\000\00010\000\000\000\000= \000 */ +{ 13161 }, /* l1-d-prefetches-ops\000legacy cache\000Level 1 data cache pr= efetch accesses\000legacy-cache-config=3D0x200\000\00010\000\000\000\000\00= 0 */ +{ 13051 }, /* l1-d-prefetches-reference\000legacy cache\000Level 1 data ca= che prefetch accesses\000legacy-cache-config=3D0x200\000\00010\000\000\000\= 000\000 */ +{ 12946 }, /* l1-d-prefetches-refs\000legacy cache\000Level 1 data cache p= refetch accesses\000legacy-cache-config=3D0x200\000\00010\000\000\000\000\0= 00 */ +{ 9421 }, /* l1-d-read\000legacy cache\000Level 1 data cache read accesses= \000legacy-cache-config=3D0\000\00010\000\000\000\000\000 */ +{ 9784 }, /* l1-d-read-access\000legacy cache\000Level 1 data cache read a= ccesses\000legacy-cache-config=3D0\000\00010\000\000\000\000\000 */ +{ 9974 }, /* l1-d-read-miss\000legacy cache\000Level 1 data cache read mis= ses\000legacy-cache-config=3D0x10000\000\00010\000\000\000\000\000 */ +{ 9877 }, /* l1-d-read-misses\000legacy cache\000Level 1 data cache read m= isses\000legacy-cache-config=3D0x10000\000\00010\000\000\000\000\000 */ +{ 9694 }, /* l1-d-read-ops\000legacy cache\000Level 1 data cache read acce= sses\000legacy-cache-config=3D0\000\00010\000\000\000\000\000 */ +{ 9598 }, /* l1-d-read-reference\000legacy cache\000Level 1 data cache rea= d accesses\000legacy-cache-config=3D0\000\00010\000\000\000\000\000 */ +{ 9507 }, /* l1-d-read-refs\000legacy cache\000Level 1 data cache read acc= esses\000legacy-cache-config=3D0\000\00010\000\000\000\000\000 */ +{ 15230 }, /* l1-d-reference\000legacy cache\000Level 1 data cache read ac= cesses\000legacy-cache-config=3D0\000\00010\000\000\000\000\000 */ +{ 15144 }, /* l1-d-refs\000legacy cache\000Level 1 data cache read accesse= s\000legacy-cache-config=3D0\000\00010\000\000\000\000\000 */ +{ 14364 }, /* l1-d-speculative-load\000legacy cache\000Level 1 data cache = prefetch accesses\000legacy-cache-config=3D0x200\000\00010\000\000\000\000\= 000 */ +{ 14807 }, /* l1-d-speculative-load-access\000legacy cache\000Level 1 data= cache prefetch accesses\000legacy-cache-config=3D0x200\000\00010\000\000\0= 00\000\000 */ +{ 15033 }, /* l1-d-speculative-load-miss\000legacy cache\000Level 1 data c= ache prefetch misses\000legacy-cache-config=3D0x10200\000\00010\000\000\000= \000\000 */ +{ 14920 }, /* l1-d-speculative-load-misses\000legacy cache\000Level 1 data= cache prefetch misses\000legacy-cache-config=3D0x10200\000\00010\000\000\0= 00\000\000 */ +{ 14697 }, /* l1-d-speculative-load-ops\000legacy cache\000Level 1 data ca= che prefetch accesses\000legacy-cache-config=3D0x200\000\00010\000\000\000\= 000\000 */ +{ 14581 }, /* l1-d-speculative-load-reference\000legacy cache\000Level 1 d= ata cache prefetch accesses\000legacy-cache-config=3D0x200\000\00010\000\00= 0\000\000\000 */ +{ 14470 }, /* l1-d-speculative-load-refs\000legacy cache\000Level 1 data c= ache prefetch accesses\000legacy-cache-config=3D0x200\000\00010\000\000\000= \000\000 */ +{ 13584 }, /* l1-d-speculative-read\000legacy cache\000Level 1 data cache = prefetch accesses\000legacy-cache-config=3D0x200\000\00010\000\000\000\000\= 000 */ +{ 14027 }, /* l1-d-speculative-read-access\000legacy cache\000Level 1 data= cache prefetch accesses\000legacy-cache-config=3D0x200\000\00010\000\000\0= 00\000\000 */ +{ 14253 }, /* l1-d-speculative-read-miss\000legacy cache\000Level 1 data c= ache prefetch misses\000legacy-cache-config=3D0x10200\000\00010\000\000\000= \000\000 */ +{ 14140 }, /* l1-d-speculative-read-misses\000legacy cache\000Level 1 data= cache prefetch misses\000legacy-cache-config=3D0x10200\000\00010\000\000\0= 00\000\000 */ +{ 13917 }, /* l1-d-speculative-read-ops\000legacy cache\000Level 1 data ca= che prefetch accesses\000legacy-cache-config=3D0x200\000\00010\000\000\000\= 000\000 */ +{ 13801 }, /* l1-d-speculative-read-reference\000legacy cache\000Level 1 d= ata cache prefetch accesses\000legacy-cache-config=3D0x200\000\00010\000\00= 0\000\000\000 */ +{ 13690 }, /* l1-d-speculative-read-refs\000legacy cache\000Level 1 data c= ache prefetch accesses\000legacy-cache-config=3D0x200\000\00010\000\000\000= \000\000 */ +{ 10069 }, /* l1-d-store\000legacy cache\000Level 1 data cache write acces= ses\000legacy-cache-config=3D0x100\000\00010\000\000\000\000\000 */ +{ 10456 }, /* l1-d-store-access\000legacy cache\000Level 1 data cache writ= e accesses\000legacy-cache-config=3D0x100\000\00010\000\000\000\000\000 */ +{ 10654 }, /* l1-d-store-miss\000legacy cache\000Level 1 data cache write = misses\000legacy-cache-config=3D0x10100\000\00010\000\000\000\000\000 */ +{ 10555 }, /* l1-d-store-misses\000legacy cache\000Level 1 data cache writ= e misses\000legacy-cache-config=3D0x10100\000\00010\000\000\000\000\000 */ +{ 10360 }, /* l1-d-store-ops\000legacy cache\000Level 1 data cache write a= ccesses\000legacy-cache-config=3D0x100\000\00010\000\000\000\000\000 */ +{ 10258 }, /* l1-d-store-reference\000legacy cache\000Level 1 data cache w= rite accesses\000legacy-cache-config=3D0x100\000\00010\000\000\000\000\000 = */ +{ 10161 }, /* l1-d-store-refs\000legacy cache\000Level 1 data cache write = accesses\000legacy-cache-config=3D0x100\000\00010\000\000\000\000\000 */ +{ 10751 }, /* l1-d-stores\000legacy cache\000Level 1 data cache write acce= sses\000legacy-cache-config=3D0x100\000\00010\000\000\000\000\000 */ +{ 11142 }, /* l1-d-stores-access\000legacy cache\000Level 1 data cache wri= te accesses\000legacy-cache-config=3D0x100\000\00010\000\000\000\000\000 */ +{ 11342 }, /* l1-d-stores-miss\000legacy cache\000Level 1 data cache write= misses\000legacy-cache-config=3D0x10100\000\00010\000\000\000\000\000 */ +{ 11242 }, /* l1-d-stores-misses\000legacy cache\000Level 1 data cache wri= te misses\000legacy-cache-config=3D0x10100\000\00010\000\000\000\000\000 */ +{ 11045 }, /* l1-d-stores-ops\000legacy cache\000Level 1 data cache write = accesses\000legacy-cache-config=3D0x100\000\00010\000\000\000\000\000 */ +{ 10942 }, /* l1-d-stores-reference\000legacy cache\000Level 1 data cache = write accesses\000legacy-cache-config=3D0x100\000\00010\000\000\000\000\000= */ +{ 10844 }, /* l1-d-stores-refs\000legacy cache\000Level 1 data cache write= accesses\000legacy-cache-config=3D0x100\000\00010\000\000\000\000\000 */ +{ 11440 }, /* l1-d-write\000legacy cache\000Level 1 data cache write acces= ses\000legacy-cache-config=3D0x100\000\00010\000\000\000\000\000 */ +{ 11827 }, /* l1-d-write-access\000legacy cache\000Level 1 data cache writ= e accesses\000legacy-cache-config=3D0x100\000\00010\000\000\000\000\000 */ +{ 12025 }, /* l1-d-write-miss\000legacy cache\000Level 1 data cache write = misses\000legacy-cache-config=3D0x10100\000\00010\000\000\000\000\000 */ +{ 11926 }, /* l1-d-write-misses\000legacy cache\000Level 1 data cache writ= e misses\000legacy-cache-config=3D0x10100\000\00010\000\000\000\000\000 */ +{ 11731 }, /* l1-d-write-ops\000legacy cache\000Level 1 data cache write a= ccesses\000legacy-cache-config=3D0x100\000\00010\000\000\000\000\000 */ +{ 11629 }, /* l1-d-write-reference\000legacy cache\000Level 1 data cache w= rite accesses\000legacy-cache-config=3D0x100\000\00010\000\000\000\000\000 = */ +{ 11532 }, /* l1-d-write-refs\000legacy cache\000Level 1 data cache write = accesses\000legacy-cache-config=3D0x100\000\00010\000\000\000\000\000 */ +{ 23238 }, /* l1-data\000legacy cache\000Level 1 data cache read accesses\= 000legacy-cache-config=3D0\000\00010\000\000\000\000\000 */ +{ 30829 }, /* l1-data-access\000legacy cache\000Level 1 data cache read ac= cesses\000legacy-cache-config=3D0\000\00010\000\000\000\000\000 */ +{ 23322 }, /* l1-data-load\000legacy cache\000Level 1 data cache read acce= sses\000legacy-cache-config=3D0\000\00010\000\000\000\000\000 */ +{ 23697 }, /* l1-data-load-access\000legacy cache\000Level 1 data cache re= ad accesses\000legacy-cache-config=3D0\000\00010\000\000\000\000\000 */ +{ 23893 }, /* l1-data-load-miss\000legacy cache\000Level 1 data cache read= misses\000legacy-cache-config=3D0x10000\000\00010\000\000\000\000\000 */ +{ 23793 }, /* l1-data-load-misses\000legacy cache\000Level 1 data cache re= ad misses\000legacy-cache-config=3D0x10000\000\00010\000\000\000\000\000 */ +{ 23604 }, /* l1-data-load-ops\000legacy cache\000Level 1 data cache read = accesses\000legacy-cache-config=3D0\000\00010\000\000\000\000\000 */ +{ 23505 }, /* l1-data-load-reference\000legacy cache\000Level 1 data cache= read accesses\000legacy-cache-config=3D0\000\00010\000\000\000\000\000 */ +{ 23411 }, /* l1-data-load-refs\000legacy cache\000Level 1 data cache read= accesses\000legacy-cache-config=3D0\000\00010\000\000\000\000\000 */ +{ 23991 }, /* l1-data-loads\000legacy cache\000Level 1 data cache read acc= esses\000legacy-cache-config=3D0\000\00010\000\000\000\000\000 */ +{ 24370 }, /* l1-data-loads-access\000legacy cache\000Level 1 data cache r= ead accesses\000legacy-cache-config=3D0\000\00010\000\000\000\000\000 */ +{ 24568 }, /* l1-data-loads-miss\000legacy cache\000Level 1 data cache rea= d misses\000legacy-cache-config=3D0x10000\000\00010\000\000\000\000\000 */ +{ 24467 }, /* l1-data-loads-misses\000legacy cache\000Level 1 data cache r= ead misses\000legacy-cache-config=3D0x10000\000\00010\000\000\000\000\000 */ +{ 24276 }, /* l1-data-loads-ops\000legacy cache\000Level 1 data cache read= accesses\000legacy-cache-config=3D0\000\00010\000\000\000\000\000 */ +{ 24176 }, /* l1-data-loads-reference\000legacy cache\000Level 1 data cach= e read accesses\000legacy-cache-config=3D0\000\00010\000\000\000\000\000 */ +{ 24081 }, /* l1-data-loads-refs\000legacy cache\000Level 1 data cache rea= d accesses\000legacy-cache-config=3D0\000\00010\000\000\000\000\000 */ +{ 31015 }, /* l1-data-miss\000legacy cache\000Level 1 data cache read miss= es\000legacy-cache-config=3D0x10000\000\00010\000\000\000\000\000 */ +{ 30920 }, /* l1-data-misses\000legacy cache\000Level 1 data cache read mi= sses\000legacy-cache-config=3D0x10000\000\00010\000\000\000\000\000 */ +{ 30741 }, /* l1-data-ops\000legacy cache\000Level 1 data cache read acces= ses\000legacy-cache-config=3D0\000\00010\000\000\000\000\000 */ +{ 27452 }, /* l1-data-prefetch\000legacy cache\000Level 1 data cache prefe= tch accesses\000legacy-cache-config=3D0x200\000\00010\000\000\000\000\000 */ +{ 27875 }, /* l1-data-prefetch-access\000legacy cache\000Level 1 data cach= e prefetch accesses\000legacy-cache-config=3D0x200\000\00010\000\000\000\00= 0\000 */ +{ 28091 }, /* l1-data-prefetch-miss\000legacy cache\000Level 1 data cache = prefetch misses\000legacy-cache-config=3D0x10200\000\00010\000\000\000\000\= 000 */ +{ 27983 }, /* l1-data-prefetch-misses\000legacy cache\000Level 1 data cach= e prefetch misses\000legacy-cache-config=3D0x10200\000\00010\000\000\000\00= 0\000 */ +{ 27770 }, /* l1-data-prefetch-ops\000legacy cache\000Level 1 data cache p= refetch accesses\000legacy-cache-config=3D0x200\000\00010\000\000\000\000\0= 00 */ +{ 27659 }, /* l1-data-prefetch-reference\000legacy cache\000Level 1 data c= ache prefetch accesses\000legacy-cache-config=3D0x200\000\00010\000\000\000= \000\000 */ +{ 27553 }, /* l1-data-prefetch-refs\000legacy cache\000Level 1 data cache = prefetch accesses\000legacy-cache-config=3D0x200\000\00010\000\000\000\000\= 000 */ +{ 28197 }, /* l1-data-prefetches\000legacy cache\000Level 1 data cache pre= fetch accesses\000legacy-cache-config=3D0x200\000\00010\000\000\000\000\000= */ +{ 28628 }, /* l1-data-prefetches-access\000legacy cache\000Level 1 data ca= che prefetch accesses\000legacy-cache-config=3D0x200\000\00010\000\000\000\= 000\000 */ +{ 28848 }, /* l1-data-prefetches-miss\000legacy cache\000Level 1 data cach= e prefetch misses\000legacy-cache-config=3D0x10200\000\00010\000\000\000\00= 0\000 */ +{ 28738 }, /* l1-data-prefetches-misses\000legacy cache\000Level 1 data ca= che prefetch misses\000legacy-cache-config=3D0x10200\000\00010\000\000\000\= 000\000 */ +{ 28521 }, /* l1-data-prefetches-ops\000legacy cache\000Level 1 data cache= prefetch accesses\000legacy-cache-config=3D0x200\000\00010\000\000\000\000= \000 */ +{ 28408 }, /* l1-data-prefetches-reference\000legacy cache\000Level 1 data= cache prefetch accesses\000legacy-cache-config=3D0x200\000\00010\000\000\0= 00\000\000 */ +{ 28300 }, /* l1-data-prefetches-refs\000legacy cache\000Level 1 data cach= e prefetch accesses\000legacy-cache-config=3D0x200\000\00010\000\000\000\00= 0\000 */ +{ 24667 }, /* l1-data-read\000legacy cache\000Level 1 data cache read acce= sses\000legacy-cache-config=3D0\000\00010\000\000\000\000\000 */ +{ 25042 }, /* l1-data-read-access\000legacy cache\000Level 1 data cache re= ad accesses\000legacy-cache-config=3D0\000\00010\000\000\000\000\000 */ +{ 25238 }, /* l1-data-read-miss\000legacy cache\000Level 1 data cache read= misses\000legacy-cache-config=3D0x10000\000\00010\000\000\000\000\000 */ +{ 25138 }, /* l1-data-read-misses\000legacy cache\000Level 1 data cache re= ad misses\000legacy-cache-config=3D0x10000\000\00010\000\000\000\000\000 */ +{ 24949 }, /* l1-data-read-ops\000legacy cache\000Level 1 data cache read = accesses\000legacy-cache-config=3D0\000\00010\000\000\000\000\000 */ +{ 24850 }, /* l1-data-read-reference\000legacy cache\000Level 1 data cache= read accesses\000legacy-cache-config=3D0\000\00010\000\000\000\000\000 */ +{ 24756 }, /* l1-data-read-refs\000legacy cache\000Level 1 data cache read= accesses\000legacy-cache-config=3D0\000\00010\000\000\000\000\000 */ +{ 30647 }, /* l1-data-reference\000legacy cache\000Level 1 data cache read= accesses\000legacy-cache-config=3D0\000\00010\000\000\000\000\000 */ +{ 30558 }, /* l1-data-refs\000legacy cache\000Level 1 data cache read acce= sses\000legacy-cache-config=3D0\000\00010\000\000\000\000\000 */ +{ 29757 }, /* l1-data-speculative-load\000legacy cache\000Level 1 data cac= he prefetch accesses\000legacy-cache-config=3D0x200\000\00010\000\000\000\0= 00\000 */ +{ 30212 }, /* l1-data-speculative-load-access\000legacy cache\000Level 1 d= ata cache prefetch accesses\000legacy-cache-config=3D0x200\000\00010\000\00= 0\000\000\000 */ +{ 30444 }, /* l1-data-speculative-load-miss\000legacy cache\000Level 1 dat= a cache prefetch misses\000legacy-cache-config=3D0x10200\000\00010\000\000\= 000\000\000 */ +{ 30328 }, /* l1-data-speculative-load-misses\000legacy cache\000Level 1 d= ata cache prefetch misses\000legacy-cache-config=3D0x10200\000\00010\000\00= 0\000\000\000 */ +{ 30099 }, /* l1-data-speculative-load-ops\000legacy cache\000Level 1 data= cache prefetch accesses\000legacy-cache-config=3D0x200\000\00010\000\000\0= 00\000\000 */ +{ 29980 }, /* l1-data-speculative-load-reference\000legacy cache\000Level = 1 data cache prefetch accesses\000legacy-cache-config=3D0x200\000\00010\000= \000\000\000\000 */ +{ 29866 }, /* l1-data-speculative-load-refs\000legacy cache\000Level 1 dat= a cache prefetch accesses\000legacy-cache-config=3D0x200\000\00010\000\000\= 000\000\000 */ +{ 28956 }, /* l1-data-speculative-read\000legacy cache\000Level 1 data cac= he prefetch accesses\000legacy-cache-config=3D0x200\000\00010\000\000\000\0= 00\000 */ +{ 29411 }, /* l1-data-speculative-read-access\000legacy cache\000Level 1 d= ata cache prefetch accesses\000legacy-cache-config=3D0x200\000\00010\000\00= 0\000\000\000 */ +{ 29643 }, /* l1-data-speculative-read-miss\000legacy cache\000Level 1 dat= a cache prefetch misses\000legacy-cache-config=3D0x10200\000\00010\000\000\= 000\000\000 */ +{ 29527 }, /* l1-data-speculative-read-misses\000legacy cache\000Level 1 d= ata cache prefetch misses\000legacy-cache-config=3D0x10200\000\00010\000\00= 0\000\000\000 */ +{ 29298 }, /* l1-data-speculative-read-ops\000legacy cache\000Level 1 data= cache prefetch accesses\000legacy-cache-config=3D0x200\000\00010\000\000\0= 00\000\000 */ +{ 29179 }, /* l1-data-speculative-read-reference\000legacy cache\000Level = 1 data cache prefetch accesses\000legacy-cache-config=3D0x200\000\00010\000= \000\000\000\000 */ +{ 29065 }, /* l1-data-speculative-read-refs\000legacy cache\000Level 1 dat= a cache prefetch accesses\000legacy-cache-config=3D0x200\000\00010\000\000\= 000\000\000 */ +{ 25336 }, /* l1-data-store\000legacy cache\000Level 1 data cache write ac= cesses\000legacy-cache-config=3D0x100\000\00010\000\000\000\000\000 */ +{ 25735 }, /* l1-data-store-access\000legacy cache\000Level 1 data cache w= rite accesses\000legacy-cache-config=3D0x100\000\00010\000\000\000\000\000 = */ +{ 25939 }, /* l1-data-store-miss\000legacy cache\000Level 1 data cache wri= te misses\000legacy-cache-config=3D0x10100\000\00010\000\000\000\000\000 */ +{ 25837 }, /* l1-data-store-misses\000legacy cache\000Level 1 data cache w= rite misses\000legacy-cache-config=3D0x10100\000\00010\000\000\000\000\000 = */ +{ 25636 }, /* l1-data-store-ops\000legacy cache\000Level 1 data cache writ= e accesses\000legacy-cache-config=3D0x100\000\00010\000\000\000\000\000 */ +{ 25531 }, /* l1-data-store-reference\000legacy cache\000Level 1 data cach= e write accesses\000legacy-cache-config=3D0x100\000\00010\000\000\000\000\0= 00 */ +{ 25431 }, /* l1-data-store-refs\000legacy cache\000Level 1 data cache wri= te accesses\000legacy-cache-config=3D0x100\000\00010\000\000\000\000\000 */ +{ 26039 }, /* l1-data-stores\000legacy cache\000Level 1 data cache write a= ccesses\000legacy-cache-config=3D0x100\000\00010\000\000\000\000\000 */ +{ 26442 }, /* l1-data-stores-access\000legacy cache\000Level 1 data cache = write accesses\000legacy-cache-config=3D0x100\000\00010\000\000\000\000\000= */ +{ 26648 }, /* l1-data-stores-miss\000legacy cache\000Level 1 data cache wr= ite misses\000legacy-cache-config=3D0x10100\000\00010\000\000\000\000\000 */ +{ 26545 }, /* l1-data-stores-misses\000legacy cache\000Level 1 data cache = write misses\000legacy-cache-config=3D0x10100\000\00010\000\000\000\000\000= */ +{ 26342 }, /* l1-data-stores-ops\000legacy cache\000Level 1 data cache wri= te accesses\000legacy-cache-config=3D0x100\000\00010\000\000\000\000\000 */ +{ 26236 }, /* l1-data-stores-reference\000legacy cache\000Level 1 data cac= he write accesses\000legacy-cache-config=3D0x100\000\00010\000\000\000\000\= 000 */ +{ 26135 }, /* l1-data-stores-refs\000legacy cache\000Level 1 data cache wr= ite accesses\000legacy-cache-config=3D0x100\000\00010\000\000\000\000\000 */ +{ 26749 }, /* l1-data-write\000legacy cache\000Level 1 data cache write ac= cesses\000legacy-cache-config=3D0x100\000\00010\000\000\000\000\000 */ +{ 27148 }, /* l1-data-write-access\000legacy cache\000Level 1 data cache w= rite accesses\000legacy-cache-config=3D0x100\000\00010\000\000\000\000\000 = */ +{ 27352 }, /* l1-data-write-miss\000legacy cache\000Level 1 data cache wri= te misses\000legacy-cache-config=3D0x10100\000\00010\000\000\000\000\000 */ +{ 27250 }, /* l1-data-write-misses\000legacy cache\000Level 1 data cache w= rite misses\000legacy-cache-config=3D0x10100\000\00010\000\000\000\000\000 = */ +{ 27049 }, /* l1-data-write-ops\000legacy cache\000Level 1 data cache writ= e accesses\000legacy-cache-config=3D0x100\000\00010\000\000\000\000\000 */ +{ 26944 }, /* l1-data-write-reference\000legacy cache\000Level 1 data cach= e write accesses\000legacy-cache-config=3D0x100\000\00010\000\000\000\000\0= 00 */ +{ 26844 }, /* l1-data-write-refs\000legacy cache\000Level 1 data cache wri= te accesses\000legacy-cache-config=3D0x100\000\00010\000\000\000\000\000 */ +{ 13 }, /* l1-dcache\000legacy cache\000Level 1 data cache read accesses\0= 00legacy-cache-config=3D0\000\00010\000\000\000\000\000 */ +{ 7752 }, /* l1-dcache-access\000legacy cache\000Level 1 data cache read a= ccesses\000legacy-cache-config=3D0\000\00010\000\000\000\000\000 */ +{ 99 }, /* l1-dcache-load\000legacy cache\000Level 1 data cache read acces= ses\000legacy-cache-config=3D0\000\00010\000\000\000\000\000 */ +{ 482 }, /* l1-dcache-load-access\000legacy cache\000Level 1 data cache re= ad accesses\000legacy-cache-config=3D0\000\00010\000\000\000\000\000 */ +{ 682 }, /* l1-dcache-load-miss\000legacy cache\000Level 1 data cache read= misses\000legacy-cache-config=3D0x10000\000\00010\000\000\000\000\000 */ +{ 580 }, /* l1-dcache-load-misses\000legacy cache\000Level 1 data cache re= ad misses\000legacy-cache-config=3D0x10000\000\00000\000\000\000\000\000 */ +{ 387 }, /* l1-dcache-load-ops\000legacy cache\000Level 1 data cache read = accesses\000legacy-cache-config=3D0\000\00010\000\000\000\000\000 */ +{ 286 }, /* l1-dcache-load-reference\000legacy cache\000Level 1 data cache= read accesses\000legacy-cache-config=3D0\000\00010\000\000\000\000\000 */ +{ 190 }, /* l1-dcache-load-refs\000legacy cache\000Level 1 data cache read= accesses\000legacy-cache-config=3D0\000\00010\000\000\000\000\000 */ +{ 782 }, /* l1-dcache-loads\000legacy cache\000Level 1 data cache read acc= esses\000legacy-cache-config=3D0\000\00000\000\000\000\000\000 */ +{ 1169 }, /* l1-dcache-loads-access\000legacy cache\000Level 1 data cache = read accesses\000legacy-cache-config=3D0\000\00010\000\000\000\000\000 */ +{ 1371 }, /* l1-dcache-loads-miss\000legacy cache\000Level 1 data cache re= ad misses\000legacy-cache-config=3D0x10000\000\00010\000\000\000\000\000 */ +{ 1268 }, /* l1-dcache-loads-misses\000legacy cache\000Level 1 data cache = read misses\000legacy-cache-config=3D0x10000\000\00010\000\000\000\000\000 = */ +{ 1073 }, /* l1-dcache-loads-ops\000legacy cache\000Level 1 data cache rea= d accesses\000legacy-cache-config=3D0\000\00010\000\000\000\000\000 */ +{ 971 }, /* l1-dcache-loads-reference\000legacy cache\000Level 1 data cach= e read accesses\000legacy-cache-config=3D0\000\00010\000\000\000\000\000 */ +{ 874 }, /* l1-dcache-loads-refs\000legacy cache\000Level 1 data cache rea= d accesses\000legacy-cache-config=3D0\000\00010\000\000\000\000\000 */ +{ 7942 }, /* l1-dcache-miss\000legacy cache\000Level 1 data cache read mis= ses\000legacy-cache-config=3D0x10000\000\00010\000\000\000\000\000 */ +{ 7845 }, /* l1-dcache-misses\000legacy cache\000Level 1 data cache read m= isses\000legacy-cache-config=3D0x10000\000\00010\000\000\000\000\000 */ +{ 7662 }, /* l1-dcache-ops\000legacy cache\000Level 1 data cache read acce= sses\000legacy-cache-config=3D0\000\00010\000\000\000\000\000 */ +{ 4313 }, /* l1-dcache-prefetch\000legacy cache\000Level 1 data cache pref= etch accesses\000legacy-cache-config=3D0x200\000\00010\000\000\000\000\000 = */ +{ 4744 }, /* l1-dcache-prefetch-access\000legacy cache\000Level 1 data cac= he prefetch accesses\000legacy-cache-config=3D0x200\000\00010\000\000\000\0= 00\000 */ +{ 4964 }, /* l1-dcache-prefetch-miss\000legacy cache\000Level 1 data cache= prefetch misses\000legacy-cache-config=3D0x10200\000\00010\000\000\000\000= \000 */ +{ 4854 }, /* l1-dcache-prefetch-misses\000legacy cache\000Level 1 data cac= he prefetch misses\000legacy-cache-config=3D0x10200\000\00000\000\000\000\0= 00\000 */ +{ 4637 }, /* l1-dcache-prefetch-ops\000legacy cache\000Level 1 data cache = prefetch accesses\000legacy-cache-config=3D0x200\000\00010\000\000\000\000\= 000 */ +{ 4524 }, /* l1-dcache-prefetch-reference\000legacy cache\000Level 1 data = cache prefetch accesses\000legacy-cache-config=3D0x200\000\00010\000\000\00= 0\000\000 */ +{ 4416 }, /* l1-dcache-prefetch-refs\000legacy cache\000Level 1 data cache= prefetch accesses\000legacy-cache-config=3D0x200\000\00010\000\000\000\000= \000 */ +{ 5072 }, /* l1-dcache-prefetches\000legacy cache\000Level 1 data cache pr= efetch accesses\000legacy-cache-config=3D0x200\000\00000\000\000\000\000\00= 0 */ +{ 5511 }, /* l1-dcache-prefetches-access\000legacy cache\000Level 1 data c= ache prefetch accesses\000legacy-cache-config=3D0x200\000\00010\000\000\000= \000\000 */ +{ 5735 }, /* l1-dcache-prefetches-miss\000legacy cache\000Level 1 data cac= he prefetch misses\000legacy-cache-config=3D0x10200\000\00010\000\000\000\0= 00\000 */ +{ 5623 }, /* l1-dcache-prefetches-misses\000legacy cache\000Level 1 data c= ache prefetch misses\000legacy-cache-config=3D0x10200\000\00010\000\000\000= \000\000 */ +{ 5402 }, /* l1-dcache-prefetches-ops\000legacy cache\000Level 1 data cach= e prefetch accesses\000legacy-cache-config=3D0x200\000\00010\000\000\000\00= 0\000 */ +{ 5287 }, /* l1-dcache-prefetches-reference\000legacy cache\000Level 1 dat= a cache prefetch accesses\000legacy-cache-config=3D0x200\000\00010\000\000\= 000\000\000 */ +{ 5177 }, /* l1-dcache-prefetches-refs\000legacy cache\000Level 1 data cac= he prefetch accesses\000legacy-cache-config=3D0x200\000\00010\000\000\000\0= 00\000 */ +{ 1472 }, /* l1-dcache-read\000legacy cache\000Level 1 data cache read acc= esses\000legacy-cache-config=3D0\000\00010\000\000\000\000\000 */ +{ 1855 }, /* l1-dcache-read-access\000legacy cache\000Level 1 data cache r= ead accesses\000legacy-cache-config=3D0\000\00010\000\000\000\000\000 */ +{ 2055 }, /* l1-dcache-read-miss\000legacy cache\000Level 1 data cache rea= d misses\000legacy-cache-config=3D0x10000\000\00010\000\000\000\000\000 */ +{ 1953 }, /* l1-dcache-read-misses\000legacy cache\000Level 1 data cache r= ead misses\000legacy-cache-config=3D0x10000\000\00010\000\000\000\000\000 */ +{ 1760 }, /* l1-dcache-read-ops\000legacy cache\000Level 1 data cache read= accesses\000legacy-cache-config=3D0\000\00010\000\000\000\000\000 */ +{ 1659 }, /* l1-dcache-read-reference\000legacy cache\000Level 1 data cach= e read accesses\000legacy-cache-config=3D0\000\00010\000\000\000\000\000 */ +{ 1563 }, /* l1-dcache-read-refs\000legacy cache\000Level 1 data cache rea= d accesses\000legacy-cache-config=3D0\000\00010\000\000\000\000\000 */ +{ 7566 }, /* l1-dcache-reference\000legacy cache\000Level 1 data cache rea= d accesses\000legacy-cache-config=3D0\000\00010\000\000\000\000\000 */ +{ 7475 }, /* l1-dcache-refs\000legacy cache\000Level 1 data cache read acc= esses\000legacy-cache-config=3D0\000\00010\000\000\000\000\000 */ +{ 6660 }, /* l1-dcache-speculative-load\000legacy cache\000Level 1 data ca= che prefetch accesses\000legacy-cache-config=3D0x200\000\00010\000\000\000\= 000\000 */ +{ 7123 }, /* l1-dcache-speculative-load-access\000legacy cache\000Level 1 = data cache prefetch accesses\000legacy-cache-config=3D0x200\000\00010\000\0= 00\000\000\000 */ +{ 7359 }, /* l1-dcache-speculative-load-miss\000legacy cache\000Level 1 da= ta cache prefetch misses\000legacy-cache-config=3D0x10200\000\00010\000\000= \000\000\000 */ +{ 7241 }, /* l1-dcache-speculative-load-misses\000legacy cache\000Level 1 = data cache prefetch misses\000legacy-cache-config=3D0x10200\000\00010\000\0= 00\000\000\000 */ +{ 7008 }, /* l1-dcache-speculative-load-ops\000legacy cache\000Level 1 dat= a cache prefetch accesses\000legacy-cache-config=3D0x200\000\00010\000\000\= 000\000\000 */ +{ 6887 }, /* l1-dcache-speculative-load-reference\000legacy cache\000Level= 1 data cache prefetch accesses\000legacy-cache-config=3D0x200\000\00010\00= 0\000\000\000\000 */ +{ 6771 }, /* l1-dcache-speculative-load-refs\000legacy cache\000Level 1 da= ta cache prefetch accesses\000legacy-cache-config=3D0x200\000\00010\000\000= \000\000\000 */ +{ 5845 }, /* l1-dcache-speculative-read\000legacy cache\000Level 1 data ca= che prefetch accesses\000legacy-cache-config=3D0x200\000\00010\000\000\000\= 000\000 */ +{ 6308 }, /* l1-dcache-speculative-read-access\000legacy cache\000Level 1 = data cache prefetch accesses\000legacy-cache-config=3D0x200\000\00010\000\0= 00\000\000\000 */ +{ 6544 }, /* l1-dcache-speculative-read-miss\000legacy cache\000Level 1 da= ta cache prefetch misses\000legacy-cache-config=3D0x10200\000\00010\000\000= \000\000\000 */ +{ 6426 }, /* l1-dcache-speculative-read-misses\000legacy cache\000Level 1 = data cache prefetch misses\000legacy-cache-config=3D0x10200\000\00010\000\0= 00\000\000\000 */ +{ 6193 }, /* l1-dcache-speculative-read-ops\000legacy cache\000Level 1 dat= a cache prefetch accesses\000legacy-cache-config=3D0x200\000\00010\000\000\= 000\000\000 */ +{ 6072 }, /* l1-dcache-speculative-read-reference\000legacy cache\000Level= 1 data cache prefetch accesses\000legacy-cache-config=3D0x200\000\00010\00= 0\000\000\000\000 */ +{ 5956 }, /* l1-dcache-speculative-read-refs\000legacy cache\000Level 1 da= ta cache prefetch accesses\000legacy-cache-config=3D0x200\000\00010\000\000= \000\000\000 */ +{ 2155 }, /* l1-dcache-store\000legacy cache\000Level 1 data cache write a= ccesses\000legacy-cache-config=3D0x100\000\00010\000\000\000\000\000 */ +{ 2562 }, /* l1-dcache-store-access\000legacy cache\000Level 1 data cache = write accesses\000legacy-cache-config=3D0x100\000\00010\000\000\000\000\000= */ +{ 2770 }, /* l1-dcache-store-miss\000legacy cache\000Level 1 data cache wr= ite misses\000legacy-cache-config=3D0x10100\000\00010\000\000\000\000\000 */ +{ 2666 }, /* l1-dcache-store-misses\000legacy cache\000Level 1 data cache = write misses\000legacy-cache-config=3D0x10100\000\00000\000\000\000\000\000= */ +{ 2461 }, /* l1-dcache-store-ops\000legacy cache\000Level 1 data cache wri= te accesses\000legacy-cache-config=3D0x100\000\00010\000\000\000\000\000 */ +{ 2354 }, /* l1-dcache-store-reference\000legacy cache\000Level 1 data cac= he write accesses\000legacy-cache-config=3D0x100\000\00010\000\000\000\000\= 000 */ +{ 2252 }, /* l1-dcache-store-refs\000legacy cache\000Level 1 data cache wr= ite accesses\000legacy-cache-config=3D0x100\000\00010\000\000\000\000\000 */ +{ 2872 }, /* l1-dcache-stores\000legacy cache\000Level 1 data cache write = accesses\000legacy-cache-config=3D0x100\000\00000\000\000\000\000\000 */ +{ 3283 }, /* l1-dcache-stores-access\000legacy cache\000Level 1 data cache= write accesses\000legacy-cache-config=3D0x100\000\00010\000\000\000\000\00= 0 */ +{ 3493 }, /* l1-dcache-stores-miss\000legacy cache\000Level 1 data cache w= rite misses\000legacy-cache-config=3D0x10100\000\00010\000\000\000\000\000 = */ +{ 3388 }, /* l1-dcache-stores-misses\000legacy cache\000Level 1 data cache= write misses\000legacy-cache-config=3D0x10100\000\00010\000\000\000\000\00= 0 */ +{ 3181 }, /* l1-dcache-stores-ops\000legacy cache\000Level 1 data cache wr= ite accesses\000legacy-cache-config=3D0x100\000\00010\000\000\000\000\000 */ +{ 3073 }, /* l1-dcache-stores-reference\000legacy cache\000Level 1 data ca= che write accesses\000legacy-cache-config=3D0x100\000\00010\000\000\000\000= \000 */ +{ 2970 }, /* l1-dcache-stores-refs\000legacy cache\000Level 1 data cache w= rite accesses\000legacy-cache-config=3D0x100\000\00010\000\000\000\000\000 = */ +{ 3596 }, /* l1-dcache-write\000legacy cache\000Level 1 data cache write a= ccesses\000legacy-cache-config=3D0x100\000\00010\000\000\000\000\000 */ +{ 4003 }, /* l1-dcache-write-access\000legacy cache\000Level 1 data cache = write accesses\000legacy-cache-config=3D0x100\000\00010\000\000\000\000\000= */ +{ 4211 }, /* l1-dcache-write-miss\000legacy cache\000Level 1 data cache wr= ite misses\000legacy-cache-config=3D0x10100\000\00010\000\000\000\000\000 */ +{ 4107 }, /* l1-dcache-write-misses\000legacy cache\000Level 1 data cache = write misses\000legacy-cache-config=3D0x10100\000\00010\000\000\000\000\000= */ +{ 3902 }, /* l1-dcache-write-ops\000legacy cache\000Level 1 data cache wri= te accesses\000legacy-cache-config=3D0x100\000\00010\000\000\000\000\000 */ +{ 3795 }, /* l1-dcache-write-reference\000legacy cache\000Level 1 data cac= he write accesses\000legacy-cache-config=3D0x100\000\00010\000\000\000\000\= 000 */ +{ 3693 }, /* l1-dcache-write-refs\000legacy cache\000Level 1 data cache wr= ite accesses\000legacy-cache-config=3D0x100\000\00010\000\000\000\000\000 */ +{ 37366 }, /* l1-i\000legacy cache\000Level 1 instruction cache read acces= ses\000legacy-cache-config=3D1\000\00010\000\000\000\000\000 */ +{ 43053 }, /* l1-i-access\000legacy cache\000Level 1 instruction cache rea= d accesses\000legacy-cache-config=3D1\000\00010\000\000\000\000\000 */ +{ 37454 }, /* l1-i-load\000legacy cache\000Level 1 instruction cache read = accesses\000legacy-cache-config=3D1\000\00010\000\000\000\000\000 */ +{ 37845 }, /* l1-i-load-access\000legacy cache\000Level 1 instruction cach= e read accesses\000legacy-cache-config=3D1\000\00010\000\000\000\000\000 */ +{ 38049 }, /* l1-i-load-miss\000legacy cache\000Level 1 instruction cache = read misses\000legacy-cache-config=3D0x10001\000\00010\000\000\000\000\000 = */ +{ 37945 }, /* l1-i-load-misses\000legacy cache\000Level 1 instruction cach= e read misses\000legacy-cache-config=3D0x10001\000\00010\000\000\000\000\00= 0 */ +{ 37748 }, /* l1-i-load-ops\000legacy cache\000Level 1 instruction cache r= ead accesses\000legacy-cache-config=3D1\000\00010\000\000\000\000\000 */ +{ 37645 }, /* l1-i-load-reference\000legacy cache\000Level 1 instruction c= ache read accesses\000legacy-cache-config=3D1\000\00010\000\000\000\000\000= */ +{ 37547 }, /* l1-i-load-refs\000legacy cache\000Level 1 instruction cache = read accesses\000legacy-cache-config=3D1\000\00010\000\000\000\000\000 */ +{ 38151 }, /* l1-i-loads\000legacy cache\000Level 1 instruction cache read= accesses\000legacy-cache-config=3D1\000\00010\000\000\000\000\000 */ +{ 38546 }, /* l1-i-loads-access\000legacy cache\000Level 1 instruction cac= he read accesses\000legacy-cache-config=3D1\000\00010\000\000\000\000\000 */ +{ 38752 }, /* l1-i-loads-miss\000legacy cache\000Level 1 instruction cache= read misses\000legacy-cache-config=3D0x10001\000\00010\000\000\000\000\000= */ +{ 38647 }, /* l1-i-loads-misses\000legacy cache\000Level 1 instruction cac= he read misses\000legacy-cache-config=3D0x10001\000\00010\000\000\000\000\0= 00 */ +{ 38448 }, /* l1-i-loads-ops\000legacy cache\000Level 1 instruction cache = read accesses\000legacy-cache-config=3D1\000\00010\000\000\000\000\000 */ +{ 38344 }, /* l1-i-loads-reference\000legacy cache\000Level 1 instruction = cache read accesses\000legacy-cache-config=3D1\000\00010\000\000\000\000\00= 0 */ +{ 38245 }, /* l1-i-loads-refs\000legacy cache\000Level 1 instruction cache= read accesses\000legacy-cache-config=3D1\000\00010\000\000\000\000\000 */ +{ 43247 }, /* l1-i-miss\000legacy cache\000Level 1 instruction cache read = misses\000legacy-cache-config=3D0x10001\000\00010\000\000\000\000\000 */ +{ 43148 }, /* l1-i-misses\000legacy cache\000Level 1 instruction cache rea= d misses\000legacy-cache-config=3D0x10001\000\00010\000\000\000\000\000 */ +{ 42961 }, /* l1-i-ops\000legacy cache\000Level 1 instruction cache read a= ccesses\000legacy-cache-config=3D1\000\00010\000\000\000\000\000 */ +{ 39552 }, /* l1-i-prefetch\000legacy cache\000Level 1 instruction cache p= refetch accesses\000legacy-cache-config=3D0x201\000\00010\000\000\000\000\0= 00 */ +{ 39991 }, /* l1-i-prefetch-access\000legacy cache\000Level 1 instruction = cache prefetch accesses\000legacy-cache-config=3D0x201\000\00010\000\000\00= 0\000\000 */ +{ 40215 }, /* l1-i-prefetch-miss\000legacy cache\000Level 1 instruction ca= che prefetch misses\000legacy-cache-config=3D0x10201\000\00010\000\000\000\= 000\000 */ +{ 40103 }, /* l1-i-prefetch-misses\000legacy cache\000Level 1 instruction = cache prefetch misses\000legacy-cache-config=3D0x10201\000\00010\000\000\00= 0\000\000 */ +{ 39882 }, /* l1-i-prefetch-ops\000legacy cache\000Level 1 instruction cac= he prefetch accesses\000legacy-cache-config=3D0x201\000\00010\000\000\000\0= 00\000 */ +{ 39767 }, /* l1-i-prefetch-reference\000legacy cache\000Level 1 instructi= on cache prefetch accesses\000legacy-cache-config=3D0x201\000\00010\000\000= \000\000\000 */ +{ 39657 }, /* l1-i-prefetch-refs\000legacy cache\000Level 1 instruction ca= che prefetch accesses\000legacy-cache-config=3D0x201\000\00010\000\000\000\= 000\000 */ +{ 40325 }, /* l1-i-prefetches\000legacy cache\000Level 1 instruction cache= prefetch accesses\000legacy-cache-config=3D0x201\000\00010\000\000\000\000= \000 */ +{ 40772 }, /* l1-i-prefetches-access\000legacy cache\000Level 1 instructio= n cache prefetch accesses\000legacy-cache-config=3D0x201\000\00010\000\000\= 000\000\000 */ +{ 41000 }, /* l1-i-prefetches-miss\000legacy cache\000Level 1 instruction = cache prefetch misses\000legacy-cache-config=3D0x10201\000\00010\000\000\00= 0\000\000 */ +{ 40886 }, /* l1-i-prefetches-misses\000legacy cache\000Level 1 instructio= n cache prefetch misses\000legacy-cache-config=3D0x10201\000\00010\000\000\= 000\000\000 */ +{ 40661 }, /* l1-i-prefetches-ops\000legacy cache\000Level 1 instruction c= ache prefetch accesses\000legacy-cache-config=3D0x201\000\00010\000\000\000= \000\000 */ +{ 40544 }, /* l1-i-prefetches-reference\000legacy cache\000Level 1 instruc= tion cache prefetch accesses\000legacy-cache-config=3D0x201\000\00010\000\0= 00\000\000\000 */ +{ 40432 }, /* l1-i-prefetches-refs\000legacy cache\000Level 1 instruction = cache prefetch accesses\000legacy-cache-config=3D0x201\000\00010\000\000\00= 0\000\000 */ +{ 38855 }, /* l1-i-read\000legacy cache\000Level 1 instruction cache read = accesses\000legacy-cache-config=3D1\000\00010\000\000\000\000\000 */ +{ 39246 }, /* l1-i-read-access\000legacy cache\000Level 1 instruction cach= e read accesses\000legacy-cache-config=3D1\000\00010\000\000\000\000\000 */ +{ 39450 }, /* l1-i-read-miss\000legacy cache\000Level 1 instruction cache = read misses\000legacy-cache-config=3D0x10001\000\00010\000\000\000\000\000 = */ +{ 39346 }, /* l1-i-read-misses\000legacy cache\000Level 1 instruction cach= e read misses\000legacy-cache-config=3D0x10001\000\00010\000\000\000\000\00= 0 */ +{ 39149 }, /* l1-i-read-ops\000legacy cache\000Level 1 instruction cache r= ead accesses\000legacy-cache-config=3D1\000\00010\000\000\000\000\000 */ +{ 39046 }, /* l1-i-read-reference\000legacy cache\000Level 1 instruction c= ache read accesses\000legacy-cache-config=3D1\000\00010\000\000\000\000\000= */ +{ 38948 }, /* l1-i-read-refs\000legacy cache\000Level 1 instruction cache = read accesses\000legacy-cache-config=3D1\000\00010\000\000\000\000\000 */ +{ 42863 }, /* l1-i-reference\000legacy cache\000Level 1 instruction cache = read accesses\000legacy-cache-config=3D1\000\00010\000\000\000\000\000 */ +{ 42770 }, /* l1-i-refs\000legacy cache\000Level 1 instruction cache read = accesses\000legacy-cache-config=3D1\000\00010\000\000\000\000\000 */ +{ 41941 }, /* l1-i-speculative-load\000legacy cache\000Level 1 instruction= cache prefetch accesses\000legacy-cache-config=3D0x201\000\00010\000\000\0= 00\000\000 */ +{ 42412 }, /* l1-i-speculative-load-access\000legacy cache\000Level 1 inst= ruction cache prefetch accesses\000legacy-cache-config=3D0x201\000\00010\00= 0\000\000\000\000 */ +{ 42652 }, /* l1-i-speculative-load-miss\000legacy cache\000Level 1 instru= ction cache prefetch misses\000legacy-cache-config=3D0x10201\000\00010\000\= 000\000\000\000 */ +{ 42532 }, /* l1-i-speculative-load-misses\000legacy cache\000Level 1 inst= ruction cache prefetch misses\000legacy-cache-config=3D0x10201\000\00010\00= 0\000\000\000\000 */ +{ 42295 }, /* l1-i-speculative-load-ops\000legacy cache\000Level 1 instruc= tion cache prefetch accesses\000legacy-cache-config=3D0x201\000\00010\000\0= 00\000\000\000 */ +{ 42172 }, /* l1-i-speculative-load-reference\000legacy cache\000Level 1 i= nstruction cache prefetch accesses\000legacy-cache-config=3D0x201\000\00010= \000\000\000\000\000 */ +{ 42054 }, /* l1-i-speculative-load-refs\000legacy cache\000Level 1 instru= ction cache prefetch accesses\000legacy-cache-config=3D0x201\000\00010\000\= 000\000\000\000 */ +{ 41112 }, /* l1-i-speculative-read\000legacy cache\000Level 1 instruction= cache prefetch accesses\000legacy-cache-config=3D0x201\000\00010\000\000\0= 00\000\000 */ +{ 41583 }, /* l1-i-speculative-read-access\000legacy cache\000Level 1 inst= ruction cache prefetch accesses\000legacy-cache-config=3D0x201\000\00010\00= 0\000\000\000\000 */ +{ 41823 }, /* l1-i-speculative-read-miss\000legacy cache\000Level 1 instru= ction cache prefetch misses\000legacy-cache-config=3D0x10201\000\00010\000\= 000\000\000\000 */ +{ 41703 }, /* l1-i-speculative-read-misses\000legacy cache\000Level 1 inst= ruction cache prefetch misses\000legacy-cache-config=3D0x10201\000\00010\00= 0\000\000\000\000 */ +{ 41466 }, /* l1-i-speculative-read-ops\000legacy cache\000Level 1 instruc= tion cache prefetch accesses\000legacy-cache-config=3D0x201\000\00010\000\0= 00\000\000\000 */ +{ 41343 }, /* l1-i-speculative-read-reference\000legacy cache\000Level 1 i= nstruction cache prefetch accesses\000legacy-cache-config=3D0x201\000\00010= \000\000\000\000\000 */ +{ 41225 }, /* l1-i-speculative-read-refs\000legacy cache\000Level 1 instru= ction cache prefetch accesses\000legacy-cache-config=3D0x201\000\00010\000\= 000\000\000\000 */ +{ 31108 }, /* l1-icache\000legacy cache\000Level 1 instruction cache read = accesses\000legacy-cache-config=3D1\000\00010\000\000\000\000\000 */ +{ 37060 }, /* l1-icache-access\000legacy cache\000Level 1 instruction cach= e read accesses\000legacy-cache-config=3D1\000\00010\000\000\000\000\000 */ +{ 31201 }, /* l1-icache-load\000legacy cache\000Level 1 instruction cache = read accesses\000legacy-cache-config=3D1\000\00010\000\000\000\000\000 */ +{ 31612 }, /* l1-icache-load-access\000legacy cache\000Level 1 instruction= cache read accesses\000legacy-cache-config=3D1\000\00010\000\000\000\000\0= 00 */ +{ 31826 }, /* l1-icache-load-miss\000legacy cache\000Level 1 instruction c= ache read misses\000legacy-cache-config=3D0x10001\000\00010\000\000\000\000= \000 */ +{ 31717 }, /* l1-icache-load-misses\000legacy cache\000Level 1 instruction= cache read misses\000legacy-cache-config=3D0x10001\000\00000\000\000\000\0= 00\000 */ +{ 31510 }, /* l1-icache-load-ops\000legacy cache\000Level 1 instruction ca= che read accesses\000legacy-cache-config=3D1\000\00010\000\000\000\000\000 = */ +{ 31402 }, /* l1-icache-load-reference\000legacy cache\000Level 1 instruct= ion cache read accesses\000legacy-cache-config=3D1\000\00010\000\000\000\00= 0\000 */ +{ 31299 }, /* l1-icache-load-refs\000legacy cache\000Level 1 instruction c= ache read accesses\000legacy-cache-config=3D1\000\00010\000\000\000\000\000= */ +{ 31933 }, /* l1-icache-loads\000legacy cache\000Level 1 instruction cache= read accesses\000legacy-cache-config=3D1\000\00000\000\000\000\000\000 */ +{ 32348 }, /* l1-icache-loads-access\000legacy cache\000Level 1 instructio= n cache read accesses\000legacy-cache-config=3D1\000\00010\000\000\000\000\= 000 */ +{ 32564 }, /* l1-icache-loads-miss\000legacy cache\000Level 1 instruction = cache read misses\000legacy-cache-config=3D0x10001\000\00010\000\000\000\00= 0\000 */ +{ 32454 }, /* l1-icache-loads-misses\000legacy cache\000Level 1 instructio= n cache read misses\000legacy-cache-config=3D0x10001\000\00010\000\000\000\= 000\000 */ +{ 32245 }, /* l1-icache-loads-ops\000legacy cache\000Level 1 instruction c= ache read accesses\000legacy-cache-config=3D1\000\00010\000\000\000\000\000= */ +{ 32136 }, /* l1-icache-loads-reference\000legacy cache\000Level 1 instruc= tion cache read accesses\000legacy-cache-config=3D1\000\00010\000\000\000\0= 00\000 */ +{ 32032 }, /* l1-icache-loads-refs\000legacy cache\000Level 1 instruction = cache read accesses\000legacy-cache-config=3D1\000\00010\000\000\000\000\00= 0 */ +{ 37264 }, /* l1-icache-miss\000legacy cache\000Level 1 instruction cache = read misses\000legacy-cache-config=3D0x10001\000\00010\000\000\000\000\000 = */ +{ 37160 }, /* l1-icache-misses\000legacy cache\000Level 1 instruction cach= e read misses\000legacy-cache-config=3D0x10001\000\00010\000\000\000\000\00= 0 */ +{ 36963 }, /* l1-icache-ops\000legacy cache\000Level 1 instruction cache r= ead accesses\000legacy-cache-config=3D1\000\00010\000\000\000\000\000 */ +{ 33404 }, /* l1-icache-prefetch\000legacy cache\000Level 1 instruction ca= che prefetch accesses\000legacy-cache-config=3D0x201\000\00010\000\000\000\= 000\000 */ +{ 33863 }, /* l1-icache-prefetch-access\000legacy cache\000Level 1 instruc= tion cache prefetch accesses\000legacy-cache-config=3D0x201\000\00010\000\0= 00\000\000\000 */ +{ 34097 }, /* l1-icache-prefetch-miss\000legacy cache\000Level 1 instructi= on cache prefetch misses\000legacy-cache-config=3D0x10201\000\00010\000\000= \000\000\000 */ +{ 33980 }, /* l1-icache-prefetch-misses\000legacy cache\000Level 1 instruc= tion cache prefetch misses\000legacy-cache-config=3D0x10201\000\00000\000\0= 00\000\000\000 */ +{ 33749 }, /* l1-icache-prefetch-ops\000legacy cache\000Level 1 instructio= n cache prefetch accesses\000legacy-cache-config=3D0x201\000\00010\000\000\= 000\000\000 */ +{ 33629 }, /* l1-icache-prefetch-reference\000legacy cache\000Level 1 inst= ruction cache prefetch accesses\000legacy-cache-config=3D0x201\000\00010\00= 0\000\000\000\000 */ +{ 33514 }, /* l1-icache-prefetch-refs\000legacy cache\000Level 1 instructi= on cache prefetch accesses\000legacy-cache-config=3D0x201\000\00010\000\000= \000\000\000 */ +{ 34212 }, /* l1-icache-prefetches\000legacy cache\000Level 1 instruction = cache prefetch accesses\000legacy-cache-config=3D0x201\000\00000\000\000\00= 0\000\000 */ +{ 34679 }, /* l1-icache-prefetches-access\000legacy cache\000Level 1 instr= uction cache prefetch accesses\000legacy-cache-config=3D0x201\000\00010\000= \000\000\000\000 */ +{ 34917 }, /* l1-icache-prefetches-miss\000legacy cache\000Level 1 instruc= tion cache prefetch misses\000legacy-cache-config=3D0x10201\000\00010\000\0= 00\000\000\000 */ +{ 34798 }, /* l1-icache-prefetches-misses\000legacy cache\000Level 1 instr= uction cache prefetch misses\000legacy-cache-config=3D0x10201\000\00010\000= \000\000\000\000 */ +{ 34563 }, /* l1-icache-prefetches-ops\000legacy cache\000Level 1 instruct= ion cache prefetch accesses\000legacy-cache-config=3D0x201\000\00010\000\00= 0\000\000\000 */ +{ 34441 }, /* l1-icache-prefetches-reference\000legacy cache\000Level 1 in= struction cache prefetch accesses\000legacy-cache-config=3D0x201\000\00010\= 000\000\000\000\000 */ +{ 34324 }, /* l1-icache-prefetches-refs\000legacy cache\000Level 1 instruc= tion cache prefetch accesses\000legacy-cache-config=3D0x201\000\00010\000\0= 00\000\000\000 */ +{ 32672 }, /* l1-icache-read\000legacy cache\000Level 1 instruction cache = read accesses\000legacy-cache-config=3D1\000\00010\000\000\000\000\000 */ +{ 33083 }, /* l1-icache-read-access\000legacy cache\000Level 1 instruction= cache read accesses\000legacy-cache-config=3D1\000\00010\000\000\000\000\0= 00 */ +{ 33297 }, /* l1-icache-read-miss\000legacy cache\000Level 1 instruction c= ache read misses\000legacy-cache-config=3D0x10001\000\00010\000\000\000\000= \000 */ +{ 33188 }, /* l1-icache-read-misses\000legacy cache\000Level 1 instruction= cache read misses\000legacy-cache-config=3D0x10001\000\00010\000\000\000\0= 00\000 */ +{ 32981 }, /* l1-icache-read-ops\000legacy cache\000Level 1 instruction ca= che read accesses\000legacy-cache-config=3D1\000\00010\000\000\000\000\000 = */ +{ 32873 }, /* l1-icache-read-reference\000legacy cache\000Level 1 instruct= ion cache read accesses\000legacy-cache-config=3D1\000\00010\000\000\000\00= 0\000 */ +{ 32770 }, /* l1-icache-read-refs\000legacy cache\000Level 1 instruction c= ache read accesses\000legacy-cache-config=3D1\000\00010\000\000\000\000\000= */ +{ 36860 }, /* l1-icache-reference\000legacy cache\000Level 1 instruction c= ache read accesses\000legacy-cache-config=3D1\000\00010\000\000\000\000\000= */ +{ 36762 }, /* l1-icache-refs\000legacy cache\000Level 1 instruction cache = read accesses\000legacy-cache-config=3D1\000\00010\000\000\000\000\000 */ +{ 35898 }, /* l1-icache-speculative-load\000legacy cache\000Level 1 instru= ction cache prefetch accesses\000legacy-cache-config=3D0x201\000\00010\000\= 000\000\000\000 */ +{ 36389 }, /* l1-icache-speculative-load-access\000legacy cache\000Level 1= instruction cache prefetch accesses\000legacy-cache-config=3D0x201\000\000= 10\000\000\000\000\000 */ +{ 36639 }, /* l1-icache-speculative-load-miss\000legacy cache\000Level 1 i= nstruction cache prefetch misses\000legacy-cache-config=3D0x10201\000\00010= \000\000\000\000\000 */ +{ 36514 }, /* l1-icache-speculative-load-misses\000legacy cache\000Level 1= instruction cache prefetch misses\000legacy-cache-config=3D0x10201\000\000= 10\000\000\000\000\000 */ +{ 36267 }, /* l1-icache-speculative-load-ops\000legacy cache\000Level 1 in= struction cache prefetch accesses\000legacy-cache-config=3D0x201\000\00010\= 000\000\000\000\000 */ +{ 36139 }, /* l1-icache-speculative-load-reference\000legacy cache\000Leve= l 1 instruction cache prefetch accesses\000legacy-cache-config=3D0x201\000\= 00010\000\000\000\000\000 */ +{ 36016 }, /* l1-icache-speculative-load-refs\000legacy cache\000Level 1 i= nstruction cache prefetch accesses\000legacy-cache-config=3D0x201\000\00010= \000\000\000\000\000 */ +{ 35034 }, /* l1-icache-speculative-read\000legacy cache\000Level 1 instru= ction cache prefetch accesses\000legacy-cache-config=3D0x201\000\00010\000\= 000\000\000\000 */ +{ 35525 }, /* l1-icache-speculative-read-access\000legacy cache\000Level 1= instruction cache prefetch accesses\000legacy-cache-config=3D0x201\000\000= 10\000\000\000\000\000 */ +{ 35775 }, /* l1-icache-speculative-read-miss\000legacy cache\000Level 1 i= nstruction cache prefetch misses\000legacy-cache-config=3D0x10201\000\00010= \000\000\000\000\000 */ +{ 35650 }, /* l1-icache-speculative-read-misses\000legacy cache\000Level 1= instruction cache prefetch misses\000legacy-cache-config=3D0x10201\000\000= 10\000\000\000\000\000 */ +{ 35403 }, /* l1-icache-speculative-read-ops\000legacy cache\000Level 1 in= struction cache prefetch accesses\000legacy-cache-config=3D0x201\000\00010\= 000\000\000\000\000 */ +{ 35275 }, /* l1-icache-speculative-read-reference\000legacy cache\000Leve= l 1 instruction cache prefetch accesses\000legacy-cache-config=3D0x201\000\= 00010\000\000\000\000\000 */ +{ 35152 }, /* l1-icache-speculative-read-refs\000legacy cache\000Level 1 i= nstruction cache prefetch accesses\000legacy-cache-config=3D0x201\000\00010= \000\000\000\000\000 */ +{ 49266 }, /* l1-instruction\000legacy cache\000Level 1 instruction cache = read accesses\000legacy-cache-config=3D1\000\00010\000\000\000\000\000 */ +{ 55483 }, /* l1-instruction-access\000legacy cache\000Level 1 instruction= cache read accesses\000legacy-cache-config=3D1\000\00010\000\000\000\000\0= 00 */ +{ 49364 }, /* l1-instruction-load\000legacy cache\000Level 1 instruction c= ache read accesses\000legacy-cache-config=3D1\000\00010\000\000\000\000\000= */ +{ 49795 }, /* l1-instruction-load-access\000legacy cache\000Level 1 instru= ction cache read accesses\000legacy-cache-config=3D1\000\00010\000\000\000\= 000\000 */ +{ 50019 }, /* l1-instruction-load-miss\000legacy cache\000Level 1 instruct= ion cache read misses\000legacy-cache-config=3D0x10001\000\00010\000\000\00= 0\000\000 */ +{ 49905 }, /* l1-instruction-load-misses\000legacy cache\000Level 1 instru= ction cache read misses\000legacy-cache-config=3D0x10001\000\00010\000\000\= 000\000\000 */ +{ 49688 }, /* l1-instruction-load-ops\000legacy cache\000Level 1 instructi= on cache read accesses\000legacy-cache-config=3D1\000\00010\000\000\000\000= \000 */ +{ 49575 }, /* l1-instruction-load-reference\000legacy cache\000Level 1 ins= truction cache read accesses\000legacy-cache-config=3D1\000\00010\000\000\0= 00\000\000 */ +{ 49467 }, /* l1-instruction-load-refs\000legacy cache\000Level 1 instruct= ion cache read accesses\000legacy-cache-config=3D1\000\00010\000\000\000\00= 0\000 */ +{ 50131 }, /* l1-instruction-loads\000legacy cache\000Level 1 instruction = cache read accesses\000legacy-cache-config=3D1\000\00010\000\000\000\000\00= 0 */ +{ 50566 }, /* l1-instruction-loads-access\000legacy cache\000Level 1 instr= uction cache read accesses\000legacy-cache-config=3D1\000\00010\000\000\000= \000\000 */ +{ 50792 }, /* l1-instruction-loads-miss\000legacy cache\000Level 1 instruc= tion cache read misses\000legacy-cache-config=3D0x10001\000\00010\000\000\0= 00\000\000 */ +{ 50677 }, /* l1-instruction-loads-misses\000legacy cache\000Level 1 instr= uction cache read misses\000legacy-cache-config=3D0x10001\000\00010\000\000= \000\000\000 */ +{ 50458 }, /* l1-instruction-loads-ops\000legacy cache\000Level 1 instruct= ion cache read accesses\000legacy-cache-config=3D1\000\00010\000\000\000\00= 0\000 */ +{ 50344 }, /* l1-instruction-loads-reference\000legacy cache\000Level 1 in= struction cache read accesses\000legacy-cache-config=3D1\000\00010\000\000\= 000\000\000 */ +{ 50235 }, /* l1-instruction-loads-refs\000legacy cache\000Level 1 instruc= tion cache read accesses\000legacy-cache-config=3D1\000\00010\000\000\000\0= 00\000 */ +{ 55697 }, /* l1-instruction-miss\000legacy cache\000Level 1 instruction c= ache read misses\000legacy-cache-config=3D0x10001\000\00010\000\000\000\000= \000 */ +{ 55588 }, /* l1-instruction-misses\000legacy cache\000Level 1 instruction= cache read misses\000legacy-cache-config=3D0x10001\000\00010\000\000\000\0= 00\000 */ +{ 55381 }, /* l1-instruction-ops\000legacy cache\000Level 1 instruction ca= che read accesses\000legacy-cache-config=3D1\000\00010\000\000\000\000\000 = */ +{ 51672 }, /* l1-instruction-prefetch\000legacy cache\000Level 1 instructi= on cache prefetch accesses\000legacy-cache-config=3D0x201\000\00010\000\000= \000\000\000 */ +{ 52151 }, /* l1-instruction-prefetch-access\000legacy cache\000Level 1 in= struction cache prefetch accesses\000legacy-cache-config=3D0x201\000\00010\= 000\000\000\000\000 */ +{ 52395 }, /* l1-instruction-prefetch-miss\000legacy cache\000Level 1 inst= ruction cache prefetch misses\000legacy-cache-config=3D0x10201\000\00010\00= 0\000\000\000\000 */ +{ 52273 }, /* l1-instruction-prefetch-misses\000legacy cache\000Level 1 in= struction cache prefetch misses\000legacy-cache-config=3D0x10201\000\00010\= 000\000\000\000\000 */ +{ 52032 }, /* l1-instruction-prefetch-ops\000legacy cache\000Level 1 instr= uction cache prefetch accesses\000legacy-cache-config=3D0x201\000\00010\000= \000\000\000\000 */ +{ 51907 }, /* l1-instruction-prefetch-reference\000legacy cache\000Level 1= instruction cache prefetch accesses\000legacy-cache-config=3D0x201\000\000= 10\000\000\000\000\000 */ +{ 51787 }, /* l1-instruction-prefetch-refs\000legacy cache\000Level 1 inst= ruction cache prefetch accesses\000legacy-cache-config=3D0x201\000\00010\00= 0\000\000\000\000 */ +{ 52515 }, /* l1-instruction-prefetches\000legacy cache\000Level 1 instruc= tion cache prefetch accesses\000legacy-cache-config=3D0x201\000\00010\000\0= 00\000\000\000 */ +{ 53002 }, /* l1-instruction-prefetches-access\000legacy cache\000Level 1 = instruction cache prefetch accesses\000legacy-cache-config=3D0x201\000\0001= 0\000\000\000\000\000 */ +{ 53250 }, /* l1-instruction-prefetches-miss\000legacy cache\000Level 1 in= struction cache prefetch misses\000legacy-cache-config=3D0x10201\000\00010\= 000\000\000\000\000 */ +{ 53126 }, /* l1-instruction-prefetches-misses\000legacy cache\000Level 1 = instruction cache prefetch misses\000legacy-cache-config=3D0x10201\000\0001= 0\000\000\000\000\000 */ +{ 52881 }, /* l1-instruction-prefetches-ops\000legacy cache\000Level 1 ins= truction cache prefetch accesses\000legacy-cache-config=3D0x201\000\00010\0= 00\000\000\000\000 */ +{ 52754 }, /* l1-instruction-prefetches-reference\000legacy cache\000Level= 1 instruction cache prefetch accesses\000legacy-cache-config=3D0x201\000\0= 0010\000\000\000\000\000 */ +{ 52632 }, /* l1-instruction-prefetches-refs\000legacy cache\000Level 1 in= struction cache prefetch accesses\000legacy-cache-config=3D0x201\000\00010\= 000\000\000\000\000 */ +{ 50905 }, /* l1-instruction-read\000legacy cache\000Level 1 instruction c= ache read accesses\000legacy-cache-config=3D1\000\00010\000\000\000\000\000= */ +{ 51336 }, /* l1-instruction-read-access\000legacy cache\000Level 1 instru= ction cache read accesses\000legacy-cache-config=3D1\000\00010\000\000\000\= 000\000 */ +{ 51560 }, /* l1-instruction-read-miss\000legacy cache\000Level 1 instruct= ion cache read misses\000legacy-cache-config=3D0x10001\000\00010\000\000\00= 0\000\000 */ +{ 51446 }, /* l1-instruction-read-misses\000legacy cache\000Level 1 instru= ction cache read misses\000legacy-cache-config=3D0x10001\000\00010\000\000\= 000\000\000 */ +{ 51229 }, /* l1-instruction-read-ops\000legacy cache\000Level 1 instructi= on cache read accesses\000legacy-cache-config=3D1\000\00010\000\000\000\000= \000 */ +{ 51116 }, /* l1-instruction-read-reference\000legacy cache\000Level 1 ins= truction cache read accesses\000legacy-cache-config=3D1\000\00010\000\000\0= 00\000\000 */ +{ 51008 }, /* l1-instruction-read-refs\000legacy cache\000Level 1 instruct= ion cache read accesses\000legacy-cache-config=3D1\000\00010\000\000\000\00= 0\000 */ +{ 55273 }, /* l1-instruction-reference\000legacy cache\000Level 1 instruct= ion cache read accesses\000legacy-cache-config=3D1\000\00010\000\000\000\00= 0\000 */ +{ 55170 }, /* l1-instruction-refs\000legacy cache\000Level 1 instruction c= ache read accesses\000legacy-cache-config=3D1\000\00010\000\000\000\000\000= */ +{ 54271 }, /* l1-instruction-speculative-load\000legacy cache\000Level 1 i= nstruction cache prefetch accesses\000legacy-cache-config=3D0x201\000\00010= \000\000\000\000\000 */ +{ 54782 }, /* l1-instruction-speculative-load-access\000legacy cache\000Le= vel 1 instruction cache prefetch accesses\000legacy-cache-config=3D0x201\00= 0\00010\000\000\000\000\000 */ +{ 55042 }, /* l1-instruction-speculative-load-miss\000legacy cache\000Leve= l 1 instruction cache prefetch misses\000legacy-cache-config=3D0x10201\000\= 00010\000\000\000\000\000 */ +{ 54912 }, /* l1-instruction-speculative-load-misses\000legacy cache\000Le= vel 1 instruction cache prefetch misses\000legacy-cache-config=3D0x10201\00= 0\00010\000\000\000\000\000 */ +{ 54655 }, /* l1-instruction-speculative-load-ops\000legacy cache\000Level= 1 instruction cache prefetch accesses\000legacy-cache-config=3D0x201\000\0= 0010\000\000\000\000\000 */ +{ 54522 }, /* l1-instruction-speculative-load-reference\000legacy cache\00= 0Level 1 instruction cache prefetch accesses\000legacy-cache-config=3D0x201= \000\00010\000\000\000\000\000 */ +{ 54394 }, /* l1-instruction-speculative-load-refs\000legacy cache\000Leve= l 1 instruction cache prefetch accesses\000legacy-cache-config=3D0x201\000\= 00010\000\000\000\000\000 */ +{ 53372 }, /* l1-instruction-speculative-read\000legacy cache\000Level 1 i= nstruction cache prefetch accesses\000legacy-cache-config=3D0x201\000\00010= \000\000\000\000\000 */ +{ 53883 }, /* l1-instruction-speculative-read-access\000legacy cache\000Le= vel 1 instruction cache prefetch accesses\000legacy-cache-config=3D0x201\00= 0\00010\000\000\000\000\000 */ +{ 54143 }, /* l1-instruction-speculative-read-miss\000legacy cache\000Leve= l 1 instruction cache prefetch misses\000legacy-cache-config=3D0x10201\000\= 00010\000\000\000\000\000 */ +{ 54013 }, /* l1-instruction-speculative-read-misses\000legacy cache\000Le= vel 1 instruction cache prefetch misses\000legacy-cache-config=3D0x10201\00= 0\00010\000\000\000\000\000 */ +{ 53756 }, /* l1-instruction-speculative-read-ops\000legacy cache\000Level= 1 instruction cache prefetch accesses\000legacy-cache-config=3D0x201\000\0= 0010\000\000\000\000\000 */ +{ 53623 }, /* l1-instruction-speculative-read-reference\000legacy cache\00= 0Level 1 instruction cache prefetch accesses\000legacy-cache-config=3D0x201= \000\00010\000\000\000\000\000 */ +{ 53495 }, /* l1-instruction-speculative-read-refs\000legacy cache\000Leve= l 1 instruction cache prefetch accesses\000legacy-cache-config=3D0x201\000\= 00010\000\000\000\000\000 */ +{ 15676 }, /* l1d\000legacy cache\000Level 1 data cache read accesses\000l= egacy-cache-config=3D0\000\00010\000\000\000\000\000 */ +{ 22971 }, /* l1d-access\000legacy cache\000Level 1 data cache read access= es\000legacy-cache-config=3D0\000\00010\000\000\000\000\000 */ +{ 15756 }, /* l1d-load\000legacy cache\000Level 1 data cache read accesses= \000legacy-cache-config=3D0\000\00010\000\000\000\000\000 */ +{ 16115 }, /* l1d-load-access\000legacy cache\000Level 1 data cache read a= ccesses\000legacy-cache-config=3D0\000\00010\000\000\000\000\000 */ +{ 16303 }, /* l1d-load-miss\000legacy cache\000Level 1 data cache read mis= ses\000legacy-cache-config=3D0x10000\000\00010\000\000\000\000\000 */ +{ 16207 }, /* l1d-load-misses\000legacy cache\000Level 1 data cache read m= isses\000legacy-cache-config=3D0x10000\000\00010\000\000\000\000\000 */ +{ 16026 }, /* l1d-load-ops\000legacy cache\000Level 1 data cache read acce= sses\000legacy-cache-config=3D0\000\00010\000\000\000\000\000 */ +{ 15931 }, /* l1d-load-reference\000legacy cache\000Level 1 data cache rea= d accesses\000legacy-cache-config=3D0\000\00010\000\000\000\000\000 */ +{ 15841 }, /* l1d-load-refs\000legacy cache\000Level 1 data cache read acc= esses\000legacy-cache-config=3D0\000\00010\000\000\000\000\000 */ +{ 16397 }, /* l1d-loads\000legacy cache\000Level 1 data cache read accesse= s\000legacy-cache-config=3D0\000\00010\000\000\000\000\000 */ +{ 16760 }, /* l1d-loads-access\000legacy cache\000Level 1 data cache read = accesses\000legacy-cache-config=3D0\000\00010\000\000\000\000\000 */ +{ 16950 }, /* l1d-loads-miss\000legacy cache\000Level 1 data cache read mi= sses\000legacy-cache-config=3D0x10000\000\00010\000\000\000\000\000 */ +{ 16853 }, /* l1d-loads-misses\000legacy cache\000Level 1 data cache read = misses\000legacy-cache-config=3D0x10000\000\00010\000\000\000\000\000 */ +{ 16670 }, /* l1d-loads-ops\000legacy cache\000Level 1 data cache read acc= esses\000legacy-cache-config=3D0\000\00010\000\000\000\000\000 */ +{ 16574 }, /* l1d-loads-reference\000legacy cache\000Level 1 data cache re= ad accesses\000legacy-cache-config=3D0\000\00010\000\000\000\000\000 */ +{ 16483 }, /* l1d-loads-refs\000legacy cache\000Level 1 data cache read ac= cesses\000legacy-cache-config=3D0\000\00010\000\000\000\000\000 */ +{ 23149 }, /* l1d-miss\000legacy cache\000Level 1 data cache read misses\0= 00legacy-cache-config=3D0x10000\000\00010\000\000\000\000\000 */ +{ 23058 }, /* l1d-misses\000legacy cache\000Level 1 data cache read misses= \000legacy-cache-config=3D0x10000\000\00010\000\000\000\000\000 */ +{ 22887 }, /* l1d-ops\000legacy cache\000Level 1 data cache read accesses\= 000legacy-cache-config=3D0\000\00010\000\000\000\000\000 */ +{ 19718 }, /* l1d-prefetch\000legacy cache\000Level 1 data cache prefetch = accesses\000legacy-cache-config=3D0x200\000\00010\000\000\000\000\000 */ +{ 20125 }, /* l1d-prefetch-access\000legacy cache\000Level 1 data cache pr= efetch accesses\000legacy-cache-config=3D0x200\000\00010\000\000\000\000\00= 0 */ +{ 20333 }, /* l1d-prefetch-miss\000legacy cache\000Level 1 data cache pref= etch misses\000legacy-cache-config=3D0x10200\000\00010\000\000\000\000\000 = */ +{ 20229 }, /* l1d-prefetch-misses\000legacy cache\000Level 1 data cache pr= efetch misses\000legacy-cache-config=3D0x10200\000\00010\000\000\000\000\00= 0 */ +{ 20024 }, /* l1d-prefetch-ops\000legacy cache\000Level 1 data cache prefe= tch accesses\000legacy-cache-config=3D0x200\000\00010\000\000\000\000\000 */ +{ 19917 }, /* l1d-prefetch-reference\000legacy cache\000Level 1 data cache= prefetch accesses\000legacy-cache-config=3D0x200\000\00010\000\000\000\000= \000 */ +{ 19815 }, /* l1d-prefetch-refs\000legacy cache\000Level 1 data cache pref= etch accesses\000legacy-cache-config=3D0x200\000\00010\000\000\000\000\000 = */ +{ 20435 }, /* l1d-prefetches\000legacy cache\000Level 1 data cache prefetc= h accesses\000legacy-cache-config=3D0x200\000\00010\000\000\000\000\000 */ +{ 20850 }, /* l1d-prefetches-access\000legacy cache\000Level 1 data cache = prefetch accesses\000legacy-cache-config=3D0x200\000\00010\000\000\000\000\= 000 */ +{ 21062 }, /* l1d-prefetches-miss\000legacy cache\000Level 1 data cache pr= efetch misses\000legacy-cache-config=3D0x10200\000\00010\000\000\000\000\00= 0 */ +{ 20956 }, /* l1d-prefetches-misses\000legacy cache\000Level 1 data cache = prefetch misses\000legacy-cache-config=3D0x10200\000\00010\000\000\000\000\= 000 */ +{ 20747 }, /* l1d-prefetches-ops\000legacy cache\000Level 1 data cache pre= fetch accesses\000legacy-cache-config=3D0x200\000\00010\000\000\000\000\000= */ +{ 20638 }, /* l1d-prefetches-reference\000legacy cache\000Level 1 data cac= he prefetch accesses\000legacy-cache-config=3D0x200\000\00010\000\000\000\0= 00\000 */ +{ 20534 }, /* l1d-prefetches-refs\000legacy cache\000Level 1 data cache pr= efetch accesses\000legacy-cache-config=3D0x200\000\00010\000\000\000\000\00= 0 */ +{ 17045 }, /* l1d-read\000legacy cache\000Level 1 data cache read accesses= \000legacy-cache-config=3D0\000\00010\000\000\000\000\000 */ +{ 17404 }, /* l1d-read-access\000legacy cache\000Level 1 data cache read a= ccesses\000legacy-cache-config=3D0\000\00010\000\000\000\000\000 */ +{ 17592 }, /* l1d-read-miss\000legacy cache\000Level 1 data cache read mis= ses\000legacy-cache-config=3D0x10000\000\00010\000\000\000\000\000 */ +{ 17496 }, /* l1d-read-misses\000legacy cache\000Level 1 data cache read m= isses\000legacy-cache-config=3D0x10000\000\00010\000\000\000\000\000 */ +{ 17315 }, /* l1d-read-ops\000legacy cache\000Level 1 data cache read acce= sses\000legacy-cache-config=3D0\000\00010\000\000\000\000\000 */ +{ 17220 }, /* l1d-read-reference\000legacy cache\000Level 1 data cache rea= d accesses\000legacy-cache-config=3D0\000\00010\000\000\000\000\000 */ +{ 17130 }, /* l1d-read-refs\000legacy cache\000Level 1 data cache read acc= esses\000legacy-cache-config=3D0\000\00010\000\000\000\000\000 */ +{ 22797 }, /* l1d-reference\000legacy cache\000Level 1 data cache read acc= esses\000legacy-cache-config=3D0\000\00010\000\000\000\000\000 */ +{ 22712 }, /* l1d-refs\000legacy cache\000Level 1 data cache read accesses= \000legacy-cache-config=3D0\000\00010\000\000\000\000\000 */ +{ 21939 }, /* l1d-speculative-load\000legacy cache\000Level 1 data cache p= refetch accesses\000legacy-cache-config=3D0x200\000\00010\000\000\000\000\0= 00 */ +{ 22378 }, /* l1d-speculative-load-access\000legacy cache\000Level 1 data = cache prefetch accesses\000legacy-cache-config=3D0x200\000\00010\000\000\00= 0\000\000 */ +{ 22602 }, /* l1d-speculative-load-miss\000legacy cache\000Level 1 data ca= che prefetch misses\000legacy-cache-config=3D0x10200\000\00010\000\000\000\= 000\000 */ +{ 22490 }, /* l1d-speculative-load-misses\000legacy cache\000Level 1 data = cache prefetch misses\000legacy-cache-config=3D0x10200\000\00010\000\000\00= 0\000\000 */ +{ 22269 }, /* l1d-speculative-load-ops\000legacy cache\000Level 1 data cac= he prefetch accesses\000legacy-cache-config=3D0x200\000\00010\000\000\000\0= 00\000 */ +{ 22154 }, /* l1d-speculative-load-reference\000legacy cache\000Level 1 da= ta cache prefetch accesses\000legacy-cache-config=3D0x200\000\00010\000\000= \000\000\000 */ +{ 22044 }, /* l1d-speculative-load-refs\000legacy cache\000Level 1 data ca= che prefetch accesses\000legacy-cache-config=3D0x200\000\00010\000\000\000\= 000\000 */ +{ 21166 }, /* l1d-speculative-read\000legacy cache\000Level 1 data cache p= refetch accesses\000legacy-cache-config=3D0x200\000\00010\000\000\000\000\0= 00 */ +{ 21605 }, /* l1d-speculative-read-access\000legacy cache\000Level 1 data = cache prefetch accesses\000legacy-cache-config=3D0x200\000\00010\000\000\00= 0\000\000 */ +{ 21829 }, /* l1d-speculative-read-miss\000legacy cache\000Level 1 data ca= che prefetch misses\000legacy-cache-config=3D0x10200\000\00010\000\000\000\= 000\000 */ +{ 21717 }, /* l1d-speculative-read-misses\000legacy cache\000Level 1 data = cache prefetch misses\000legacy-cache-config=3D0x10200\000\00010\000\000\00= 0\000\000 */ +{ 21496 }, /* l1d-speculative-read-ops\000legacy cache\000Level 1 data cac= he prefetch accesses\000legacy-cache-config=3D0x200\000\00010\000\000\000\0= 00\000 */ +{ 21381 }, /* l1d-speculative-read-reference\000legacy cache\000Level 1 da= ta cache prefetch accesses\000legacy-cache-config=3D0x200\000\00010\000\000= \000\000\000 */ +{ 21271 }, /* l1d-speculative-read-refs\000legacy cache\000Level 1 data ca= che prefetch accesses\000legacy-cache-config=3D0x200\000\00010\000\000\000\= 000\000 */ +{ 17686 }, /* l1d-store\000legacy cache\000Level 1 data cache write access= es\000legacy-cache-config=3D0x100\000\00010\000\000\000\000\000 */ +{ 18069 }, /* l1d-store-access\000legacy cache\000Level 1 data cache write= accesses\000legacy-cache-config=3D0x100\000\00010\000\000\000\000\000 */ +{ 18265 }, /* l1d-store-miss\000legacy cache\000Level 1 data cache write m= isses\000legacy-cache-config=3D0x10100\000\00010\000\000\000\000\000 */ +{ 18167 }, /* l1d-store-misses\000legacy cache\000Level 1 data cache write= misses\000legacy-cache-config=3D0x10100\000\00010\000\000\000\000\000 */ +{ 17974 }, /* l1d-store-ops\000legacy cache\000Level 1 data cache write ac= cesses\000legacy-cache-config=3D0x100\000\00010\000\000\000\000\000 */ +{ 17873 }, /* l1d-store-reference\000legacy cache\000Level 1 data cache wr= ite accesses\000legacy-cache-config=3D0x100\000\00010\000\000\000\000\000 */ +{ 17777 }, /* l1d-store-refs\000legacy cache\000Level 1 data cache write a= ccesses\000legacy-cache-config=3D0x100\000\00010\000\000\000\000\000 */ +{ 18361 }, /* l1d-stores\000legacy cache\000Level 1 data cache write acces= ses\000legacy-cache-config=3D0x100\000\00010\000\000\000\000\000 */ +{ 18748 }, /* l1d-stores-access\000legacy cache\000Level 1 data cache writ= e accesses\000legacy-cache-config=3D0x100\000\00010\000\000\000\000\000 */ +{ 18946 }, /* l1d-stores-miss\000legacy cache\000Level 1 data cache write = misses\000legacy-cache-config=3D0x10100\000\00010\000\000\000\000\000 */ +{ 18847 }, /* l1d-stores-misses\000legacy cache\000Level 1 data cache writ= e misses\000legacy-cache-config=3D0x10100\000\00010\000\000\000\000\000 */ +{ 18652 }, /* l1d-stores-ops\000legacy cache\000Level 1 data cache write a= ccesses\000legacy-cache-config=3D0x100\000\00010\000\000\000\000\000 */ +{ 18550 }, /* l1d-stores-reference\000legacy cache\000Level 1 data cache w= rite accesses\000legacy-cache-config=3D0x100\000\00010\000\000\000\000\000 = */ +{ 18453 }, /* l1d-stores-refs\000legacy cache\000Level 1 data cache write = accesses\000legacy-cache-config=3D0x100\000\00010\000\000\000\000\000 */ +{ 19043 }, /* l1d-write\000legacy cache\000Level 1 data cache write access= es\000legacy-cache-config=3D0x100\000\00010\000\000\000\000\000 */ +{ 19426 }, /* l1d-write-access\000legacy cache\000Level 1 data cache write= accesses\000legacy-cache-config=3D0x100\000\00010\000\000\000\000\000 */ +{ 19622 }, /* l1d-write-miss\000legacy cache\000Level 1 data cache write m= isses\000legacy-cache-config=3D0x10100\000\00010\000\000\000\000\000 */ +{ 19524 }, /* l1d-write-misses\000legacy cache\000Level 1 data cache write= misses\000legacy-cache-config=3D0x10100\000\00010\000\000\000\000\000 */ +{ 19331 }, /* l1d-write-ops\000legacy cache\000Level 1 data cache write ac= cesses\000legacy-cache-config=3D0x100\000\00010\000\000\000\000\000 */ +{ 19230 }, /* l1d-write-reference\000legacy cache\000Level 1 data cache wr= ite accesses\000legacy-cache-config=3D0x100\000\00010\000\000\000\000\000 */ +{ 19134 }, /* l1d-write-refs\000legacy cache\000Level 1 data cache write a= ccesses\000legacy-cache-config=3D0x100\000\00010\000\000\000\000\000 */ +{ 43344 }, /* l1i\000legacy cache\000Level 1 instruction cache read access= es\000legacy-cache-config=3D1\000\00010\000\000\000\000\000 */ +{ 48978 }, /* l1i-access\000legacy cache\000Level 1 instruction cache read= accesses\000legacy-cache-config=3D1\000\00010\000\000\000\000\000 */ +{ 43431 }, /* l1i-load\000legacy cache\000Level 1 instruction cache read a= ccesses\000legacy-cache-config=3D1\000\00010\000\000\000\000\000 */ +{ 43818 }, /* l1i-load-access\000legacy cache\000Level 1 instruction cache= read accesses\000legacy-cache-config=3D1\000\00010\000\000\000\000\000 */ +{ 44020 }, /* l1i-load-miss\000legacy cache\000Level 1 instruction cache r= ead misses\000legacy-cache-config=3D0x10001\000\00010\000\000\000\000\000 */ +{ 43917 }, /* l1i-load-misses\000legacy cache\000Level 1 instruction cache= read misses\000legacy-cache-config=3D0x10001\000\00010\000\000\000\000\000= */ +{ 43722 }, /* l1i-load-ops\000legacy cache\000Level 1 instruction cache re= ad accesses\000legacy-cache-config=3D1\000\00010\000\000\000\000\000 */ +{ 43620 }, /* l1i-load-reference\000legacy cache\000Level 1 instruction ca= che read accesses\000legacy-cache-config=3D1\000\00010\000\000\000\000\000 = */ +{ 43523 }, /* l1i-load-refs\000legacy cache\000Level 1 instruction cache r= ead accesses\000legacy-cache-config=3D1\000\00010\000\000\000\000\000 */ +{ 44121 }, /* l1i-loads\000legacy cache\000Level 1 instruction cache read = accesses\000legacy-cache-config=3D1\000\00010\000\000\000\000\000 */ +{ 44512 }, /* l1i-loads-access\000legacy cache\000Level 1 instruction cach= e read accesses\000legacy-cache-config=3D1\000\00010\000\000\000\000\000 */ +{ 44716 }, /* l1i-loads-miss\000legacy cache\000Level 1 instruction cache = read misses\000legacy-cache-config=3D0x10001\000\00010\000\000\000\000\000 = */ +{ 44612 }, /* l1i-loads-misses\000legacy cache\000Level 1 instruction cach= e read misses\000legacy-cache-config=3D0x10001\000\00010\000\000\000\000\00= 0 */ +{ 44415 }, /* l1i-loads-ops\000legacy cache\000Level 1 instruction cache r= ead accesses\000legacy-cache-config=3D1\000\00010\000\000\000\000\000 */ +{ 44312 }, /* l1i-loads-reference\000legacy cache\000Level 1 instruction c= ache read accesses\000legacy-cache-config=3D1\000\00010\000\000\000\000\000= */ +{ 44214 }, /* l1i-loads-refs\000legacy cache\000Level 1 instruction cache = read accesses\000legacy-cache-config=3D1\000\00010\000\000\000\000\000 */ +{ 49170 }, /* l1i-miss\000legacy cache\000Level 1 instruction cache read m= isses\000legacy-cache-config=3D0x10001\000\00010\000\000\000\000\000 */ +{ 49072 }, /* l1i-misses\000legacy cache\000Level 1 instruction cache read= misses\000legacy-cache-config=3D0x10001\000\00010\000\000\000\000\000 */ +{ 48887 }, /* l1i-ops\000legacy cache\000Level 1 instruction cache read ac= cesses\000legacy-cache-config=3D1\000\00010\000\000\000\000\000 */ +{ 45508 }, /* l1i-prefetch\000legacy cache\000Level 1 instruction cache pr= efetch accesses\000legacy-cache-config=3D0x201\000\00010\000\000\000\000\00= 0 */ +{ 45943 }, /* l1i-prefetch-access\000legacy cache\000Level 1 instruction c= ache prefetch accesses\000legacy-cache-config=3D0x201\000\00010\000\000\000= \000\000 */ +{ 46165 }, /* l1i-prefetch-miss\000legacy cache\000Level 1 instruction cac= he prefetch misses\000legacy-cache-config=3D0x10201\000\00010\000\000\000\0= 00\000 */ +{ 46054 }, /* l1i-prefetch-misses\000legacy cache\000Level 1 instruction c= ache prefetch misses\000legacy-cache-config=3D0x10201\000\00010\000\000\000= \000\000 */ +{ 45835 }, /* l1i-prefetch-ops\000legacy cache\000Level 1 instruction cach= e prefetch accesses\000legacy-cache-config=3D0x201\000\00010\000\000\000\00= 0\000 */ +{ 45721 }, /* l1i-prefetch-reference\000legacy cache\000Level 1 instructio= n cache prefetch accesses\000legacy-cache-config=3D0x201\000\00010\000\000\= 000\000\000 */ +{ 45612 }, /* l1i-prefetch-refs\000legacy cache\000Level 1 instruction cac= he prefetch accesses\000legacy-cache-config=3D0x201\000\00010\000\000\000\0= 00\000 */ +{ 46274 }, /* l1i-prefetches\000legacy cache\000Level 1 instruction cache = prefetch accesses\000legacy-cache-config=3D0x201\000\00010\000\000\000\000\= 000 */ +{ 46717 }, /* l1i-prefetches-access\000legacy cache\000Level 1 instruction= cache prefetch accesses\000legacy-cache-config=3D0x201\000\00010\000\000\0= 00\000\000 */ +{ 46943 }, /* l1i-prefetches-miss\000legacy cache\000Level 1 instruction c= ache prefetch misses\000legacy-cache-config=3D0x10201\000\00010\000\000\000= \000\000 */ +{ 46830 }, /* l1i-prefetches-misses\000legacy cache\000Level 1 instruction= cache prefetch misses\000legacy-cache-config=3D0x10201\000\00010\000\000\0= 00\000\000 */ +{ 46607 }, /* l1i-prefetches-ops\000legacy cache\000Level 1 instruction ca= che prefetch accesses\000legacy-cache-config=3D0x201\000\00010\000\000\000\= 000\000 */ +{ 46491 }, /* l1i-prefetches-reference\000legacy cache\000Level 1 instruct= ion cache prefetch accesses\000legacy-cache-config=3D0x201\000\00010\000\00= 0\000\000\000 */ +{ 46380 }, /* l1i-prefetches-refs\000legacy cache\000Level 1 instruction c= ache prefetch accesses\000legacy-cache-config=3D0x201\000\00010\000\000\000= \000\000 */ +{ 44818 }, /* l1i-read\000legacy cache\000Level 1 instruction cache read a= ccesses\000legacy-cache-config=3D1\000\00010\000\000\000\000\000 */ +{ 45205 }, /* l1i-read-access\000legacy cache\000Level 1 instruction cache= read accesses\000legacy-cache-config=3D1\000\00010\000\000\000\000\000 */ +{ 45407 }, /* l1i-read-miss\000legacy cache\000Level 1 instruction cache r= ead misses\000legacy-cache-config=3D0x10001\000\00010\000\000\000\000\000 */ +{ 45304 }, /* l1i-read-misses\000legacy cache\000Level 1 instruction cache= read misses\000legacy-cache-config=3D0x10001\000\00010\000\000\000\000\000= */ +{ 45109 }, /* l1i-read-ops\000legacy cache\000Level 1 instruction cache re= ad accesses\000legacy-cache-config=3D1\000\00010\000\000\000\000\000 */ +{ 45007 }, /* l1i-read-reference\000legacy cache\000Level 1 instruction ca= che read accesses\000legacy-cache-config=3D1\000\00010\000\000\000\000\000 = */ +{ 44910 }, /* l1i-read-refs\000legacy cache\000Level 1 instruction cache r= ead accesses\000legacy-cache-config=3D1\000\00010\000\000\000\000\000 */ +{ 48790 }, /* l1i-reference\000legacy cache\000Level 1 instruction cache r= ead accesses\000legacy-cache-config=3D1\000\00010\000\000\000\000\000 */ +{ 48698 }, /* l1i-refs\000legacy cache\000Level 1 instruction cache read a= ccesses\000legacy-cache-config=3D1\000\00010\000\000\000\000\000 */ +{ 47876 }, /* l1i-speculative-load\000legacy cache\000Level 1 instruction = cache prefetch accesses\000legacy-cache-config=3D0x201\000\00010\000\000\00= 0\000\000 */ +{ 48343 }, /* l1i-speculative-load-access\000legacy cache\000Level 1 instr= uction cache prefetch accesses\000legacy-cache-config=3D0x201\000\00010\000= \000\000\000\000 */ +{ 48581 }, /* l1i-speculative-load-miss\000legacy cache\000Level 1 instruc= tion cache prefetch misses\000legacy-cache-config=3D0x10201\000\00010\000\0= 00\000\000\000 */ +{ 48462 }, /* l1i-speculative-load-misses\000legacy cache\000Level 1 instr= uction cache prefetch misses\000legacy-cache-config=3D0x10201\000\00010\000= \000\000\000\000 */ +{ 48227 }, /* l1i-speculative-load-ops\000legacy cache\000Level 1 instruct= ion cache prefetch accesses\000legacy-cache-config=3D0x201\000\00010\000\00= 0\000\000\000 */ +{ 48105 }, /* l1i-speculative-load-reference\000legacy cache\000Level 1 in= struction cache prefetch accesses\000legacy-cache-config=3D0x201\000\00010\= 000\000\000\000\000 */ +{ 47988 }, /* l1i-speculative-load-refs\000legacy cache\000Level 1 instruc= tion cache prefetch accesses\000legacy-cache-config=3D0x201\000\00010\000\0= 00\000\000\000 */ +{ 47054 }, /* l1i-speculative-read\000legacy cache\000Level 1 instruction = cache prefetch accesses\000legacy-cache-config=3D0x201\000\00010\000\000\00= 0\000\000 */ +{ 47521 }, /* l1i-speculative-read-access\000legacy cache\000Level 1 instr= uction cache prefetch accesses\000legacy-cache-config=3D0x201\000\00010\000= \000\000\000\000 */ +{ 47759 }, /* l1i-speculative-read-miss\000legacy cache\000Level 1 instruc= tion cache prefetch misses\000legacy-cache-config=3D0x10201\000\00010\000\0= 00\000\000\000 */ +{ 47640 }, /* l1i-speculative-read-misses\000legacy cache\000Level 1 instr= uction cache prefetch misses\000legacy-cache-config=3D0x10201\000\00010\000= \000\000\000\000 */ +{ 47405 }, /* l1i-speculative-read-ops\000legacy cache\000Level 1 instruct= ion cache prefetch accesses\000legacy-cache-config=3D0x201\000\00010\000\00= 0\000\000\000 */ +{ 47283 }, /* l1i-speculative-read-reference\000legacy cache\000Level 1 in= struction cache prefetch accesses\000legacy-cache-config=3D0x201\000\00010\= 000\000\000\000\000 */ +{ 47166 }, /* l1i-speculative-read-refs\000legacy cache\000Level 1 instruc= tion cache prefetch accesses\000legacy-cache-config=3D0x201\000\00010\000\0= 00\000\000\000 */ +{ 63212 }, /* l2\000legacy cache\000Level 2 (or higher) last level cache r= ead accesses\000legacy-cache-config=3D2\000\00010\000\000\000\000\000 */ +{ 71765 }, /* l2-access\000legacy cache\000Level 2 (or higher) last level = cache read accesses\000legacy-cache-config=3D2\000\00010\000\000\000\000\00= 0 */ +{ 63309 }, /* l2-load\000legacy cache\000Level 2 (or higher) last level ca= che read accesses\000legacy-cache-config=3D2\000\00010\000\000\000\000\000 = */ +{ 63736 }, /* l2-load-access\000legacy cache\000Level 2 (or higher) last l= evel cache read accesses\000legacy-cache-config=3D2\000\00010\000\000\000\0= 00\000 */ +{ 63958 }, /* l2-load-miss\000legacy cache\000Level 2 (or higher) last lev= el cache read misses\000legacy-cache-config=3D0x10002\000\00010\000\000\000= \000\000 */ +{ 63845 }, /* l2-load-misses\000legacy cache\000Level 2 (or higher) last l= evel cache read misses\000legacy-cache-config=3D0x10002\000\00010\000\000\0= 00\000\000 */ +{ 63630 }, /* l2-load-ops\000legacy cache\000Level 2 (or higher) last leve= l cache read accesses\000legacy-cache-config=3D2\000\00010\000\000\000\000\= 000 */ +{ 63518 }, /* l2-load-reference\000legacy cache\000Level 2 (or higher) las= t level cache read accesses\000legacy-cache-config=3D2\000\00010\000\000\00= 0\000\000 */ +{ 63411 }, /* l2-load-refs\000legacy cache\000Level 2 (or higher) last lev= el cache read accesses\000legacy-cache-config=3D2\000\00010\000\000\000\000= \000 */ +{ 64069 }, /* l2-loads\000legacy cache\000Level 2 (or higher) last level c= ache read accesses\000legacy-cache-config=3D2\000\00010\000\000\000\000\000= */ +{ 64500 }, /* l2-loads-access\000legacy cache\000Level 2 (or higher) last = level cache read accesses\000legacy-cache-config=3D2\000\00010\000\000\000\= 000\000 */ +{ 64724 }, /* l2-loads-miss\000legacy cache\000Level 2 (or higher) last le= vel cache read misses\000legacy-cache-config=3D0x10002\000\00010\000\000\00= 0\000\000 */ +{ 64610 }, /* l2-loads-misses\000legacy cache\000Level 2 (or higher) last = level cache read misses\000legacy-cache-config=3D0x10002\000\00010\000\000\= 000\000\000 */ +{ 64393 }, /* l2-loads-ops\000legacy cache\000Level 2 (or higher) last lev= el cache read accesses\000legacy-cache-config=3D2\000\00010\000\000\000\000= \000 */ +{ 64280 }, /* l2-loads-reference\000legacy cache\000Level 2 (or higher) la= st level cache read accesses\000legacy-cache-config=3D2\000\00010\000\000\0= 00\000\000 */ +{ 64172 }, /* l2-loads-refs\000legacy cache\000Level 2 (or higher) last le= vel cache read accesses\000legacy-cache-config=3D2\000\00010\000\000\000\00= 0\000 */ +{ 71977 }, /* l2-miss\000legacy cache\000Level 2 (or higher) last level ca= che read misses\000legacy-cache-config=3D0x10002\000\00010\000\000\000\000\= 000 */ +{ 71869 }, /* l2-misses\000legacy cache\000Level 2 (or higher) last level = cache read misses\000legacy-cache-config=3D0x10002\000\00010\000\000\000\00= 0\000 */ +{ 71664 }, /* l2-ops\000legacy cache\000Level 2 (or higher) last level cac= he read accesses\000legacy-cache-config=3D2\000\00010\000\000\000\000\000 */ +{ 67985 }, /* l2-prefetch\000legacy cache\000Level 2 (or higher) last leve= l cache prefetch accesses\000legacy-cache-config=3D0x202\000\00010\000\000\= 000\000\000 */ +{ 68460 }, /* l2-prefetch-access\000legacy cache\000Level 2 (or higher) la= st level cache prefetch accesses\000legacy-cache-config=3D0x202\000\00010\0= 00\000\000\000\000 */ +{ 68702 }, /* l2-prefetch-miss\000legacy cache\000Level 2 (or higher) last= level cache prefetch misses\000legacy-cache-config=3D0x10202\000\00010\000= \000\000\000\000 */ +{ 68581 }, /* l2-prefetch-misses\000legacy cache\000Level 2 (or higher) la= st level cache prefetch misses\000legacy-cache-config=3D0x10202\000\00010\0= 00\000\000\000\000 */ +{ 68342 }, /* l2-prefetch-ops\000legacy cache\000Level 2 (or higher) last = level cache prefetch accesses\000legacy-cache-config=3D0x202\000\00010\000\= 000\000\000\000 */ +{ 68218 }, /* l2-prefetch-reference\000legacy cache\000Level 2 (or higher)= last level cache prefetch accesses\000legacy-cache-config=3D0x202\000\0001= 0\000\000\000\000\000 */ +{ 68099 }, /* l2-prefetch-refs\000legacy cache\000Level 2 (or higher) last= level cache prefetch accesses\000legacy-cache-config=3D0x202\000\00010\000= \000\000\000\000 */ +{ 68821 }, /* l2-prefetches\000legacy cache\000Level 2 (or higher) last le= vel cache prefetch accesses\000legacy-cache-config=3D0x202\000\00010\000\00= 0\000\000\000 */ +{ 69304 }, /* l2-prefetches-access\000legacy cache\000Level 2 (or higher) = last level cache prefetch accesses\000legacy-cache-config=3D0x202\000\00010= \000\000\000\000\000 */ +{ 69550 }, /* l2-prefetches-miss\000legacy cache\000Level 2 (or higher) la= st level cache prefetch misses\000legacy-cache-config=3D0x10202\000\00010\0= 00\000\000\000\000 */ +{ 69427 }, /* l2-prefetches-misses\000legacy cache\000Level 2 (or higher) = last level cache prefetch misses\000legacy-cache-config=3D0x10202\000\00010= \000\000\000\000\000 */ +{ 69184 }, /* l2-prefetches-ops\000legacy cache\000Level 2 (or higher) las= t level cache prefetch accesses\000legacy-cache-config=3D0x202\000\00010\00= 0\000\000\000\000 */ +{ 69058 }, /* l2-prefetches-reference\000legacy cache\000Level 2 (or highe= r) last level cache prefetch accesses\000legacy-cache-config=3D0x202\000\00= 010\000\000\000\000\000 */ +{ 68937 }, /* l2-prefetches-refs\000legacy cache\000Level 2 (or higher) la= st level cache prefetch accesses\000legacy-cache-config=3D0x202\000\00010\0= 00\000\000\000\000 */ +{ 64836 }, /* l2-read\000legacy cache\000Level 2 (or higher) last level ca= che read accesses\000legacy-cache-config=3D2\000\00010\000\000\000\000\000 = */ +{ 65263 }, /* l2-read-access\000legacy cache\000Level 2 (or higher) last l= evel cache read accesses\000legacy-cache-config=3D2\000\00010\000\000\000\0= 00\000 */ +{ 65485 }, /* l2-read-miss\000legacy cache\000Level 2 (or higher) last lev= el cache read misses\000legacy-cache-config=3D0x10002\000\00010\000\000\000= \000\000 */ +{ 65372 }, /* l2-read-misses\000legacy cache\000Level 2 (or higher) last l= evel cache read misses\000legacy-cache-config=3D0x10002\000\00010\000\000\0= 00\000\000 */ +{ 65157 }, /* l2-read-ops\000legacy cache\000Level 2 (or higher) last leve= l cache read accesses\000legacy-cache-config=3D2\000\00010\000\000\000\000\= 000 */ +{ 65045 }, /* l2-read-reference\000legacy cache\000Level 2 (or higher) las= t level cache read accesses\000legacy-cache-config=3D2\000\00010\000\000\00= 0\000\000 */ +{ 64938 }, /* l2-read-refs\000legacy cache\000Level 2 (or higher) last lev= el cache read accesses\000legacy-cache-config=3D2\000\00010\000\000\000\000= \000 */ +{ 71557 }, /* l2-reference\000legacy cache\000Level 2 (or higher) last lev= el cache read accesses\000legacy-cache-config=3D2\000\00010\000\000\000\000= \000 */ +{ 71455 }, /* l2-refs\000legacy cache\000Level 2 (or higher) last level ca= che read accesses\000legacy-cache-config=3D2\000\00010\000\000\000\000\000 = */ +{ 70563 }, /* l2-speculative-load\000legacy cache\000Level 2 (or higher) l= ast level cache prefetch accesses\000legacy-cache-config=3D0x202\000\00010\= 000\000\000\000\000 */ +{ 71070 }, /* l2-speculative-load-access\000legacy cache\000Level 2 (or hi= gher) last level cache prefetch accesses\000legacy-cache-config=3D0x202\000= \00010\000\000\000\000\000 */ +{ 71328 }, /* l2-speculative-load-miss\000legacy cache\000Level 2 (or high= er) last level cache prefetch misses\000legacy-cache-config=3D0x10202\000\0= 0010\000\000\000\000\000 */ +{ 71199 }, /* l2-speculative-load-misses\000legacy cache\000Level 2 (or hi= gher) last level cache prefetch misses\000legacy-cache-config=3D0x10202\000= \00010\000\000\000\000\000 */ +{ 70944 }, /* l2-speculative-load-ops\000legacy cache\000Level 2 (or highe= r) last level cache prefetch accesses\000legacy-cache-config=3D0x202\000\00= 010\000\000\000\000\000 */ +{ 70812 }, /* l2-speculative-load-reference\000legacy cache\000Level 2 (or= higher) last level cache prefetch accesses\000legacy-cache-config=3D0x202\= 000\00010\000\000\000\000\000 */ +{ 70685 }, /* l2-speculative-load-refs\000legacy cache\000Level 2 (or high= er) last level cache prefetch accesses\000legacy-cache-config=3D0x202\000\0= 0010\000\000\000\000\000 */ +{ 69671 }, /* l2-speculative-read\000legacy cache\000Level 2 (or higher) l= ast level cache prefetch accesses\000legacy-cache-config=3D0x202\000\00010\= 000\000\000\000\000 */ +{ 70178 }, /* l2-speculative-read-access\000legacy cache\000Level 2 (or hi= gher) last level cache prefetch accesses\000legacy-cache-config=3D0x202\000= \00010\000\000\000\000\000 */ +{ 70436 }, /* l2-speculative-read-miss\000legacy cache\000Level 2 (or high= er) last level cache prefetch misses\000legacy-cache-config=3D0x10202\000\0= 0010\000\000\000\000\000 */ +{ 70307 }, /* l2-speculative-read-misses\000legacy cache\000Level 2 (or hi= gher) last level cache prefetch misses\000legacy-cache-config=3D0x10202\000= \00010\000\000\000\000\000 */ +{ 70052 }, /* l2-speculative-read-ops\000legacy cache\000Level 2 (or highe= r) last level cache prefetch accesses\000legacy-cache-config=3D0x202\000\00= 010\000\000\000\000\000 */ +{ 69920 }, /* l2-speculative-read-reference\000legacy cache\000Level 2 (or= higher) last level cache prefetch accesses\000legacy-cache-config=3D0x202\= 000\00010\000\000\000\000\000 */ +{ 69793 }, /* l2-speculative-read-refs\000legacy cache\000Level 2 (or high= er) last level cache prefetch accesses\000legacy-cache-config=3D0x202\000\0= 0010\000\000\000\000\000 */ +{ 65596 }, /* l2-store\000legacy cache\000Level 2 (or higher) last level c= ache write accesses\000legacy-cache-config=3D0x102\000\00010\000\000\000\00= 0\000 */ +{ 66047 }, /* l2-store-access\000legacy cache\000Level 2 (or higher) last = level cache write accesses\000legacy-cache-config=3D0x102\000\00010\000\000= \000\000\000 */ +{ 66277 }, /* l2-store-miss\000legacy cache\000Level 2 (or higher) last le= vel cache write misses\000legacy-cache-config=3D0x10102\000\00010\000\000\0= 00\000\000 */ +{ 66162 }, /* l2-store-misses\000legacy cache\000Level 2 (or higher) last = level cache write misses\000legacy-cache-config=3D0x10102\000\00010\000\000= \000\000\000 */ +{ 65935 }, /* l2-store-ops\000legacy cache\000Level 2 (or higher) last lev= el cache write accesses\000legacy-cache-config=3D0x102\000\00010\000\000\00= 0\000\000 */ +{ 65817 }, /* l2-store-reference\000legacy cache\000Level 2 (or higher) la= st level cache write accesses\000legacy-cache-config=3D0x102\000\00010\000\= 000\000\000\000 */ +{ 65704 }, /* l2-store-refs\000legacy cache\000Level 2 (or higher) last le= vel cache write accesses\000legacy-cache-config=3D0x102\000\00010\000\000\0= 00\000\000 */ +{ 66390 }, /* l2-stores\000legacy cache\000Level 2 (or higher) last level = cache write accesses\000legacy-cache-config=3D0x102\000\00010\000\000\000\0= 00\000 */ +{ 66845 }, /* l2-stores-access\000legacy cache\000Level 2 (or higher) last= level cache write accesses\000legacy-cache-config=3D0x102\000\00010\000\00= 0\000\000\000 */ +{ 67077 }, /* l2-stores-miss\000legacy cache\000Level 2 (or higher) last l= evel cache write misses\000legacy-cache-config=3D0x10102\000\00010\000\000\= 000\000\000 */ +{ 66961 }, /* l2-stores-misses\000legacy cache\000Level 2 (or higher) last= level cache write misses\000legacy-cache-config=3D0x10102\000\00010\000\00= 0\000\000\000 */ +{ 66732 }, /* l2-stores-ops\000legacy cache\000Level 2 (or higher) last le= vel cache write accesses\000legacy-cache-config=3D0x102\000\00010\000\000\0= 00\000\000 */ +{ 66613 }, /* l2-stores-reference\000legacy cache\000Level 2 (or higher) l= ast level cache write accesses\000legacy-cache-config=3D0x102\000\00010\000= \000\000\000\000 */ +{ 66499 }, /* l2-stores-refs\000legacy cache\000Level 2 (or higher) last l= evel cache write accesses\000legacy-cache-config=3D0x102\000\00010\000\000\= 000\000\000 */ +{ 67191 }, /* l2-write\000legacy cache\000Level 2 (or higher) last level c= ache write accesses\000legacy-cache-config=3D0x102\000\00010\000\000\000\00= 0\000 */ +{ 67642 }, /* l2-write-access\000legacy cache\000Level 2 (or higher) last = level cache write accesses\000legacy-cache-config=3D0x102\000\00010\000\000= \000\000\000 */ +{ 67872 }, /* l2-write-miss\000legacy cache\000Level 2 (or higher) last le= vel cache write misses\000legacy-cache-config=3D0x10102\000\00010\000\000\0= 00\000\000 */ +{ 67757 }, /* l2-write-misses\000legacy cache\000Level 2 (or higher) last = level cache write misses\000legacy-cache-config=3D0x10102\000\00010\000\000= \000\000\000 */ +{ 67530 }, /* l2-write-ops\000legacy cache\000Level 2 (or higher) last lev= el cache write accesses\000legacy-cache-config=3D0x102\000\00010\000\000\00= 0\000\000 */ +{ 67412 }, /* l2-write-reference\000legacy cache\000Level 2 (or higher) la= st level cache write accesses\000legacy-cache-config=3D0x102\000\00010\000\= 000\000\000\000 */ +{ 67299 }, /* l2-write-refs\000legacy cache\000Level 2 (or higher) last le= vel cache write accesses\000legacy-cache-config=3D0x102\000\00010\000\000\0= 00\000\000 */ +{ 55804 }, /* llc\000legacy cache\000Last level cache read accesses\000leg= acy-cache-config=3D2\000\00010\000\000\000\000\000 */ +{ 62951 }, /* llc-access\000legacy cache\000Last level cache read accesses= \000legacy-cache-config=3D2\000\00010\000\000\000\000\000 */ +{ 55882 }, /* llc-load\000legacy cache\000Last level cache read accesses\0= 00legacy-cache-config=3D2\000\00010\000\000\000\000\000 */ +{ 56233 }, /* llc-load-access\000legacy cache\000Last level cache read acc= esses\000legacy-cache-config=3D2\000\00010\000\000\000\000\000 */ +{ 56417 }, /* llc-load-miss\000legacy cache\000Last level cache read misse= s\000legacy-cache-config=3D0x10002\000\00010\000\000\000\000\000 */ +{ 56323 }, /* llc-load-misses\000legacy cache\000Last level cache read mis= ses\000legacy-cache-config=3D0x10002\000\00000\000\000\000\000\000 */ +{ 56146 }, /* llc-load-ops\000legacy cache\000Last level cache read access= es\000legacy-cache-config=3D2\000\00010\000\000\000\000\000 */ +{ 56053 }, /* llc-load-reference\000legacy cache\000Last level cache read = accesses\000legacy-cache-config=3D2\000\00010\000\000\000\000\000 */ +{ 55965 }, /* llc-load-refs\000legacy cache\000Last level cache read acces= ses\000legacy-cache-config=3D2\000\00010\000\000\000\000\000 */ +{ 56509 }, /* llc-loads\000legacy cache\000Last level cache read accesses\= 000legacy-cache-config=3D2\000\00000\000\000\000\000\000 */ +{ 56864 }, /* llc-loads-access\000legacy cache\000Last level cache read ac= cesses\000legacy-cache-config=3D2\000\00010\000\000\000\000\000 */ +{ 57050 }, /* llc-loads-miss\000legacy cache\000Last level cache read miss= es\000legacy-cache-config=3D0x10002\000\00010\000\000\000\000\000 */ +{ 56955 }, /* llc-loads-misses\000legacy cache\000Last level cache read mi= sses\000legacy-cache-config=3D0x10002\000\00010\000\000\000\000\000 */ +{ 56776 }, /* llc-loads-ops\000legacy cache\000Last level cache read acces= ses\000legacy-cache-config=3D2\000\00010\000\000\000\000\000 */ +{ 56682 }, /* llc-loads-reference\000legacy cache\000Last level cache read= accesses\000legacy-cache-config=3D2\000\00010\000\000\000\000\000 */ +{ 56593 }, /* llc-loads-refs\000legacy cache\000Last level cache read acce= sses\000legacy-cache-config=3D2\000\00010\000\000\000\000\000 */ +{ 63125 }, /* llc-miss\000legacy cache\000Last level cache read misses\000= legacy-cache-config=3D0x10002\000\00010\000\000\000\000\000 */ +{ 63036 }, /* llc-misses\000legacy cache\000Last level cache read misses\0= 00legacy-cache-config=3D0x10002\000\00010\000\000\000\000\000 */ +{ 62869 }, /* llc-ops\000legacy cache\000Last level cache read accesses\00= 0legacy-cache-config=3D2\000\00010\000\000\000\000\000 */ +{ 59760 }, /* llc-prefetch\000legacy cache\000Last level cache prefetch ac= cesses\000legacy-cache-config=3D0x202\000\00010\000\000\000\000\000 */ +{ 60159 }, /* llc-prefetch-access\000legacy cache\000Last level cache pref= etch accesses\000legacy-cache-config=3D0x202\000\00010\000\000\000\000\000 = */ +{ 60363 }, /* llc-prefetch-miss\000legacy cache\000Last level cache prefet= ch misses\000legacy-cache-config=3D0x10202\000\00010\000\000\000\000\000 */ +{ 60261 }, /* llc-prefetch-misses\000legacy cache\000Last level cache pref= etch misses\000legacy-cache-config=3D0x10202\000\00000\000\000\000\000\000 = */ +{ 60060 }, /* llc-prefetch-ops\000legacy cache\000Last level cache prefetc= h accesses\000legacy-cache-config=3D0x202\000\00010\000\000\000\000\000 */ +{ 59955 }, /* llc-prefetch-reference\000legacy cache\000Last level cache p= refetch accesses\000legacy-cache-config=3D0x202\000\00010\000\000\000\000\0= 00 */ +{ 59855 }, /* llc-prefetch-refs\000legacy cache\000Last level cache prefet= ch accesses\000legacy-cache-config=3D0x202\000\00010\000\000\000\000\000 */ +{ 60463 }, /* llc-prefetches\000legacy cache\000Last level cache prefetch = accesses\000legacy-cache-config=3D0x202\000\00000\000\000\000\000\000 */ +{ 60870 }, /* llc-prefetches-access\000legacy cache\000Last level cache pr= efetch accesses\000legacy-cache-config=3D0x202\000\00010\000\000\000\000\00= 0 */ +{ 61078 }, /* llc-prefetches-miss\000legacy cache\000Last level cache pref= etch misses\000legacy-cache-config=3D0x10202\000\00010\000\000\000\000\000 = */ +{ 60974 }, /* llc-prefetches-misses\000legacy cache\000Last level cache pr= efetch misses\000legacy-cache-config=3D0x10202\000\00010\000\000\000\000\00= 0 */ +{ 60769 }, /* llc-prefetches-ops\000legacy cache\000Last level cache prefe= tch accesses\000legacy-cache-config=3D0x202\000\00010\000\000\000\000\000 */ +{ 60662 }, /* llc-prefetches-reference\000legacy cache\000Last level cache= prefetch accesses\000legacy-cache-config=3D0x202\000\00010\000\000\000\000= \000 */ +{ 60560 }, /* llc-prefetches-refs\000legacy cache\000Last level cache pref= etch accesses\000legacy-cache-config=3D0x202\000\00010\000\000\000\000\000 = */ +{ 57143 }, /* llc-read\000legacy cache\000Last level cache read accesses\0= 00legacy-cache-config=3D2\000\00010\000\000\000\000\000 */ +{ 57494 }, /* llc-read-access\000legacy cache\000Last level cache read acc= esses\000legacy-cache-config=3D2\000\00010\000\000\000\000\000 */ +{ 57678 }, /* llc-read-miss\000legacy cache\000Last level cache read misse= s\000legacy-cache-config=3D0x10002\000\00010\000\000\000\000\000 */ +{ 57584 }, /* llc-read-misses\000legacy cache\000Last level cache read mis= ses\000legacy-cache-config=3D0x10002\000\00010\000\000\000\000\000 */ +{ 57407 }, /* llc-read-ops\000legacy cache\000Last level cache read access= es\000legacy-cache-config=3D2\000\00010\000\000\000\000\000 */ +{ 57314 }, /* llc-read-reference\000legacy cache\000Last level cache read = accesses\000legacy-cache-config=3D2\000\00010\000\000\000\000\000 */ +{ 57226 }, /* llc-read-refs\000legacy cache\000Last level cache read acces= ses\000legacy-cache-config=3D2\000\00010\000\000\000\000\000 */ +{ 62781 }, /* llc-reference\000legacy cache\000Last level cache read acces= ses\000legacy-cache-config=3D2\000\00010\000\000\000\000\000 */ +{ 62698 }, /* llc-refs\000legacy cache\000Last level cache read accesses\0= 00legacy-cache-config=3D2\000\00010\000\000\000\000\000 */ +{ 61939 }, /* llc-speculative-load\000legacy cache\000Last level cache pre= fetch accesses\000legacy-cache-config=3D0x202\000\00010\000\000\000\000\000= */ +{ 62370 }, /* llc-speculative-load-access\000legacy cache\000Last level ca= che prefetch accesses\000legacy-cache-config=3D0x202\000\00010\000\000\000\= 000\000 */ +{ 62590 }, /* llc-speculative-load-miss\000legacy cache\000Last level cach= e prefetch misses\000legacy-cache-config=3D0x10202\000\00010\000\000\000\00= 0\000 */ +{ 62480 }, /* llc-speculative-load-misses\000legacy cache\000Last level ca= che prefetch misses\000legacy-cache-config=3D0x10202\000\00010\000\000\000\= 000\000 */ +{ 62263 }, /* llc-speculative-load-ops\000legacy cache\000Last level cache= prefetch accesses\000legacy-cache-config=3D0x202\000\00010\000\000\000\000= \000 */ +{ 62150 }, /* llc-speculative-load-reference\000legacy cache\000Last level= cache prefetch accesses\000legacy-cache-config=3D0x202\000\00010\000\000\0= 00\000\000 */ +{ 62042 }, /* llc-speculative-load-refs\000legacy cache\000Last level cach= e prefetch accesses\000legacy-cache-config=3D0x202\000\00010\000\000\000\00= 0\000 */ +{ 61180 }, /* llc-speculative-read\000legacy cache\000Last level cache pre= fetch accesses\000legacy-cache-config=3D0x202\000\00010\000\000\000\000\000= */ +{ 61611 }, /* llc-speculative-read-access\000legacy cache\000Last level ca= che prefetch accesses\000legacy-cache-config=3D0x202\000\00010\000\000\000\= 000\000 */ +{ 61831 }, /* llc-speculative-read-miss\000legacy cache\000Last level cach= e prefetch misses\000legacy-cache-config=3D0x10202\000\00010\000\000\000\00= 0\000 */ +{ 61721 }, /* llc-speculative-read-misses\000legacy cache\000Last level ca= che prefetch misses\000legacy-cache-config=3D0x10202\000\00010\000\000\000\= 000\000 */ +{ 61504 }, /* llc-speculative-read-ops\000legacy cache\000Last level cache= prefetch accesses\000legacy-cache-config=3D0x202\000\00010\000\000\000\000= \000 */ +{ 61391 }, /* llc-speculative-read-reference\000legacy cache\000Last level= cache prefetch accesses\000legacy-cache-config=3D0x202\000\00010\000\000\0= 00\000\000 */ +{ 61283 }, /* llc-speculative-read-refs\000legacy cache\000Last level cach= e prefetch accesses\000legacy-cache-config=3D0x202\000\00010\000\000\000\00= 0\000 */ +{ 57770 }, /* llc-store\000legacy cache\000Last level cache write accesses= \000legacy-cache-config=3D0x102\000\00010\000\000\000\000\000 */ +{ 58145 }, /* llc-store-access\000legacy cache\000Last level cache write a= ccesses\000legacy-cache-config=3D0x102\000\00010\000\000\000\000\000 */ +{ 58337 }, /* llc-store-miss\000legacy cache\000Last level cache write mis= ses\000legacy-cache-config=3D0x10102\000\00010\000\000\000\000\000 */ +{ 58241 }, /* llc-store-misses\000legacy cache\000Last level cache write m= isses\000legacy-cache-config=3D0x10102\000\00000\000\000\000\000\000 */ +{ 58052 }, /* llc-store-ops\000legacy cache\000Last level cache write acce= sses\000legacy-cache-config=3D0x102\000\00010\000\000\000\000\000 */ +{ 57953 }, /* llc-store-reference\000legacy cache\000Last level cache writ= e accesses\000legacy-cache-config=3D0x102\000\00010\000\000\000\000\000 */ +{ 57859 }, /* llc-store-refs\000legacy cache\000Last level cache write acc= esses\000legacy-cache-config=3D0x102\000\00010\000\000\000\000\000 */ +{ 58431 }, /* llc-stores\000legacy cache\000Last level cache write accesse= s\000legacy-cache-config=3D0x102\000\00000\000\000\000\000\000 */ +{ 58810 }, /* llc-stores-access\000legacy cache\000Last level cache write = accesses\000legacy-cache-config=3D0x102\000\00010\000\000\000\000\000 */ +{ 59004 }, /* llc-stores-miss\000legacy cache\000Last level cache write mi= sses\000legacy-cache-config=3D0x10102\000\00010\000\000\000\000\000 */ +{ 58907 }, /* llc-stores-misses\000legacy cache\000Last level cache write = misses\000legacy-cache-config=3D0x10102\000\00010\000\000\000\000\000 */ +{ 58716 }, /* llc-stores-ops\000legacy cache\000Last level cache write acc= esses\000legacy-cache-config=3D0x102\000\00010\000\000\000\000\000 */ +{ 58616 }, /* llc-stores-reference\000legacy cache\000Last level cache wri= te accesses\000legacy-cache-config=3D0x102\000\00010\000\000\000\000\000 */ +{ 58521 }, /* llc-stores-refs\000legacy cache\000Last level cache write ac= cesses\000legacy-cache-config=3D0x102\000\00010\000\000\000\000\000 */ +{ 59099 }, /* llc-write\000legacy cache\000Last level cache write accesses= \000legacy-cache-config=3D0x102\000\00010\000\000\000\000\000 */ +{ 59474 }, /* llc-write-access\000legacy cache\000Last level cache write a= ccesses\000legacy-cache-config=3D0x102\000\00010\000\000\000\000\000 */ +{ 59666 }, /* llc-write-miss\000legacy cache\000Last level cache write mis= ses\000legacy-cache-config=3D0x10102\000\00010\000\000\000\000\000 */ +{ 59570 }, /* llc-write-misses\000legacy cache\000Last level cache write m= isses\000legacy-cache-config=3D0x10102\000\00010\000\000\000\000\000 */ +{ 59381 }, /* llc-write-ops\000legacy cache\000Last level cache write acce= sses\000legacy-cache-config=3D0x102\000\00010\000\000\000\000\000 */ +{ 59282 }, /* llc-write-reference\000legacy cache\000Last level cache writ= e accesses\000legacy-cache-config=3D0x102\000\00010\000\000\000\000\000 */ +{ 59188 }, /* llc-write-refs\000legacy cache\000Last level cache write acc= esses\000legacy-cache-config=3D0x102\000\00010\000\000\000\000\000 */ +{ 114128 }, /* node\000legacy cache\000Local memory read accesses\000legac= y-cache-config=3D6\000\00010\000\000\000\000\000 */ +{ 121053 }, /* node-access\000legacy cache\000Local memory read accesses\0= 00legacy-cache-config=3D6\000\00010\000\000\000\000\000 */ +{ 114203 }, /* node-load\000legacy cache\000Local memory read accesses\000= legacy-cache-config=3D6\000\00010\000\000\000\000\000 */ +{ 114542 }, /* node-load-access\000legacy cache\000Local memory read acces= ses\000legacy-cache-config=3D6\000\00010\000\000\000\000\000 */ +{ 114720 }, /* node-load-miss\000legacy cache\000Local memory read misses\= 000legacy-cache-config=3D0x10006\000\00010\000\000\000\000\000 */ +{ 114629 }, /* node-load-misses\000legacy cache\000Local memory read misse= s\000legacy-cache-config=3D0x10006\000\00000\000\000\000\000\000 */ +{ 114458 }, /* node-load-ops\000legacy cache\000Local memory read accesses= \000legacy-cache-config=3D6\000\00010\000\000\000\000\000 */ +{ 114368 }, /* node-load-reference\000legacy cache\000Local memory read ac= cesses\000legacy-cache-config=3D6\000\00010\000\000\000\000\000 */ +{ 114283 }, /* node-load-refs\000legacy cache\000Local memory read accesse= s\000legacy-cache-config=3D6\000\00010\000\000\000\000\000 */ +{ 114809 }, /* node-loads\000legacy cache\000Local memory read accesses\00= 0legacy-cache-config=3D6\000\00000\000\000\000\000\000 */ +{ 115152 }, /* node-loads-access\000legacy cache\000Local memory read acce= sses\000legacy-cache-config=3D6\000\00010\000\000\000\000\000 */ +{ 115332 }, /* node-loads-miss\000legacy cache\000Local memory read misses= \000legacy-cache-config=3D0x10006\000\00010\000\000\000\000\000 */ +{ 115240 }, /* node-loads-misses\000legacy cache\000Local memory read miss= es\000legacy-cache-config=3D0x10006\000\00010\000\000\000\000\000 */ +{ 115067 }, /* node-loads-ops\000legacy cache\000Local memory read accesse= s\000legacy-cache-config=3D6\000\00010\000\000\000\000\000 */ +{ 114976 }, /* node-loads-reference\000legacy cache\000Local memory read a= ccesses\000legacy-cache-config=3D6\000\00010\000\000\000\000\000 */ +{ 114890 }, /* node-loads-refs\000legacy cache\000Local memory read access= es\000legacy-cache-config=3D6\000\00010\000\000\000\000\000 */ +{ 121221 }, /* node-miss\000legacy cache\000Local memory read misses\000le= gacy-cache-config=3D0x10006\000\00010\000\000\000\000\000 */ +{ 121135 }, /* node-misses\000legacy cache\000Local memory read misses\000= legacy-cache-config=3D0x10006\000\00010\000\000\000\000\000 */ +{ 120974 }, /* node-ops\000legacy cache\000Local memory read accesses\000l= egacy-cache-config=3D6\000\00010\000\000\000\000\000 */ +{ 117955 }, /* node-prefetch\000legacy cache\000Local memory prefetch acce= sses\000legacy-cache-config=3D0x206\000\00010\000\000\000\000\000 */ +{ 118342 }, /* node-prefetch-access\000legacy cache\000Local memory prefet= ch accesses\000legacy-cache-config=3D0x206\000\00010\000\000\000\000\000 */ +{ 118540 }, /* node-prefetch-miss\000legacy cache\000Local memory prefetch= misses\000legacy-cache-config=3D0x10206\000\00010\000\000\000\000\000 */ +{ 118441 }, /* node-prefetch-misses\000legacy cache\000Local memory prefet= ch misses\000legacy-cache-config=3D0x10206\000\00000\000\000\000\000\000 */ +{ 118246 }, /* node-prefetch-ops\000legacy cache\000Local memory prefetch = accesses\000legacy-cache-config=3D0x206\000\00010\000\000\000\000\000 */ +{ 118144 }, /* node-prefetch-reference\000legacy cache\000Local memory pre= fetch accesses\000legacy-cache-config=3D0x206\000\00010\000\000\000\000\000= */ +{ 118047 }, /* node-prefetch-refs\000legacy cache\000Local memory prefetch= accesses\000legacy-cache-config=3D0x206\000\00010\000\000\000\000\000 */ +{ 118637 }, /* node-prefetches\000legacy cache\000Local memory prefetch ac= cesses\000legacy-cache-config=3D0x206\000\00000\000\000\000\000\000 */ +{ 119032 }, /* node-prefetches-access\000legacy cache\000Local memory pref= etch accesses\000legacy-cache-config=3D0x206\000\00010\000\000\000\000\000 = */ +{ 119234 }, /* node-prefetches-miss\000legacy cache\000Local memory prefet= ch misses\000legacy-cache-config=3D0x10206\000\00010\000\000\000\000\000 */ +{ 119133 }, /* node-prefetches-misses\000legacy cache\000Local memory pref= etch misses\000legacy-cache-config=3D0x10206\000\00010\000\000\000\000\000 = */ +{ 118934 }, /* node-prefetches-ops\000legacy cache\000Local memory prefetc= h accesses\000legacy-cache-config=3D0x206\000\00010\000\000\000\000\000 */ +{ 118830 }, /* node-prefetches-reference\000legacy cache\000Local memory p= refetch accesses\000legacy-cache-config=3D0x206\000\00010\000\000\000\000\0= 00 */ +{ 118731 }, /* node-prefetches-refs\000legacy cache\000Local memory prefet= ch accesses\000legacy-cache-config=3D0x206\000\00010\000\000\000\000\000 */ +{ 115422 }, /* node-read\000legacy cache\000Local memory read accesses\000= legacy-cache-config=3D6\000\00010\000\000\000\000\000 */ +{ 115761 }, /* node-read-access\000legacy cache\000Local memory read acces= ses\000legacy-cache-config=3D6\000\00010\000\000\000\000\000 */ +{ 115939 }, /* node-read-miss\000legacy cache\000Local memory read misses\= 000legacy-cache-config=3D0x10006\000\00010\000\000\000\000\000 */ +{ 115848 }, /* node-read-misses\000legacy cache\000Local memory read misse= s\000legacy-cache-config=3D0x10006\000\00010\000\000\000\000\000 */ +{ 115677 }, /* node-read-ops\000legacy cache\000Local memory read accesses= \000legacy-cache-config=3D6\000\00010\000\000\000\000\000 */ +{ 115587 }, /* node-read-reference\000legacy cache\000Local memory read ac= cesses\000legacy-cache-config=3D6\000\00010\000\000\000\000\000 */ +{ 115502 }, /* node-read-refs\000legacy cache\000Local memory read accesse= s\000legacy-cache-config=3D6\000\00010\000\000\000\000\000 */ +{ 120889 }, /* node-reference\000legacy cache\000Local memory read accesse= s\000legacy-cache-config=3D6\000\00010\000\000\000\000\000 */ +{ 120809 }, /* node-refs\000legacy cache\000Local memory read accesses\000= legacy-cache-config=3D6\000\00010\000\000\000\000\000 */ +{ 120071 }, /* node-speculative-load\000legacy cache\000Local memory prefe= tch accesses\000legacy-cache-config=3D0x206\000\00010\000\000\000\000\000 */ +{ 120490 }, /* node-speculative-load-access\000legacy cache\000Local memor= y prefetch accesses\000legacy-cache-config=3D0x206\000\00010\000\000\000\00= 0\000 */ +{ 120704 }, /* node-speculative-load-miss\000legacy cache\000Local memory = prefetch misses\000legacy-cache-config=3D0x10206\000\00010\000\000\000\000\= 000 */ +{ 120597 }, /* node-speculative-load-misses\000legacy cache\000Local memor= y prefetch misses\000legacy-cache-config=3D0x10206\000\00010\000\000\000\00= 0\000 */ +{ 120386 }, /* node-speculative-load-ops\000legacy cache\000Local memory p= refetch accesses\000legacy-cache-config=3D0x206\000\00010\000\000\000\000\0= 00 */ +{ 120276 }, /* node-speculative-load-reference\000legacy cache\000Local me= mory prefetch accesses\000legacy-cache-config=3D0x206\000\00010\000\000\000= \000\000 */ +{ 120171 }, /* node-speculative-load-refs\000legacy cache\000Local memory = prefetch accesses\000legacy-cache-config=3D0x206\000\00010\000\000\000\000\= 000 */ +{ 119333 }, /* node-speculative-read\000legacy cache\000Local memory prefe= tch accesses\000legacy-cache-config=3D0x206\000\00010\000\000\000\000\000 */ +{ 119752 }, /* node-speculative-read-access\000legacy cache\000Local memor= y prefetch accesses\000legacy-cache-config=3D0x206\000\00010\000\000\000\00= 0\000 */ +{ 119966 }, /* node-speculative-read-miss\000legacy cache\000Local memory = prefetch misses\000legacy-cache-config=3D0x10206\000\00010\000\000\000\000\= 000 */ +{ 119859 }, /* node-speculative-read-misses\000legacy cache\000Local memor= y prefetch misses\000legacy-cache-config=3D0x10206\000\00010\000\000\000\00= 0\000 */ +{ 119648 }, /* node-speculative-read-ops\000legacy cache\000Local memory p= refetch accesses\000legacy-cache-config=3D0x206\000\00010\000\000\000\000\0= 00 */ +{ 119538 }, /* node-speculative-read-reference\000legacy cache\000Local me= mory prefetch accesses\000legacy-cache-config=3D0x206\000\00010\000\000\000= \000\000 */ +{ 119433 }, /* node-speculative-read-refs\000legacy cache\000Local memory = prefetch accesses\000legacy-cache-config=3D0x206\000\00010\000\000\000\000\= 000 */ +{ 116028 }, /* node-store\000legacy cache\000Local memory write accesses\0= 00legacy-cache-config=3D0x106\000\00010\000\000\000\000\000 */ +{ 116391 }, /* node-store-access\000legacy cache\000Local memory write acc= esses\000legacy-cache-config=3D0x106\000\00010\000\000\000\000\000 */ +{ 116577 }, /* node-store-miss\000legacy cache\000Local memory write misse= s\000legacy-cache-config=3D0x10106\000\00010\000\000\000\000\000 */ +{ 116484 }, /* node-store-misses\000legacy cache\000Local memory write mis= ses\000legacy-cache-config=3D0x10106\000\00000\000\000\000\000\000 */ +{ 116301 }, /* node-store-ops\000legacy cache\000Local memory write access= es\000legacy-cache-config=3D0x106\000\00010\000\000\000\000\000 */ +{ 116205 }, /* node-store-reference\000legacy cache\000Local memory write = accesses\000legacy-cache-config=3D0x106\000\00010\000\000\000\000\000 */ +{ 116114 }, /* node-store-refs\000legacy cache\000Local memory write acces= ses\000legacy-cache-config=3D0x106\000\00010\000\000\000\000\000 */ +{ 116668 }, /* node-stores\000legacy cache\000Local memory write accesses\= 000legacy-cache-config=3D0x106\000\00000\000\000\000\000\000 */ +{ 117035 }, /* node-stores-access\000legacy cache\000Local memory write ac= cesses\000legacy-cache-config=3D0x106\000\00010\000\000\000\000\000 */ +{ 117223 }, /* node-stores-miss\000legacy cache\000Local memory write miss= es\000legacy-cache-config=3D0x10106\000\00010\000\000\000\000\000 */ +{ 117129 }, /* node-stores-misses\000legacy cache\000Local memory write mi= sses\000legacy-cache-config=3D0x10106\000\00010\000\000\000\000\000 */ +{ 116944 }, /* node-stores-ops\000legacy cache\000Local memory write acces= ses\000legacy-cache-config=3D0x106\000\00010\000\000\000\000\000 */ +{ 116847 }, /* node-stores-reference\000legacy cache\000Local memory write= accesses\000legacy-cache-config=3D0x106\000\00010\000\000\000\000\000 */ +{ 116755 }, /* node-stores-refs\000legacy cache\000Local memory write acce= sses\000legacy-cache-config=3D0x106\000\00010\000\000\000\000\000 */ +{ 117315 }, /* node-write\000legacy cache\000Local memory write accesses\0= 00legacy-cache-config=3D0x106\000\00010\000\000\000\000\000 */ +{ 117678 }, /* node-write-access\000legacy cache\000Local memory write acc= esses\000legacy-cache-config=3D0x106\000\00010\000\000\000\000\000 */ +{ 117864 }, /* node-write-miss\000legacy cache\000Local memory write misse= s\000legacy-cache-config=3D0x10106\000\00010\000\000\000\000\000 */ +{ 117771 }, /* node-write-misses\000legacy cache\000Local memory write mis= ses\000legacy-cache-config=3D0x10106\000\00010\000\000\000\000\000 */ +{ 117588 }, /* node-write-ops\000legacy cache\000Local memory write access= es\000legacy-cache-config=3D0x106\000\00010\000\000\000\000\000 */ +{ 117492 }, /* node-write-reference\000legacy cache\000Local memory write = accesses\000legacy-cache-config=3D0x106\000\00010\000\000\000\000\000 */ +{ 117401 }, /* node-write-refs\000legacy cache\000Local memory write acces= ses\000legacy-cache-config=3D0x106\000\00010\000\000\000\000\000 */ +{ 123400 }, /* ref-cycles\000legacy hardware\000Total cycles; not affected= by CPU frequency scaling\000legacy-hardware-config=3D9\000\00000\000\000\0= 00\000\000 */ +{ 123094 }, /* stalled-cycles-backend\000legacy hardware\000Stalled cycles= during retirement [This event is an alias of idle-cycles-backend]\000legac= y-hardware-config=3D8\000\00000\000\000\000\000\000 */ +{ 122795 }, /* stalled-cycles-frontend\000legacy hardware\000Stalled cycle= s during issue [This event is an alias of idle-cycles-frontend]\000legacy-h= ardware-config=3D7\000\00000\000\000\000\000\000 */ +}; static const struct compact_pmu_event pmu_events__common_software[] =3D { -{ 1035 }, /* alignment-faults\000software\000Number of kernel handled memo= ry alignment faults\000config=3D7\000\00000\000\000\000\000\000 */ -{ 1334 }, /* bpf-output\000software\000An event used by BPF programs to wr= ite to the perf ring buffer\000config=3D0xa\000\00000\000\000\000\000\000 */ -{ 1436 }, /* cgroup-switches\000software\000Number of context switches to = a task in a different cgroup\000config=3D0xb\000\00000\000\000\000\000\000 = */ -{ 357 }, /* context-switches\000software\000Number of context switches [Th= is event is an alias of cs]\000config=3D3\000\00000\000\000\000\000\000 */ -{ 9 }, /* cpu-clock\000software\000Per-CPU high-resolution timer based eve= nt\000config=3D0\000\00000\000\000\000\000\000 */ -{ 559 }, /* cpu-migrations\000software\000Number of times a process has mi= grated to a new CPU [This event is an alias of migrations]\000config=3D4\00= 0\00000\000\000\000\000\000 */ -{ 458 }, /* cs\000software\000Number of context switches [This event is an= alias of context-switches]\000config=3D3\000\00000\000\000\000\000\000 */ -{ 1254 }, /* dummy\000software\000A placeholder event that doesn't count a= nything\000config=3D9\000\00000\000\000\000\000\000 */ -{ 1127 }, /* emulation-faults\000software\000Number of kernel handled unim= plemented instruction faults handled through emulation\000config=3D8\000\00= 000\000\000\000\000\000 */ -{ 167 }, /* faults\000software\000Number of page faults [This event is an = alias of page-faults]\000config=3D2\000\00000\000\000\000\000\000 */ -{ 932 }, /* major-faults\000software\000Number of major page faults. Major= faults require I/O to handle\000config=3D6\000\00000\000\000\000\000\000 */ -{ 691 }, /* migrations\000software\000Number of times a process has migrat= ed to a new CPU [This event is an alias of cpu-migrations]\000config=3D4\00= 0\00000\000\000\000\000\000 */ -{ 823 }, /* minor-faults\000software\000Number of minor page faults. Minor= faults don't require I/O to handle\000config=3D5\000\00000\000\000\000\000= \000 */ -{ 262 }, /* page-faults\000software\000Number of page faults [This event i= s an alias of faults]\000config=3D2\000\00000\000\000\000\000\000 */ -{ 87 }, /* task-clock\000software\000Per-task high-resolution timer based = event\000config=3D1\000\00000\000\000\000\000\000 */ +{ 124547 }, /* alignment-faults\000software\000Number of kernel handled me= mory alignment faults\000config=3D7\000\00000\000\000\000\000\000 */ +{ 124846 }, /* bpf-output\000software\000An event used by BPF programs to = write to the perf ring buffer\000config=3D0xa\000\00000\000\000\000\000\000= */ +{ 124948 }, /* cgroup-switches\000software\000Number of context switches t= o a task in a different cgroup\000config=3D0xb\000\00000\000\000\000\000\00= 0 */ +{ 123869 }, /* context-switches\000software\000Number of context switches = [This event is an alias of cs]\000config=3D3\000\00000\000\000\000\000\000 = */ +{ 123521 }, /* cpu-clock\000software\000Per-CPU high-resolution timer base= d event\000config=3D0\000\00000\000\000\000\000\000 */ +{ 124071 }, /* cpu-migrations\000software\000Number of times a process has= migrated to a new CPU [This event is an alias of migrations]\000config=3D4= \000\00000\000\000\000\000\000 */ +{ 123970 }, /* cs\000software\000Number of context switches [This event is= an alias of context-switches]\000config=3D3\000\00000\000\000\000\000\000 = */ +{ 124766 }, /* dummy\000software\000A placeholder event that doesn't count= anything\000config=3D9\000\00000\000\000\000\000\000 */ +{ 124639 }, /* emulation-faults\000software\000Number of kernel handled un= implemented instruction faults handled through emulation\000config=3D8\000\= 00000\000\000\000\000\000 */ +{ 123679 }, /* faults\000software\000Number of page faults [This event is = an alias of page-faults]\000config=3D2\000\00000\000\000\000\000\000 */ +{ 124444 }, /* major-faults\000software\000Number of major page faults. Ma= jor faults require I/O to handle\000config=3D6\000\00000\000\000\000\000\00= 0 */ +{ 124203 }, /* migrations\000software\000Number of times a process has mig= rated to a new CPU [This event is an alias of cpu-migrations]\000config=3D4= \000\00000\000\000\000\000\000 */ +{ 124335 }, /* minor-faults\000software\000Number of minor page faults. Mi= nor faults don't require I/O to handle\000config=3D5\000\00000\000\000\000\= 000\000 */ +{ 123774 }, /* page-faults\000software\000Number of page faults [This even= t is an alias of faults]\000config=3D2\000\00000\000\000\000\000\000 */ +{ 123599 }, /* task-clock\000software\000Per-task high-resolution timer ba= sed event\000config=3D1\000\00000\000\000\000\000\000 */ }; static const struct compact_pmu_event pmu_events__common_tool[] =3D { -{ 1544 }, /* duration_time\000tool\000Wall clock interval time in nanoseco= nds\000config=3D1\000\00000\000\000\000\000\000 */ -{ 1758 }, /* has_pmem\000tool\0001 if persistent memory installed otherwis= e 0\000config=3D4\000\00000\000\000\000\000\000 */ -{ 1834 }, /* num_cores\000tool\000Number of cores. A core consists of 1 or= more thread, with each thread being associated with a logical Linux CPU\00= 0config=3D5\000\00000\000\000\000\000\000 */ -{ 1979 }, /* num_cpus\000tool\000Number of logical Linux CPUs. There may b= e multiple such CPUs on a core\000config=3D6\000\00000\000\000\000\000\000 = */ -{ 2082 }, /* num_cpus_online\000tool\000Number of online logical Linux CPU= s. There may be multiple such CPUs on a core\000config=3D7\000\00000\000\00= 0\000\000\000 */ -{ 2199 }, /* num_dies\000tool\000Number of dies. Each die has 1 or more co= res\000config=3D8\000\00000\000\000\000\000\000 */ -{ 2275 }, /* num_packages\000tool\000Number of packages. Each package has = 1 or more die\000config=3D9\000\00000\000\000\000\000\000 */ -{ 2361 }, /* slots\000tool\000Number of functional units that in parallel = can execute parts of an instruction\000config=3D0xa\000\00000\000\000\000\0= 00\000 */ -{ 2471 }, /* smt_on\000tool\0001 if simultaneous multithreading (aka hyper= threading) is enable otherwise 0\000config=3D0xb\000\00000\000\000\000\000\= 000 */ -{ 1690 }, /* system_time\000tool\000System/kernel time in nanoseconds\000c= onfig=3D3\000\00000\000\000\000\000\000 */ -{ 2578 }, /* system_tsc_freq\000tool\000The amount a Time Stamp Counter (T= SC) increases per second\000config=3D0xc\000\00000\000\000\000\000\000 */ -{ 1620 }, /* user_time\000tool\000User (non-kernel) time in nanoseconds\00= 0config=3D2\000\00000\000\000\000\000\000 */ +{ 125056 }, /* duration_time\000tool\000Wall clock interval time in nanose= conds\000config=3D1\000\00000\000\000\000\000\000 */ +{ 125270 }, /* has_pmem\000tool\0001 if persistent memory installed otherw= ise 0\000config=3D4\000\00000\000\000\000\000\000 */ +{ 125346 }, /* num_cores\000tool\000Number of cores. A core consists of 1 = or more thread, with each thread being associated with a logical Linux CPU\= 000config=3D5\000\00000\000\000\000\000\000 */ +{ 125491 }, /* num_cpus\000tool\000Number of logical Linux CPUs. There may= be multiple such CPUs on a core\000config=3D6\000\00000\000\000\000\000\00= 0 */ +{ 125594 }, /* num_cpus_online\000tool\000Number of online logical Linux C= PUs. There may be multiple such CPUs on a core\000config=3D7\000\00000\000\= 000\000\000\000 */ +{ 125711 }, /* num_dies\000tool\000Number of dies. Each die has 1 or more = cores\000config=3D8\000\00000\000\000\000\000\000 */ +{ 125787 }, /* num_packages\000tool\000Number of packages. Each package ha= s 1 or more die\000config=3D9\000\00000\000\000\000\000\000 */ +{ 125873 }, /* slots\000tool\000Number of functional units that in paralle= l can execute parts of an instruction\000config=3D0xa\000\00000\000\000\000= \000\000 */ +{ 125983 }, /* smt_on\000tool\0001 if simultaneous multithreading (aka hyp= erthreading) is enable otherwise 0\000config=3D0xb\000\00000\000\000\000\00= 0\000 */ +{ 125202 }, /* system_time\000tool\000System/kernel time in nanoseconds\00= 0config=3D3\000\00000\000\000\000\000\000 */ +{ 126090 }, /* system_tsc_freq\000tool\000The amount a Time Stamp Counter = (TSC) increases per second\000config=3D0xc\000\00000\000\000\000\000\000 */ +{ 125132 }, /* user_time\000tool\000User (non-kernel) time in nanoseconds\= 000config=3D2\000\00000\000\000\000\000\000 */ =20 }; =20 const struct pmu_table_entry pmu_events__common[] =3D { +{ + .entries =3D pmu_events__common_default_core, + .num_entries =3D ARRAY_SIZE(pmu_events__common_default_core), + .pmu_name =3D { 0 /* default_core\000 */ }, +}, { .entries =3D pmu_events__common_software, .num_entries =3D ARRAY_SIZE(pmu_events__common_software), - .pmu_name =3D { 0 /* software\000 */ }, + .pmu_name =3D { 123512 /* software\000 */ }, }, { .entries =3D pmu_events__common_tool, .num_entries =3D ARRAY_SIZE(pmu_events__common_tool), - .pmu_name =3D { 1539 /* tool\000 */ }, + .pmu_name =3D { 125051 /* tool\000 */ }, }, }; =20 static const struct compact_pmu_event pmu_events__test_soc_cpu_default_cor= e[] =3D { -{ 2690 }, /* bp_l1_btb_correct\000branch\000L1 BTB Correction\000event=3D0= x8a\000\00000\000\000\000\000\000 */ -{ 2752 }, /* bp_l2_btb_correct\000branch\000L2 BTB Correction\000event=3D0= x8b\000\00000\000\000\000\000\000 */ -{ 3014 }, /* dispatch_blocked.any\000other\000Memory cluster signals to bl= ock micro-op dispatch for any reason\000event=3D9,period=3D200000,umask=3D0= x20\000\00000\000\000\000\000\000 */ -{ 3147 }, /* eist_trans\000other\000Number of Enhanced Intel SpeedStep(R) = Technology (EIST) transitions\000event=3D0x3a,period=3D200000\000\00000\000= \000\000\000\000 */ -{ 2814 }, /* l3_cache_rd\000cache\000L3 cache access, read\000event=3D0x40= \000\00000\000\000\000\000Attributable Level 3 cache access, read\000 */ -{ 2912 }, /* segment_reg_loads.any\000other\000Number of segment register = loads\000event=3D6,period=3D200000,umask=3D0x80\000\00000\000\000\000\000\0= 00 */ +{ 126189 }, /* bp_l1_btb_correct\000branch\000L1 BTB Correction\000event= =3D0x8a\000\00000\000\000\000\000\000 */ +{ 126251 }, /* bp_l2_btb_correct\000branch\000L2 BTB Correction\000event= =3D0x8b\000\00000\000\000\000\000\000 */ +{ 126513 }, /* dispatch_blocked.any\000other\000Memory cluster signals to = block micro-op dispatch for any reason\000event=3D9,period=3D200000,umask= =3D0x20\000\00000\000\000\000\000\000 */ +{ 126646 }, /* eist_trans\000other\000Number of Enhanced Intel SpeedStep(R= ) Technology (EIST) transitions\000event=3D0x3a,period=3D200000\000\00000\0= 00\000\000\000\000 */ +{ 126313 }, /* l3_cache_rd\000cache\000L3 cache access, read\000event=3D0x= 40\000\00000\000\000\000\000Attributable Level 3 cache access, read\000 */ +{ 126411 }, /* segment_reg_loads.any\000other\000Number of segment registe= r loads\000event=3D6,period=3D200000,umask=3D0x80\000\00000\000\000\000\000= \000 */ }; static const struct compact_pmu_event pmu_events__test_soc_cpu_hisi_sccl_d= drc[] =3D { -{ 3280 }, /* uncore_hisi_ddrc.flux_wcmd\000uncore\000DDRC write commands\0= 00event=3D2\000\00000\000\000\000\000\000 */ +{ 126779 }, /* uncore_hisi_ddrc.flux_wcmd\000uncore\000DDRC write commands= \000event=3D2\000\00000\000\000\000\000\000 */ }; static const struct compact_pmu_event pmu_events__test_soc_cpu_hisi_sccl_l= 3c[] =3D { -{ 3642 }, /* uncore_hisi_l3c.rd_hit_cpipe\000uncore\000Total read hits\000= event=3D7\000\00000\000\000\000\000\000 */ +{ 127141 }, /* uncore_hisi_l3c.rd_hit_cpipe\000uncore\000Total read hits\0= 00event=3D7\000\00000\000\000\000\000\000 */ }; static const struct compact_pmu_event pmu_events__test_soc_cpu_uncore_cbox= [] =3D { -{ 3516 }, /* event-hyphen\000uncore\000UNC_CBO_HYPHEN\000event=3D0xe0\000\= 00000\000\000\000\000\000 */ -{ 3570 }, /* event-two-hyph\000uncore\000UNC_CBO_TWO_HYPH\000event=3D0xc0\= 000\00000\000\000\000\000\000 */ -{ 3362 }, /* unc_cbo_xsnp_response.miss_eviction\000uncore\000A cross-core= snoop resulted from L3 Eviction which misses in some processor core\000eve= nt=3D0x22,umask=3D0x81\000\00000\000\000\000\000\000 */ +{ 127015 }, /* event-hyphen\000uncore\000UNC_CBO_HYPHEN\000event=3D0xe0\00= 0\00000\000\000\000\000\000 */ +{ 127069 }, /* event-two-hyph\000uncore\000UNC_CBO_TWO_HYPH\000event=3D0xc= 0\000\00000\000\000\000\000\000 */ +{ 126861 }, /* unc_cbo_xsnp_response.miss_eviction\000uncore\000A cross-co= re snoop resulted from L3 Eviction which misses in some processor core\000e= vent=3D0x22,umask=3D0x81\000\00000\000\000\000\000\000 */ }; static const struct compact_pmu_event pmu_events__test_soc_cpu_uncore_imc[= ] =3D { -{ 3825 }, /* uncore_imc.cache_hits\000uncore\000Total cache hits\000event= =3D0x34\000\00000\000\000\000\000\000 */ +{ 127324 }, /* uncore_imc.cache_hits\000uncore\000Total cache hits\000even= t=3D0x34\000\00000\000\000\000\000\000 */ }; static const struct compact_pmu_event pmu_events__test_soc_cpu_uncore_imc_= free_running[] =3D { -{ 3734 }, /* uncore_imc_free_running.cache_miss\000uncore\000Total cache m= isses\000event=3D0x12\000\00000\000\000\000\000\000 */ +{ 127233 }, /* uncore_imc_free_running.cache_miss\000uncore\000Total cache= misses\000event=3D0x12\000\00000\000\000\000\000\000 */ =20 }; =20 @@ -167,51 +2634,51 @@ const struct pmu_table_entry pmu_events__test_soc_cp= u[] =3D { { .entries =3D pmu_events__test_soc_cpu_default_core, .num_entries =3D ARRAY_SIZE(pmu_events__test_soc_cpu_default_core), - .pmu_name =3D { 2677 /* default_core\000 */ }, + .pmu_name =3D { 0 /* default_core\000 */ }, }, { .entries =3D pmu_events__test_soc_cpu_hisi_sccl_ddrc, .num_entries =3D ARRAY_SIZE(pmu_events__test_soc_cpu_hisi_sccl_ddrc), - .pmu_name =3D { 3265 /* hisi_sccl,ddrc\000 */ }, + .pmu_name =3D { 126764 /* hisi_sccl,ddrc\000 */ }, }, { .entries =3D pmu_events__test_soc_cpu_hisi_sccl_l3c, .num_entries =3D ARRAY_SIZE(pmu_events__test_soc_cpu_hisi_sccl_l3c), - .pmu_name =3D { 3628 /* hisi_sccl,l3c\000 */ }, + .pmu_name =3D { 127127 /* hisi_sccl,l3c\000 */ }, }, { .entries =3D pmu_events__test_soc_cpu_uncore_cbox, .num_entries =3D ARRAY_SIZE(pmu_events__test_soc_cpu_uncore_cbox), - .pmu_name =3D { 3350 /* uncore_cbox\000 */ }, + .pmu_name =3D { 126849 /* uncore_cbox\000 */ }, }, { .entries =3D pmu_events__test_soc_cpu_uncore_imc, .num_entries =3D ARRAY_SIZE(pmu_events__test_soc_cpu_uncore_imc), - .pmu_name =3D { 3814 /* uncore_imc\000 */ }, + .pmu_name =3D { 127313 /* uncore_imc\000 */ }, }, { .entries =3D pmu_events__test_soc_cpu_uncore_imc_free_running, .num_entries =3D ARRAY_SIZE(pmu_events__test_soc_cpu_uncore_imc_free_= running), - .pmu_name =3D { 3710 /* uncore_imc_free_running\000 */ }, + .pmu_name =3D { 127209 /* uncore_imc_free_running\000 */ }, }, }; =20 static const struct compact_pmu_event pmu_metrics__test_soc_cpu_default_co= re[] =3D { -{ 4243 }, /* CPI\000\0001 / IPC\000\000\000\000\000\000\000\00000 */ -{ 4924 }, /* DCache_L2_All\000\000DCache_L2_All_Hits + DCache_L2_All_Miss\= 000\000\000\000\000\000\000\00000 */ -{ 4696 }, /* DCache_L2_All_Hits\000\000l2_rqsts.demand_data_rd_hit + l2_rq= sts.pf_hit + l2_rqsts.rfo_hit\000\000\000\000\000\000\000\00000 */ -{ 4790 }, /* DCache_L2_All_Miss\000\000max(l2_rqsts.all_demand_data_rd - l= 2_rqsts.demand_data_rd_hit, 0) + l2_rqsts.pf_miss + l2_rqsts.rfo_miss\000\0= 00\000\000\000\000\000\00000 */ -{ 4988 }, /* DCache_L2_Hits\000\000d_ratio(DCache_L2_All_Hits, DCache_L2_A= ll)\000\000\000\000\000\000\000\00000 */ -{ 5056 }, /* DCache_L2_Misses\000\000d_ratio(DCache_L2_All_Miss, DCache_L2= _All)\000\000\000\000\000\000\000\00000 */ -{ 4328 }, /* Frontend_Bound_SMT\000\000idq_uops_not_delivered.core / (4 * = (cpu_clk_unhalted.thread / 2 * (1 + cpu_clk_unhalted.one_thread_active / cp= u_clk_unhalted.ref_xclk)))\000\000\000\000\000\000\000\00000 */ -{ 4265 }, /* IPC\000group1\000inst_retired.any / cpu_clk_unhalted.thread\0= 00\000\000\000\000\000\000\00000 */ -{ 5190 }, /* L1D_Cache_Fill_BW\000\00064 * l1d.replacement / 1e9 / duratio= n_time\000\000\000\000\000\000\000\00000 */ -{ 5126 }, /* M1\000\000ipc + M2\000\000\000\000\000\000\000\00000 */ -{ 5148 }, /* M2\000\000ipc + M1\000\000\000\000\000\000\000\00000 */ -{ 5170 }, /* M3\000\0001 / M3\000\000\000\000\000\000\000\00000 */ -{ 4625 }, /* cache_miss_cycles\000group1\000dcache_miss_cpi + icache_miss_= cycles\000\000\000\000\000\000\000\00000 */ -{ 4494 }, /* dcache_miss_cpi\000\000l1d\\-loads\\-misses / inst_retired.an= y\000\000\000\000\000\000\000\00000 */ -{ 4558 }, /* icache_miss_cycles\000\000l1i\\-loads\\-misses / inst_retired= .any\000\000\000\000\000\000\000\00000 */ +{ 127742 }, /* CPI\000\0001 / IPC\000\000\000\000\000\000\000\00000 */ +{ 128423 }, /* DCache_L2_All\000\000DCache_L2_All_Hits + DCache_L2_All_Mis= s\000\000\000\000\000\000\000\00000 */ +{ 128195 }, /* DCache_L2_All_Hits\000\000l2_rqsts.demand_data_rd_hit + l2_= rqsts.pf_hit + l2_rqsts.rfo_hit\000\000\000\000\000\000\000\00000 */ +{ 128289 }, /* DCache_L2_All_Miss\000\000max(l2_rqsts.all_demand_data_rd -= l2_rqsts.demand_data_rd_hit, 0) + l2_rqsts.pf_miss + l2_rqsts.rfo_miss\000= \000\000\000\000\000\000\00000 */ +{ 128487 }, /* DCache_L2_Hits\000\000d_ratio(DCache_L2_All_Hits, DCache_L2= _All)\000\000\000\000\000\000\000\00000 */ +{ 128555 }, /* DCache_L2_Misses\000\000d_ratio(DCache_L2_All_Miss, DCache_= L2_All)\000\000\000\000\000\000\000\00000 */ +{ 127827 }, /* Frontend_Bound_SMT\000\000idq_uops_not_delivered.core / (4 = * (cpu_clk_unhalted.thread / 2 * (1 + cpu_clk_unhalted.one_thread_active / = cpu_clk_unhalted.ref_xclk)))\000\000\000\000\000\000\000\00000 */ +{ 127764 }, /* IPC\000group1\000inst_retired.any / cpu_clk_unhalted.thread= \000\000\000\000\000\000\000\00000 */ +{ 128689 }, /* L1D_Cache_Fill_BW\000\00064 * l1d.replacement / 1e9 / durat= ion_time\000\000\000\000\000\000\000\00000 */ +{ 128625 }, /* M1\000\000ipc + M2\000\000\000\000\000\000\000\00000 */ +{ 128647 }, /* M2\000\000ipc + M1\000\000\000\000\000\000\000\00000 */ +{ 128669 }, /* M3\000\0001 / M3\000\000\000\000\000\000\000\00000 */ +{ 128124 }, /* cache_miss_cycles\000group1\000dcache_miss_cpi + icache_mis= s_cycles\000\000\000\000\000\000\000\00000 */ +{ 127993 }, /* dcache_miss_cpi\000\000l1d\\-loads\\-misses / inst_retired.= any\000\000\000\000\000\000\000\00000 */ +{ 128057 }, /* icache_miss_cycles\000\000l1i\\-loads\\-misses / inst_retir= ed.any\000\000\000\000\000\000\000\00000 */ =20 }; =20 @@ -219,18 +2686,18 @@ const struct pmu_table_entry pmu_metrics__test_soc_c= pu[] =3D { { .entries =3D pmu_metrics__test_soc_cpu_default_core, .num_entries =3D ARRAY_SIZE(pmu_metrics__test_soc_cpu_default_core), - .pmu_name =3D { 2677 /* default_core\000 */ }, + .pmu_name =3D { 0 /* default_core\000 */ }, }, }; =20 static const struct compact_pmu_event pmu_events__test_soc_sys_uncore_sys_= ccn_pmu[] =3D { -{ 4004 }, /* sys_ccn_pmu.read_cycles\000uncore\000ccn read-cycles event\00= 0config=3D0x2c\0000x01\00000\000\000\000\000\000 */ +{ 127503 }, /* sys_ccn_pmu.read_cycles\000uncore\000ccn read-cycles event\= 000config=3D0x2c\0000x01\00000\000\000\000\000\000 */ }; static const struct compact_pmu_event pmu_events__test_soc_sys_uncore_sys_= cmn_pmu[] =3D { -{ 4100 }, /* sys_cmn_pmu.hnf_cache_miss\000uncore\000Counts total cache mi= sses in first lookup result (high priority)\000eventid=3D1,type=3D5\000(434= |436|43c|43a).*\00000\000\000\000\000\000 */ +{ 127599 }, /* sys_cmn_pmu.hnf_cache_miss\000uncore\000Counts total cache = misses in first lookup result (high priority)\000eventid=3D1,type=3D5\000(4= 34|436|43c|43a).*\00000\000\000\000\000\000 */ }; static const struct compact_pmu_event pmu_events__test_soc_sys_uncore_sys_= ddr_pmu[] =3D { -{ 3909 }, /* sys_ddr_pmu.write_cycles\000uncore\000ddr write-cycles event\= 000event=3D0x2b\000v8\00000\000\000\000\000\000 */ +{ 127408 }, /* sys_ddr_pmu.write_cycles\000uncore\000ddr write-cycles even= t\000event=3D0x2b\000v8\00000\000\000\000\000\000 */ =20 }; =20 @@ -238,17 +2705,17 @@ const struct pmu_table_entry pmu_events__test_soc_sy= s[] =3D { { .entries =3D pmu_events__test_soc_sys_uncore_sys_ccn_pmu, .num_entries =3D ARRAY_SIZE(pmu_events__test_soc_sys_uncore_sys_ccn_p= mu), - .pmu_name =3D { 3985 /* uncore_sys_ccn_pmu\000 */ }, + .pmu_name =3D { 127484 /* uncore_sys_ccn_pmu\000 */ }, }, { .entries =3D pmu_events__test_soc_sys_uncore_sys_cmn_pmu, .num_entries =3D ARRAY_SIZE(pmu_events__test_soc_sys_uncore_sys_cmn_p= mu), - .pmu_name =3D { 4081 /* uncore_sys_cmn_pmu\000 */ }, + .pmu_name =3D { 127580 /* uncore_sys_cmn_pmu\000 */ }, }, { .entries =3D pmu_events__test_soc_sys_uncore_sys_ddr_pmu, .num_entries =3D ARRAY_SIZE(pmu_events__test_soc_sys_uncore_sys_ddr_p= mu), - .pmu_name =3D { 3890 /* uncore_sys_ddr_pmu\000 */ }, + .pmu_name =3D { 127389 /* uncore_sys_ddr_pmu\000 */ }, }, }; =20 diff --git a/tools/perf/pmu-events/make_legacy_cache.py b/tools/perf/pmu-ev= ents/make_legacy_cache.py new file mode 100755 index 000000000000..28a1ff804f86 --- /dev/null +++ b/tools/perf/pmu-events/make_legacy_cache.py @@ -0,0 +1,129 @@ +#!/usr/bin/env python3 +# SPDX-License-Identifier: (LGPL-2.1 OR BSD-2-Clause) +import json + +hw_cache_id =3D [ + (0, # PERF_COUNT_HW_CACHE_L1D + ["L1-dcache", "l1-d", "l1d", "L1-data",], + [0, 1, 2,], # read, write, prefetch + "Level 1 data cache", + ), + (1, # PERF_COUNT_HW_CACHE_L1I + ["L1-icache", "l1-i", "l1i", "L1-instruction",], + [0, 2,], # read, prefetch + "Level 1 instruction cache", + ), + (2, # PERF_COUNT_HW_CACHE_LL + ["LLC", "L2"], + [0, 1, 2,], # read, write, prefetch + "Last level cache", + ), + (3, # PERF_COUNT_HW_CACHE_DTLB + ["dTLB", "d-tlb", "Data-TLB",], + [0, 1, 2,], # read, write, prefetch + "Data TLB", + ), + (4, # PERF_COUNT_HW_CACHE_ITLB + ["iTLB", "i-tlb", "Instruction-TLB",], + [0,], # read + "Instruction TLB", + ), + (5, # PERF_COUNT_HW_CACHE_BPU + ["branch", "branches", "bpu", "btb", "bpc",], + [0,], # read + "Branch prediction unit", + ), + (6, # PERF_COUNT_HW_CACHE_NODE + ["node",], + [0, 1, 2,], # read, write, prefetch + "Local memory", + ), +] + +hw_cache_op =3D [ + (0, # PERF_COUNT_HW_CACHE_OP_READ + ["load", "loads", "read",], + "read"), + (1, # PERF_COUNT_HW_CACHE_OP_WRITE + ["store", "stores", "write",], + "write"), + (2, # PERF_COUNT_HW_CACHE_OP_PREFETCH + ["prefetch", "prefetches", "speculative-read", "speculative-load"= ,], + "prefetch"), +] + +hw_cache_result =3D [ + (0, # PERF_COUNT_HW_CACHE_RESULT_ACCESS + ["refs", "Reference", "ops", "access",], + "accesses"), + (1, # PERF_COUNT_HW_CACHE_RESULT_MISS + ["misses", "miss",], + "misses"), +] + +events =3D [] +def add_event(name: str, + cache_id: int, cache_op: int, cache_result: int, + desc: str, + deprecated: bool) -> None: + # Avoid conflicts with PERF_TYPE_HARDWARE events which are higher prio= rity. + if name in ["branch-misses", "branches"]: + return + + # Tweak and deprecate L2 named events. + if name.startswith("L2"): + desc =3D desc.replace("Last level cache", "Level 2 (or higher) las= t level cache") + deprecated =3D True + + event =3D { + "EventName": name, + "BriefDescription": desc, + "LegacyCacheCode": f"0x{cache_id | (cache_op << 8) | (cache_result= << 16):06x}", + } + + # Deprecate events with the name starting L2 as it is actively + # confusing as on many machines it actually means the L3 cache. + if deprecated: + event["Deprecated"] =3D "1" + events.append(event) + +for (cache_id, names, ops, cache_desc) in hw_cache_id: + for name in names: + add_event(name, + cache_id, + 0, # PERF_COUNT_HW_CACHE_OP_READ + 0, # PERF_COUNT_HW_CACHE_RESULT_ACCESS + f"{cache_desc} read accesses.", + deprecated=3DTrue) + + for (op, op_names, op_desc) in hw_cache_op: + if op not in ops: + continue + for op_name in op_names: + deprecated =3D (names[0] !=3D name or op_names[1] !=3D op_= name) + add_event(f"{name}-{op_name}", + cache_id, + op, + 0, # PERF_COUNT_HW_CACHE_RESULT_ACCESS + f"{cache_desc} {op_desc} accesses.", + deprecated) + + for (result, result_names, result_desc) in hw_cache_resul= t: + for result_name in result_names: + deprecated =3D ((names[0] !=3D name or op_names[0]= !=3D op_name) or + (result =3D=3D 0) or (result_names[0= ] !=3D result_name)) + add_event(f"{name}-{op_name}-{result_name}", + cache_id, op, result, + f"{cache_desc} {op_desc} {result_desc}.", + deprecated) + + for (result, result_names, result_desc) in hw_cache_result: + for result_name in result_names: + add_event(f"{name}-{result_name}", + cache_id, + 0, # PERF_COUNT_HW_CACHE_OP_READ + result, + f"{cache_desc} read {result_desc}.", + deprecated=3DTrue) + +print(json.dumps(events, indent=3D2)) --=20 2.51.0.534.gc79095c0ca-goog From nobody Thu Oct 2 03:27:35 2025 Received: from mail-pj1-f74.google.com (mail-pj1-f74.google.com [209.85.216.74]) (using TLSv1.2 with cipher ECDHE-RSA-AES128-GCM-SHA256 (128/128 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id F09A32765D0 for ; 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Mon, 22 Sep 2025 21:19:19 -0700 (PDT) Date: Mon, 22 Sep 2025 21:18:33 -0700 In-Reply-To: <20250923041844.400164-1-irogers@google.com> Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: Mime-Version: 1.0 References: <20250923041844.400164-1-irogers@google.com> X-Mailer: git-send-email 2.51.0.534.gc79095c0ca-goog Message-ID: <20250923041844.400164-15-irogers@google.com> Subject: [PATCH v5 14/25] perf print-events: Remove print_hwcache_events From: Ian Rogers To: Peter Zijlstra , Ingo Molnar , Arnaldo Carvalho de Melo , Namhyung Kim , Mark Rutland , Alexander Shishkin , Jiri Olsa , Ian Rogers , Adrian Hunter , Kan Liang , James Clark , Xu Yang , Thomas Falcon , Andi Kleen , linux-kernel@vger.kernel.org, linux-perf-users@vger.kernel.org, bpf@vger.kernel.org, Atish Patra , Beeman Strong , Leo Yan , Vince Weaver Cc: Thomas Richter Content-Transfer-Encoding: quoted-printable Content-Type: text/plain; charset="utf-8" Now legacy cache events are in json there's no need for a specific printing routine. To support the previous filtered version use an event glob of "legacy cache" which matches the topic of the json events. Tested-by: Thomas Richter Signed-off-by: Ian Rogers --- tools/perf/builtin-list.c | 16 +++++++--- tools/perf/util/print-events.c | 55 ---------------------------------- tools/perf/util/print-events.h | 1 - 3 files changed, 12 insertions(+), 60 deletions(-) diff --git a/tools/perf/builtin-list.c b/tools/perf/builtin-list.c index caf42276bd0f..b6720ef3adf6 100644 --- a/tools/perf/builtin-list.c +++ b/tools/perf/builtin-list.c @@ -652,9 +652,18 @@ int cmd_list(int argc, const char **argv) } default_ps.pmu_glob =3D old_pmu_glob; } else if (strcmp(argv[i], "cache") =3D=3D 0 || - strcmp(argv[i], "hwcache") =3D=3D 0) - print_hwcache_events(&print_cb, ps); - else if (strcmp(argv[i], "pmu") =3D=3D 0) { + strcmp(argv[i], "hwcache") =3D=3D 0) { + char *old_event_glob =3D default_ps.event_glob; + + default_ps.event_glob =3D strdup("legacy cache"); + if (!default_ps.event_glob) { + ret =3D -1; + goto out; + } + perf_pmus__print_pmu_events(&print_cb, ps); + zfree(&default_ps.event_glob); + default_ps.event_glob =3D old_event_glob; + } else if (strcmp(argv[i], "pmu") =3D=3D 0) { default_ps.exclude_abi =3D true; perf_pmus__print_pmu_events(&print_cb, ps); default_ps.exclude_abi =3D false; @@ -707,7 +716,6 @@ int cmd_list(int argc, const char **argv) default_ps.event_glob =3D s; print_symbol_events(&print_cb, ps, PERF_TYPE_HARDWARE, event_symbols_hw, PERF_COUNT_HW_MAX); - print_hwcache_events(&print_cb, ps); perf_pmus__print_pmu_events(&print_cb, ps); print_sdt_events(&print_cb, ps); default_ps.metrics =3D true; diff --git a/tools/perf/util/print-events.c b/tools/perf/util/print-events.c index 4153124a9948..91a5d9c7882b 100644 --- a/tools/perf/util/print-events.c +++ b/tools/perf/util/print-events.c @@ -186,59 +186,6 @@ bool is_event_supported(u8 type, u64 config) return ret; } =20 -int print_hwcache_events(const struct print_callbacks *print_cb, void *pri= nt_state) -{ - struct perf_pmu *pmu =3D NULL; - const char *event_type_descriptor =3D event_type_descriptors[PERF_TYPE_HW= _CACHE]; - - /* - * Only print core PMUs, skipping uncore for performance and - * PERF_TYPE_SOFTWARE that can succeed in opening legacy cache evenst. - */ - while ((pmu =3D perf_pmus__scan_core(pmu)) !=3D NULL) { - if (pmu->is_uncore || pmu->type =3D=3D PERF_TYPE_SOFTWARE) - continue; - - for (int type =3D 0; type < PERF_COUNT_HW_CACHE_MAX; type++) { - for (int op =3D 0; op < PERF_COUNT_HW_CACHE_OP_MAX; op++) { - /* skip invalid cache type */ - if (!evsel__is_cache_op_valid(type, op)) - continue; - - for (int res =3D 0; res < PERF_COUNT_HW_CACHE_RESULT_MAX; res++) { - char name[64]; - char alias_name[128]; - __u64 config; - int ret; - - __evsel__hw_cache_type_op_res_name(type, op, res, - name, sizeof(name)); - - ret =3D parse_events__decode_legacy_cache(name, pmu->type, - &config); - if (ret || !is_event_supported(PERF_TYPE_HW_CACHE, config)) - continue; - snprintf(alias_name, sizeof(alias_name), "%s/%s/", - pmu->name, name); - print_cb->print_event(print_state, - "cache", - pmu->name, - pmu->type, - name, - alias_name, - /*scale_unit=3D*/NULL, - /*deprecated=3D*/false, - event_type_descriptor, - /*desc=3D*/NULL, - /*long_desc=3D*/NULL, - /*encoding_desc=3D*/NULL); - } - } - } - } - return 0; -} - void print_symbol_events(const struct print_callbacks *print_cb, void *pri= nt_state, unsigned int type, const struct event_symbol *syms, unsigned int max) @@ -434,8 +381,6 @@ void print_events(const struct print_callbacks *print_c= b, void *print_state) print_symbol_events(print_cb, print_state, PERF_TYPE_HARDWARE, event_symbols_hw, PERF_COUNT_HW_MAX); =20 - print_hwcache_events(print_cb, print_state); - perf_pmus__print_pmu_events(print_cb, print_state); =20 print_cb->print_event(print_state, diff --git a/tools/perf/util/print-events.h b/tools/perf/util/print-events.h index d6ba384f0c66..44e5dbd91400 100644 --- a/tools/perf/util/print-events.h +++ b/tools/perf/util/print-events.h @@ -32,7 +32,6 @@ struct print_callbacks { =20 /** Print all events, the default when no options are specified. */ void print_events(const struct print_callbacks *print_cb, void *print_stat= e); -int print_hwcache_events(const struct print_callbacks *print_cb, void *pri= nt_state); void print_sdt_events(const struct print_callbacks *print_cb, void *print_= state); void print_symbol_events(const struct print_callbacks *print_cb, void *pri= nt_state, unsigned int type, const struct event_symbol *syms, --=20 2.51.0.534.gc79095c0ca-goog From nobody Thu Oct 2 03:27:35 2025 Received: from mail-pl1-f201.google.com (mail-pl1-f201.google.com [209.85.214.201]) (using TLSv1.2 with cipher ECDHE-RSA-AES128-GCM-SHA256 (128/128 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id E2AC829B8E5 for ; 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Mon, 22 Sep 2025 21:19:21 -0700 (PDT) Date: Mon, 22 Sep 2025 21:18:34 -0700 In-Reply-To: <20250923041844.400164-1-irogers@google.com> Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: Mime-Version: 1.0 References: <20250923041844.400164-1-irogers@google.com> X-Mailer: git-send-email 2.51.0.534.gc79095c0ca-goog Message-ID: <20250923041844.400164-16-irogers@google.com> Subject: [PATCH v5 15/25] perf print-events: Remove print_symbol_events From: Ian Rogers To: Peter Zijlstra , Ingo Molnar , Arnaldo Carvalho de Melo , Namhyung Kim , Mark Rutland , Alexander Shishkin , Jiri Olsa , Ian Rogers , Adrian Hunter , Kan Liang , James Clark , Xu Yang , Thomas Falcon , Andi Kleen , linux-kernel@vger.kernel.org, linux-perf-users@vger.kernel.org, bpf@vger.kernel.org, Atish Patra , Beeman Strong , Leo Yan , Vince Weaver Cc: Thomas Richter Content-Transfer-Encoding: quoted-printable Content-Type: text/plain; charset="utf-8" Now legacy hardware events are in json there's no need for a specific printing routine that previously served for both hardware and software events. The associated event_symbols_hw is also removed. To support the previous filtered version use an event glob of "legacy hardware" which matches the topic of the json events. Tested-by: Thomas Richter Signed-off-by: Ian Rogers --- tools/perf/builtin-list.c | 18 +++++++---- tools/perf/util/parse-events.c | 43 ------------------------- tools/perf/util/parse-events.h | 1 - tools/perf/util/print-events.c | 57 ---------------------------------- tools/perf/util/print-events.h | 3 -- 5 files changed, 12 insertions(+), 110 deletions(-) diff --git a/tools/perf/builtin-list.c b/tools/perf/builtin-list.c index b6720ef3adf6..16400366f827 100644 --- a/tools/perf/builtin-list.c +++ b/tools/perf/builtin-list.c @@ -633,10 +633,18 @@ int cmd_list(int argc, const char **argv) zfree(&default_ps.pmu_glob); default_ps.pmu_glob =3D old_pmu_glob; } else if (strcmp(argv[i], "hw") =3D=3D 0 || - strcmp(argv[i], "hardware") =3D=3D 0) - print_symbol_events(&print_cb, ps, PERF_TYPE_HARDWARE, - event_symbols_hw, PERF_COUNT_HW_MAX); - else if (strcmp(argv[i], "sw") =3D=3D 0 || + strcmp(argv[i], "hardware") =3D=3D 0) { + char *old_event_glob =3D default_ps.event_glob; + + default_ps.event_glob =3D strdup("legacy hardware"); + if (!default_ps.event_glob) { + ret =3D -1; + goto out; + } + perf_pmus__print_pmu_events(&print_cb, ps); + zfree(&default_ps.event_glob); + default_ps.event_glob =3D old_event_glob; + } else if (strcmp(argv[i], "sw") =3D=3D 0 || strcmp(argv[i], "software") =3D=3D 0) { char *old_pmu_glob =3D default_ps.pmu_glob; static const char * const sw_globs[] =3D { "software", "tool" }; @@ -714,8 +722,6 @@ int cmd_list(int argc, const char **argv) continue; } default_ps.event_glob =3D s; - print_symbol_events(&print_cb, ps, PERF_TYPE_HARDWARE, - event_symbols_hw, PERF_COUNT_HW_MAX); perf_pmus__print_pmu_events(&print_cb, ps); print_sdt_events(&print_cb, ps); default_ps.metrics =3D true; diff --git a/tools/perf/util/parse-events.c b/tools/perf/util/parse-events.c index f9c52eadac46..8d3eda3badfd 100644 --- a/tools/perf/util/parse-events.c +++ b/tools/perf/util/parse-events.c @@ -42,49 +42,6 @@ static int parse_events_terms__copy(const struct parse_e= vents_terms *src, struct parse_events_terms *dest); static int parse_events_terms__to_strbuf(const struct parse_events_terms *= terms, struct strbuf *sb); =20 -const struct event_symbol event_symbols_hw[PERF_COUNT_HW_MAX] =3D { - [PERF_COUNT_HW_CPU_CYCLES] =3D { - .symbol =3D "cpu-cycles", - .alias =3D "cycles", - }, - [PERF_COUNT_HW_INSTRUCTIONS] =3D { - .symbol =3D "instructions", - .alias =3D "", - }, - [PERF_COUNT_HW_CACHE_REFERENCES] =3D { - .symbol =3D "cache-references", - .alias =3D "", - }, - [PERF_COUNT_HW_CACHE_MISSES] =3D { - .symbol =3D "cache-misses", - .alias =3D "", - }, - [PERF_COUNT_HW_BRANCH_INSTRUCTIONS] =3D { - .symbol =3D "branch-instructions", - .alias =3D "branches", - }, - [PERF_COUNT_HW_BRANCH_MISSES] =3D { - .symbol =3D "branch-misses", - .alias =3D "", - }, - [PERF_COUNT_HW_BUS_CYCLES] =3D { - .symbol =3D "bus-cycles", - .alias =3D "", - }, - [PERF_COUNT_HW_STALLED_CYCLES_FRONTEND] =3D { - .symbol =3D "stalled-cycles-frontend", - .alias =3D "idle-cycles-frontend", - }, - [PERF_COUNT_HW_STALLED_CYCLES_BACKEND] =3D { - .symbol =3D "stalled-cycles-backend", - .alias =3D "idle-cycles-backend", - }, - [PERF_COUNT_HW_REF_CPU_CYCLES] =3D { - .symbol =3D "ref-cycles", - .alias =3D "", - }, -}; - static const char *const event_types[] =3D { [PERF_TYPE_HARDWARE] =3D "hardware", [PERF_TYPE_SOFTWARE] =3D "software", diff --git a/tools/perf/util/parse-events.h b/tools/perf/util/parse-events.h index 0db5e223e10d..23a42395d516 100644 --- a/tools/perf/util/parse-events.h +++ b/tools/perf/util/parse-events.h @@ -265,7 +265,6 @@ struct event_symbol { const char *symbol; const char *alias; }; -extern const struct event_symbol event_symbols_hw[]; =20 char *parse_events_formats_error_string(char *additional_terms); =20 diff --git a/tools/perf/util/print-events.c b/tools/perf/util/print-events.c index 91a5d9c7882b..8f3ed83853a9 100644 --- a/tools/perf/util/print-events.c +++ b/tools/perf/util/print-events.c @@ -186,60 +186,6 @@ bool is_event_supported(u8 type, u64 config) return ret; } =20 -void print_symbol_events(const struct print_callbacks *print_cb, void *pri= nt_state, - unsigned int type, const struct event_symbol *syms, - unsigned int max) -{ - struct strlist *evt_name_list =3D strlist__new(NULL, NULL); - struct str_node *nd; - - if (!evt_name_list) { - pr_debug("Failed to allocate new strlist for symbol events\n"); - return; - } - for (unsigned int i =3D 0; i < max; i++) { - /* - * New attr.config still not supported here, the latest - * example was PERF_COUNT_SW_CGROUP_SWITCHES - */ - if (syms[i].symbol =3D=3D NULL) - continue; - - if (!is_event_supported(type, i)) - continue; - - if (strlen(syms[i].alias)) { - char name[MAX_NAME_LEN]; - - snprintf(name, MAX_NAME_LEN, "%s OR %s", syms[i].symbol, syms[i].alias); - strlist__add(evt_name_list, name); - } else - strlist__add(evt_name_list, syms[i].symbol); - } - - strlist__for_each_entry(nd, evt_name_list) { - char *alias =3D strstr(nd->s, " OR "); - - if (alias) { - *alias =3D '\0'; - alias +=3D 4; - } - print_cb->print_event(print_state, - /*topic=3D*/NULL, - /*pmu_name=3D*/NULL, - type, - nd->s, - alias, - /*scale_unit=3D*/NULL, - /*deprecated=3D*/false, - event_type_descriptors[type], - /*desc=3D*/NULL, - /*long_desc=3D*/NULL, - /*encoding_desc=3D*/NULL); - } - strlist__delete(evt_name_list); -} - /** struct mep - RB-tree node for building printing information. */ struct mep { /** nd - RB-tree element. */ @@ -378,9 +324,6 @@ void metricgroup__print(const struct print_callbacks *p= rint_cb, void *print_stat */ void print_events(const struct print_callbacks *print_cb, void *print_stat= e) { - print_symbol_events(print_cb, print_state, PERF_TYPE_HARDWARE, - event_symbols_hw, PERF_COUNT_HW_MAX); - perf_pmus__print_pmu_events(print_cb, print_state); =20 print_cb->print_event(print_state, diff --git a/tools/perf/util/print-events.h b/tools/perf/util/print-events.h index 44e5dbd91400..eabba5d4a1fd 100644 --- a/tools/perf/util/print-events.h +++ b/tools/perf/util/print-events.h @@ -33,9 +33,6 @@ struct print_callbacks { /** Print all events, the default when no options are specified. */ void print_events(const struct print_callbacks *print_cb, void *print_stat= e); void print_sdt_events(const struct print_callbacks *print_cb, void *print_= state); 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AJvYcCUt8ipoVUKNLPuQzhCJLagGnELKpaHZL66EHYrA+/EAPEyFOT5Mqgg7CIhWba7RdVOVNLvn7azdqATjQV4=@vger.kernel.org X-Gm-Message-State: AOJu0YzBNA9qVqJPsaRtt0DyrlxDlJGJFR6zMQ6up81YVUSvQt35KZi3 D+0/tqRMU4MoZdOgCNmcP7OUR0gEYDaurVmf4wUcvxB16YIJYwPGIjBWiaNkGiamg5h/7FnSkxV HX60zB1OMlg== X-Google-Smtp-Source: AGHT+IFqC4Xqhf8j8Z8yTwJ7aTBXIAhTFgDUx5eO3GDl+P0M/OUTg7eLCb/CU6J49xb2WKVRnaifUqZtoZQv X-Received: from pfwp40.prod.google.com ([2002:a05:6a00:26e8:b0:77f:24f4:40f7]) (user=irogers job=prod-delivery.src-stubby-dispatcher) by 2002:a05:6a00:9298:b0:77f:210c:75c9 with SMTP id d2e1a72fcca58-77f53b0fe3cmr1560612b3a.21.1758601163604; Mon, 22 Sep 2025 21:19:23 -0700 (PDT) Date: Mon, 22 Sep 2025 21:18:35 -0700 In-Reply-To: <20250923041844.400164-1-irogers@google.com> Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: Mime-Version: 1.0 References: <20250923041844.400164-1-irogers@google.com> X-Mailer: git-send-email 2.51.0.534.gc79095c0ca-goog Message-ID: <20250923041844.400164-17-irogers@google.com> Subject: [PATCH v5 16/25] perf parse-events: Remove hard coded legacy hardware and cache parsing From: Ian Rogers To: Peter Zijlstra , Ingo Molnar , Arnaldo Carvalho de Melo , Namhyung Kim , Mark Rutland , Alexander Shishkin , Jiri Olsa , Ian Rogers , Adrian Hunter , Kan Liang , James Clark , Xu Yang , Thomas Falcon , Andi Kleen , linux-kernel@vger.kernel.org, linux-perf-users@vger.kernel.org, bpf@vger.kernel.org, Atish Patra , Beeman Strong , Leo Yan , Vince Weaver Cc: Thomas Richter Content-Transfer-Encoding: quoted-printable Content-Type: text/plain; charset="utf-8" Now that legacy hardware and cache events are in json, having the lexer match the specific event is no longer necessary and generic PMU parsing can take place. Because of this remove the specific term parsing, event adding, and passing of alternate_hw_config which was now always PERF_COUNT_HW_MAX. This mirrors a similar change for software events in commit 6e9fa4131abb ("perf parse-events: Remove non-json software events"). With no hard coded legacy hardware or cache events the wild card, case insensitivity, etc. is consistent for events. This does, however, mean events like cycles will wild card against all PMUs. A change does the same was originally posted and merged from: https://lore.kernel.org/r/20240416061533.921723-10-irogers@google.com and reverted by Linus in commit 4f1b067359ac ("Revert "perf parse-events: Prefer sysfs/JSON hardware events over legacy"") due to his dislike for the cycles behavior on ARM. Earlier patches in this series make perf record event opening failures non-fatal and hide the cycles event's failure to open on ARM in perf record, so it is expected the behavior will now be transparent in perf record. perf stat with a cycles event will wildcard open the event on all PMUs. The change to support legacy events with PMUs was done to clean up Intel's hybrid PMU implementation. Having sysfs/json events with increased priority to legacy was requested by Mark Rutland to fix Apple-M PMU issues wrt broken legacy events on that PMU. It was requested that RISC-V be able to add events to the perf tool json so the PMU driver didn't need to map legacy events to config encodings: https://lore.kernel.org/lkml/20240217005738.3744121-1-atishp@rivosinc.com/ A previous series of patches decreasing legacy hardware event priorities was posted in: https://lore.kernel.org/lkml/20250416045117.876775-1-irogers@google.com/ Namhyung Kim mentioned that hardware and software events can be implemented similarly: https://lore.kernel.org/lkml/aIJmJns2lopxf3EK@google.com/ Tested-by: Thomas Richter Signed-off-by: Ian Rogers --- tools/perf/util/parse-events.c | 190 ++------------------------------- tools/perf/util/parse-events.h | 14 +-- tools/perf/util/parse-events.l | 52 --------- tools/perf/util/parse-events.y | 114 +------------------- tools/perf/util/pmu.c | 9 +- 5 files changed, 17 insertions(+), 362 deletions(-) diff --git a/tools/perf/util/parse-events.c b/tools/perf/util/parse-events.c index 8d3eda3badfd..05268248df77 100644 --- a/tools/perf/util/parse-events.c +++ b/tools/perf/util/parse-events.c @@ -429,110 +429,7 @@ bool parse_events__filter_pmu(const struct parse_even= ts_state *parse_state, static int parse_events_add_pmu(struct parse_events_state *parse_state, struct list_head *list, struct perf_pmu *pmu, const struct parse_events_terms *const_parsed_terms, - struct evsel *first_wildcard_match, u64 alternate_hw_config); - -int parse_events_add_cache(struct list_head *list, int *idx, const char *n= ame, - struct parse_events_state *parse_state, - struct parse_events_terms *parsed_terms, - void *loc_) -{ - YYLTYPE *loc =3D loc_; - struct perf_pmu *pmu =3D NULL; - bool found_supported =3D false; - const char *config_name =3D get_config_name(parsed_terms); - const char *metric_id =3D get_config_metric_id(parsed_terms); - struct perf_cpu_map *cpus =3D get_config_cpu(parsed_terms, parse_state->f= ake_pmu); - int ret =3D 0; - struct evsel *first_wildcard_match =3D NULL; - - while ((pmu =3D perf_pmus__scan_for_event(pmu, name)) !=3D NULL) { - LIST_HEAD(config_terms); - struct perf_event_attr attr; - - if (parse_events__filter_pmu(parse_state, pmu)) - continue; - - if (perf_pmu__have_event(pmu, name)) { - /* - * The PMU has the event so add as not a legacy cache - * event. - */ - struct parse_events_terms temp_terms; - struct parse_events_term *term; - char *config =3D strdup(name); - - if (!config) - goto out_err; - - parse_events_terms__init(&temp_terms); - if (!parsed_terms) - parsed_terms =3D &temp_terms; - - if (parse_events_term__num(&term, - PARSE_EVENTS__TERM_TYPE_USER, - config, /*num=3D*/1, /*novalue=3D*/true, - loc, /*loc_val=3D*/NULL) < 0) { - zfree(&config); - goto out_err; - } - list_add(&term->list, &parsed_terms->terms); - - ret =3D parse_events_add_pmu(parse_state, list, pmu, - parsed_terms, - first_wildcard_match, - /*alternate_hw_config=3D*/PERF_COUNT_HW_MAX); - list_del_init(&term->list); - parse_events_term__delete(term); - parse_events_terms__exit(&temp_terms); - if (ret) - goto out_err; - found_supported =3D true; - if (first_wildcard_match =3D=3D NULL) - first_wildcard_match =3D - container_of(list->prev, struct evsel, core.node); - continue; - } - - if (!pmu->is_core) { - /* Legacy cache events are only supported by core PMUs. */ - continue; - } - - memset(&attr, 0, sizeof(attr)); - attr.type =3D PERF_TYPE_HW_CACHE; - - ret =3D parse_events__decode_legacy_cache(name, pmu->type, &attr.config); - if (ret) - return ret; - - found_supported =3D true; - - if (parsed_terms) { - if (config_attr(&attr, parsed_terms, parse_state, config_term_common)) { - ret =3D -EINVAL; - goto out_err; - } - if (get_config_terms(parsed_terms, &config_terms)) { - ret =3D -ENOMEM; - goto out_err; - } - } - - if (__add_event(list, idx, &attr, /*init_attr*/true, config_name ?: name, - metric_id, pmu, &config_terms, first_wildcard_match, - cpus, /*alternate_hw_config=3D*/PERF_COUNT_HW_MAX) =3D=3D NULL) - ret =3D -ENOMEM; - - if (first_wildcard_match =3D=3D NULL) - first_wildcard_match =3D container_of(list->prev, struct evsel, core.no= de); - free_config_terms(&config_terms); - if (ret) - goto out_err; - } -out_err: - perf_cpu_map__put(cpus); - return found_supported ? 0 : -EINVAL; -} + struct evsel *first_wildcard_match); =20 static void tracepoint_error(struct parse_events_error *e, int err, const char *sys, const char *name, int column) @@ -823,8 +720,6 @@ const char *parse_events__term_type_str(enum parse_even= ts__term_type term_type) [PARSE_EVENTS__TERM_TYPE_AUX_SAMPLE_SIZE] =3D "aux-sample-size", [PARSE_EVENTS__TERM_TYPE_METRIC_ID] =3D "metric-id", [PARSE_EVENTS__TERM_TYPE_RAW] =3D "raw", - [PARSE_EVENTS__TERM_TYPE_LEGACY_CACHE] =3D "legacy-cache", - [PARSE_EVENTS__TERM_TYPE_HARDWARE] =3D "hardware", [PARSE_EVENTS__TERM_TYPE_LEGACY_HARDWARE_CONFIG] =3D "legacy-hardware-co= nfig", [PARSE_EVENTS__TERM_TYPE_LEGACY_CACHE_CONFIG] =3D "legacy-cache-config", [PARSE_EVENTS__TERM_TYPE_CPU] =3D "cpu", @@ -876,8 +771,6 @@ config_term_avail(enum parse_events__term_type term_typ= e, struct parse_events_er case PARSE_EVENTS__TERM_TYPE_AUX_ACTION: case PARSE_EVENTS__TERM_TYPE_AUX_SAMPLE_SIZE: case PARSE_EVENTS__TERM_TYPE_RAW: - case PARSE_EVENTS__TERM_TYPE_LEGACY_CACHE: - case PARSE_EVENTS__TERM_TYPE_HARDWARE: case PARSE_EVENTS__TERM_TYPE_LEGACY_HARDWARE_CONFIG: case PARSE_EVENTS__TERM_TYPE_LEGACY_CACHE_CONFIG: default: @@ -1035,8 +928,6 @@ do { \ } case PARSE_EVENTS__TERM_TYPE_DRV_CFG: case PARSE_EVENTS__TERM_TYPE_USER: - case PARSE_EVENTS__TERM_TYPE_LEGACY_CACHE: - case PARSE_EVENTS__TERM_TYPE_HARDWARE: case PARSE_EVENTS__TERM_TYPE_LEGACY_HARDWARE_CONFIG: case PARSE_EVENTS__TERM_TYPE_LEGACY_CACHE_CONFIG: default: @@ -1123,59 +1014,6 @@ static int config_term_pmu(struct perf_event_attr *a= ttr, attr->type =3D PERF_TYPE_HW_CACHE; return 0; } - if (term->type_term =3D=3D PARSE_EVENTS__TERM_TYPE_LEGACY_CACHE) { - struct perf_pmu *pmu =3D perf_pmus__find_by_type(attr->type); - - if (!pmu) { - char *err_str; - - if (asprintf(&err_str, "Failed to find PMU for type %d", attr->type) >= =3D 0) - parse_events_error__handle(parse_state->error, term->err_term, - err_str, /*help=3D*/NULL); - return -EINVAL; - } - /* - * Rewrite the PMU event to a legacy cache one unless the PMU - * doesn't support legacy cache events or the event is present - * within the PMU. - */ - if (perf_pmu__supports_legacy_cache(pmu) && - !perf_pmu__have_event(pmu, term->config)) { - attr->type =3D PERF_TYPE_HW_CACHE; - return parse_events__decode_legacy_cache(term->config, pmu->type, - &attr->config); - } else { - term->type_term =3D PARSE_EVENTS__TERM_TYPE_USER; - term->no_value =3D true; - } - } - if (term->type_term =3D=3D PARSE_EVENTS__TERM_TYPE_HARDWARE) { - struct perf_pmu *pmu =3D perf_pmus__find_by_type(attr->type); - - if (!pmu) { - char *err_str; - - if (asprintf(&err_str, "Failed to find PMU for type %d", attr->type) >= =3D 0) - parse_events_error__handle(parse_state->error, term->err_term, - err_str, /*help=3D*/NULL); - return -EINVAL; - } - /* - * If the PMU has a sysfs or json event prefer it over - * legacy. ARM requires this. - */ - if (perf_pmu__have_event(pmu, term->config)) { - term->type_term =3D PARSE_EVENTS__TERM_TYPE_USER; - term->no_value =3D true; - term->alternate_hw_config =3D true; - } else { - attr->type =3D PERF_TYPE_HARDWARE; - attr->config =3D term->val.num; - if (perf_pmus__supports_extended_type()) - attr->config |=3D (__u64)pmu->type << PERF_PMU_TYPE_SHIFT; - } - return 0; - } if (term->type_term =3D=3D PARSE_EVENTS__TERM_TYPE_USER || term->type_term =3D=3D PARSE_EVENTS__TERM_TYPE_DRV_CFG) { /* @@ -1220,8 +1058,6 @@ static int config_term_tracepoint(struct perf_event_a= ttr *attr, case PARSE_EVENTS__TERM_TYPE_PERCORE: case PARSE_EVENTS__TERM_TYPE_METRIC_ID: case PARSE_EVENTS__TERM_TYPE_RAW: - case PARSE_EVENTS__TERM_TYPE_LEGACY_CACHE: - case PARSE_EVENTS__TERM_TYPE_HARDWARE: case PARSE_EVENTS__TERM_TYPE_CPU: default: parse_events_error__handle(parse_state->error, term->err_term, @@ -1355,8 +1191,6 @@ do { \ case PARSE_EVENTS__TERM_TYPE_NAME: case PARSE_EVENTS__TERM_TYPE_METRIC_ID: case PARSE_EVENTS__TERM_TYPE_RAW: - case PARSE_EVENTS__TERM_TYPE_LEGACY_CACHE: - case PARSE_EVENTS__TERM_TYPE_HARDWARE: case PARSE_EVENTS__TERM_TYPE_CPU: default: break; @@ -1412,8 +1246,6 @@ static int get_config_chgs(struct perf_pmu *pmu, stru= ct parse_events_terms *head case PARSE_EVENTS__TERM_TYPE_AUX_SAMPLE_SIZE: case PARSE_EVENTS__TERM_TYPE_METRIC_ID: case PARSE_EVENTS__TERM_TYPE_RAW: - case PARSE_EVENTS__TERM_TYPE_LEGACY_CACHE: - case PARSE_EVENTS__TERM_TYPE_HARDWARE: case PARSE_EVENTS__TERM_TYPE_CPU: default: break; @@ -1537,8 +1369,9 @@ static bool config_term_percore(struct list_head *con= fig_terms) static int parse_events_add_pmu(struct parse_events_state *parse_state, struct list_head *list, struct perf_pmu *pmu, const struct parse_events_terms *const_parsed_terms, - struct evsel *first_wildcard_match, u64 alternate_hw_config) + struct evsel *first_wildcard_match) { + u64 alternate_hw_config =3D PERF_COUNT_HW_MAX; struct perf_event_attr attr; struct perf_pmu_info info; struct evsel *evsel; @@ -1671,7 +1504,7 @@ static int parse_events_add_pmu(struct parse_events_s= tate *parse_state, } =20 int parse_events_multi_pmu_add(struct parse_events_state *parse_state, - const char *event_name, u64 hw_config, + const char *event_name, const struct parse_events_terms *const_parsed_terms, struct list_head **listp, void *loc_) { @@ -1723,7 +1556,7 @@ int parse_events_multi_pmu_add(struct parse_events_st= ate *parse_state, continue; =20 if (!parse_events_add_pmu(parse_state, list, pmu, - &parsed_terms, first_wildcard_match, hw_config)) { + &parsed_terms, first_wildcard_match)) { struct strbuf sb; =20 strbuf_init(&sb, /*hint=3D*/ 0); @@ -1738,7 +1571,7 @@ int parse_events_multi_pmu_add(struct parse_events_st= ate *parse_state, =20 if (parse_state->fake_pmu) { if (!parse_events_add_pmu(parse_state, list, perf_pmus__fake_pmu(), &par= sed_terms, - first_wildcard_match, hw_config)) { + first_wildcard_match)) { struct strbuf sb; =20 strbuf_init(&sb, /*hint=3D*/ 0); @@ -1780,15 +1613,13 @@ int parse_events_multi_pmu_add_or_add_pmu(struct pa= rse_events_state *parse_state /* Attempt to add to list assuming event_or_pmu is a PMU name. */ pmu =3D perf_pmus__find(event_or_pmu); if (pmu && !parse_events_add_pmu(parse_state, *listp, pmu, const_parsed_t= erms, - first_wildcard_match, - /*alternate_hw_config=3D*/PERF_COUNT_HW_MAX)) + first_wildcard_match)) return 0; =20 if (parse_state->fake_pmu) { if (!parse_events_add_pmu(parse_state, *listp, perf_pmus__fake_pmu(), const_parsed_terms, - first_wildcard_match, - /*alternate_hw_config=3D*/PERF_COUNT_HW_MAX)) + first_wildcard_match)) return 0; } =20 @@ -1801,8 +1632,7 @@ int parse_events_multi_pmu_add_or_add_pmu(struct pars= e_events_state *parse_state =20 if (!parse_events_add_pmu(parse_state, *listp, pmu, const_parsed_terms, - first_wildcard_match, - /*alternate_hw_config=3D*/PERF_COUNT_HW_MAX)) { + first_wildcard_match)) { ok++; parse_state->wild_card_pmus =3D true; } @@ -1816,7 +1646,7 @@ int parse_events_multi_pmu_add_or_add_pmu(struct pars= e_events_state *parse_state =20 /* Failure to add, assume event_or_pmu is an event name. */ zfree(listp); - if (!parse_events_multi_pmu_add(parse_state, event_or_pmu, PERF_COUNT_HW_= MAX, + if (!parse_events_multi_pmu_add(parse_state, event_or_pmu, const_parsed_terms, listp, loc)) return 0; =20 diff --git a/tools/perf/util/parse-events.h b/tools/perf/util/parse-events.h index 23a42395d516..7f0a6e30e342 100644 --- a/tools/perf/util/parse-events.h +++ b/tools/perf/util/parse-events.h @@ -79,8 +79,6 @@ enum parse_events__term_type { PARSE_EVENTS__TERM_TYPE_AUX_SAMPLE_SIZE, PARSE_EVENTS__TERM_TYPE_METRIC_ID, PARSE_EVENTS__TERM_TYPE_RAW, - PARSE_EVENTS__TERM_TYPE_LEGACY_CACHE, - PARSE_EVENTS__TERM_TYPE_HARDWARE, PARSE_EVENTS__TERM_TYPE_CPU, PARSE_EVENTS__TERM_TYPE_LEGACY_HARDWARE_CONFIG, PARSE_EVENTS__TERM_TYPE_LEGACY_CACHE_CONFIG, @@ -132,12 +130,6 @@ struct parse_events_term { * value is assumed to be 1. An event name also has no value. */ bool no_value; - /** - * @alternate_hw_config: config is the event name but num is an - * alternate PERF_TYPE_HARDWARE config value which is often nice for the - * sake of quick matching. - */ - bool alternate_hw_config; }; =20 struct parse_events_error { @@ -234,10 +226,6 @@ int parse_events_add_numeric(struct parse_events_state= *parse_state, u32 type, u64 config, const struct parse_events_terms *head_config, bool wildcard); -int parse_events_add_cache(struct list_head *list, int *idx, const char *n= ame, - struct parse_events_state *parse_state, - struct parse_events_terms *parsed_terms, - void *loc); int parse_events__decode_legacy_cache(const char *name, int pmu_type, __u6= 4 *config); int parse_events_add_breakpoint(struct parse_events_state *parse_state, struct list_head *list, @@ -249,7 +237,7 @@ struct evsel *parse_events__add_event(int idx, struct p= erf_event_attr *attr, struct perf_pmu *pmu); =20 int parse_events_multi_pmu_add(struct parse_events_state *parse_state, - const char *event_name, u64 hw_config, + const char *event_name, const struct parse_events_terms *const_parsed_terms, struct list_head **listp, void *loc); =20 diff --git a/tools/perf/util/parse-events.l b/tools/perf/util/parse-events.l index 29a8d43a47a9..cceeeb85d23e 100644 --- a/tools/perf/util/parse-events.l +++ b/tools/perf/util/parse-events.l @@ -75,11 +75,6 @@ static int quoted_str(yyscan_t scanner, int token) return token; } =20 -static int lc_str(yyscan_t scanner, const struct parse_events_state *state) -{ - return str(scanner, state->match_legacy_cache_terms ? PE_LEGACY_CACHE : P= E_NAME); -} - /* * This function is called when the parser gets two kind of input: * @@ -117,14 +112,6 @@ do { \ yyless(0); \ } while (0) =20 -static int sym(yyscan_t scanner, int config) -{ - YYSTYPE *yylval =3D parse_events_get_lval(scanner); - - yylval->num =3D config; - return PE_VALUE_SYM_HW; -} - static int term(yyscan_t scanner, enum parse_events__term_type type) { YYSTYPE *yylval =3D parse_events_get_lval(scanner); @@ -133,16 +120,6 @@ static int term(yyscan_t scanner, enum parse_events__t= erm_type type) return PE_TERM; } =20 -static int hw_term(yyscan_t scanner, int config) -{ - YYSTYPE *yylval =3D parse_events_get_lval(scanner); - char *text =3D parse_events_get_text(scanner); - - yylval->hardware_term.str =3D strdup(text); - yylval->hardware_term.num =3D PERF_TYPE_HARDWARE + config; - return PE_TERM_HW; -} - static void modifiers_error(struct parse_events_state *parse_state, yyscan= _t scanner, int pos, char mod_char, const char *mod_name) { @@ -257,8 +234,6 @@ drv_cfg_term [a-zA-Z0-9_\.]+(=3D[a-zA-Z0-9_*?\.:]+)? */ modifier_event [ukhpPGHSDIWebRX]{1,17} modifier_bp [rwx]{1,3} -lc_type (L1-dcache|l1-d|l1d|L1-data|L1-icache|l1-i|l1i|L1-instruction|LLC= |L2|dTLB|d-tlb|Data-TLB|iTLB|i-tlb|Instruction-TLB|branch|branches|bpu|btb|= bpc|node) -lc_op_result (load|loads|read|store|stores|write|prefetch|prefetches|specu= lative-read|speculative-load|refs|Reference|ops|access|misses|miss) digit [0-9] non_digit [^0-9] =20 @@ -339,23 +314,10 @@ metric-id { return term(yyscanner, PARSE_EVENTS__TER= M_TYPE_METRIC_ID); } cpu { return term(yyscanner, PARSE_EVENTS__TERM_TYPE_CPU); } legacy-hardware-config { return term(yyscanner, PARSE_EVENTS__TERM_TYPE_L= EGACY_HARDWARE_CONFIG); } legacy-cache-config { return term(yyscanner, PARSE_EVENTS__TERM_TYPE_LEGAC= Y_CACHE_CONFIG); } -cpu-cycles|cycles { return hw_term(yyscanner, PERF_COUNT_HW_CPU_CYCLES)= ; } -stalled-cycles-frontend|idle-cycles-frontend { return hw_term(yyscanner, P= ERF_COUNT_HW_STALLED_CYCLES_FRONTEND); } -stalled-cycles-backend|idle-cycles-backend { return hw_term(yyscanner, PER= F_COUNT_HW_STALLED_CYCLES_BACKEND); } -instructions { return hw_term(yyscanner, PERF_COUNT_HW_INSTRUCTIONS); } -cache-references { return hw_term(yyscanner, PERF_COUNT_HW_CACHE_REFERE= NCES); } -cache-misses { return hw_term(yyscanner, PERF_COUNT_HW_CACHE_MISSES); } -branch-instructions|branches { return hw_term(yyscanner, PERF_COUNT_HW_B= RANCH_INSTRUCTIONS); } -branch-misses { return hw_term(yyscanner, PERF_COUNT_HW_BRANCH_MISSES)= ; } -bus-cycles { return hw_term(yyscanner, PERF_COUNT_HW_BUS_CYCLES); } -ref-cycles { return hw_term(yyscanner, PERF_COUNT_HW_REF_CPU_CYCLES); } r{num_raw_hex} { return str(yyscanner, PE_RAW); } r0x{num_raw_hex} { return str(yyscanner, PE_RAW); } , { return ','; } "/" { BEGIN(INITIAL); return '/'; } -{lc_type} { return lc_str(yyscanner, _parse_state); } -{lc_type}-{lc_op_result} { return lc_str(yyscanner, _parse_state); } -{lc_type}-{lc_op_result}-{lc_op_result} { return lc_str(yyscanner, _parse_= state); } {num_dec} { return value(_parse_state, yyscanner, 10); } {num_hex} { return value(_parse_state, yyscanner, 16); } {term_name} { return str(yyscanner, PE_NAME); } @@ -394,20 +356,6 @@ r0x{num_raw_hex} { return str(yyscanner, PE_RAW); } <> { BEGIN(INITIAL); } } =20 -cpu-cycles|cycles { return sym(yyscanner, PERF_COUNT_HW_CPU_CYCLES); } -stalled-cycles-frontend|idle-cycles-frontend { return sym(yyscanner, PERF_= COUNT_HW_STALLED_CYCLES_FRONTEND); } -stalled-cycles-backend|idle-cycles-backend { return sym(yyscanner, PERF_CO= UNT_HW_STALLED_CYCLES_BACKEND); } -instructions { return sym(yyscanner, PERF_COUNT_HW_INSTRUCTIONS); } -cache-references { return sym(yyscanner, PERF_COUNT_HW_CACHE_REFERENCES= ); } -cache-misses { return sym(yyscanner, PERF_COUNT_HW_CACHE_MISSES); } -branch-instructions|branches { return sym(yyscanner, PERF_COUNT_HW_BRANC= H_INSTRUCTIONS); } -branch-misses { return sym(yyscanner, PERF_COUNT_HW_BRANCH_MISSES); } -bus-cycles { return sym(yyscanner, PERF_COUNT_HW_BUS_CYCLES); } -ref-cycles { return sym(yyscanner, PERF_COUNT_HW_REF_CPU_CYCLES); } - -{lc_type} { return str(yyscanner, PE_LEGACY_CACHE); } -{lc_type}-{lc_op_result} { return str(yyscanner, PE_LEGACY_CACHE); } -{lc_type}-{lc_op_result}-{lc_op_result} { return str(yyscanner, PE_LEGACY_= CACHE); } mem: { BEGIN(mem); return PE_PREFIX_MEM; } r{num_raw_hex} { return str(yyscanner, PE_RAW); } {num_dec} { return value(_parse_state, yyscanner, 10); } diff --git a/tools/perf/util/parse-events.y b/tools/perf/util/parse-events.y index ced26c549c33..c194de5ec1ec 100644 --- a/tools/perf/util/parse-events.y +++ b/tools/perf/util/parse-events.y @@ -55,22 +55,18 @@ static void free_list_evsel(struct list_head* list_evse= l) %} =20 %token PE_START_EVENTS PE_START_TERMS -%token PE_VALUE PE_VALUE_SYM_HW PE_TERM +%token PE_VALUE PE_TERM %token PE_EVENT_NAME %token PE_RAW PE_NAME %token PE_MODIFIER_EVENT PE_MODIFIER_BP PE_BP_COLON PE_BP_SLASH -%token PE_LEGACY_CACHE %token PE_PREFIX_MEM %token PE_ERROR %token PE_DRV_CFG_TERM -%token PE_TERM_HW %type PE_VALUE -%type PE_VALUE_SYM_HW %type PE_MODIFIER_EVENT %type PE_TERM %type PE_RAW %type PE_NAME -%type PE_LEGACY_CACHE %type PE_MODIFIER_BP %type PE_EVENT_NAME %type PE_DRV_CFG_TERM @@ -83,8 +79,6 @@ static void free_list_evsel(struct list_head* list_evsel) %type opt_pmu_config %destructor { parse_events_terms__delete ($$); } %type event_pmu -%type event_legacy_symbol -%type event_legacy_cache %type event_legacy_mem %type event_legacy_tracepoint %type event_legacy_numeric @@ -100,8 +94,6 @@ static void free_list_evsel(struct list_head* list_evsel) %destructor { free_list_evsel ($$); } %type tracepoint_name %destructor { free ($$.sys); free ($$.event); } -%type PE_TERM_HW -%destructor { free ($$.str); } =20 %union { @@ -116,10 +108,6 @@ static void free_list_evsel(struct list_head* list_evs= el) char *sys; char *event; } tracepoint_name; - struct hardware_term { - char *str; - u64 num; - } hardware_term; } %% =20 @@ -262,8 +250,6 @@ PE_EVENT_NAME event_def event_def =20 event_def: event_pmu | - event_legacy_symbol | - event_legacy_cache sep_dc | event_legacy_mem sep_dc | event_legacy_tracepoint sep_dc | event_legacy_numeric sep_dc | @@ -288,7 +274,7 @@ PE_NAME sep_dc struct list_head *list; int err; =20 - err =3D parse_events_multi_pmu_add(_parse_state, $1, PERF_COUNT_HW_MAX, N= ULL, &list, &@1); + err =3D parse_events_multi_pmu_add(_parse_state, $1, /*const_parsed_terms= */NULL, &list, &@1); if (err < 0) { struct parse_events_state *parse_state =3D _parse_state; struct parse_events_error *error =3D parse_state->error; @@ -304,66 +290,6 @@ PE_NAME sep_dc $$ =3D list; } =20 -event_legacy_symbol: -PE_VALUE_SYM_HW '/' event_config '/' -{ - struct list_head *list; - int err; - - list =3D alloc_list(); - if (!list) - YYNOMEM; - err =3D parse_events_add_numeric(_parse_state, list, - PERF_TYPE_HARDWARE, $1, - $3, - /*wildcard=3D*/true); - parse_events_terms__delete($3); - if (err) { - free_list_evsel(list); - PE_ABORT(err); - } - $$ =3D list; -} -| -PE_VALUE_SYM_HW sep_slash_slash_dc -{ - struct list_head *list; - int err; - - list =3D alloc_list(); - if (!list) - YYNOMEM; - err =3D parse_events_add_numeric(_parse_state, list, - PERF_TYPE_HARDWARE, $1, - /*head_config=3D*/NULL, - /*wildcard=3D*/true); - if (err) - PE_ABORT(err); - $$ =3D list; -} - -event_legacy_cache: -PE_LEGACY_CACHE opt_event_config -{ - struct parse_events_state *parse_state =3D _parse_state; - struct list_head *list; - int err; - - list =3D alloc_list(); - if (!list) - YYNOMEM; - - err =3D parse_events_add_cache(list, &parse_state->idx, $1, parse_state, = $2, &@1); - - parse_events_terms__delete($2); - free($1); - if (err) { - free_list_evsel(list); - PE_ABORT(err); - } - $$ =3D list; -} - event_legacy_mem: PE_PREFIX_MEM PE_VALUE PE_BP_SLASH PE_VALUE PE_BP_COLON PE_MODIFIER_BP opt= _event_config { @@ -582,12 +508,7 @@ event_term $$ =3D head; } =20 -name_or_raw: PE_RAW | PE_NAME | PE_LEGACY_CACHE -| -PE_TERM_HW -{ - $$ =3D $1.str; -} +name_or_raw: PE_RAW | PE_NAME =20 event_term: PE_RAW @@ -629,19 +550,6 @@ name_or_raw '=3D' PE_VALUE $$ =3D term; } | -PE_LEGACY_CACHE -{ - struct parse_events_term *term; - int err =3D parse_events_term__num(&term, PARSE_EVENTS__TERM_TYPE_LEGACY_= CACHE, - $1, /*num=3D*/1, /*novalue=3D*/true, &@1, /*loc_val=3D*/NULL); - - if (err) { - free($1); - PE_ABORT(err); - } - $$ =3D term; -} -| PE_NAME { struct parse_events_term *term; @@ -655,20 +563,6 @@ PE_NAME $$ =3D term; } | -PE_TERM_HW -{ - struct parse_events_term *term; - int err =3D parse_events_term__num(&term, PARSE_EVENTS__TERM_TYPE_HARDWAR= E, - $1.str, $1.num & 255, /*novalue=3D*/false, - &@1, /*loc_val=3D*/NULL); - - if (err) { - free($1.str); - PE_ABORT(err); - } - $$ =3D term; -} -| PE_TERM '=3D' name_or_raw { struct parse_events_term *term; @@ -737,8 +631,6 @@ PE_DRV_CFG_TERM =20 sep_dc: ':' | =20 -sep_slash_slash_dc: '/' '/' | ':' | - %% =20 void parse_events_error(YYLTYPE *loc, void *_parse_state, diff --git a/tools/perf/util/pmu.c b/tools/perf/util/pmu.c index 7f5bdb6688db..b98413c37df2 100644 --- a/tools/perf/util/pmu.c +++ b/tools/perf/util/pmu.c @@ -1920,9 +1920,6 @@ int perf_pmu__check_alias(struct perf_pmu *pmu, struc= t parse_events_terms *head_ if (alias->per_pkg) info->per_pkg =3D true; =20 - if (term->alternate_hw_config) - *alternate_hw_config =3D term->val.num; - info->retirement_latency_mean =3D alias->retirement_latency_mean; info->retirement_latency_min =3D alias->retirement_latency_min; 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charset="utf-8" Rather than distributing the code doing similar things to evlist__new_default, use the one implementation so that paranoia and wildcard scanning can be optimized. Signed-off-by: Ian Rogers --- tools/perf/builtin-record.c | 8 ++++++-- 1 file changed, 6 insertions(+), 2 deletions(-) diff --git a/tools/perf/builtin-record.c b/tools/perf/builtin-record.c index effe6802c1a3..e7c0e5363797 100644 --- a/tools/perf/builtin-record.c +++ b/tools/perf/builtin-record.c @@ -4343,9 +4343,13 @@ int cmd_record(int argc, const char **argv) record.opts.tail_synthesize =3D true; =20 if (rec->evlist->core.nr_entries =3D=3D 0) { - err =3D parse_event(rec->evlist, "cycles:P"); - if (err) + struct evlist *def_evlist =3D evlist__new_default(); + + if (!def_evlist) goto out; + + evlist__splice_list_tail(rec->evlist, &def_evlist->core.entries); + evlist__delete(def_evlist); } =20 if (rec->opts.target.tid && !rec->opts.no_inherit_set) --=20 2.51.0.534.gc79095c0ca-goog From nobody Thu Oct 2 03:27:35 2025 Received: from mail-pg1-f202.google.com (mail-pg1-f202.google.com [209.85.215.202]) (using TLSv1.2 with cipher ECDHE-RSA-AES128-GCM-SHA256 (128/128 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id 8824E2BEFF3 for ; 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Mon, 22 Sep 2025 21:19:27 -0700 (PDT) Date: Mon, 22 Sep 2025 21:18:37 -0700 In-Reply-To: <20250923041844.400164-1-irogers@google.com> Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: Mime-Version: 1.0 References: <20250923041844.400164-1-irogers@google.com> X-Mailer: git-send-email 2.51.0.534.gc79095c0ca-goog Message-ID: <20250923041844.400164-19-irogers@google.com> Subject: [PATCH v5 18/25] perf top: Use evlist__new_default when no events specified From: Ian Rogers To: Peter Zijlstra , Ingo Molnar , Arnaldo Carvalho de Melo , Namhyung Kim , Mark Rutland , Alexander Shishkin , Jiri Olsa , Ian Rogers , Adrian Hunter , Kan Liang , James Clark , Xu Yang , Thomas Falcon , Andi Kleen , linux-kernel@vger.kernel.org, linux-perf-users@vger.kernel.org, bpf@vger.kernel.org, Atish Patra , Beeman Strong , Leo Yan , Vince Weaver Content-Transfer-Encoding: quoted-printable Content-Type: text/plain; charset="utf-8" Rather than distributing the code doing similar things to evlist__new_default, use the one implementation so that paranoia and wildcard scanning can be optimized. Signed-off-by: Ian Rogers --- tools/perf/builtin-top.c | 8 +++++--- 1 file changed, 5 insertions(+), 3 deletions(-) diff --git a/tools/perf/builtin-top.c b/tools/perf/builtin-top.c index a11f629c7d76..710604c4f6f6 100644 --- a/tools/perf/builtin-top.c +++ b/tools/perf/builtin-top.c @@ -1695,11 +1695,13 @@ int cmd_top(int argc, const char **argv) goto out_delete_evlist; =20 if (!top.evlist->core.nr_entries) { - bool can_profile_kernel =3D perf_event_paranoid_check(1); - int err =3D parse_event(top.evlist, can_profile_kernel ? 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charset="utf-8" Rather than wildcard matching the cycles event specify only the core PMUs. This avoids potentially loading unnecessary uncore PMUs. Signed-off-by: Ian Rogers --- tools/perf/util/evlist.c | 18 +++++++++++++----- 1 file changed, 13 insertions(+), 5 deletions(-) diff --git a/tools/perf/util/evlist.c b/tools/perf/util/evlist.c index 80d8387e6b97..e8217efdda53 100644 --- a/tools/perf/util/evlist.c +++ b/tools/perf/util/evlist.c @@ -101,16 +101,24 @@ struct evlist *evlist__new_default(void) { struct evlist *evlist =3D evlist__new(); bool can_profile_kernel; - int err; + struct perf_pmu *pmu =3D NULL; =20 if (!evlist) return NULL; =20 can_profile_kernel =3D perf_event_paranoid_check(1); - err =3D parse_event(evlist, can_profile_kernel ? "cycles:P" : "cycles:Pu"= ); - if (err) { - evlist__delete(evlist); - return NULL; + + while ((pmu =3D perf_pmus__scan_core(pmu)) !=3D NULL) { + char buf[256]; + int err; + + snprintf(buf, sizeof(buf), "%s/cycles/%s", pmu->name, + can_profile_kernel ? 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charset="utf-8" Ensure both the perf_event_attr and alternate_hw_config are checked in the match. Don't mask the config if the perf_event_attr isn't a HARDWARE or HW_CACHE event. Add common early exit cases. Signed-off-by: Ian Rogers --- tools/perf/util/evsel.c | 21 ++++++++++++--------- 1 file changed, 12 insertions(+), 9 deletions(-) diff --git a/tools/perf/util/evsel.c b/tools/perf/util/evsel.c index 6a31f9699b49..8c60f79a76ca 100644 --- a/tools/perf/util/evsel.c +++ b/tools/perf/util/evsel.c @@ -1863,16 +1863,19 @@ bool __evsel__match(const struct evsel *evsel, u32 = type, u64 config) u32 e_type =3D evsel->core.attr.type; u64 e_config =3D evsel->core.attr.config; =20 - if (e_type !=3D type) { - return type =3D=3D PERF_TYPE_HARDWARE && evsel->pmu && evsel->pmu->is_co= re && - evsel->alternate_hw_config =3D=3D config; - } - - if ((type =3D=3D PERF_TYPE_HARDWARE || type =3D=3D PERF_TYPE_HW_CACHE) && - perf_pmus__supports_extended_type()) + if (e_type =3D=3D type && e_config =3D=3D config) + return true; + if (type !=3D PERF_TYPE_HARDWARE && type !=3D PERF_TYPE_HW_CACHE) + return false; + if ((e_type =3D=3D PERF_TYPE_HARDWARE || e_type =3D=3D PERF_TYPE_HW_CACHE= ) && + perf_pmus__supports_extended_type()) e_config &=3D PERF_HW_EVENT_MASK; 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AJvYcCWEl7b9WoaO+gQKrVOz/mz5HsqDqjhB6CmZE/sXYBo6BWvO4Z2o/WMF+jol6FexfSsf9kitP3B44RlpUv8=@vger.kernel.org X-Gm-Message-State: AOJu0Ywy76t4ZnPO+9P60m8+i0gtppikRad40V7rVQp+FQzvxNtVT3MJ vYV/d04V15u9IhgTgMChuV2ZSJWwz/OSfD6c9+CStHQrOcRWerxqo7+KYZkAjWwO/ic4Ov2x+vE KVZMbwopgNw== X-Google-Smtp-Source: AGHT+IFVm0hE0It3ERinAuwVBOc5Sest9A5brcYMXmMSGb4/jWFOwOV2oYhjBHAvD+G4xeuZkrHQTmSoPhhT X-Received: from oacpc10.prod.google.com ([2002:a05:6871:7a0a:b0:302:5983:b870]) (user=irogers job=prod-delivery.src-stubby-dispatcher) by 2002:a05:6870:d38c:b0:332:bb5f:cf28 with SMTP id 586e51a60fabf-34c88b0c492mr532508fac.47.1758601174077; Mon, 22 Sep 2025 21:19:34 -0700 (PDT) Date: Mon, 22 Sep 2025 21:18:40 -0700 In-Reply-To: <20250923041844.400164-1-irogers@google.com> Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: Mime-Version: 1.0 References: <20250923041844.400164-1-irogers@google.com> X-Mailer: git-send-email 2.51.0.534.gc79095c0ca-goog Message-ID: <20250923041844.400164-22-irogers@google.com> Subject: [PATCH v5 21/25] perf test parse-events: Use evsel__match for legacy events From: Ian Rogers To: Peter Zijlstra , Ingo Molnar , Arnaldo Carvalho de Melo , Namhyung Kim , Mark Rutland , Alexander Shishkin , Jiri Olsa , Ian Rogers , Adrian Hunter , Kan Liang , James Clark , Xu Yang , Thomas Falcon , Andi Kleen , linux-kernel@vger.kernel.org, linux-perf-users@vger.kernel.org, bpf@vger.kernel.org, Atish Patra , Beeman Strong , Leo Yan , Vince Weaver Content-Transfer-Encoding: quoted-printable Content-Type: text/plain; charset="utf-8" Switch from the test's assert_hw/test_config to the common evsel__match code that appropriately handles events with both legacy and sysfs/json encoding. For tests asserting that a config value matches that placed in the perf_event_attr just directly compare the config values. Signed-off-by: Ian Rogers --- tools/perf/tests/parse-events.c | 290 ++++++++------------------------ 1 file changed, 70 insertions(+), 220 deletions(-) diff --git a/tools/perf/tests/parse-events.c b/tools/perf/tests/parse-event= s.c index 4e55b0d295bd..d0f1e05139ac 100644 --- a/tools/perf/tests/parse-events.c +++ b/tools/perf/tests/parse-events.c @@ -155,60 +155,38 @@ static int test__checkevent_numeric(struct evlist *ev= list) =20 TEST_ASSERT_VAL("wrong number of entries", 1 =3D=3D evlist->core.nr_entri= es); TEST_ASSERT_VAL("wrong type", 1 =3D=3D evsel->core.attr.type); - TEST_ASSERT_VAL("wrong config", test_config(evsel, 1)); + TEST_ASSERT_VAL("wrong config", 1 =3D=3D evsel->core.attr.config); return TEST_OK; } =20 =20 -static int assert_hw(struct perf_evsel *evsel, enum perf_hw_id id, const c= har *name) -{ - struct perf_pmu *pmu; - - if (evsel->attr.type =3D=3D PERF_TYPE_HARDWARE) { - TEST_ASSERT_VAL("wrong config", test_perf_config(evsel, id)); - return 0; - } - pmu =3D perf_pmus__find_by_type(evsel->attr.type); - - TEST_ASSERT_VAL("unexpected PMU type", pmu); - TEST_ASSERT_VAL("PMU missing event", perf_pmu__have_event(pmu, name)); - return 0; -} - static int test__checkevent_symbolic_name(struct evlist *evlist) { - struct perf_evsel *evsel; + struct evsel *evsel; =20 TEST_ASSERT_VAL("wrong number of entries", 0 !=3D evlist->core.nr_entries= ); =20 - perf_evlist__for_each_evsel(&evlist->core, evsel) { - int ret =3D assert_hw(evsel, PERF_COUNT_HW_INSTRUCTIONS, "instructions"); - - if (ret) - return ret; - } + evlist__for_each_entry(evlist, evsel) + TEST_ASSERT_VAL("unexpected event", evsel__match(evsel, HARDWARE, HW_INS= TRUCTIONS)); =20 return TEST_OK; } =20 static int test__checkevent_symbolic_name_config(struct evlist *evlist) { - struct perf_evsel *evsel; + struct evsel *evsel; =20 TEST_ASSERT_VAL("wrong number of entries", 0 !=3D evlist->core.nr_entries= ); =20 - perf_evlist__for_each_evsel(&evlist->core, evsel) { - int ret =3D assert_hw(evsel, PERF_COUNT_HW_CPU_CYCLES, "cycles"); - - if (ret) - return ret; + evlist__for_each_entry(evlist, evsel) { + TEST_ASSERT_VAL("unexpected event", evsel__match(evsel, HARDWARE, HW_CPU= _CYCLES)); /* * The period value gets configured within evlist__config, * while this test executes only parse events method. */ - TEST_ASSERT_VAL("wrong period", 0 =3D=3D evsel->attr.sample_period); - TEST_ASSERT_VAL("wrong config1", 0 =3D=3D evsel->attr.config1); - TEST_ASSERT_VAL("wrong config2", 1 =3D=3D evsel->attr.config2); + TEST_ASSERT_VAL("wrong period", 0 =3D=3D evsel->core.attr.sample_period); + TEST_ASSERT_VAL("wrong config1", 0 =3D=3D evsel->core.attr.config1); + TEST_ASSERT_VAL("wrong config2", 1 =3D=3D evsel->core.attr.config2); } return TEST_OK; } @@ -218,8 +196,7 @@ static int test__checkevent_symbolic_alias(struct evlis= t *evlist) struct evsel *evsel =3D evlist__first(evlist); =20 TEST_ASSERT_VAL("wrong number of entries", 1 =3D=3D evlist->core.nr_entri= es); - TEST_ASSERT_VAL("wrong type", PERF_TYPE_SOFTWARE =3D=3D evsel->core.attr.= type); - TEST_ASSERT_VAL("wrong config", test_config(evsel, PERF_COUNT_SW_PAGE_FAU= LTS)); + TEST_ASSERT_VAL("wrong type/config", evsel__match(evsel, SOFTWARE, SW_PAG= E_FAULTS)); return TEST_OK; } =20 @@ -242,7 +219,7 @@ static int test__checkevent_breakpoint(struct evlist *e= vlist) =20 TEST_ASSERT_VAL("wrong number of entries", 1 =3D=3D evlist->core.nr_entri= es); TEST_ASSERT_VAL("wrong type", PERF_TYPE_BREAKPOINT =3D=3D evsel->core.att= r.type); - TEST_ASSERT_VAL("wrong config", test_config(evsel, 0)); + TEST_ASSERT_VAL("wrong config", 0 =3D=3D evsel->core.attr.config); TEST_ASSERT_VAL("wrong bp_type", (HW_BREAKPOINT_R | HW_BREAKPOINT_W) =3D= =3D evsel->core.attr.bp_type); TEST_ASSERT_VAL("wrong bp_len", HW_BREAKPOINT_LEN_4 =3D=3D @@ -256,7 +233,7 @@ static int test__checkevent_breakpoint_x(struct evlist = *evlist) =20 TEST_ASSERT_VAL("wrong number of entries", 1 =3D=3D evlist->core.nr_entri= es); TEST_ASSERT_VAL("wrong type", PERF_TYPE_BREAKPOINT =3D=3D evsel->core.att= r.type); - TEST_ASSERT_VAL("wrong config", test_config(evsel, 0)); + TEST_ASSERT_VAL("wrong config", 0 =3D=3D evsel->core.attr.config); TEST_ASSERT_VAL("wrong bp_type", HW_BREAKPOINT_X =3D=3D evsel->core.attr.bp_type); TEST_ASSERT_VAL("wrong bp_len", default_breakpoint_len() =3D=3D evsel->co= re.attr.bp_len); @@ -270,7 +247,7 @@ static int test__checkevent_breakpoint_r(struct evlist = *evlist) TEST_ASSERT_VAL("wrong number of entries", 1 =3D=3D evlist->core.nr_entri= es); TEST_ASSERT_VAL("wrong type", PERF_TYPE_BREAKPOINT =3D=3D evsel->core.attr.type); - TEST_ASSERT_VAL("wrong config", test_config(evsel, 0)); + TEST_ASSERT_VAL("wrong config", 0 =3D=3D evsel->core.attr.config); TEST_ASSERT_VAL("wrong bp_type", HW_BREAKPOINT_R =3D=3D evsel->core.attr.bp_type); TEST_ASSERT_VAL("wrong bp_len", @@ -285,7 +262,7 @@ static int test__checkevent_breakpoint_w(struct evlist = *evlist) TEST_ASSERT_VAL("wrong number of entries", 1 =3D=3D evlist->core.nr_entri= es); TEST_ASSERT_VAL("wrong type", PERF_TYPE_BREAKPOINT =3D=3D evsel->core.attr.type); - TEST_ASSERT_VAL("wrong config", test_config(evsel, 0)); + TEST_ASSERT_VAL("wrong config", 0 =3D=3D evsel->core.attr.config); TEST_ASSERT_VAL("wrong bp_type", HW_BREAKPOINT_W =3D=3D evsel->core.attr.bp_type); TEST_ASSERT_VAL("wrong bp_len", @@ -300,7 +277,7 @@ static int test__checkevent_breakpoint_rw(struct evlist= *evlist) TEST_ASSERT_VAL("wrong number of entries", 1 =3D=3D evlist->core.nr_entri= es); TEST_ASSERT_VAL("wrong type", PERF_TYPE_BREAKPOINT =3D=3D evsel->core.attr.type); - TEST_ASSERT_VAL("wrong config", test_config(evsel, 0)); + TEST_ASSERT_VAL("wrong config", 0 =3D=3D evsel->core.attr.config); TEST_ASSERT_VAL("wrong bp_type", (HW_BREAKPOINT_R|HW_BREAKPOINT_W) =3D=3D evsel->core.attr.bp_type); TEST_ASSERT_VAL("wrong bp_len", @@ -633,7 +610,7 @@ static int test__checkevent_list(struct evlist *evlist) /* r1 */ TEST_ASSERT_VAL("wrong type", PERF_TYPE_TRACEPOINT !=3D evsel->core.attr.= type); while (evsel->core.attr.type !=3D PERF_TYPE_TRACEPOINT) { - TEST_ASSERT_VAL("wrong config", test_config(evsel, 1)); + TEST_ASSERT_VAL("wrong config", 1 =3D=3D evsel->core.attr.config); TEST_ASSERT_VAL("wrong config1", 0 =3D=3D evsel->core.attr.config1); TEST_ASSERT_VAL("wrong config2", 0 =3D=3D evsel->core.attr.config2); TEST_ASSERT_VAL("wrong config3", 0 =3D=3D evsel->core.attr.config3); @@ -657,7 +634,7 @@ static int test__checkevent_list(struct evlist *evlist) /* 1:1:hp */ evsel =3D evsel__next(evsel); TEST_ASSERT_VAL("wrong type", 1 =3D=3D evsel->core.attr.type); - TEST_ASSERT_VAL("wrong config", test_config(evsel, 1)); + TEST_ASSERT_VAL("wrong config", 1 =3D=3D evsel->core.attr.config); TEST_ASSERT_VAL("wrong exclude_user", evsel->core.attr.exclude_user); TEST_ASSERT_VAL("wrong exclude_kernel", evsel->core.attr.exclude_kernel); TEST_ASSERT_VAL("wrong exclude_hv", !evsel->core.attr.exclude_hv); @@ -673,14 +650,14 @@ static int test__checkevent_pmu_name(struct evlist *e= vlist) /* cpu/config=3D1,name=3Dkrava/u */ TEST_ASSERT_VAL("wrong number of entries", 2 =3D=3D evlist->core.nr_entri= es); TEST_ASSERT_VAL("wrong type", PERF_TYPE_RAW =3D=3D evsel->core.attr.type); - TEST_ASSERT_VAL("wrong config", test_config(evsel, 1)); + TEST_ASSERT_VAL("wrong config", 1 =3D=3D evsel->core.attr.config); TEST_ASSERT_VAL("wrong name", evsel__name_is(evsel, "krava")); =20 /* cpu/config=3D2/u" */ evsel =3D evsel__next(evsel); TEST_ASSERT_VAL("wrong number of entries", 2 =3D=3D evlist->core.nr_entri= es); TEST_ASSERT_VAL("wrong type", PERF_TYPE_RAW =3D=3D evsel->core.attr.type); - TEST_ASSERT_VAL("wrong config", test_config(evsel, 2)); + TEST_ASSERT_VAL("wrong config", 2 =3D=3D evsel->core.attr.config); TEST_ASSERT_VAL("wrong name", evsel__name_is(evsel, "cpu/config=3D2/u")); =20 return TEST_OK; @@ -693,7 +670,7 @@ static int test__checkevent_pmu_partial_time_callgraph(= struct evlist *evlist) /* cpu/config=3D1,call-graph=3Dfp,time,period=3D100000/ */ TEST_ASSERT_VAL("wrong number of entries", 2 =3D=3D evlist->core.nr_entri= es); TEST_ASSERT_VAL("wrong type", PERF_TYPE_RAW =3D=3D evsel->core.attr.type); - TEST_ASSERT_VAL("wrong config", test_config(evsel, 1)); + TEST_ASSERT_VAL("wrong config", 1 =3D=3D evsel->core.attr.config); /* * The period, time and callgraph value gets configured within evlist__co= nfig, * while this test executes only parse events method. @@ -705,7 +682,7 @@ static int test__checkevent_pmu_partial_time_callgraph(= struct evlist *evlist) /* cpu/config=3D2,call-graph=3Dno,time=3D0,period=3D2000/ */ evsel =3D evsel__next(evsel); TEST_ASSERT_VAL("wrong type", PERF_TYPE_RAW =3D=3D evsel->core.attr.type); - TEST_ASSERT_VAL("wrong config", test_config(evsel, 2)); + TEST_ASSERT_VAL("wrong config", 2 =3D=3D evsel->core.attr.config); /* * The period, time and callgraph value gets configured within evlist__co= nfig, * while this test executes only parse events method. @@ -855,7 +832,7 @@ static int test__checkterms_simple(struct parse_events_= terms *terms) =20 static int test__group1(struct evlist *evlist) { - struct evsel *evsel, *leader; + struct evsel *evsel =3D NULL, *leader; =20 TEST_ASSERT_VAL("wrong number of entries", evlist->core.nr_entries =3D=3D (num_core_entries() * 2)); @@ -863,14 +840,9 @@ static int test__group1(struct evlist *evlist) evlist__nr_groups(evlist) =3D=3D num_core_entries()); =20 for (int i =3D 0; i < num_core_entries(); i++) { - int ret; - /* instructions:k */ evsel =3D leader =3D (i =3D=3D 0 ? evlist__first(evlist) : evsel__next(e= vsel)); - ret =3D assert_hw(&evsel->core, PERF_COUNT_HW_INSTRUCTIONS, "instruction= s"); - if (ret) - return ret; - + TEST_ASSERT_VAL("unexpected event", evsel__match(evsel, HARDWARE, HW_INS= TRUCTIONS)); TEST_ASSERT_VAL("wrong exclude_user", evsel->core.attr.exclude_user); TEST_ASSERT_VAL("wrong exclude_kernel", !evsel->core.attr.exclude_kernel= ); TEST_ASSERT_VAL("wrong exclude_hv", evsel->core.attr.exclude_hv); @@ -884,10 +856,7 @@ static int test__group1(struct evlist *evlist) =20 /* cycles:upp */ evsel =3D evsel__next(evsel); - ret =3D assert_hw(&evsel->core, PERF_COUNT_HW_CPU_CYCLES, "cycles"); - if (ret) - return ret; - + TEST_ASSERT_VAL("unexpected event", evsel__match(evsel, HARDWARE, HW_CPU= _CYCLES)); TEST_ASSERT_VAL("wrong exclude_user", !evsel->core.attr.exclude_user); TEST_ASSERT_VAL("wrong exclude_kernel", evsel->core.attr.exclude_kernel); TEST_ASSERT_VAL("wrong exclude_hv", evsel->core.attr.exclude_hv); @@ -914,13 +883,9 @@ static int test__group2(struct evlist *evlist) TEST_ASSERT_VAL("wrong number of groups", 1 =3D=3D evlist__nr_groups(evli= st)); =20 evlist__for_each_entry(evlist, evsel) { - int ret; - - if (evsel->core.attr.type =3D=3D PERF_TYPE_SOFTWARE) { + if (evsel__match(evsel, SOFTWARE, SW_PAGE_FAULTS)) { /* faults + :ku modifier */ leader =3D evsel; - TEST_ASSERT_VAL("wrong config", - test_config(evsel, PERF_COUNT_SW_PAGE_FAULTS)); TEST_ASSERT_VAL("wrong exclude_user", !evsel->core.attr.exclude_user); TEST_ASSERT_VAL("wrong exclude_kernel", !evsel->core.attr.exclude_kerne= l); TEST_ASSERT_VAL("wrong exclude_hv", evsel->core.attr.exclude_hv); @@ -933,8 +898,7 @@ static int test__group2(struct evlist *evlist) TEST_ASSERT_VAL("wrong sample_read", !evsel->sample_read); continue; } - if (evsel->core.attr.type =3D=3D PERF_TYPE_HARDWARE && - test_config(evsel, PERF_COUNT_HW_BRANCH_INSTRUCTIONS)) { + if (evsel__match(evsel, HARDWARE, HW_BRANCH_INSTRUCTIONS)) { /* branches + :u modifier */ TEST_ASSERT_VAL("wrong exclude_user", !evsel->core.attr.exclude_user); TEST_ASSERT_VAL("wrong exclude_kernel", evsel->core.attr.exclude_kernel= ); @@ -948,10 +912,7 @@ static int test__group2(struct evlist *evlist) continue; } /* cycles:k */ - ret =3D assert_hw(&evsel->core, PERF_COUNT_HW_CPU_CYCLES, "cycles"); - if (ret) - return ret; - + TEST_ASSERT_VAL("unexpected event", evsel__match(evsel, HARDWARE, HW_CPU= _CYCLES)); TEST_ASSERT_VAL("wrong exclude_user", evsel->core.attr.exclude_user); TEST_ASSERT_VAL("wrong exclude_kernel", !evsel->core.attr.exclude_kernel= ); TEST_ASSERT_VAL("wrong exclude_hv", evsel->core.attr.exclude_hv); @@ -967,7 +928,6 @@ static int test__group2(struct evlist *evlist) static int test__group3(struct evlist *evlist __maybe_unused) { struct evsel *evsel, *group1_leader =3D NULL, *group2_leader =3D NULL; - int ret; =20 TEST_ASSERT_VAL("wrong number of entries", evlist->core.nr_entries =3D=3D (3 * perf_pmus__num_core_pmus() + 2)); @@ -998,8 +958,7 @@ static int test__group3(struct evlist *evlist __maybe_u= nused) TEST_ASSERT_VAL("wrong sample_read", !evsel->sample_read); continue; } - if (evsel->core.attr.type =3D=3D PERF_TYPE_HARDWARE && - test_config(evsel, PERF_COUNT_HW_CPU_CYCLES)) { + if (evsel__match(evsel, HARDWARE, HW_CPU_CYCLES)) { if (evsel->core.attr.exclude_user) { /* group1 cycles:kppp */ TEST_ASSERT_VAL("wrong exclude_user", @@ -1042,7 +1001,7 @@ static int test__group3(struct evlist *evlist __maybe= _unused) } if (evsel->core.attr.type =3D=3D 1) { /* group2 1:3 + G modifier */ - TEST_ASSERT_VAL("wrong config", test_config(evsel, 3)); + TEST_ASSERT_VAL("wrong config", 3 =3D=3D evsel->core.attr.config); TEST_ASSERT_VAL("wrong exclude_user", !evsel->core.attr.exclude_user); TEST_ASSERT_VAL("wrong exclude_kernel", !evsel->core.attr.exclude_kerne= l); TEST_ASSERT_VAL("wrong exclude_hv", !evsel->core.attr.exclude_hv); @@ -1055,10 +1014,7 @@ static int test__group3(struct evlist *evlist __mayb= e_unused) continue; } /* instructions:u */ - ret =3D assert_hw(&evsel->core, PERF_COUNT_HW_INSTRUCTIONS, "instruction= s"); - if (ret) - return ret; - + TEST_ASSERT_VAL("unexpected event", evsel__match(evsel, HARDWARE, HW_INS= TRUCTIONS)); TEST_ASSERT_VAL("wrong exclude_user", !evsel->core.attr.exclude_user); TEST_ASSERT_VAL("wrong exclude_kernel", evsel->core.attr.exclude_kernel); TEST_ASSERT_VAL("wrong exclude_hv", evsel->core.attr.exclude_hv); @@ -1073,7 +1029,7 @@ static int test__group3(struct evlist *evlist __maybe= _unused) =20 static int test__group4(struct evlist *evlist __maybe_unused) { - struct evsel *evsel, *leader; + struct evsel *evsel =3D NULL, *leader; =20 TEST_ASSERT_VAL("wrong number of entries", evlist->core.nr_entries =3D=3D (num_core_entries() * 2)); @@ -1081,14 +1037,9 @@ static int test__group4(struct evlist *evlist __mayb= e_unused) num_core_entries() =3D=3D evlist__nr_groups(evlist)); =20 for (int i =3D 0; i < num_core_entries(); i++) { - int ret; - /* cycles:u + p */ evsel =3D leader =3D (i =3D=3D 0 ? evlist__first(evlist) : evsel__next(e= vsel)); - ret =3D assert_hw(&evsel->core, PERF_COUNT_HW_CPU_CYCLES, "cycles"); - if (ret) - return ret; - + TEST_ASSERT_VAL("unexpected event", evsel__match(evsel, HARDWARE, HW_CPU= _CYCLES)); TEST_ASSERT_VAL("wrong exclude_user", !evsel->core.attr.exclude_user); TEST_ASSERT_VAL("wrong exclude_kernel", evsel->core.attr.exclude_kernel); TEST_ASSERT_VAL("wrong exclude_hv", evsel->core.attr.exclude_hv); @@ -1103,10 +1054,7 @@ static int test__group4(struct evlist *evlist __mayb= e_unused) =20 /* instructions:kp + p */ evsel =3D evsel__next(evsel); - ret =3D assert_hw(&evsel->core, PERF_COUNT_HW_INSTRUCTIONS, "instruction= s"); - if (ret) - return ret; - + TEST_ASSERT_VAL("unexpected event", evsel__match(evsel, HARDWARE, HW_INS= TRUCTIONS)); TEST_ASSERT_VAL("wrong exclude_user", evsel->core.attr.exclude_user); TEST_ASSERT_VAL("wrong exclude_kernel", !evsel->core.attr.exclude_kernel= ); TEST_ASSERT_VAL("wrong exclude_hv", evsel->core.attr.exclude_hv); @@ -1123,7 +1071,6 @@ static int test__group4(struct evlist *evlist __maybe= _unused) static int test__group5(struct evlist *evlist __maybe_unused) { struct evsel *evsel =3D NULL, *leader; - int ret; =20 TEST_ASSERT_VAL("wrong number of entries", evlist->core.nr_entries =3D=3D (5 * num_core_entries())); @@ -1133,10 +1080,7 @@ static int test__group5(struct evlist *evlist __mayb= e_unused) for (int i =3D 0; i < num_core_entries(); i++) { /* cycles + G */ evsel =3D leader =3D (i =3D=3D 0 ? evlist__first(evlist) : evsel__next(e= vsel)); - ret =3D assert_hw(&evsel->core, PERF_COUNT_HW_CPU_CYCLES, "cycles"); - if (ret) - return ret; - + TEST_ASSERT_VAL("unexpected event", evsel__match(evsel, HARDWARE, HW_CPU= _CYCLES)); TEST_ASSERT_VAL("wrong exclude_user", !evsel->core.attr.exclude_user); TEST_ASSERT_VAL("wrong exclude_kernel", !evsel->core.attr.exclude_kernel= ); TEST_ASSERT_VAL("wrong exclude_hv", !evsel->core.attr.exclude_hv); @@ -1151,10 +1095,7 @@ static int test__group5(struct evlist *evlist __mayb= e_unused) =20 /* instructions + G */ evsel =3D evsel__next(evsel); - ret =3D assert_hw(&evsel->core, PERF_COUNT_HW_INSTRUCTIONS, "instruction= s"); - if (ret) - return ret; - + TEST_ASSERT_VAL("unexpected event", evsel__match(evsel, HARDWARE, HW_INS= TRUCTIONS)); TEST_ASSERT_VAL("wrong exclude_user", !evsel->core.attr.exclude_user); TEST_ASSERT_VAL("wrong exclude_kernel", !evsel->core.attr.exclude_kernel= ); TEST_ASSERT_VAL("wrong exclude_hv", !evsel->core.attr.exclude_hv); @@ -1168,10 +1109,7 @@ static int test__group5(struct evlist *evlist __mayb= e_unused) for (int i =3D 0; i < num_core_entries(); i++) { /* cycles:G */ evsel =3D leader =3D evsel__next(evsel); - ret =3D assert_hw(&evsel->core, PERF_COUNT_HW_CPU_CYCLES, "cycles"); - if (ret) - return ret; - + TEST_ASSERT_VAL("unexpected event", evsel__match(evsel, HARDWARE, HW_CPU= _CYCLES)); TEST_ASSERT_VAL("wrong exclude_user", !evsel->core.attr.exclude_user); TEST_ASSERT_VAL("wrong exclude_kernel", !evsel->core.attr.exclude_kernel= ); TEST_ASSERT_VAL("wrong exclude_hv", !evsel->core.attr.exclude_hv); @@ -1186,10 +1124,7 @@ static int test__group5(struct evlist *evlist __mayb= e_unused) =20 /* instructions:G */ evsel =3D evsel__next(evsel); - ret =3D assert_hw(&evsel->core, PERF_COUNT_HW_INSTRUCTIONS, "instruction= s"); - if (ret) - return ret; - + TEST_ASSERT_VAL("unexpected event", evsel__match(evsel, HARDWARE, HW_INS= TRUCTIONS)); TEST_ASSERT_VAL("wrong exclude_user", !evsel->core.attr.exclude_user); TEST_ASSERT_VAL("wrong exclude_kernel", !evsel->core.attr.exclude_kernel= ); TEST_ASSERT_VAL("wrong exclude_hv", !evsel->core.attr.exclude_hv); @@ -1202,10 +1137,7 @@ static int test__group5(struct evlist *evlist __mayb= e_unused) for (int i =3D 0; i < num_core_entries(); i++) { /* cycles */ evsel =3D evsel__next(evsel); - ret =3D assert_hw(&evsel->core, PERF_COUNT_HW_CPU_CYCLES, "cycles"); - if (ret) - return ret; - + TEST_ASSERT_VAL("unexpected event", evsel__match(evsel, HARDWARE, HW_CPU= _CYCLES)); TEST_ASSERT_VAL("wrong exclude_user", !evsel->core.attr.exclude_user); TEST_ASSERT_VAL("wrong exclude_kernel", !evsel->core.attr.exclude_kernel= ); TEST_ASSERT_VAL("wrong exclude_hv", !evsel->core.attr.exclude_hv); @@ -1227,14 +1159,9 @@ static int test__group_gh1(struct evlist *evlist) evlist__nr_groups(evlist) =3D=3D num_core_entries()); =20 for (int i =3D 0; i < num_core_entries(); i++) { - int ret; - /* cycles + :H group modifier */ evsel =3D leader =3D (i =3D=3D 0 ? evlist__first(evlist) : evsel__next(e= vsel)); - ret =3D assert_hw(&evsel->core, PERF_COUNT_HW_CPU_CYCLES, "cycles"); - if (ret) - return ret; - + TEST_ASSERT_VAL("unexpected event", evsel__match(evsel, HARDWARE, HW_CPU= _CYCLES)); TEST_ASSERT_VAL("wrong exclude_user", !evsel->core.attr.exclude_user); TEST_ASSERT_VAL("wrong exclude_kernel", !evsel->core.attr.exclude_kernel= ); TEST_ASSERT_VAL("wrong exclude_hv", !evsel->core.attr.exclude_hv); @@ -1248,10 +1175,7 @@ static int test__group_gh1(struct evlist *evlist) =20 /* cache-misses:G + :H group modifier */ evsel =3D evsel__next(evsel); - ret =3D assert_hw(&evsel->core, PERF_COUNT_HW_CACHE_MISSES, "cache-misse= s"); - if (ret) - return ret; - + TEST_ASSERT_VAL("unexpected event", evsel__match(evsel, HARDWARE, HW_CAC= HE_MISSES)); TEST_ASSERT_VAL("wrong exclude_user", !evsel->core.attr.exclude_user); TEST_ASSERT_VAL("wrong exclude_kernel", !evsel->core.attr.exclude_kernel= ); TEST_ASSERT_VAL("wrong exclude_hv", !evsel->core.attr.exclude_hv); @@ -1274,14 +1198,9 @@ static int test__group_gh2(struct evlist *evlist) evlist__nr_groups(evlist) =3D=3D num_core_entries()); =20 for (int i =3D 0; i < num_core_entries(); i++) { - int ret; - /* cycles + :G group modifier */ evsel =3D leader =3D (i =3D=3D 0 ? evlist__first(evlist) : evsel__next(e= vsel)); - ret =3D assert_hw(&evsel->core, PERF_COUNT_HW_CPU_CYCLES, "cycles"); - if (ret) - return ret; - + TEST_ASSERT_VAL("unexpected event", evsel__match(evsel, HARDWARE, HW_CPU= _CYCLES)); TEST_ASSERT_VAL("wrong exclude_user", !evsel->core.attr.exclude_user); TEST_ASSERT_VAL("wrong exclude_kernel", !evsel->core.attr.exclude_kernel= ); TEST_ASSERT_VAL("wrong exclude_hv", !evsel->core.attr.exclude_hv); @@ -1295,10 +1214,7 @@ static int test__group_gh2(struct evlist *evlist) =20 /* cache-misses:H + :G group modifier */ evsel =3D evsel__next(evsel); - ret =3D assert_hw(&evsel->core, PERF_COUNT_HW_CACHE_MISSES, "cache-misse= s"); - if (ret) - return ret; - + TEST_ASSERT_VAL("unexpected event", evsel__match(evsel, HARDWARE, HW_CAC= HE_MISSES)); TEST_ASSERT_VAL("wrong exclude_user", !evsel->core.attr.exclude_user); TEST_ASSERT_VAL("wrong exclude_kernel", !evsel->core.attr.exclude_kernel= ); TEST_ASSERT_VAL("wrong exclude_hv", !evsel->core.attr.exclude_hv); @@ -1321,14 +1237,9 @@ static int test__group_gh3(struct evlist *evlist) evlist__nr_groups(evlist) =3D=3D num_core_entries()); =20 for (int i =3D 0; i < num_core_entries(); i++) { - int ret; - /* cycles:G + :u group modifier */ evsel =3D leader =3D (i =3D=3D 0 ? evlist__first(evlist) : evsel__next(e= vsel)); - ret =3D assert_hw(&evsel->core, PERF_COUNT_HW_CPU_CYCLES, "cycles"); - if (ret) - return ret; - + TEST_ASSERT_VAL("unexpected event", evsel__match(evsel, HARDWARE, HW_CPU= _CYCLES)); TEST_ASSERT_VAL("wrong exclude_user", !evsel->core.attr.exclude_user); TEST_ASSERT_VAL("wrong exclude_kernel", evsel->core.attr.exclude_kernel); TEST_ASSERT_VAL("wrong exclude_hv", evsel->core.attr.exclude_hv); @@ -1342,10 +1253,7 @@ static int test__group_gh3(struct evlist *evlist) =20 /* cache-misses:H + :u group modifier */ evsel =3D evsel__next(evsel); - ret =3D assert_hw(&evsel->core, PERF_COUNT_HW_CACHE_MISSES, "cache-misse= s"); - if (ret) - return ret; - + TEST_ASSERT_VAL("unexpected event", evsel__match(evsel, HARDWARE, HW_CAC= HE_MISSES)); TEST_ASSERT_VAL("wrong exclude_user", !evsel->core.attr.exclude_user); TEST_ASSERT_VAL("wrong exclude_kernel", evsel->core.attr.exclude_kernel); TEST_ASSERT_VAL("wrong exclude_hv", evsel->core.attr.exclude_hv); @@ -1368,14 +1276,9 @@ static int test__group_gh4(struct evlist *evlist) evlist__nr_groups(evlist) =3D=3D num_core_entries()); =20 for (int i =3D 0; i < num_core_entries(); i++) { - int ret; - /* cycles:G + :uG group modifier */ evsel =3D leader =3D (i =3D=3D 0 ? evlist__first(evlist) : evsel__next(e= vsel)); - ret =3D assert_hw(&evsel->core, PERF_COUNT_HW_CPU_CYCLES, "cycles"); - if (ret) - return ret; - + TEST_ASSERT_VAL("unexpected event", evsel__match(evsel, HARDWARE, HW_CPU= _CYCLES)); TEST_ASSERT_VAL("wrong exclude_user", !evsel->core.attr.exclude_user); TEST_ASSERT_VAL("wrong exclude_kernel", evsel->core.attr.exclude_kernel); TEST_ASSERT_VAL("wrong exclude_hv", evsel->core.attr.exclude_hv); @@ -1389,10 +1292,7 @@ static int test__group_gh4(struct evlist *evlist) =20 /* cache-misses:H + :uG group modifier */ evsel =3D evsel__next(evsel); - ret =3D assert_hw(&evsel->core, PERF_COUNT_HW_CACHE_MISSES, "cache-misse= s"); - if (ret) - return ret; - + TEST_ASSERT_VAL("unexpected event", evsel__match(evsel, HARDWARE, HW_CAC= HE_MISSES)); TEST_ASSERT_VAL("wrong exclude_user", !evsel->core.attr.exclude_user); TEST_ASSERT_VAL("wrong exclude_kernel", evsel->core.attr.exclude_kernel); TEST_ASSERT_VAL("wrong exclude_hv", evsel->core.attr.exclude_hv); @@ -1413,14 +1313,9 @@ static int test__leader_sample1(struct evlist *evlis= t) evlist->core.nr_entries =3D=3D (3 * num_core_entries())); =20 for (int i =3D 0; i < num_core_entries(); i++) { - int ret; - /* cycles - sampling group leader */ evsel =3D leader =3D (i =3D=3D 0 ? evlist__first(evlist) : evsel__next(e= vsel)); - ret =3D assert_hw(&evsel->core, PERF_COUNT_HW_CPU_CYCLES, "cycles"); - if (ret) - return ret; - + TEST_ASSERT_VAL("unexpected event", evsel__match(evsel, HARDWARE, HW_CPU= _CYCLES)); TEST_ASSERT_VAL("wrong exclude_user", !evsel->core.attr.exclude_user); TEST_ASSERT_VAL("wrong exclude_kernel", !evsel->core.attr.exclude_kernel= ); TEST_ASSERT_VAL("wrong exclude_hv", !evsel->core.attr.exclude_hv); @@ -1433,10 +1328,7 @@ static int test__leader_sample1(struct evlist *evlis= t) =20 /* cache-misses - not sampling */ evsel =3D evsel__next(evsel); - ret =3D assert_hw(&evsel->core, PERF_COUNT_HW_CACHE_MISSES, "cache-misse= s"); - if (ret) - return ret; - + TEST_ASSERT_VAL("unexpected event", evsel__match(evsel, HARDWARE, HW_CAC= HE_MISSES)); TEST_ASSERT_VAL("wrong exclude_user", !evsel->core.attr.exclude_user); TEST_ASSERT_VAL("wrong exclude_kernel", !evsel->core.attr.exclude_kernel= ); TEST_ASSERT_VAL("wrong exclude_hv", !evsel->core.attr.exclude_hv); @@ -1448,10 +1340,8 @@ static int test__leader_sample1(struct evlist *evlis= t) =20 /* branch-misses - not sampling */ evsel =3D evsel__next(evsel); - ret =3D assert_hw(&evsel->core, PERF_COUNT_HW_BRANCH_MISSES, "branch-mis= ses"); - if (ret) - return ret; - + TEST_ASSERT_VAL("unexpected event", + evsel__match(evsel, HARDWARE, HW_BRANCH_MISSES)); TEST_ASSERT_VAL("wrong exclude_user", !evsel->core.attr.exclude_user); TEST_ASSERT_VAL("wrong exclude_kernel", !evsel->core.attr.exclude_kernel= ); TEST_ASSERT_VAL("wrong exclude_hv", !evsel->core.attr.exclude_hv); @@ -1473,14 +1363,9 @@ static int test__leader_sample2(struct evlist *evlis= t __maybe_unused) evlist->core.nr_entries =3D=3D (2 * num_core_entries())); =20 for (int i =3D 0; i < num_core_entries(); i++) { - int ret; - /* instructions - sampling group leader */ evsel =3D leader =3D (i =3D=3D 0 ? evlist__first(evlist) : evsel__next(e= vsel)); - ret =3D assert_hw(&evsel->core, PERF_COUNT_HW_INSTRUCTIONS, "instruction= s"); - if (ret) - return ret; - + TEST_ASSERT_VAL("unexpected event", evsel__match(evsel, HARDWARE, HW_INS= TRUCTIONS)); TEST_ASSERT_VAL("wrong exclude_user", !evsel->core.attr.exclude_user); TEST_ASSERT_VAL("wrong exclude_kernel", evsel->core.attr.exclude_kernel); TEST_ASSERT_VAL("wrong exclude_hv", evsel->core.attr.exclude_hv); @@ -1493,10 +1378,8 @@ static int test__leader_sample2(struct evlist *evlis= t __maybe_unused) =20 /* branch-misses - not sampling */ evsel =3D evsel__next(evsel); - ret =3D assert_hw(&evsel->core, PERF_COUNT_HW_BRANCH_MISSES, "branch-mis= ses"); - if (ret) - return ret; - + TEST_ASSERT_VAL("unexpected event", + evsel__match(evsel, HARDWARE, HW_BRANCH_MISSES)); TEST_ASSERT_VAL("wrong exclude_user", !evsel->core.attr.exclude_user); TEST_ASSERT_VAL("wrong exclude_kernel", evsel->core.attr.exclude_kernel); TEST_ASSERT_VAL("wrong exclude_hv", evsel->core.attr.exclude_hv); @@ -1536,14 +1419,9 @@ static int test__pinned_group(struct evlist *evlist) evlist->core.nr_entries =3D=3D (3 * num_core_entries())); =20 for (int i =3D 0; i < num_core_entries(); i++) { - int ret; - /* cycles - group leader */ evsel =3D leader =3D (i =3D=3D 0 ? evlist__first(evlist) : evsel__next(e= vsel)); - ret =3D assert_hw(&evsel->core, PERF_COUNT_HW_CPU_CYCLES, "cycles"); - if (ret) - return ret; - + TEST_ASSERT_VAL("unexpected event", evsel__match(evsel, HARDWARE, HW_CPU= _CYCLES)); TEST_ASSERT_VAL("wrong group name", !evsel->group_name); TEST_ASSERT_VAL("wrong leader", evsel__has_leader(evsel, leader)); /* TODO: The group modifier is not copied to the split group leader. */ @@ -1552,18 +1430,13 @@ static int test__pinned_group(struct evlist *evlist) =20 /* cache-misses - can not be pinned, but will go on with the leader */ evsel =3D evsel__next(evsel); - ret =3D assert_hw(&evsel->core, PERF_COUNT_HW_CACHE_MISSES, "cache-misse= s"); - if (ret) - return ret; - + TEST_ASSERT_VAL("unexpected event", evsel__match(evsel, HARDWARE, HW_CAC= HE_MISSES)); TEST_ASSERT_VAL("wrong pinned", !evsel->core.attr.pinned); =20 /* branch-misses - ditto */ evsel =3D evsel__next(evsel); - ret =3D assert_hw(&evsel->core, PERF_COUNT_HW_BRANCH_MISSES, "branch-mis= ses"); - if (ret) - return ret; - + TEST_ASSERT_VAL("unexpected event", + evsel__match(evsel, HARDWARE, HW_BRANCH_MISSES)); TEST_ASSERT_VAL("wrong pinned", !evsel->core.attr.pinned); } return TEST_OK; @@ -1590,14 +1463,9 @@ static int test__exclusive_group(struct evlist *evli= st) evlist->core.nr_entries =3D=3D 3 * num_core_entries()); =20 for (int i =3D 0; i < num_core_entries(); i++) { - int ret; - /* cycles - group leader */ evsel =3D leader =3D (i =3D=3D 0 ? evlist__first(evlist) : evsel__next(e= vsel)); - ret =3D assert_hw(&evsel->core, PERF_COUNT_HW_CPU_CYCLES, "cycles"); - if (ret) - return ret; - + TEST_ASSERT_VAL("unexpected event", evsel__match(evsel, HARDWARE, HW_CPU= _CYCLES)); TEST_ASSERT_VAL("wrong group name", !evsel->group_name); TEST_ASSERT_VAL("wrong leader", evsel__has_leader(evsel, leader)); /* TODO: The group modifier is not copied to the split group leader. */ @@ -1606,18 +1474,13 @@ static int test__exclusive_group(struct evlist *evl= ist) =20 /* cache-misses - can not be pinned, but will go on with the leader */ evsel =3D evsel__next(evsel); - ret =3D assert_hw(&evsel->core, PERF_COUNT_HW_CACHE_MISSES, "cache-misse= s"); - if (ret) - return ret; - + TEST_ASSERT_VAL("unexpected event", evsel__match(evsel, HARDWARE, HW_CAC= HE_MISSES)); TEST_ASSERT_VAL("wrong exclusive", !evsel->core.attr.exclusive); =20 /* branch-misses - ditto */ evsel =3D evsel__next(evsel); - ret =3D assert_hw(&evsel->core, PERF_COUNT_HW_BRANCH_MISSES, "branch-mis= ses"); - if (ret) - return ret; - + TEST_ASSERT_VAL("unexpected event", + evsel__match(evsel, HARDWARE, HW_BRANCH_MISSES)); TEST_ASSERT_VAL("wrong exclusive", !evsel->core.attr.exclusive); } return TEST_OK; @@ -1628,7 +1491,7 @@ static int test__checkevent_breakpoint_len(struct evl= ist *evlist) =20 TEST_ASSERT_VAL("wrong number of entries", 1 =3D=3D evlist->core.nr_entri= es); TEST_ASSERT_VAL("wrong type", PERF_TYPE_BREAKPOINT =3D=3D evsel->core.att= r.type); - TEST_ASSERT_VAL("wrong config", test_config(evsel, 0)); + TEST_ASSERT_VAL("wrong config", 0 =3D=3D evsel->core.attr.config); TEST_ASSERT_VAL("wrong bp_type", (HW_BREAKPOINT_R | HW_BREAKPOINT_W) =3D= =3D evsel->core.attr.bp_type); TEST_ASSERT_VAL("wrong bp_len", HW_BREAKPOINT_LEN_1 =3D=3D @@ -1643,7 +1506,7 @@ static int test__checkevent_breakpoint_len_w(struct e= vlist *evlist) =20 TEST_ASSERT_VAL("wrong number of entries", 1 =3D=3D evlist->core.nr_entri= es); TEST_ASSERT_VAL("wrong type", PERF_TYPE_BREAKPOINT =3D=3D evsel->core.att= r.type); - TEST_ASSERT_VAL("wrong config", test_config(evsel, 0)); + TEST_ASSERT_VAL("wrong config", 0 =3D=3D evsel->core.attr.config); TEST_ASSERT_VAL("wrong bp_type", HW_BREAKPOINT_W =3D=3D evsel->core.attr.bp_type); TEST_ASSERT_VAL("wrong bp_len", HW_BREAKPOINT_LEN_2 =3D=3D @@ -1671,8 +1534,7 @@ static int test__checkevent_precise_max_modifier(stru= ct evlist *evlist) =20 TEST_ASSERT_VAL("wrong number of entries", evlist->core.nr_entries =3D=3D 1 + num_core_entries()); - TEST_ASSERT_VAL("wrong type", PERF_TYPE_SOFTWARE =3D=3D evsel->core.attr.= type); - TEST_ASSERT_VAL("wrong config", test_config(evsel, PERF_COUNT_SW_TASK_CLO= CK)); + TEST_ASSERT_VAL("wrong type/config", evsel__match(evsel, SOFTWARE, SW_TAS= K_CLOCK)); return TEST_OK; } =20 @@ -1752,18 +1614,15 @@ static int test__checkevent_raw_pmu(struct evlist *= evlist) =20 TEST_ASSERT_VAL("wrong number of entries", 1 =3D=3D evlist->core.nr_entri= es); TEST_ASSERT_VAL("wrong type", PERF_TYPE_SOFTWARE =3D=3D evsel->core.attr.= type); - TEST_ASSERT_VAL("wrong config", test_config(evsel, 0x1a)); + TEST_ASSERT_VAL("wrong config", 0x1a =3D=3D evsel->core.attr.config); return TEST_OK; } =20 static int test__sym_event_slash(struct evlist *evlist) { struct evsel *evsel =3D evlist__first(evlist); - int ret =3D assert_hw(&evsel->core, PERF_COUNT_HW_CPU_CYCLES, "cycles"); - - if (ret) - return ret; =20 + TEST_ASSERT_VAL("unexpected event", evsel__match(evsel, HARDWARE, HW_CPU_= CYCLES)); TEST_ASSERT_VAL("wrong exclude_kernel", evsel->core.attr.exclude_kernel); return TEST_OK; } @@ -1771,11 +1630,8 @@ static int test__sym_event_slash(struct evlist *evli= st) static int test__sym_event_dc(struct evlist *evlist) { struct evsel *evsel =3D evlist__first(evlist); - int ret =3D assert_hw(&evsel->core, PERF_COUNT_HW_CPU_CYCLES, "cycles"); - - if (ret) - return ret; =20 + TEST_ASSERT_VAL("unexpected event", evsel__match(evsel, HARDWARE, HW_CPU_= CYCLES)); TEST_ASSERT_VAL("wrong exclude_user", evsel->core.attr.exclude_user); return TEST_OK; } @@ -1783,11 +1639,8 @@ static int test__sym_event_dc(struct evlist *evlist) static int test__term_equal_term(struct evlist *evlist) { struct evsel *evsel =3D evlist__first(evlist); - int ret =3D assert_hw(&evsel->core, PERF_COUNT_HW_CPU_CYCLES, "cycles"); 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Mon, 22 Sep 2025 21:19:37 -0700 (PDT) Date: Mon, 22 Sep 2025 21:18:41 -0700 In-Reply-To: <20250923041844.400164-1-irogers@google.com> Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: Mime-Version: 1.0 References: <20250923041844.400164-1-irogers@google.com> X-Mailer: git-send-email 2.51.0.534.gc79095c0ca-goog Message-ID: <20250923041844.400164-23-irogers@google.com> Subject: [PATCH v5 22/25] perf test parse-events: Remove cpu PMU requirement From: Ian Rogers To: Peter Zijlstra , Ingo Molnar , Arnaldo Carvalho de Melo , Namhyung Kim , Mark Rutland , Alexander Shishkin , Jiri Olsa , Ian Rogers , Adrian Hunter , Kan Liang , James Clark , Xu Yang , Thomas Falcon , Andi Kleen , linux-kernel@vger.kernel.org, linux-perf-users@vger.kernel.org, bpf@vger.kernel.org, Atish Patra , Beeman Strong , Leo Yan , Vince Weaver Content-Transfer-Encoding: quoted-printable Content-Type: text/plain; charset="utf-8" In the event parse string, switch "cpu" to "default_core" and then rewrite this to the first core PMU name prior to parsing. This enables testing with a PMU on hybrid x86 and other systems that don't use "cpu" for the core PMU name. The name "default_core" is already used by jevents. Update test expectations to match. Signed-off-by: Ian Rogers --- tools/perf/tests/parse-events.c | 141 ++++++++++++++------------------ 1 file changed, 63 insertions(+), 78 deletions(-) diff --git a/tools/perf/tests/parse-events.c b/tools/perf/tests/parse-event= s.c index d0f1e05139ac..4f197f34621b 100644 --- a/tools/perf/tests/parse-events.c +++ b/tools/perf/tests/parse-events.c @@ -646,19 +646,22 @@ static int test__checkevent_list(struct evlist *evlis= t) static int test__checkevent_pmu_name(struct evlist *evlist) { struct evsel *evsel =3D evlist__first(evlist); + struct perf_pmu *core_pmu =3D perf_pmus__find_core_pmu(); + char buf[256]; =20 - /* cpu/config=3D1,name=3Dkrava/u */ + /* default_core/config=3D1,name=3Dkrava/u */ TEST_ASSERT_VAL("wrong number of entries", 2 =3D=3D evlist->core.nr_entri= es); TEST_ASSERT_VAL("wrong type", PERF_TYPE_RAW =3D=3D evsel->core.attr.type); TEST_ASSERT_VAL("wrong config", 1 =3D=3D evsel->core.attr.config); TEST_ASSERT_VAL("wrong name", evsel__name_is(evsel, "krava")); =20 - /* cpu/config=3D2/u" */ + /* default_core/config=3D2/u" */ evsel =3D evsel__next(evsel); TEST_ASSERT_VAL("wrong number of entries", 2 =3D=3D evlist->core.nr_entri= es); TEST_ASSERT_VAL("wrong type", PERF_TYPE_RAW =3D=3D evsel->core.attr.type); TEST_ASSERT_VAL("wrong config", 2 =3D=3D evsel->core.attr.config); - TEST_ASSERT_VAL("wrong name", evsel__name_is(evsel, "cpu/config=3D2/u")); + snprintf(buf, sizeof(buf), "%s/config=3D2/u", core_pmu->name); + TEST_ASSERT_VAL("wrong name", evsel__name_is(evsel, buf)); =20 return TEST_OK; } @@ -667,7 +670,7 @@ static int test__checkevent_pmu_partial_time_callgraph(= struct evlist *evlist) { struct evsel *evsel =3D evlist__first(evlist); =20 - /* cpu/config=3D1,call-graph=3Dfp,time,period=3D100000/ */ + /* default_core/config=3D1,call-graph=3Dfp,time,period=3D100000/ */ TEST_ASSERT_VAL("wrong number of entries", 2 =3D=3D evlist->core.nr_entri= es); TEST_ASSERT_VAL("wrong type", PERF_TYPE_RAW =3D=3D evsel->core.attr.type); TEST_ASSERT_VAL("wrong config", 1 =3D=3D evsel->core.attr.config); @@ -679,7 +682,7 @@ static int test__checkevent_pmu_partial_time_callgraph(= struct evlist *evlist) TEST_ASSERT_VAL("wrong callgraph", !evsel__has_callchain(evsel)); TEST_ASSERT_VAL("wrong time", !(PERF_SAMPLE_TIME & evsel->core.attr.samp= le_type)); =20 - /* cpu/config=3D2,call-graph=3Dno,time=3D0,period=3D2000/ */ + /* default_core/config=3D2,call-graph=3Dno,time=3D0,period=3D2000/ */ evsel =3D evsel__next(evsel); TEST_ASSERT_VAL("wrong type", PERF_TYPE_RAW =3D=3D evsel->core.attr.type); TEST_ASSERT_VAL("wrong config", 2 =3D=3D evsel->core.attr.config); @@ -702,7 +705,8 @@ static int test__checkevent_pmu_events(struct evlist *e= vlist) =20 evlist__for_each_entry(evlist, evsel) { TEST_ASSERT_VAL("wrong type", PERF_TYPE_RAW =3D=3D evsel->core.attr.type= || - strcmp(evsel->pmu->name, "cpu")); + !strncmp(evsel__name(evsel), evsel->pmu->name, + strlen(evsel->pmu->name))); TEST_ASSERT_VAL("wrong exclude_user", !evsel->core.attr.exclude_user); TEST_ASSERT_VAL("wrong exclude_kernel", evsel->core.attr.exclude_kernel); TEST_ASSERT_VAL("wrong exclude_hv", evsel->core.attr.exclude_hv); @@ -735,7 +739,7 @@ static int test__checkevent_pmu_events_mix(struct evlis= t *evlist) TEST_ASSERT_VAL("wrong pinned", !evsel->core.attr.pinned); TEST_ASSERT_VAL("wrong exclusive", !evsel->core.attr.exclusive); } - /* cpu/pmu-event/u*/ + /* default_core/pmu-event/u*/ evsel =3D evsel__next(evsel); TEST_ASSERT_VAL("wrong type", evsel__find_pmu(evsel)->is_core); TEST_ASSERT_VAL("wrong exclude_user", @@ -1570,14 +1574,9 @@ static int test__checkevent_config_cache(struct evli= st *evlist) return test__checkevent_genhw(evlist); } =20 -static bool test__pmu_cpu_valid(void) +static bool test__pmu_default_core_event_valid(void) { - return !!perf_pmus__find("cpu"); -} - -static bool test__pmu_cpu_event_valid(void) -{ - struct perf_pmu *pmu =3D perf_pmus__find("cpu"); + struct perf_pmu *pmu =3D perf_pmus__find_core_pmu(); =20 if (!pmu) return false; @@ -2103,26 +2102,23 @@ static const struct evlist_test test__events[] =3D { =20 static const struct evlist_test test__events_pmu[] =3D { { - .name =3D "cpu/config=3D10,config1=3D1,config2=3D3,period=3D1000/u", - .valid =3D test__pmu_cpu_valid, + .name =3D "default_core/config=3D10,config1=3D1,config2=3D3,period=3D10= 00/u", .check =3D test__checkevent_pmu, /* 0 */ }, { - .name =3D "cpu/config=3D1,name=3Dkrava/u,cpu/config=3D2/u", - .valid =3D test__pmu_cpu_valid, + .name =3D "default_core/config=3D1,name=3Dkrava/u,default_core/config= =3D2/u", .check =3D test__checkevent_pmu_name, /* 1 */ }, { - .name =3D "cpu/config=3D1,call-graph=3Dfp,time,period=3D100000/,cpu/con= fig=3D2,call-graph=3Dno,time=3D0,period=3D2000/", - .valid =3D test__pmu_cpu_valid, + .name =3D "default_core/config=3D1,call-graph=3Dfp,time,period=3D100000= /,default_core/config=3D2,call-graph=3Dno,time=3D0,period=3D2000/", .check =3D test__checkevent_pmu_partial_time_callgraph, /* 2 */ }, { - .name =3D "cpu/name=3D'COMPLEX_CYCLES_NAME:orig=3Dcycles,desc=3Dchip-cl= ock-ticks',period=3D0x1,event=3D0x2/ukp", - .valid =3D test__pmu_cpu_event_valid, + .name =3D "default_core/name=3D'COMPLEX_CYCLES_NAME:orig=3Dcycles,desc= =3Dchip-clock-ticks',period=3D0x1,event=3D0x2/ukp", + .valid =3D test__pmu_default_core_event_valid, .check =3D test__checkevent_complex_name, /* 3 */ }, @@ -2137,158 +2133,132 @@ static const struct evlist_test test__events_pmu[= ] =3D { /* 5 */ }, { - .name =3D "cpu/L1-dcache-load-miss/", - .valid =3D test__pmu_cpu_valid, + .name =3D "default_core/L1-dcache-load-miss/", .check =3D test__checkevent_genhw, /* 6 */ }, { - .name =3D "cpu/L1-dcache-load-miss/kp", - .valid =3D test__pmu_cpu_valid, + .name =3D "default_core/L1-dcache-load-miss/kp", .check =3D test__checkevent_genhw_modifier, /* 7 */ }, { - .name =3D "cpu/L1-dcache-misses,name=3Dcachepmu/", - .valid =3D test__pmu_cpu_valid, + .name =3D "default_core/L1-dcache-misses,name=3Dcachepmu/", .check =3D test__checkevent_config_cache, /* 8 */ }, { - .name =3D "cpu/instructions/", - .valid =3D test__pmu_cpu_valid, + .name =3D "default_core/instructions/", .check =3D test__checkevent_symbolic_name, /* 9 */ }, { - .name =3D "cpu/cycles,period=3D100000,config2/", - .valid =3D test__pmu_cpu_valid, + .name =3D "default_core/cycles,period=3D100000,config2/", .check =3D test__checkevent_symbolic_name_config, /* 0 */ }, { - .name =3D "cpu/instructions/h", - .valid =3D test__pmu_cpu_valid, + .name =3D "default_core/instructions/h", .check =3D test__checkevent_symbolic_name_modifier, /* 1 */ }, { - .name =3D "cpu/instructions/G", - .valid =3D test__pmu_cpu_valid, + .name =3D "default_core/instructions/G", .check =3D test__checkevent_exclude_host_modifier, /* 2 */ }, { - .name =3D "cpu/instructions/H", - .valid =3D test__pmu_cpu_valid, + .name =3D "default_core/instructions/H", .check =3D test__checkevent_exclude_guest_modifier, /* 3 */ }, { - .name =3D "{cpu/instructions/k,cpu/cycles/upp}", - .valid =3D test__pmu_cpu_valid, + .name =3D "{default_core/instructions/k,default_core/cycles/upp}", .check =3D test__group1, /* 4 */ }, { - .name =3D "{cpu/cycles/u,cpu/instructions/kp}:p", - .valid =3D test__pmu_cpu_valid, + .name =3D "{default_core/cycles/u,default_core/instructions/kp}:p", .check =3D test__group4, /* 5 */ }, { - .name =3D "{cpu/cycles/,cpu/cache-misses/G}:H", - .valid =3D test__pmu_cpu_valid, + .name =3D "{default_core/cycles/,default_core/cache-misses/G}:H", .check =3D test__group_gh1, /* 6 */ }, { - .name =3D "{cpu/cycles/,cpu/cache-misses/H}:G", - .valid =3D test__pmu_cpu_valid, + .name =3D "{default_core/cycles/,default_core/cache-misses/H}:G", .check =3D test__group_gh2, /* 7 */ }, { - .name =3D "{cpu/cycles/G,cpu/cache-misses/H}:u", - .valid =3D test__pmu_cpu_valid, + .name =3D "{default_core/cycles/G,default_core/cache-misses/H}:u", .check =3D test__group_gh3, /* 8 */ }, { - .name =3D "{cpu/cycles/G,cpu/cache-misses/H}:uG", - .valid =3D test__pmu_cpu_valid, + .name =3D "{default_core/cycles/G,default_core/cache-misses/H}:uG", .check =3D test__group_gh4, /* 9 */ }, { - .name =3D "{cpu/cycles/,cpu/cache-misses/,cpu/branch-misses/}:S", - .valid =3D test__pmu_cpu_valid, + .name =3D "{default_core/cycles/,default_core/cache-misses/,default_cor= e/branch-misses/}:S", .check =3D test__leader_sample1, /* 0 */ }, { - .name =3D "{cpu/instructions/,cpu/branch-misses/}:Su", - .valid =3D test__pmu_cpu_valid, + .name =3D "{default_core/instructions/,default_core/branch-misses/}:Su", .check =3D test__leader_sample2, /* 1 */ }, { - .name =3D "cpu/instructions/uDp", - .valid =3D test__pmu_cpu_valid, + .name =3D "default_core/instructions/uDp", .check =3D test__checkevent_pinned_modifier, /* 2 */ }, { - .name =3D "{cpu/cycles/,cpu/cache-misses/,cpu/branch-misses/}:D", - .valid =3D test__pmu_cpu_valid, + .name =3D "{default_core/cycles/,default_core/cache-misses/,default_cor= e/branch-misses/}:D", .check =3D test__pinned_group, /* 3 */ }, { - .name =3D "cpu/instructions/I", - .valid =3D test__pmu_cpu_valid, + .name =3D "default_core/instructions/I", .check =3D test__checkevent_exclude_idle_modifier, /* 4 */ }, { - .name =3D "cpu/instructions/kIG", - .valid =3D test__pmu_cpu_valid, + .name =3D "default_core/instructions/kIG", .check =3D test__checkevent_exclude_idle_modifier_1, /* 5 */ }, { - .name =3D "cpu/cycles/u", - .valid =3D test__pmu_cpu_valid, + .name =3D "default_core/cycles/u", .check =3D test__sym_event_slash, /* 6 */ }, { - .name =3D "cpu/cycles/k", - .valid =3D test__pmu_cpu_valid, + .name =3D "default_core/cycles/k", .check =3D test__sym_event_dc, /* 7 */ }, { - .name =3D "cpu/instructions/uep", - .valid =3D test__pmu_cpu_valid, + .name =3D "default_core/instructions/uep", .check =3D test__checkevent_exclusive_modifier, /* 8 */ }, { - .name =3D "{cpu/cycles/,cpu/cache-misses/,cpu/branch-misses/}:e", - .valid =3D test__pmu_cpu_valid, + .name =3D "{default_core/cycles/,default_core/cache-misses/,default_cor= e/branch-misses/}:e", .check =3D test__exclusive_group, /* 9 */ }, { - .name =3D "cpu/cycles,name=3Dname/", - .valid =3D test__pmu_cpu_valid, + .name =3D "default_core/cycles,name=3Dname/", .check =3D test__term_equal_term, /* 0 */ }, { - .name =3D "cpu/cycles,name=3Dl1d/", - .valid =3D test__pmu_cpu_valid, + .name =3D "default_core/cycles,name=3Dl1d/", .check =3D test__term_equal_legacy, /* 1 */ }, @@ -2378,15 +2348,30 @@ static int combine_test_results(int existing, int l= atest) static int test_events(const struct evlist_test *events, int cnt) { int ret =3D TEST_OK; + struct perf_pmu *core_pmu =3D perf_pmus__find_core_pmu(); =20 for (int i =3D 0; i < cnt; i++) { - const struct evlist_test *e =3D &events[i]; + struct evlist_test e =3D events[i]; int test_ret; + const char *pos =3D e.name; + char buf[1024], *buf_pos =3D buf, *end; + + while ((end =3D strstr(pos, "default_core"))) { + size_t len =3D end - pos; + + strncpy(buf_pos, pos, len); + pos =3D end + 12; + buf_pos +=3D len; + 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u/xyW+VBbjee2Xq+iuMKREC+qtyD+XQ8myasOCNnhbZa21navXhkCQNIAEJsF4+yfpsNUezIrXn Bbjjlg8CNhA== X-Google-Smtp-Source: AGHT+IGWp2qzmdaD/9P+NZzg4BtuVDVcrbuR6Y4GJ3eU5LtzSkHc0WCx5dhdYZWvarADZIxi3DZGFesI+ygN X-Received: from pgci187.prod.google.com ([2002:a63:6dc4:0:b0:b4e:547e:d9bd]) (user=irogers job=prod-delivery.src-stubby-dispatcher) by 2002:a05:6a20:748a:b0:262:9461:2e5b with SMTP id adf61e73a8af0-2cffd6a334bmr1811288637.53.1758601179660; Mon, 22 Sep 2025 21:19:39 -0700 (PDT) Date: Mon, 22 Sep 2025 21:18:42 -0700 In-Reply-To: <20250923041844.400164-1-irogers@google.com> Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: Mime-Version: 1.0 References: <20250923041844.400164-1-irogers@google.com> X-Mailer: git-send-email 2.51.0.534.gc79095c0ca-goog Message-ID: <20250923041844.400164-24-irogers@google.com> Subject: [PATCH v5 23/25] perf test parse-events: Without a PMU use cpu-cycles rather than cycles From: Ian Rogers To: Peter Zijlstra , Ingo Molnar , Arnaldo Carvalho de Melo , Namhyung Kim , Mark Rutland , Alexander Shishkin , Jiri Olsa , Ian Rogers , Adrian Hunter , Kan Liang , James Clark , Xu Yang , Thomas Falcon , Andi Kleen , linux-kernel@vger.kernel.org, linux-perf-users@vger.kernel.org, bpf@vger.kernel.org, Atish Patra , Beeman Strong , Leo Yan , Vince Weaver Content-Transfer-Encoding: quoted-printable Content-Type: text/plain; charset="utf-8" Without a PMU perf matches an event against any PMU with the event. Unfortunately some PMU drivers advertise a "cycles" event which is typically just a core event. Switch to using "cpu-cycles" which is an indentical legacy event but avoids the multiple PMU confusion introduced by the PMU drivers. Note, on x86 cpu-cycles is also a sysfs event but cycles isn't. Signed-off-by: Ian Rogers --- tools/perf/tests/parse-events.c | 57 +++++++++++++++++---------------- 1 file changed, 30 insertions(+), 27 deletions(-) diff --git a/tools/perf/tests/parse-events.c b/tools/perf/tests/parse-event= s.c index 4f197f34621b..8a48a671e593 100644 --- a/tools/perf/tests/parse-events.c +++ b/tools/perf/tests/parse-events.c @@ -585,9 +585,10 @@ static int test__checkevent_pmu(struct evlist *evlist) { =20 struct evsel *evsel =3D evlist__first(evlist); + struct perf_pmu *core_pmu =3D perf_pmus__find_core_pmu(); =20 TEST_ASSERT_VAL("wrong number of entries", 1 =3D=3D evlist->core.nr_entri= es); - TEST_ASSERT_VAL("wrong type", PERF_TYPE_RAW =3D=3D evsel->core.attr.type); + TEST_ASSERT_VAL("wrong type", core_pmu->type =3D=3D evsel->core.attr.type= ); TEST_ASSERT_VAL("wrong config", test_config(evsel, 10)); TEST_ASSERT_VAL("wrong config1", 1 =3D=3D evsel->core.attr.config1); TEST_ASSERT_VAL("wrong config2", 3 =3D=3D evsel->core.attr.config2); @@ -651,14 +652,14 @@ static int test__checkevent_pmu_name(struct evlist *e= vlist) =20 /* default_core/config=3D1,name=3Dkrava/u */ TEST_ASSERT_VAL("wrong number of entries", 2 =3D=3D evlist->core.nr_entri= es); - TEST_ASSERT_VAL("wrong type", PERF_TYPE_RAW =3D=3D evsel->core.attr.type); + TEST_ASSERT_VAL("wrong type", core_pmu->type =3D=3D evsel->core.attr.type= ); TEST_ASSERT_VAL("wrong config", 1 =3D=3D evsel->core.attr.config); TEST_ASSERT_VAL("wrong name", evsel__name_is(evsel, "krava")); =20 /* default_core/config=3D2/u" */ evsel =3D evsel__next(evsel); TEST_ASSERT_VAL("wrong number of entries", 2 =3D=3D evlist->core.nr_entri= es); - TEST_ASSERT_VAL("wrong type", PERF_TYPE_RAW =3D=3D evsel->core.attr.type); + TEST_ASSERT_VAL("wrong type", core_pmu->type =3D=3D evsel->core.attr.type= ); TEST_ASSERT_VAL("wrong config", 2 =3D=3D evsel->core.attr.config); snprintf(buf, sizeof(buf), "%s/config=3D2/u", core_pmu->name); TEST_ASSERT_VAL("wrong name", evsel__name_is(evsel, buf)); @@ -669,10 +670,11 @@ static int test__checkevent_pmu_name(struct evlist *e= vlist) static int test__checkevent_pmu_partial_time_callgraph(struct evlist *evli= st) { struct evsel *evsel =3D evlist__first(evlist); + struct perf_pmu *core_pmu =3D perf_pmus__find_core_pmu(); =20 /* default_core/config=3D1,call-graph=3Dfp,time,period=3D100000/ */ TEST_ASSERT_VAL("wrong number of entries", 2 =3D=3D evlist->core.nr_entri= es); - TEST_ASSERT_VAL("wrong type", PERF_TYPE_RAW =3D=3D evsel->core.attr.type); + TEST_ASSERT_VAL("wrong type", core_pmu->type =3D=3D evsel->core.attr.type= ); TEST_ASSERT_VAL("wrong config", 1 =3D=3D evsel->core.attr.config); /* * The period, time and callgraph value gets configured within evlist__co= nfig, @@ -684,7 +686,7 @@ static int test__checkevent_pmu_partial_time_callgraph(= struct evlist *evlist) =20 /* default_core/config=3D2,call-graph=3Dno,time=3D0,period=3D2000/ */ evsel =3D evsel__next(evsel); - TEST_ASSERT_VAL("wrong type", PERF_TYPE_RAW =3D=3D evsel->core.attr.type); + TEST_ASSERT_VAL("wrong type", core_pmu->type =3D=3D evsel->core.attr.type= ); TEST_ASSERT_VAL("wrong config", 2 =3D=3D evsel->core.attr.config); /* * The period, time and callgraph value gets configured within evlist__co= nfig, @@ -700,11 +702,12 @@ static int test__checkevent_pmu_partial_time_callgrap= h(struct evlist *evlist) static int test__checkevent_pmu_events(struct evlist *evlist) { struct evsel *evsel; + struct perf_pmu *core_pmu =3D perf_pmus__find_core_pmu(); =20 TEST_ASSERT_VAL("wrong number of entries", 1 <=3D evlist->core.nr_entries= ); =20 evlist__for_each_entry(evlist, evsel) { - TEST_ASSERT_VAL("wrong type", PERF_TYPE_RAW =3D=3D evsel->core.attr.type= || + TEST_ASSERT_VAL("wrong type", core_pmu->type =3D=3D evsel->core.attr.typ= e || !strncmp(evsel__name(evsel), evsel->pmu->name, strlen(evsel->pmu->name))); TEST_ASSERT_VAL("wrong exclude_user", !evsel->core.attr.exclude_user); @@ -1603,7 +1606,7 @@ static int test__checkevent_complex_name(struct evlis= t *evlist) =20 TEST_ASSERT_VAL("wrong complex name parsing", evsel__name_is(evsel, - "COMPLEX_CYCLES_NAME:orig=3Dcycles,desc=3Dchip-clock-ticks")); + "COMPLEX_CYCLES_NAME:orig=3Dcpu-cycles,desc=3Dchip-clock-ticks"= )); return TEST_OK; } =20 @@ -1740,7 +1743,7 @@ static const struct evlist_test test__events[] =3D { /* 4 */ }, { - .name =3D "cycles/period=3D100000,config2/", + .name =3D "cpu-cycles/period=3D100000,config2/", .check =3D test__checkevent_symbolic_name_config, /* 5 */ }, @@ -1855,27 +1858,27 @@ static const struct evlist_test test__events[] =3D { /* 7 */ }, { - .name =3D "{instructions:k,cycles:upp}", + .name =3D "{instructions:k,cpu-cycles:upp}", .check =3D test__group1, /* 8 */ }, { - .name =3D "{faults:k,branches}:u,cycles:k", + .name =3D "{faults:k,branches}:u,cpu-cycles:k", .check =3D test__group2, /* 9 */ }, { - .name =3D "group1{syscalls:sys_enter_openat:H,cycles:kppp},group2{cycle= s,1:3}:G,instructions:u", + .name =3D "group1{syscalls:sys_enter_openat:H,cpu-cycles:kppp},group2{c= pu-cycles,1:3}:G,instructions:u", .check =3D test__group3, /* 0 */ }, { - .name =3D "{cycles:u,instructions:kp}:p", + .name =3D "{cpu-cycles:u,instructions:kp}:p", .check =3D test__group4, /* 1 */ }, { - .name =3D "{cycles,instructions}:G,{cycles:G,instructions:G},cycles", + .name =3D "{cpu-cycles,instructions}:G,{cpu-cycles:G,instructions:G},cp= u-cycles", .check =3D test__group5, /* 2 */ }, @@ -1885,27 +1888,27 @@ static const struct evlist_test test__events[] =3D { /* 3 */ }, { - .name =3D "{cycles,cache-misses:G}:H", + .name =3D "{cpu-cycles,cache-misses:G}:H", .check =3D test__group_gh1, /* 4 */ }, { - .name =3D "{cycles,cache-misses:H}:G", + .name =3D "{cpu-cycles,cache-misses:H}:G", .check =3D test__group_gh2, /* 5 */ }, { - .name =3D "{cycles:G,cache-misses:H}:u", + .name =3D "{cpu-cycles:G,cache-misses:H}:u", .check =3D test__group_gh3, /* 6 */ }, { - .name =3D "{cycles:G,cache-misses:H}:uG", + .name =3D "{cpu-cycles:G,cache-misses:H}:uG", .check =3D test__group_gh4, /* 7 */ }, { - .name =3D "{cycles,cache-misses,branch-misses}:S", + .name =3D "{cpu-cycles,cache-misses,branch-misses}:S", .check =3D test__leader_sample1, /* 8 */ }, @@ -1920,7 +1923,7 @@ static const struct evlist_test test__events[] =3D { /* 0 */ }, { - .name =3D "{cycles,cache-misses,branch-misses}:D", + .name =3D "{cpu-cycles,cache-misses,branch-misses}:D", .check =3D test__pinned_group, /* 1 */ }, @@ -1958,7 +1961,7 @@ static const struct evlist_test test__events[] =3D { /* 6 */ }, { - .name =3D "task-clock:P,cycles", + .name =3D "task-clock:P,cpu-cycles", .check =3D test__checkevent_precise_max_modifier, /* 7 */ }, @@ -1989,17 +1992,17 @@ static const struct evlist_test test__events[] =3D { /* 2 */ }, { - .name =3D "cycles/name=3D'COMPLEX_CYCLES_NAME:orig=3Dcycles,desc=3Dchip= -clock-ticks'/Duk", + .name =3D "cpu-cycles/name=3D'COMPLEX_CYCLES_NAME:orig=3Dcpu-cycles,des= c=3Dchip-clock-ticks'/Duk", .check =3D test__checkevent_complex_name, /* 3 */ }, { - .name =3D "cycles//u", + .name =3D "cpu-cycles//u", .check =3D test__sym_event_slash, /* 4 */ }, { - .name =3D "cycles:k", + .name =3D "cpu-cycles:k", .check =3D test__sym_event_dc, /* 5 */ }, @@ -2009,17 +2012,17 @@ static const struct evlist_test test__events[] =3D { /* 6 */ }, { - .name =3D "{cycles,cache-misses,branch-misses}:e", + .name =3D "{cpu-cycles,cache-misses,branch-misses}:e", .check =3D test__exclusive_group, /* 7 */ }, { - .name =3D "cycles/name=3Dname/", + .name =3D "cpu-cycles/name=3Dname/", .check =3D test__term_equal_term, /* 8 */ }, { - .name =3D "cycles/name=3Dl1d/", + .name =3D "cpu-cycles/name=3Dl1d/", .check =3D test__term_equal_legacy, /* 9 */ }, @@ -2117,7 +2120,7 @@ static const struct evlist_test test__events_pmu[] = =3D { /* 2 */ }, { - .name =3D "default_core/name=3D'COMPLEX_CYCLES_NAME:orig=3Dcycles,desc= =3Dchip-clock-ticks',period=3D0x1,event=3D0x2/ukp", + .name =3D "default_core/name=3D'COMPLEX_CYCLES_NAME:orig=3Dcpu-cycles,d= esc=3Dchip-clock-ticks',period=3D0x1,event=3D0x2/ukp", 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Mon, 22 Sep 2025 21:19:41 -0700 (PDT) Date: Mon, 22 Sep 2025 21:18:43 -0700 In-Reply-To: <20250923041844.400164-1-irogers@google.com> Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: Mime-Version: 1.0 References: <20250923041844.400164-1-irogers@google.com> X-Mailer: git-send-email 2.51.0.534.gc79095c0ca-goog Message-ID: <20250923041844.400164-25-irogers@google.com> Subject: [PATCH v5 24/25] perf stat: Avoid wildcarding PMUs for default events From: Ian Rogers To: Peter Zijlstra , Ingo Molnar , Arnaldo Carvalho de Melo , Namhyung Kim , Mark Rutland , Alexander Shishkin , Jiri Olsa , Ian Rogers , Adrian Hunter , Kan Liang , James Clark , Xu Yang , Thomas Falcon , Andi Kleen , linux-kernel@vger.kernel.org, linux-perf-users@vger.kernel.org, bpf@vger.kernel.org, Atish Patra , Beeman Strong , Leo Yan , Vince Weaver Content-Transfer-Encoding: quoted-printable Content-Type: text/plain; charset="utf-8" Without a PMU perf matches an event against any PMU with the event. Unfortunately some PMU drivers advertise a "cycles" event which is typically just a core event. To make perf's behavior consistent, just look up default events with their designated PMU types. Signed-off-by: Ian Rogers --- tools/perf/builtin-stat.c | 133 +++++++++++++++++++++++++++----------- 1 file changed, 94 insertions(+), 39 deletions(-) diff --git a/tools/perf/builtin-stat.c b/tools/perf/builtin-stat.c index 303628189004..4615aa3f2b7f 100644 --- a/tools/perf/builtin-stat.c +++ b/tools/perf/builtin-stat.c @@ -1824,6 +1824,38 @@ static int perf_stat_init_aggr_mode_file(struct perf= _stat *st) return 0; } =20 +/* Add given software event to evlist without wildcarding. */ +static int parse_software_event(struct evlist *evlist, const char *event, + struct parse_events_error *err) +{ + char buf[256]; + + snprintf(buf, sizeof(buf), "software/%s,name=3D%s/", event, event); + return parse_events(evlist, buf, err); +} + +/* Add legacy hardware/hardware-cache event to evlist for all core PMUs wi= thout wildcarding. */ +static int parse_hardware_event(struct evlist *evlist, const char *event, + struct parse_events_error *err) +{ + char buf[256]; + struct perf_pmu *pmu =3D NULL; + + while ((pmu =3D perf_pmus__scan_core(pmu)) !=3D NULL) { + int ret; + + if (perf_pmus__num_core_pmus() =3D=3D 1) + snprintf(buf, sizeof(buf), "%s/%s,name=3D%s/", pmu->name, event, event); + else + snprintf(buf, sizeof(buf), "%s/%s/", pmu->name, event); + + ret =3D parse_events(evlist, buf, err); + if (ret) + return ret; + } + return 0; +} + /* * Add default events, if there were no attributes specified or * if -d/--detailed, -d -d or -d -d -d is used: @@ -1947,26 +1979,31 @@ static int add_default_events(void) =20 if (!evlist->core.nr_entries && !evsel_list->core.nr_entries) { /* No events so add defaults. */ - if (target__has_cpu(&target)) - ret =3D parse_events(evlist, "cpu-clock", &err); - else - ret =3D parse_events(evlist, "task-clock", &err); - if (ret) - goto out; - - ret =3D parse_events(evlist, - "context-switches," - "cpu-migrations," - "page-faults," - "instructions," - "cycles," - "stalled-cycles-frontend," - "stalled-cycles-backend," - "branches," - "branch-misses", - &err); - if (ret) - goto out; + const char *sw_events[] =3D { + target__has_cpu(&target) ? "cpu-clock" : "task-clock", + "context-switches", + "cpu-migrations", + "page-faults", + }; + const char *hw_events[] =3D { + "instructions", + "cycles", + "stalled-cycles-frontend", + "stalled-cycles-backend", + "branches", + "branch-misses", + }; + + for (size_t i =3D 0; i < ARRAY_SIZE(sw_events); i++) { + ret =3D parse_software_event(evlist, sw_events[i], &err); + if (ret) + goto out; + } + for (size_t i =3D 0; i < ARRAY_SIZE(hw_events); i++) { + ret =3D parse_hardware_event(evlist, hw_events[i], &err); + if (ret) + goto out; + } =20 /* * Add TopdownL1 metrics if they exist. To minimize @@ -2008,35 +2045,53 @@ static int add_default_events(void) * Detailed stats (-d), covering the L1 and last level data * caches: */ - ret =3D parse_events(evlist, - "L1-dcache-loads," - "L1-dcache-load-misses," - "LLC-loads," - "LLC-load-misses", - &err); + const char *hw_events[] =3D { + "L1-dcache-loads", + "L1-dcache-load-misses", + "LLC-loads", + "LLC-load-misses", + }; + + for (size_t i =3D 0; i < ARRAY_SIZE(hw_events); i++) { + ret =3D parse_hardware_event(evlist, hw_events[i], &err); + if (ret) + goto out; + } } if (!ret && detailed_run >=3D 2) { /* * Very detailed stats (-d -d), covering the instruction cache * and the TLB caches: */ - ret =3D parse_events(evlist, - "L1-icache-loads," - "L1-icache-load-misses," - "dTLB-loads," - "dTLB-load-misses," - "iTLB-loads," - "iTLB-load-misses", - &err); + const char *hw_events[] =3D { + "L1-icache-loads", + "L1-icache-load-misses", + "dTLB-loads", + "dTLB-load-misses", + "iTLB-loads", + "iTLB-load-misses", + }; + + for (size_t i =3D 0; i < ARRAY_SIZE(hw_events); i++) { + ret =3D parse_hardware_event(evlist, hw_events[i], &err); + if (ret) + goto out; + } } if (!ret && detailed_run >=3D 3) { /* * Very, very detailed stats (-d -d -d), adding prefetch events: */ - ret =3D parse_events(evlist, - "L1-dcache-prefetches," - "L1-dcache-prefetch-misses", - &err); + const char *hw_events[] =3D { + "L1-dcache-prefetches", + "L1-dcache-prefetch-misses", + }; + + for (size_t i =3D 0; i < ARRAY_SIZE(hw_events); i++) { + ret =3D parse_hardware_event(evlist, hw_events[i], &err); + if (ret) + goto out; + } } out: if (!ret) { @@ -2045,7 +2100,7 @@ static int add_default_events(void) * Make at least one event non-skippable so fatal errors are visible. * 'cycles' always used to be default and non-skippable, so use that. */ - if (strcmp("cycles", evsel__name(evsel))) + if (!evsel__match(evsel, HARDWARE, HW_CPU_CYCLES)) evsel->skippable =3D true; } } --=20 2.51.0.534.gc79095c0ca-goog From nobody Thu Oct 2 03:27:35 2025 Received: from mail-pj1-f73.google.com (mail-pj1-f73.google.com [209.85.216.73]) (using TLSv1.2 with cipher ECDHE-RSA-AES128-GCM-SHA256 (128/128 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id 26F992D97B6 for ; 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Mon, 22 Sep 2025 21:19:43 -0700 (PDT) Date: Mon, 22 Sep 2025 21:18:44 -0700 In-Reply-To: <20250923041844.400164-1-irogers@google.com> Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: Mime-Version: 1.0 References: <20250923041844.400164-1-irogers@google.com> X-Mailer: git-send-email 2.51.0.534.gc79095c0ca-goog Message-ID: <20250923041844.400164-26-irogers@google.com> Subject: [PATCH v5 25/25] perf test: Switch cycles event to cpu-cycles From: Ian Rogers To: Peter Zijlstra , Ingo Molnar , Arnaldo Carvalho de Melo , Namhyung Kim , Mark Rutland , Alexander Shishkin , Jiri Olsa , Ian Rogers , Adrian Hunter , Kan Liang , James Clark , Xu Yang , Thomas Falcon , Andi Kleen , linux-kernel@vger.kernel.org, linux-perf-users@vger.kernel.org, bpf@vger.kernel.org, Atish Patra , Beeman Strong , Leo Yan , Vince Weaver Content-Transfer-Encoding: quoted-printable Content-Type: text/plain; charset="utf-8" Without a PMU perf matches an event against any PMU with the event. Unfortunately some PMU drivers advertise a "cycles" event which is typically just a core event. As tests assume a core event, switch to use "cpu-cycles" that avoids the overloaded "cycles" event on troublesome PMUs and is so far not overloaded. Note, on x86 this changes a legacy event into a sysfs one. Signed-off-by: Ian Rogers --- tools/perf/tests/code-reading.c | 2 +- tools/perf/tests/keep-tracking.c | 2 +- tools/perf/tests/perf-time-to-tsc.c | 4 ++-- tools/perf/tests/switch-tracking.c | 2 +- 4 files changed, 5 insertions(+), 5 deletions(-) diff --git a/tools/perf/tests/code-reading.c b/tools/perf/tests/code-readin= g.c index 9c2091310191..4574a7e528ec 100644 --- a/tools/perf/tests/code-reading.c +++ b/tools/perf/tests/code-reading.c @@ -649,7 +649,7 @@ static int do_test_code_reading(bool try_kcore) struct map *map; bool have_vmlinux, have_kcore; struct dso *dso; - const char *events[] =3D { "cycles", "cycles:u", "cpu-clock", "cpu-clock:= u", NULL }; + const char *events[] =3D { "cpu-cycles", "cpu-cycles:u", "cpu-clock", "cp= u-clock:u", NULL }; int evidx =3D 0; struct perf_env host_env; =20 diff --git a/tools/perf/tests/keep-tracking.c b/tools/perf/tests/keep-track= ing.c index eafb49eb0b56..729cc9cc1cb7 100644 --- a/tools/perf/tests/keep-tracking.c +++ b/tools/perf/tests/keep-tracking.c @@ -90,7 +90,7 @@ static int test__keep_tracking(struct test_suite *test __= maybe_unused, int subte perf_evlist__set_maps(&evlist->core, cpus, threads); =20 CHECK__(parse_event(evlist, "dummy:u")); - CHECK__(parse_event(evlist, "cycles:u")); + CHECK__(parse_event(evlist, "cpu-cycles:u")); =20 evlist__config(evlist, &opts, NULL); =20 diff --git a/tools/perf/tests/perf-time-to-tsc.c b/tools/perf/tests/perf-ti= me-to-tsc.c index d4437410c99f..cca41bd37ae3 100644 --- a/tools/perf/tests/perf-time-to-tsc.c +++ b/tools/perf/tests/perf-time-to-tsc.c @@ -101,11 +101,11 @@ static int test__perf_time_to_tsc(struct test_suite *= test __maybe_unused, int su =20 perf_evlist__set_maps(&evlist->core, cpus, threads); =20 - CHECK__(parse_event(evlist, "cycles:u")); + CHECK__(parse_event(evlist, "cpu-cycles:u")); =20 evlist__config(evlist, &opts, NULL); =20 - /* For hybrid "cycles:u", it creates two events */ + /* For hybrid "cpu-cycles:u", it creates two events */ evlist__for_each_entry(evlist, evsel) { evsel->core.attr.comm =3D 1; evsel->core.attr.disabled =3D 1; diff --git a/tools/perf/tests/switch-tracking.c b/tools/perf/tests/switch-t= racking.c index 5be294014d3b..15791fcb76b2 100644 --- a/tools/perf/tests/switch-tracking.c +++ b/tools/perf/tests/switch-tracking.c @@ -332,7 +332,7 @@ static int process_events(struct evlist *evlist, static int test__switch_tracking(struct test_suite *test __maybe_unused, i= nt subtest __maybe_unused) { const char *sched_switch =3D "sched:sched_switch"; - const char *cycles =3D "cycles:u"; + const char *cycles =3D "cpu-cycles:u"; struct switch_tracking switch_tracking =3D { .tids =3D NULL, }; struct record_opts opts =3D { .mmap_pages =3D UINT_MAX, --=20 2.51.0.534.gc79095c0ca-goog