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Mon, 22 Sep 2025 17:21:10 -0700 From: Besar Wicaksono To: , , CC: , , , , , , , , , , "Besar Wicaksono" Subject: [PATCH v2 5/5] perf/arm_cspmu: nvidia: Add pmevfiltr2 support Date: Tue, 23 Sep 2025 00:18:40 +0000 Message-ID: <20250923001840.1586078-6-bwicaksono@nvidia.com> X-Mailer: git-send-email 2.50.1 In-Reply-To: <20250923001840.1586078-1-bwicaksono@nvidia.com> References: <20250923001840.1586078-1-bwicaksono@nvidia.com> Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable X-NV-OnPremToCloud: ExternallySecured X-EOPAttributedMessage: 0 X-MS-PublicTrafficType: Email X-MS-TrafficTypeDiagnostic: DS1PEPF0001708E:EE_|MN2PR12MB4360:EE_ X-MS-Office365-Filtering-Correlation-Id: aeed8419-e5bf-4c2b-96bb-08ddfa371f7c X-MS-Exchange-SenderADCheck: 1 X-MS-Exchange-AntiSpam-Relay: 0 X-Microsoft-Antispam: BCL:0;ARA:13230040|36860700013|82310400026|376014|1800799024; X-Microsoft-Antispam-Message-Info: =?us-ascii?Q?otFjBXWDuY6rN7KcAs/pGBtXgdwlujB0xI3hUCO9BcXxGN4uUI7HrkRVpJna?= =?us-ascii?Q?5rTTLewHCeIFaImjFJe0eE2riP2H43q/mdXB8mden5E6YaWqZndIxDytpvJ7?= =?us-ascii?Q?fS+ZmdLworjnrb41Orxu/kBwyX2C+73YT4WwtspjUzePgNkVNZBiZcilGZd3?= =?us-ascii?Q?8rvtHjPu+yI7rGrrMlV4cLJyOwQGg5lzBOG2AT93lXHT4hBkuW4Zzsi3gI+C?= =?us-ascii?Q?BC+/lWEkcuo2+SnfWARs88q7ST6TIR9m/Bh82bN8BQHnVzVmeGACzm9r+tqD?= =?us-ascii?Q?fmEYy93CVn5Z7vFGtAwW+m4VPif0CilSxrC+c1rwZ4dlWMFOVXOz5LraxEKR?= =?us-ascii?Q?908Jb4g4V0LasgiyNpzRa6FT51UVFYRFiiqUjtFdeIOm2kDPp9nc9g+Z1cOT?= =?us-ascii?Q?kaoyKgU7vQp9xySnxh72R2MViccWPlylnkRSFju/PTk+DL9HcxPhF/stc+rU?= =?us-ascii?Q?KDnD8/iRau4vJkYkCcVXg4Ulc/du3+F/PKVJCIBda+PymG5dlDKlyUGmTgC3?= =?us-ascii?Q?CjX2iVctZIzJBn0z/DBd9YwDt9kqver+C4NSJ3A06hUEAYHG7TYm5R1oaZtX?= =?us-ascii?Q?J2X6/e7LRAYzZRKPCBJSonZHunTkqhBetctMdsyNkAFY5yJNINF/dWPEeK1R?= =?us-ascii?Q?ju1FflLm8t1jRmkO2rq3/ggbwMhv3rGyeI3CWtEm9x3Pbpn4jI1oIgwPK5Bo?= =?us-ascii?Q?4qq0Lbg3u3vtU48CHZRKOvrI89HtK+00jEcL2x+VldZQ3XpXaah6bRwdEfh5?= =?us-ascii?Q?MgFUAYtL7MuNHHl4OgU2wY1AupdUXeUTUvHZUsQWnoLhzpeY+x9A64o4c0wC?= =?us-ascii?Q?6cxOVmwJCIBACNm+MRqzF2E+qpg9MrNNYdstW7LShVw9wKvHzKd4O02jdeoI?= =?us-ascii?Q?kGhTyI+pV2SpS3wGIXp8FJnR3hYV+zNPHnITevEqwdohSTKQ0AWOpQ60R/sS?= =?us-ascii?Q?Kn0hmq1MnCbSPWMSvA7ZyyywYWNB4+NO8/5jOj6QEj/Wc+EL0RpBWSYENx+e?= =?us-ascii?Q?WSLkKY7u5dZ7ybD758J5Ics65lc4mjNQbT8cP+jOj9FWmcTTy2O6nNDdDDyn?= =?us-ascii?Q?27wftofxjMEI9zl3Rwv0qkubqzrDg7vC4JpVcH7Nb+sOBAnLRclE+L7xt331?= =?us-ascii?Q?nZ/ls7BmJi3X4NVSecfaBcRA09NFQ5vpDYJr6IAT0+DIlcQHPNYv27JBCgkP?= =?us-ascii?Q?YRZ/aqxlHpQlMYJR1awbS0nwEScfWjYQeebDpRUU3fIihUK3m3bFzWXH1pe3?= =?us-ascii?Q?ev9EmTgA6jIq+epgzh38Xm8R/y1Z4TDnWeULEtJ9q4jtFzgCACVyjF6QRvtS?= =?us-ascii?Q?0Di/1uRrbnNw4482hp3UYRouS5k9iR94r6j5hoZ18KdqysZL/d0okA8gF+cG?= =?us-ascii?Q?QYnvkBOA4Qify7JToPMF0zEJ7OEx0p0yT6nuOjMMO7xxcL9srnw/E7wnUbNM?= =?us-ascii?Q?rIQCcv8hinC3IMr1ucXRLAKs9D4o1BWM4aY8vtCZ7YvKE1sncCfSgO5d0FXA?= =?us-ascii?Q?l4pvZHYeXtOksJimpxeOtnvSwwwzwpOlZVG8?= X-Forefront-Antispam-Report: CIP:216.228.117.160;CTRY:US;LANG:en;SCL:1;SRV:;IPV:NLI;SFV:NSPM;H:mail.nvidia.com;PTR:dc6edge1.nvidia.com;CAT:NONE;SFS:(13230040)(36860700013)(82310400026)(376014)(1800799024);DIR:OUT;SFP:1101; X-OriginatorOrg: Nvidia.com X-MS-Exchange-CrossTenant-OriginalArrivalTime: 23 Sep 2025 00:21:21.3325 (UTC) X-MS-Exchange-CrossTenant-Network-Message-Id: aeed8419-e5bf-4c2b-96bb-08ddfa371f7c X-MS-Exchange-CrossTenant-Id: 43083d15-7273-40c1-b7db-39efd9ccc17a X-MS-Exchange-CrossTenant-OriginalAttributedTenantConnectingIp: TenantId=43083d15-7273-40c1-b7db-39efd9ccc17a;Ip=[216.228.117.160];Helo=[mail.nvidia.com] X-MS-Exchange-CrossTenant-AuthSource: DS1PEPF0001708E.namprd03.prod.outlook.com X-MS-Exchange-CrossTenant-AuthAs: Anonymous X-MS-Exchange-CrossTenant-FromEntityHeader: HybridOnPrem X-MS-Exchange-Transport-CrossTenantHeadersStamped: MN2PR12MB4360 Content-Type: text/plain; charset="utf-8" Support NVIDIA PMU that utilizes the optional event filter2 register. Signed-off-by: Besar Wicaksono --- drivers/perf/arm_cspmu/nvidia_cspmu.c | 176 +++++++++++++++++++------- 1 file changed, 133 insertions(+), 43 deletions(-) diff --git a/drivers/perf/arm_cspmu/nvidia_cspmu.c b/drivers/perf/arm_cspmu= /nvidia_cspmu.c index ac91dc46501d..e06a06d3407b 100644 --- a/drivers/perf/arm_cspmu/nvidia_cspmu.c +++ b/drivers/perf/arm_cspmu/nvidia_cspmu.c @@ -40,10 +40,21 @@ =20 struct nv_cspmu_ctx { const char *name; - u32 filter_mask; - u32 filter_default_val; + struct attribute **event_attr; struct attribute **format_attr; + + u32 filter_mask; + u32 filter_default_val; + u32 filter2_mask; + u32 filter2_default_val; + + u32 (*get_filter)(const struct perf_event *event); + u32 (*get_filter2)(const struct perf_event *event); + + void *data; + + int (*init_data)(struct arm_cspmu *cspmu); }; =20 static struct attribute *scf_pmu_event_attrs[] =3D { @@ -144,6 +155,7 @@ static struct attribute *cnvlink_pmu_format_attrs[] =3D= { static struct attribute *generic_pmu_format_attrs[] =3D { ARM_CSPMU_FORMAT_EVENT_ATTR, ARM_CSPMU_FORMAT_FILTER_ATTR, + ARM_CSPMU_FORMAT_FILTER2_ATTR, NULL, }; =20 @@ -184,13 +196,36 @@ static u32 nv_cspmu_event_filter(const struct perf_ev= ent *event) return filter_val; } =20 +static u32 nv_cspmu_event_filter2(const struct perf_event *event) +{ + const struct nv_cspmu_ctx *ctx =3D + to_nv_cspmu_ctx(to_arm_cspmu(event->pmu)); + + const u32 filter_val =3D event->attr.config2 & ctx->filter2_mask; + + if (filter_val =3D=3D 0) + return ctx->filter2_default_val; + + return filter_val; +} + static void nv_cspmu_set_ev_filter(struct arm_cspmu *cspmu, const struct perf_event *event) { - u32 filter =3D nv_cspmu_event_filter(event); - u32 offset =3D PMEVFILTR + (4 * event->hw.idx); + u32 filter, offset; + const struct nv_cspmu_ctx *ctx =3D + to_nv_cspmu_ctx(to_arm_cspmu(event->pmu)); + offset =3D 4 * event->hw.idx; =20 - writel(filter, cspmu->base0 + offset); + if (ctx->get_filter) { + filter =3D ctx->get_filter(event); + writel(filter, cspmu->base0 + PMEVFILTR + offset); + } + + if (ctx->get_filter2) { + filter =3D ctx->get_filter2(event); + writel(filter, cspmu->base0 + PMEVFILT2R + offset); + } } =20 static void nv_cspmu_set_cc_filter(struct arm_cspmu *cspmu, @@ -210,74 +245,120 @@ enum nv_cspmu_name_fmt { struct nv_cspmu_match { u32 prodid; u32 prodid_mask; - u64 filter_mask; - u32 filter_default_val; const char *name_pattern; enum nv_cspmu_name_fmt name_fmt; - struct attribute **event_attr; - struct attribute **format_attr; + struct nv_cspmu_ctx template_ctx; + struct arm_cspmu_impl_ops ops; }; =20 static const struct nv_cspmu_match nv_cspmu_match[] =3D { { .prodid =3D 0x10300000, .prodid_mask =3D NV_PRODID_MASK, - .filter_mask =3D NV_PCIE_FILTER_ID_MASK, - .filter_default_val =3D NV_PCIE_FILTER_ID_MASK, .name_pattern =3D "nvidia_pcie_pmu_%u", .name_fmt =3D NAME_FMT_SOCKET, - .event_attr =3D mcf_pmu_event_attrs, - .format_attr =3D pcie_pmu_format_attrs + .template_ctx =3D { + .event_attr =3D mcf_pmu_event_attrs, + .format_attr =3D pcie_pmu_format_attrs, + .filter_mask =3D NV_PCIE_FILTER_ID_MASK, + .filter_default_val =3D NV_PCIE_FILTER_ID_MASK, + .filter2_mask =3D 0x0, + .filter2_default_val =3D 0x0, + .get_filter =3D nv_cspmu_event_filter, + .get_filter2 =3D NULL, + .data =3D NULL, + .init_data =3D NULL + }, }, { .prodid =3D 0x10400000, .prodid_mask =3D NV_PRODID_MASK, - .filter_mask =3D NV_NVL_C2C_FILTER_ID_MASK, - .filter_default_val =3D NV_NVL_C2C_FILTER_ID_MASK, .name_pattern =3D "nvidia_nvlink_c2c1_pmu_%u", .name_fmt =3D NAME_FMT_SOCKET, - .event_attr =3D mcf_pmu_event_attrs, - .format_attr =3D nvlink_c2c_pmu_format_attrs + .template_ctx =3D { + .event_attr =3D mcf_pmu_event_attrs, + .format_attr =3D nvlink_c2c_pmu_format_attrs, + .filter_mask =3D NV_NVL_C2C_FILTER_ID_MASK, + .filter_default_val =3D NV_NVL_C2C_FILTER_ID_MASK, + .filter2_mask =3D 0x0, + .filter2_default_val =3D 0x0, + .get_filter =3D nv_cspmu_event_filter, + .get_filter2 =3D NULL, + .data =3D NULL, + .init_data =3D NULL + }, }, { .prodid =3D 0x10500000, .prodid_mask =3D NV_PRODID_MASK, - .filter_mask =3D NV_NVL_C2C_FILTER_ID_MASK, - .filter_default_val =3D NV_NVL_C2C_FILTER_ID_MASK, .name_pattern =3D "nvidia_nvlink_c2c0_pmu_%u", .name_fmt =3D NAME_FMT_SOCKET, - .event_attr =3D mcf_pmu_event_attrs, - .format_attr =3D nvlink_c2c_pmu_format_attrs + .template_ctx =3D { + .event_attr =3D mcf_pmu_event_attrs, + .format_attr =3D nvlink_c2c_pmu_format_attrs, + .filter_mask =3D NV_NVL_C2C_FILTER_ID_MASK, + .filter_default_val =3D NV_NVL_C2C_FILTER_ID_MASK, + .filter2_mask =3D 0x0, + .filter2_default_val =3D 0x0, + .get_filter =3D nv_cspmu_event_filter, + .get_filter2 =3D NULL, + .data =3D NULL, + .init_data =3D NULL + }, }, { .prodid =3D 0x10600000, .prodid_mask =3D NV_PRODID_MASK, - .filter_mask =3D NV_CNVL_FILTER_ID_MASK, - .filter_default_val =3D NV_CNVL_FILTER_ID_MASK, .name_pattern =3D "nvidia_cnvlink_pmu_%u", .name_fmt =3D NAME_FMT_SOCKET, - .event_attr =3D mcf_pmu_event_attrs, - .format_attr =3D cnvlink_pmu_format_attrs + .template_ctx =3D { + .event_attr =3D mcf_pmu_event_attrs, + .format_attr =3D cnvlink_pmu_format_attrs, + .filter_mask =3D NV_CNVL_FILTER_ID_MASK, + .filter_default_val =3D NV_CNVL_FILTER_ID_MASK, + .filter2_mask =3D 0x0, + .filter2_default_val =3D 0x0, + .get_filter =3D nv_cspmu_event_filter, + .get_filter2 =3D NULL, + .data =3D NULL, + .init_data =3D NULL + }, }, { .prodid =3D 0x2CF00000, .prodid_mask =3D NV_PRODID_MASK, - .filter_mask =3D 0x0, - .filter_default_val =3D 0x0, .name_pattern =3D "nvidia_scf_pmu_%u", .name_fmt =3D NAME_FMT_SOCKET, - .event_attr =3D scf_pmu_event_attrs, - .format_attr =3D scf_pmu_format_attrs + .template_ctx =3D { + .event_attr =3D scf_pmu_event_attrs, + .format_attr =3D scf_pmu_format_attrs, + .filter_mask =3D 0x0, + .filter_default_val =3D 0x0, + .filter2_mask =3D 0x0, + .filter2_default_val =3D 0x0, + .get_filter =3D nv_cspmu_event_filter, + .get_filter2 =3D NULL, + .data =3D NULL, + .init_data =3D NULL + }, }, { .prodid =3D 0, .prodid_mask =3D 0, - .filter_mask =3D NV_GENERIC_FILTER_ID_MASK, - .filter_default_val =3D NV_GENERIC_FILTER_ID_MASK, .name_pattern =3D "nvidia_uncore_pmu_%u", .name_fmt =3D NAME_FMT_GENERIC, - .event_attr =3D generic_pmu_event_attrs, - .format_attr =3D generic_pmu_format_attrs + .template_ctx =3D { + .event_attr =3D generic_pmu_event_attrs, + .format_attr =3D generic_pmu_format_attrs, + .filter_mask =3D NV_GENERIC_FILTER_ID_MASK, + .filter_default_val =3D NV_GENERIC_FILTER_ID_MASK, + .filter2_mask =3D NV_GENERIC_FILTER_ID_MASK, + .filter2_default_val =3D NV_GENERIC_FILTER_ID_MASK, + .get_filter =3D nv_cspmu_event_filter, + .get_filter2 =3D nv_cspmu_event_filter2, + .data =3D NULL, + .init_data =3D NULL + }, }, }; =20 @@ -310,6 +391,14 @@ static char *nv_cspmu_format_name(const struct arm_csp= mu *cspmu, return name; } =20 +#define SET_OP(name, impl, match, default_op) \ + do { \ + if (match->ops.name) \ + impl->name =3D match->ops.name; \ + else if (default_op !=3D NULL) \ + impl->name =3D default_op; \ + } while (false) + static int nv_cspmu_init_ops(struct arm_cspmu *cspmu) { struct nv_cspmu_ctx *ctx; @@ -330,20 +419,21 @@ static int nv_cspmu_init_ops(struct arm_cspmu *cspmu) break; } =20 - ctx->name =3D nv_cspmu_format_name(cspmu, match); - ctx->filter_mask =3D match->filter_mask; - ctx->filter_default_val =3D match->filter_default_val; - ctx->event_attr =3D match->event_attr; - ctx->format_attr =3D match->format_attr; + /* Initialize the context with the matched template. */ + memcpy(ctx, &match->template_ctx, sizeof(struct nv_cspmu_ctx)); + ctx->name =3D nv_cspmu_format_name(cspmu, match); =20 cspmu->impl.ctx =3D ctx; =20 /* NVIDIA specific callbacks. */ - impl_ops->set_cc_filter =3D nv_cspmu_set_cc_filter; - impl_ops->set_ev_filter =3D nv_cspmu_set_ev_filter; - impl_ops->get_event_attrs =3D nv_cspmu_get_event_attrs; - impl_ops->get_format_attrs =3D nv_cspmu_get_format_attrs; - impl_ops->get_name =3D nv_cspmu_get_name; + SET_OP(set_cc_filter, impl_ops, match, nv_cspmu_set_cc_filter); + SET_OP(set_ev_filter, impl_ops, match, nv_cspmu_set_ev_filter); + SET_OP(get_event_attrs, impl_ops, match, nv_cspmu_get_event_attrs); + SET_OP(get_format_attrs, impl_ops, match, nv_cspmu_get_format_attrs); + SET_OP(get_name, impl_ops, match, nv_cspmu_get_name); + + if (ctx->init_data) + return ctx->init_data(cspmu); =20 return 0; } --=20 2.50.1