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Mon, 22 Sep 2025 17:20:39 -0700 From: Besar Wicaksono To: , , CC: , , , , , , , , , , "Besar Wicaksono" Subject: [PATCH v2 1/5] perf/arm_cspmu: Add arm_cspmu_acpi_dev_get Date: Tue, 23 Sep 2025 00:18:36 +0000 Message-ID: <20250923001840.1586078-2-bwicaksono@nvidia.com> X-Mailer: git-send-email 2.50.1 In-Reply-To: <20250923001840.1586078-1-bwicaksono@nvidia.com> References: <20250923001840.1586078-1-bwicaksono@nvidia.com> Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable X-NV-OnPremToCloud: ExternallySecured X-EOPAttributedMessage: 0 X-MS-PublicTrafficType: Email X-MS-TrafficTypeDiagnostic: BL02EPF00021F6B:EE_|SA1PR12MB9248:EE_ X-MS-Office365-Filtering-Correlation-Id: 0be270a7-0f62-4513-b5d1-08ddfa3710dd X-MS-Exchange-SenderADCheck: 1 X-MS-Exchange-AntiSpam-Relay: 0 X-Microsoft-Antispam: BCL:0;ARA:13230040|36860700013|376014|82310400026|1800799024; X-Microsoft-Antispam-Message-Info: =?us-ascii?Q?92NF/MA0BxF20B+tSKieN6TgvbL2FPp4fCyYmGtwTEthJjAZIG58TSx8eIjX?= =?us-ascii?Q?jf6y2nvS3+6/UvKme0WwsNC+rfwj0eL2t8TFfDHyXbN3pNmK3pdTY+byykrM?= =?us-ascii?Q?Rr3kN+7t8Wo/vokmtHTyiBo45PaG0yxsYQLve2gBOETDLaAnw6bH5vYf1cvu?= =?us-ascii?Q?A2Zw/rmq2Cucf7qnKoRrLLkH4FAKHX6iOW8eEQY8TIrEcXAfBKqHBY7hGKWM?= =?us-ascii?Q?2uewOGe8yG1OqaEiKT/WrgDhq7ODDRh9V1auW/hSJvSh5esYKEgDTJYtmBCe?= =?us-ascii?Q?ndurb1ulqmnnBXDnCjqXFNPj+U2hJsNgb+HgYvdC2ZJ3yhJTZCMopadSMUG1?= =?us-ascii?Q?IUFlh8WqwDU6McMS5JHYa0T8IEvKsmTqkgNzMciRbg81XZxp4qEChnDmEmuW?= =?us-ascii?Q?cIulSTscAIJoZ37yY4Bfu5I36E/xVvvYNq9Ns7SMjT+RV9XN9MyQDgQ4Waoo?= =?us-ascii?Q?T8Wp+g5GESlU3FnixtJWz7OxrFz7f64CnagttdjXcRt1IC1PdVDc83r3fMCe?= =?us-ascii?Q?OZjxHsuk5nL8IxRrtuN1+20fjKp35T6YjgVgpI5UBz1ZN6UmeYqpL6yaGeHd?= =?us-ascii?Q?SNTmNfzfUCeYlIeu0y09v+7f+Utc0d7icHdBfMxBkzyjYOWbI1H/j/E0g0dO?= =?us-ascii?Q?96+7dt9xyINa2HYz9jN9G7C9E5Fw09dFCNfv8Jm1NWmegkRWpbWhe24K4LWI?= =?us-ascii?Q?XzVec6LXaJHMpEFa7vCM8TN2/w/nBKEtwf3QJDFd5pCTCACg5DtGUegYa5Uc?= =?us-ascii?Q?ghVvaME9tu+dNgTotI69PgmFR+DhXFqRF7Db2rUSp7A+ojs+0v1XqVka1E9k?= =?us-ascii?Q?znU50NpyOwA499BAL3oHvrzaMzbu1WWDqrcdBPOSBxPbDtDxZhjJ9ZHUlDO/?= =?us-ascii?Q?0TNpfjXns4O5WCmlyQeDBxh6fsnWdWT032QvTrYVmCjR7rYEBXBbFe27gxhq?= =?us-ascii?Q?BlHMb1aG47Sw3MO3QkSoDvPdwJDWEG9eT7Lxn1IQBgtWlpMfPXJql13fLrFK?= =?us-ascii?Q?IFmGfUW7uPAeydXN+SL+ngu/e3jqNCBjzjR8O050pXKmiy6JTxoBsB8PzEhC?= =?us-ascii?Q?HMdiakUt9p5Ni93s081IDyHN01dvZIs0ZAhoioMTTt5JH1ryP2rdPaMPe2qc?= =?us-ascii?Q?0ngNxdbS6TYZtavYUOPEiel3ESWf/TSnlPDlW4/IhFLjiH5mPeRpbs12++1+?= =?us-ascii?Q?V4TEr/3yO9e8gZW99t2utJTASjKalLS3mSCyekocvjbokvyw+0Hf7J78djeW?= =?us-ascii?Q?ASTJzg1EZ6FsFRMGc3LzeKtWjkYcaber8epMdmx2UbSGLJoHPAHWMZ6v1y8r?= =?us-ascii?Q?ugNt9UsyXTFUKrrmcUa64VFO7kpUXSUCNlnSCp6Ot5318jLazgDAZ67fGixt?= =?us-ascii?Q?T1dhVJYhSKNqGLo50krso611GRotnNWnAGR4L2xyvlftPGrWKswe04/u13Nr?= =?us-ascii?Q?7v5B/N04vZimjtGqGGMNAL90wdVOFYJIcYyxFs2OcPrrAu//siu3+mFOrel5?= =?us-ascii?Q?gBTWcmjQc0o0V91OLSyNKR+Nl5ifC3Nl6Ion?= X-Forefront-Antispam-Report: CIP:216.228.117.161;CTRY:US;LANG:en;SCL:1;SRV:;IPV:NLI;SFV:NSPM;H:mail.nvidia.com;PTR:dc6edge2.nvidia.com;CAT:NONE;SFS:(13230040)(36860700013)(376014)(82310400026)(1800799024);DIR:OUT;SFP:1101; X-OriginatorOrg: Nvidia.com X-MS-Exchange-CrossTenant-OriginalArrivalTime: 23 Sep 2025 00:20:56.7770 (UTC) X-MS-Exchange-CrossTenant-Network-Message-Id: 0be270a7-0f62-4513-b5d1-08ddfa3710dd X-MS-Exchange-CrossTenant-Id: 43083d15-7273-40c1-b7db-39efd9ccc17a X-MS-Exchange-CrossTenant-OriginalAttributedTenantConnectingIp: TenantId=43083d15-7273-40c1-b7db-39efd9ccc17a;Ip=[216.228.117.161];Helo=[mail.nvidia.com] X-MS-Exchange-CrossTenant-AuthSource: BL02EPF00021F6B.namprd02.prod.outlook.com X-MS-Exchange-CrossTenant-AuthAs: Anonymous X-MS-Exchange-CrossTenant-FromEntityHeader: HybridOnPrem X-MS-Exchange-Transport-CrossTenantHeadersStamped: SA1PR12MB9248 Content-Type: text/plain; charset="utf-8" Add interface to get ACPI device associated with the PMU. This ACPI device may contain additional properties not covered by the standard properties. Signed-off-by: Besar Wicaksono --- drivers/perf/arm_cspmu/arm_cspmu.c | 22 ++++++++++++++++++++++ drivers/perf/arm_cspmu/arm_cspmu.h | 9 +++++++++ 2 files changed, 31 insertions(+) diff --git a/drivers/perf/arm_cspmu/arm_cspmu.c b/drivers/perf/arm_cspmu/ar= m_cspmu.c index efa9b229e701..75b2d80f783e 100644 --- a/drivers/perf/arm_cspmu/arm_cspmu.c +++ b/drivers/perf/arm_cspmu/arm_cspmu.c @@ -1090,6 +1090,28 @@ static int arm_cspmu_acpi_get_cpus(struct arm_cspmu = *cspmu) =20 return 0; } + +struct acpi_device *arm_cspmu_acpi_dev_get(const struct arm_cspmu *cspmu) +{ + char hid[16]; + char uid[16]; + struct acpi_device *adev; + const struct acpi_apmt_node *apmt_node; + + apmt_node =3D arm_cspmu_apmt_node(cspmu->dev); + if (!apmt_node || apmt_node->type !=3D ACPI_APMT_NODE_TYPE_ACPI) + return NULL; + + memset(hid, 0, sizeof(hid)); + memset(uid, 0, sizeof(uid)); + + memcpy(hid, &apmt_node->inst_primary, sizeof(apmt_node->inst_primary)); + sprintf(uid, "%u", apmt_node->inst_secondary); + + adev =3D acpi_dev_get_first_match_dev(hid, uid, -1); + return adev; +} +EXPORT_SYMBOL_GPL(arm_cspmu_acpi_dev_get); #else static int arm_cspmu_acpi_get_cpus(struct arm_cspmu *cspmu) { diff --git a/drivers/perf/arm_cspmu/arm_cspmu.h b/drivers/perf/arm_cspmu/ar= m_cspmu.h index 19684b76bd96..9c5f11f98acd 100644 --- a/drivers/perf/arm_cspmu/arm_cspmu.h +++ b/drivers/perf/arm_cspmu/arm_cspmu.h @@ -8,6 +8,7 @@ #ifndef __ARM_CSPMU_H__ #define __ARM_CSPMU_H__ =20 +#include #include #include #include @@ -222,4 +223,12 @@ int arm_cspmu_impl_register(const struct arm_cspmu_imp= l_match *impl_match); /* Unregister vendor backend. */ void arm_cspmu_impl_unregister(const struct arm_cspmu_impl_match *impl_mat= ch); =20 +#if defined(CONFIG_ACPI) +/** + * Get ACPI device associated with the PMU. + * The caller is responsible for calling acpi_dev_put() on the returned de= vice. + */ +struct acpi_device *arm_cspmu_acpi_dev_get(const struct arm_cspmu *cspmu); +#endif + #endif /* __ARM_CSPMU_H__ */ --=20 2.50.1 From nobody Thu Oct 2 03:27:32 2025 Received: from CH1PR05CU001.outbound.protection.outlook.com (mail-northcentralusazon11010041.outbound.protection.outlook.com [52.101.193.41]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id 6DF221B043F; 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X-OriginatorOrg: Nvidia.com X-MS-Exchange-CrossTenant-OriginalArrivalTime: 23 Sep 2025 00:21:02.6270 (UTC) X-MS-Exchange-CrossTenant-Network-Message-Id: 16ebe464-9f06-4704-e24b-08ddfa37145a X-MS-Exchange-CrossTenant-Id: 43083d15-7273-40c1-b7db-39efd9ccc17a X-MS-Exchange-CrossTenant-OriginalAttributedTenantConnectingIp: TenantId=43083d15-7273-40c1-b7db-39efd9ccc17a;Ip=[216.228.117.161];Helo=[mail.nvidia.com] X-MS-Exchange-CrossTenant-AuthSource: BL02EPF00021F6A.namprd02.prod.outlook.com X-MS-Exchange-CrossTenant-AuthAs: Anonymous X-MS-Exchange-CrossTenant-FromEntityHeader: HybridOnPrem X-MS-Exchange-Transport-CrossTenantHeadersStamped: SA5PPF7F0CA3746 Content-Type: text/plain; charset="utf-8" Implementer may need to reset a filter config when stopping a counter, thus adding a callback for this. Signed-off-by: Besar Wicaksono --- drivers/perf/arm_cspmu/arm_cspmu.c | 4 ++++ drivers/perf/arm_cspmu/arm_cspmu.h | 4 +++- 2 files changed, 7 insertions(+), 1 deletion(-) diff --git a/drivers/perf/arm_cspmu/arm_cspmu.c b/drivers/perf/arm_cspmu/ar= m_cspmu.c index 75b2d80f783e..43770c8ecd14 100644 --- a/drivers/perf/arm_cspmu/arm_cspmu.c +++ b/drivers/perf/arm_cspmu/arm_cspmu.c @@ -815,6 +815,10 @@ static void arm_cspmu_stop(struct perf_event *event, i= nt pmu_flags) return; =20 arm_cspmu_disable_counter(cspmu, hwc->idx); + + if (cspmu->impl.ops.reset_ev_filter) + cspmu->impl.ops.reset_ev_filter(cspmu, event); + arm_cspmu_event_update(event); =20 hwc->state |=3D PERF_HES_STOPPED | PERF_HES_UPTODATE; diff --git a/drivers/perf/arm_cspmu/arm_cspmu.h b/drivers/perf/arm_cspmu/ar= m_cspmu.h index 9c5f11f98acd..21d7e6e2f2da 100644 --- a/drivers/perf/arm_cspmu/arm_cspmu.h +++ b/drivers/perf/arm_cspmu/arm_cspmu.h @@ -153,11 +153,13 @@ struct arm_cspmu_impl_ops { bool (*is_cycle_counter_event)(const struct perf_event *event); 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X-OriginatorOrg: Nvidia.com X-MS-Exchange-CrossTenant-OriginalArrivalTime: 23 Sep 2025 00:21:05.6725 (UTC) X-MS-Exchange-CrossTenant-Network-Message-Id: 5ad9c191-0159-4d00-9528-08ddfa37162b X-MS-Exchange-CrossTenant-Id: 43083d15-7273-40c1-b7db-39efd9ccc17a X-MS-Exchange-CrossTenant-OriginalAttributedTenantConnectingIp: TenantId=43083d15-7273-40c1-b7db-39efd9ccc17a;Ip=[216.228.117.161];Helo=[mail.nvidia.com] X-MS-Exchange-CrossTenant-AuthSource: BL02EPF00021F6B.namprd02.prod.outlook.com X-MS-Exchange-CrossTenant-AuthAs: Anonymous X-MS-Exchange-CrossTenant-FromEntityHeader: HybridOnPrem X-MS-Exchange-Transport-CrossTenantHeadersStamped: DS0PR12MB8414 Content-Type: text/plain; charset="utf-8" The PMIIDR value is composed by the values in PMPIDR registers. We can use PMPIDR registers as alternative for device identification for systems that do not implement PMIIDR. Reviewed-by: Ilkka Koskinen Signed-off-by: Besar Wicaksono --- drivers/perf/arm_cspmu/arm_cspmu.c | 44 +++++++++++++++++++++++++-- drivers/perf/arm_cspmu/arm_cspmu.h | 35 +++++++++++++++++++-- drivers/perf/arm_cspmu/nvidia_cspmu.c | 2 +- 3 files changed, 75 insertions(+), 6 deletions(-) diff --git a/drivers/perf/arm_cspmu/arm_cspmu.c b/drivers/perf/arm_cspmu/ar= m_cspmu.c index 43770c8ecd14..d0ec1eb8272f 100644 --- a/drivers/perf/arm_cspmu/arm_cspmu.c +++ b/drivers/perf/arm_cspmu/arm_cspmu.c @@ -322,14 +322,14 @@ static struct arm_cspmu_impl_match impl_match[] =3D { { .module_name =3D "nvidia_cspmu", .pmiidr_val =3D ARM_CSPMU_IMPL_ID_NVIDIA, - .pmiidr_mask =3D ARM_CSPMU_PMIIDR_IMPLEMENTER, + .pmiidr_mask =3D PMIIDR_IMPLEMENTER, .module =3D NULL, .impl_init_ops =3D NULL, }, { .module_name =3D "ampere_cspmu", .pmiidr_val =3D ARM_CSPMU_IMPL_ID_AMPERE, - .pmiidr_mask =3D ARM_CSPMU_PMIIDR_IMPLEMENTER, + .pmiidr_mask =3D PMIIDR_IMPLEMENTER, .module =3D NULL, .impl_init_ops =3D NULL, }, @@ -351,6 +351,44 @@ static struct arm_cspmu_impl_match *arm_cspmu_impl_mat= ch_get(u32 pmiidr) return NULL; } =20 +static u32 arm_cspmu_get_pmiidr(struct arm_cspmu *cspmu) +{ + u32 pmiidr, pmpidr; + + pmiidr =3D readl(cspmu->base0 + PMIIDR); + + if (pmiidr !=3D 0) + return pmiidr; + + /* Construct PMIIDR value from PMPIDRs. */ + + pmpidr =3D readl(cspmu->base0 + PMPIDR0); + pmiidr |=3D FIELD_PREP(PMIIDR_PRODUCTID_PART_0, + FIELD_GET(PMPIDR0_PART_0, pmpidr)); + + pmpidr =3D readl(cspmu->base0 + PMPIDR1); + pmiidr |=3D FIELD_PREP(PMIIDR_PRODUCTID_PART_1, + FIELD_GET(PMPIDR1_PART_1, pmpidr)); + pmiidr |=3D FIELD_PREP(PMIIDR_IMPLEMENTER_DES_0, + FIELD_GET(PMPIDR1_DES_0, pmpidr)); + + pmpidr =3D readl(cspmu->base0 + PMPIDR2); + pmiidr |=3D FIELD_PREP(PMIIDR_VARIANT, + FIELD_GET(PMPIDR2_REVISION, pmpidr)); + pmiidr |=3D FIELD_PREP(PMIIDR_IMPLEMENTER_DES_1, + FIELD_GET(PMPIDR2_DES_1, pmpidr)); + + pmpidr =3D readl(cspmu->base0 + PMPIDR3); + pmiidr |=3D FIELD_PREP(PMIIDR_REVISION, + FIELD_GET(PMPIDR3_REVAND, pmpidr)); + + pmpidr =3D readl(cspmu->base0 + PMPIDR4); + pmiidr |=3D FIELD_PREP(PMIIDR_IMPLEMENTER_DES_2, + FIELD_GET(PMPIDR4_DES_2, pmpidr)); + + return pmiidr; +} + #define DEFAULT_IMPL_OP(name) .name =3D arm_cspmu_##name =20 static int arm_cspmu_init_impl_ops(struct arm_cspmu *cspmu) @@ -361,7 +399,7 @@ static int arm_cspmu_init_impl_ops(struct arm_cspmu *cs= pmu) =20 /* Start with a default PMU implementation */ cspmu->impl.module =3D THIS_MODULE; - cspmu->impl.pmiidr =3D readl(cspmu->base0 + PMIIDR); + cspmu->impl.pmiidr =3D arm_cspmu_get_pmiidr(cspmu); cspmu->impl.ops =3D (struct arm_cspmu_impl_ops) { DEFAULT_IMPL_OP(get_event_attrs), DEFAULT_IMPL_OP(get_format_attrs), diff --git a/drivers/perf/arm_cspmu/arm_cspmu.h b/drivers/perf/arm_cspmu/ar= m_cspmu.h index 21d7e6e2f2da..16799d596e9a 100644 --- a/drivers/perf/arm_cspmu/arm_cspmu.h +++ b/drivers/perf/arm_cspmu/arm_cspmu.h @@ -87,6 +87,11 @@ #define PMCFGR 0xE00 #define PMCR 0xE04 #define PMIIDR 0xE08 +#define PMPIDR0 0xFE0 +#define PMPIDR1 0xFE4 +#define PMPIDR2 0xFE8 +#define PMPIDR3 0xFEC +#define PMPIDR4 0xFD0 =20 /* PMCFGR register field */ #define PMCFGR_NCG GENMASK(31, 28) @@ -116,8 +121,34 @@ #define PMCR_E BIT(0) =20 /* PMIIDR register field */ -#define ARM_CSPMU_PMIIDR_IMPLEMENTER GENMASK(11, 0) -#define ARM_CSPMU_PMIIDR_PRODUCTID GENMASK(31, 20) +#define PMIIDR_IMPLEMENTER GENMASK(11, 0) +#define PMIIDR_IMPLEMENTER_DES_0 GENMASK(3, 0) +#define PMIIDR_IMPLEMENTER_DES_1 GENMASK(6, 4) +#define PMIIDR_IMPLEMENTER_DES_2 GENMASK(11, 8) +#define PMIIDR_REVISION GENMASK(15, 12) +#define PMIIDR_VARIANT GENMASK(19, 16) +#define PMIIDR_PRODUCTID GENMASK(31, 20) +#define PMIIDR_PRODUCTID_PART_0 GENMASK(27, 20) +#define PMIIDR_PRODUCTID_PART_1 GENMASK(31, 28) + +/* PMPIDR0 register field */ +#define PMPIDR0_PART_0 GENMASK(7, 0) + +/* PMPIDR1 register field */ +#define PMPIDR1_DES_0 GENMASK(7, 4) +#define PMPIDR1_PART_1 GENMASK(3, 0) + +/* PMPIDR2 register field */ +#define PMPIDR2_REVISION GENMASK(7, 4) +#define PMPIDR2_DES_1 GENMASK(2, 0) + +/* PMPIDR3 register field */ +#define PMPIDR3_REVAND GENMASK(7, 4) +#define PMPIDR3_CMOD GENMASK(3, 0) + +/* PMPIDR4 register field */ +#define PMPIDR4_SIZE GENMASK(7, 4) +#define PMPIDR4_DES_2 GENMASK(3, 0) =20 /* JEDEC-assigned JEP106 identification code */ #define ARM_CSPMU_IMPL_ID_NVIDIA 0x36B diff --git a/drivers/perf/arm_cspmu/nvidia_cspmu.c b/drivers/perf/arm_cspmu= /nvidia_cspmu.c index dc6d4e3e2a1b..b6cec351a142 100644 --- a/drivers/perf/arm_cspmu/nvidia_cspmu.c +++ b/drivers/perf/arm_cspmu/nvidia_cspmu.c @@ -322,7 +322,7 @@ static int nv_cspmu_init_ops(struct arm_cspmu *cspmu) if (!ctx) return -ENOMEM; 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X-OriginatorOrg: Nvidia.com X-MS-Exchange-CrossTenant-OriginalArrivalTime: 23 Sep 2025 00:21:01.9241 (UTC) X-MS-Exchange-CrossTenant-Network-Message-Id: 0d3d8925-e1be-4e48-1e0a-08ddfa3713e4 X-MS-Exchange-CrossTenant-Id: 43083d15-7273-40c1-b7db-39efd9ccc17a X-MS-Exchange-CrossTenant-OriginalAttributedTenantConnectingIp: TenantId=43083d15-7273-40c1-b7db-39efd9ccc17a;Ip=[216.228.117.160];Helo=[mail.nvidia.com] X-MS-Exchange-CrossTenant-AuthSource: DS1PEPF00017094.namprd03.prod.outlook.com X-MS-Exchange-CrossTenant-AuthAs: Anonymous X-MS-Exchange-CrossTenant-FromEntityHeader: HybridOnPrem X-MS-Exchange-Transport-CrossTenantHeadersStamped: SN7PR12MB8028 Content-Type: text/plain; charset="utf-8" Distinguish NVIDIA devices by revision and variant bits in PMIIDR register in addition to product id. Reviewed-by: Ilkka Koskinen Signed-off-by: Besar Wicaksono --- drivers/perf/arm_cspmu/nvidia_cspmu.c | 18 ++++++++---------- 1 file changed, 8 insertions(+), 10 deletions(-) diff --git a/drivers/perf/arm_cspmu/nvidia_cspmu.c b/drivers/perf/arm_cspmu= /nvidia_cspmu.c index b6cec351a142..ac91dc46501d 100644 --- a/drivers/perf/arm_cspmu/nvidia_cspmu.c +++ b/drivers/perf/arm_cspmu/nvidia_cspmu.c @@ -23,7 +23,7 @@ =20 #define NV_GENERIC_FILTER_ID_MASK GENMASK_ULL(31, 0) =20 -#define NV_PRODID_MASK GENMASK(31, 0) +#define NV_PRODID_MASK (PMIIDR_PRODUCTID | PMIIDR_VARIANT | PMIIDR_REVISIO= N) =20 #define NV_FORMAT_NAME_GENERIC 0 =20 @@ -220,7 +220,7 @@ struct nv_cspmu_match { =20 static const struct nv_cspmu_match nv_cspmu_match[] =3D { { - .prodid =3D 0x103, + .prodid =3D 0x10300000, .prodid_mask =3D NV_PRODID_MASK, .filter_mask =3D NV_PCIE_FILTER_ID_MASK, .filter_default_val =3D NV_PCIE_FILTER_ID_MASK, @@ -230,7 +230,7 @@ static const struct nv_cspmu_match nv_cspmu_match[] =3D= { .format_attr =3D pcie_pmu_format_attrs }, { - .prodid =3D 0x104, + .prodid =3D 0x10400000, .prodid_mask =3D NV_PRODID_MASK, .filter_mask =3D NV_NVL_C2C_FILTER_ID_MASK, .filter_default_val =3D NV_NVL_C2C_FILTER_ID_MASK, @@ -240,7 +240,7 @@ static const struct nv_cspmu_match nv_cspmu_match[] =3D= { .format_attr =3D nvlink_c2c_pmu_format_attrs }, { - .prodid =3D 0x105, + .prodid =3D 0x10500000, .prodid_mask =3D NV_PRODID_MASK, .filter_mask =3D NV_NVL_C2C_FILTER_ID_MASK, .filter_default_val =3D NV_NVL_C2C_FILTER_ID_MASK, @@ -250,7 +250,7 @@ static const struct nv_cspmu_match nv_cspmu_match[] =3D= { .format_attr =3D nvlink_c2c_pmu_format_attrs }, { - .prodid =3D 0x106, + .prodid =3D 0x10600000, .prodid_mask =3D NV_PRODID_MASK, .filter_mask =3D NV_CNVL_FILTER_ID_MASK, .filter_default_val =3D NV_CNVL_FILTER_ID_MASK, @@ -260,7 +260,7 @@ static const struct nv_cspmu_match nv_cspmu_match[] =3D= { .format_attr =3D cnvlink_pmu_format_attrs }, { - .prodid =3D 0x2CF, + .prodid =3D 0x2CF00000, .prodid_mask =3D NV_PRODID_MASK, .filter_mask =3D 0x0, .filter_default_val =3D 0x0, @@ -312,7 +312,6 @@ static char *nv_cspmu_format_name(const struct arm_cspm= u *cspmu, =20 static int nv_cspmu_init_ops(struct arm_cspmu *cspmu) { - u32 prodid; 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X-OriginatorOrg: Nvidia.com X-MS-Exchange-CrossTenant-OriginalArrivalTime: 23 Sep 2025 00:21:21.3325 (UTC) X-MS-Exchange-CrossTenant-Network-Message-Id: aeed8419-e5bf-4c2b-96bb-08ddfa371f7c X-MS-Exchange-CrossTenant-Id: 43083d15-7273-40c1-b7db-39efd9ccc17a X-MS-Exchange-CrossTenant-OriginalAttributedTenantConnectingIp: TenantId=43083d15-7273-40c1-b7db-39efd9ccc17a;Ip=[216.228.117.160];Helo=[mail.nvidia.com] X-MS-Exchange-CrossTenant-AuthSource: DS1PEPF0001708E.namprd03.prod.outlook.com X-MS-Exchange-CrossTenant-AuthAs: Anonymous X-MS-Exchange-CrossTenant-FromEntityHeader: HybridOnPrem X-MS-Exchange-Transport-CrossTenantHeadersStamped: MN2PR12MB4360 Content-Type: text/plain; charset="utf-8" Support NVIDIA PMU that utilizes the optional event filter2 register. Signed-off-by: Besar Wicaksono --- drivers/perf/arm_cspmu/nvidia_cspmu.c | 176 +++++++++++++++++++------- 1 file changed, 133 insertions(+), 43 deletions(-) diff --git a/drivers/perf/arm_cspmu/nvidia_cspmu.c b/drivers/perf/arm_cspmu= /nvidia_cspmu.c index ac91dc46501d..e06a06d3407b 100644 --- a/drivers/perf/arm_cspmu/nvidia_cspmu.c +++ b/drivers/perf/arm_cspmu/nvidia_cspmu.c @@ -40,10 +40,21 @@ =20 struct nv_cspmu_ctx { const char *name; - u32 filter_mask; - u32 filter_default_val; + struct attribute **event_attr; struct attribute **format_attr; + + u32 filter_mask; + u32 filter_default_val; + u32 filter2_mask; + u32 filter2_default_val; + + u32 (*get_filter)(const struct perf_event *event); + u32 (*get_filter2)(const struct perf_event *event); + + void *data; + + int (*init_data)(struct arm_cspmu *cspmu); }; =20 static struct attribute *scf_pmu_event_attrs[] =3D { @@ -144,6 +155,7 @@ static struct attribute *cnvlink_pmu_format_attrs[] =3D= { static struct attribute *generic_pmu_format_attrs[] =3D { ARM_CSPMU_FORMAT_EVENT_ATTR, ARM_CSPMU_FORMAT_FILTER_ATTR, + ARM_CSPMU_FORMAT_FILTER2_ATTR, NULL, }; =20 @@ -184,13 +196,36 @@ static u32 nv_cspmu_event_filter(const struct perf_ev= ent *event) return filter_val; } =20 +static u32 nv_cspmu_event_filter2(const struct perf_event *event) +{ + const struct nv_cspmu_ctx *ctx =3D + to_nv_cspmu_ctx(to_arm_cspmu(event->pmu)); + + const u32 filter_val =3D event->attr.config2 & ctx->filter2_mask; + + if (filter_val =3D=3D 0) + return ctx->filter2_default_val; + + return filter_val; +} + static void nv_cspmu_set_ev_filter(struct arm_cspmu *cspmu, const struct perf_event *event) { - u32 filter =3D nv_cspmu_event_filter(event); - u32 offset =3D PMEVFILTR + (4 * event->hw.idx); + u32 filter, offset; + const struct nv_cspmu_ctx *ctx =3D + to_nv_cspmu_ctx(to_arm_cspmu(event->pmu)); + offset =3D 4 * event->hw.idx; =20 - writel(filter, cspmu->base0 + offset); + if (ctx->get_filter) { + filter =3D ctx->get_filter(event); + writel(filter, cspmu->base0 + PMEVFILTR + offset); + } + + if (ctx->get_filter2) { + filter =3D ctx->get_filter2(event); + writel(filter, cspmu->base0 + PMEVFILT2R + offset); + } } =20 static void nv_cspmu_set_cc_filter(struct arm_cspmu *cspmu, @@ -210,74 +245,120 @@ enum nv_cspmu_name_fmt { struct nv_cspmu_match { u32 prodid; u32 prodid_mask; - u64 filter_mask; - u32 filter_default_val; const char *name_pattern; enum nv_cspmu_name_fmt name_fmt; - struct attribute **event_attr; - struct attribute **format_attr; + struct nv_cspmu_ctx template_ctx; + struct arm_cspmu_impl_ops ops; }; =20 static const struct nv_cspmu_match nv_cspmu_match[] =3D { { .prodid =3D 0x10300000, .prodid_mask =3D NV_PRODID_MASK, - .filter_mask =3D NV_PCIE_FILTER_ID_MASK, - .filter_default_val =3D NV_PCIE_FILTER_ID_MASK, .name_pattern =3D "nvidia_pcie_pmu_%u", .name_fmt =3D NAME_FMT_SOCKET, - .event_attr =3D mcf_pmu_event_attrs, - .format_attr =3D pcie_pmu_format_attrs + .template_ctx =3D { + .event_attr =3D mcf_pmu_event_attrs, + .format_attr =3D pcie_pmu_format_attrs, + .filter_mask =3D NV_PCIE_FILTER_ID_MASK, + .filter_default_val =3D NV_PCIE_FILTER_ID_MASK, + .filter2_mask =3D 0x0, + .filter2_default_val =3D 0x0, + .get_filter =3D nv_cspmu_event_filter, + .get_filter2 =3D NULL, + .data =3D NULL, + .init_data =3D NULL + }, }, { .prodid =3D 0x10400000, .prodid_mask =3D NV_PRODID_MASK, - .filter_mask =3D NV_NVL_C2C_FILTER_ID_MASK, - .filter_default_val =3D NV_NVL_C2C_FILTER_ID_MASK, .name_pattern =3D "nvidia_nvlink_c2c1_pmu_%u", .name_fmt =3D NAME_FMT_SOCKET, - .event_attr =3D mcf_pmu_event_attrs, - .format_attr =3D nvlink_c2c_pmu_format_attrs + .template_ctx =3D { + .event_attr =3D mcf_pmu_event_attrs, + .format_attr =3D nvlink_c2c_pmu_format_attrs, + .filter_mask =3D NV_NVL_C2C_FILTER_ID_MASK, + .filter_default_val =3D NV_NVL_C2C_FILTER_ID_MASK, + .filter2_mask =3D 0x0, + .filter2_default_val =3D 0x0, + .get_filter =3D nv_cspmu_event_filter, + .get_filter2 =3D NULL, + .data =3D NULL, + .init_data =3D NULL + }, }, { .prodid =3D 0x10500000, .prodid_mask =3D NV_PRODID_MASK, - .filter_mask =3D NV_NVL_C2C_FILTER_ID_MASK, - .filter_default_val =3D NV_NVL_C2C_FILTER_ID_MASK, .name_pattern =3D "nvidia_nvlink_c2c0_pmu_%u", .name_fmt =3D NAME_FMT_SOCKET, - .event_attr =3D mcf_pmu_event_attrs, - .format_attr =3D nvlink_c2c_pmu_format_attrs + .template_ctx =3D { + .event_attr =3D mcf_pmu_event_attrs, + .format_attr =3D nvlink_c2c_pmu_format_attrs, + .filter_mask =3D NV_NVL_C2C_FILTER_ID_MASK, + .filter_default_val =3D NV_NVL_C2C_FILTER_ID_MASK, + .filter2_mask =3D 0x0, + .filter2_default_val =3D 0x0, + .get_filter =3D nv_cspmu_event_filter, + .get_filter2 =3D NULL, + .data =3D NULL, + .init_data =3D NULL + }, }, { .prodid =3D 0x10600000, .prodid_mask =3D NV_PRODID_MASK, - .filter_mask =3D NV_CNVL_FILTER_ID_MASK, - .filter_default_val =3D NV_CNVL_FILTER_ID_MASK, .name_pattern =3D "nvidia_cnvlink_pmu_%u", .name_fmt =3D NAME_FMT_SOCKET, - .event_attr =3D mcf_pmu_event_attrs, - .format_attr =3D cnvlink_pmu_format_attrs + .template_ctx =3D { + .event_attr =3D mcf_pmu_event_attrs, + .format_attr =3D cnvlink_pmu_format_attrs, + .filter_mask =3D NV_CNVL_FILTER_ID_MASK, + .filter_default_val =3D NV_CNVL_FILTER_ID_MASK, + .filter2_mask =3D 0x0, + .filter2_default_val =3D 0x0, + .get_filter =3D nv_cspmu_event_filter, + .get_filter2 =3D NULL, + .data =3D NULL, + .init_data =3D NULL + }, }, { .prodid =3D 0x2CF00000, .prodid_mask =3D NV_PRODID_MASK, - .filter_mask =3D 0x0, - .filter_default_val =3D 0x0, .name_pattern =3D "nvidia_scf_pmu_%u", .name_fmt =3D NAME_FMT_SOCKET, - .event_attr =3D scf_pmu_event_attrs, - .format_attr =3D scf_pmu_format_attrs + .template_ctx =3D { + .event_attr =3D scf_pmu_event_attrs, + .format_attr =3D scf_pmu_format_attrs, + .filter_mask =3D 0x0, + .filter_default_val =3D 0x0, + .filter2_mask =3D 0x0, + .filter2_default_val =3D 0x0, + .get_filter =3D nv_cspmu_event_filter, + .get_filter2 =3D NULL, + .data =3D NULL, + .init_data =3D NULL + }, }, { .prodid =3D 0, .prodid_mask =3D 0, - .filter_mask =3D NV_GENERIC_FILTER_ID_MASK, - .filter_default_val =3D NV_GENERIC_FILTER_ID_MASK, .name_pattern =3D "nvidia_uncore_pmu_%u", .name_fmt =3D NAME_FMT_GENERIC, - .event_attr =3D generic_pmu_event_attrs, - .format_attr =3D generic_pmu_format_attrs + .template_ctx =3D { + .event_attr =3D generic_pmu_event_attrs, + .format_attr =3D generic_pmu_format_attrs, + .filter_mask =3D NV_GENERIC_FILTER_ID_MASK, + .filter_default_val =3D NV_GENERIC_FILTER_ID_MASK, + .filter2_mask =3D NV_GENERIC_FILTER_ID_MASK, + .filter2_default_val =3D NV_GENERIC_FILTER_ID_MASK, + .get_filter =3D nv_cspmu_event_filter, + .get_filter2 =3D nv_cspmu_event_filter2, + .data =3D NULL, + .init_data =3D NULL + }, }, }; =20 @@ -310,6 +391,14 @@ static char *nv_cspmu_format_name(const struct arm_csp= mu *cspmu, return name; } =20 +#define SET_OP(name, impl, match, default_op) \ + do { \ + if (match->ops.name) \ + impl->name =3D match->ops.name; \ + else if (default_op !=3D NULL) \ + impl->name =3D default_op; \ + } while (false) + static int nv_cspmu_init_ops(struct arm_cspmu *cspmu) { struct nv_cspmu_ctx *ctx; @@ -330,20 +419,21 @@ static int nv_cspmu_init_ops(struct arm_cspmu *cspmu) break; } =20 - ctx->name =3D nv_cspmu_format_name(cspmu, match); - ctx->filter_mask =3D match->filter_mask; - ctx->filter_default_val =3D match->filter_default_val; - ctx->event_attr =3D match->event_attr; - ctx->format_attr =3D match->format_attr; + /* Initialize the context with the matched template. */ + memcpy(ctx, &match->template_ctx, sizeof(struct nv_cspmu_ctx)); + ctx->name =3D nv_cspmu_format_name(cspmu, match); =20 cspmu->impl.ctx =3D ctx; =20 /* NVIDIA specific callbacks. */ - impl_ops->set_cc_filter =3D nv_cspmu_set_cc_filter; - impl_ops->set_ev_filter =3D nv_cspmu_set_ev_filter; - impl_ops->get_event_attrs =3D nv_cspmu_get_event_attrs; - impl_ops->get_format_attrs =3D nv_cspmu_get_format_attrs; - impl_ops->get_name =3D nv_cspmu_get_name; + SET_OP(set_cc_filter, impl_ops, match, nv_cspmu_set_cc_filter); + SET_OP(set_ev_filter, impl_ops, match, nv_cspmu_set_ev_filter); + SET_OP(get_event_attrs, impl_ops, match, nv_cspmu_get_event_attrs); + SET_OP(get_format_attrs, impl_ops, match, nv_cspmu_get_format_attrs); + SET_OP(get_name, impl_ops, match, nv_cspmu_get_name); + + if (ctx->init_data) + return ctx->init_data(cspmu); =20 return 0; } --=20 2.50.1