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Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Content-Transfer-Encoding: quoted-printable Message-Id: <20250923-v4-patch-final-v1-1-2283ad7cbf88@thundersoft.com> References: <20250923-v4-patch-final-v1-0-2283ad7cbf88@thundersoft.com> In-Reply-To: <20250923-v4-patch-final-v1-0-2283ad7cbf88@thundersoft.com> To: Rob Herring , Krzysztof Kozlowski , Conor Dooley , Ge Gordon , BST Linux Kernel Upstream Group , Catalin Marinas , Will Deacon , Ulf Hansson , Adrian Hunter , Arnd Bergmann Cc: devicetree@vger.kernel.org, linux-kernel@vger.kernel.org, linux-arm-kernel@lists.infradead.org, linux-mmc@vger.kernel.org, soc@lists.linux.dev, Albert Yang X-Mailer: b4 0.14.2 X-Developer-Signature: v=1; a=ed25519-sha256; t=1758607828; l=1195; i=yangzh0906@thundersoft.com; s=20250814; h=from:subject:message-id; bh=To99qns2zIXO51nztUpDVeLTKR/SUM5m6vG3Z0d9mV0=; b=n6u/4gLR0xKZcjrIKnlqsvmqSYP53mO5T6o2D3OTbvhgdVK5clLU23j27vcnVsi8ukoOplW+y C3gA5zsFROdCnEA/SuVHq/2Z03qIG8ST3G/CZg/HxfXnSyCuSyLCoo5 X-Developer-Key: i=yangzh0906@thundersoft.com; a=ed25519; pk=bEcgALL9KpUg/m7zH44r50xa/re91dI9SA0vGV1/bu4= X-HM-Tid: 0a997531ea2509cckunmfc27e25b4e01f5 X-HM-MType: 1 X-HM-Spam-Status: e1kfGhgUHx5ZQUpXWQgPGg8OCBgUHx5ZQUlOS1dZFg8aDwILHllBWSg2Ly tZV1koWUFITzdXWS1ZQUlXWQ8JGhUIEh9ZQVkaGBpKVkxIHh1NTx5CTUkYQlYVFAkWGhdVEwETFh oSFyQUDg9ZV1kYEgtZQVlKSkxVSkNPVUpJQlVKSE9ZV1kWGg8SFR0UWUFZT0tIVUpLSU9PT0hVSk tLVUpCS0tZBg++ DKIM-Signature: a=rsa-sha256; b=SN/zKi+YVII4pB67yrsOXEVx+2yvQOtit8lh7jbXqQ4yWChJkN/YD2zn+eY3tAoAJ32L2pSq2h1GbWpaguP1S0Gs/TtC1nZffRQb5PEhZqthBy4CX8TrJnsLeLhH4Qsh2T+Xf55/qkVa2pcFlpGWxo9PepS8NzQPPJzfkIfw67Y=; c=relaxed/relaxed; s=default; d=thundersoft.com; v=1; bh=JDcHxGOvabpWrg24OH+LFpYkmiRSfnuaNCDEqWh+fbE=; h=date:mime-version:subject:message-id:from; Black Sesame Technologies Co., Ltd.s a leading automotive-grade computing SoC and SoC-based intelligent vehicle solution provider. Link: https://bst.ai/. Signed-off-by: Albert Yang Acked-by: Rob Herring (Arm) --- Changes for v4: - adjust ^bst to the correct order - adjust Acked-by order Changes for v3: - No changes Changes for v2: - No changes --- Documentation/devicetree/bindings/vendor-prefixes.yaml | 2 ++ 1 file changed, 2 insertions(+) diff --git a/Documentation/devicetree/bindings/vendor-prefixes.yaml b/Docum= entation/devicetree/bindings/vendor-prefixes.yaml index 9ec8947dfcad2fa53b2dca2ca06a63710771a600..084ba39016ae23150dd8f140da1= 6f9b1cd55f4cf 100644 --- a/Documentation/devicetree/bindings/vendor-prefixes.yaml +++ b/Documentation/devicetree/bindings/vendor-prefixes.yaml @@ -243,6 +243,8 @@ patternProperties: description: Shanghai Broadmobi Communication Technology Co.,Ltd. "^bsh,.*": description: BSH Hausgeraete GmbH + "^bst,.*": + description: Black Sesame Technologies Co., Ltd. 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charset="utf-8" Content-Transfer-Encoding: quoted-printable Message-Id: <20250923-v4-patch-final-v1-2-2283ad7cbf88@thundersoft.com> References: <20250923-v4-patch-final-v1-0-2283ad7cbf88@thundersoft.com> In-Reply-To: <20250923-v4-patch-final-v1-0-2283ad7cbf88@thundersoft.com> To: Rob Herring , Krzysztof Kozlowski , Conor Dooley , Ge Gordon , BST Linux Kernel Upstream Group , Catalin Marinas , Will Deacon , Ulf Hansson , Adrian Hunter , Arnd Bergmann Cc: devicetree@vger.kernel.org, linux-kernel@vger.kernel.org, linux-arm-kernel@lists.infradead.org, linux-mmc@vger.kernel.org, soc@lists.linux.dev, Albert Yang , Krzysztof Kozlowski X-Mailer: b4 0.14.2 X-Developer-Signature: v=1; a=ed25519-sha256; t=1758607828; l=1892; i=yangzh0906@thundersoft.com; s=20250814; h=from:subject:message-id; bh=eWqieNtDLZJBpQIXEibnf+P3a6GVeHnQ5dMPHSti1nI=; b=ooly4LSDwkrjPNsdIM9qUiMJZDxlx0PMeSMu/5TzTp+ZKRh97izHCDoR1OsTpaMc+4snOuWAN CTb6obAD2pSBsdJzbQ4EWSyg7a8GzMTeBsk/vs81gUHuBc8UySKxFQr X-Developer-Key: i=yangzh0906@thundersoft.com; a=ed25519; pk=bEcgALL9KpUg/m7zH44r50xa/re91dI9SA0vGV1/bu4= X-HM-Tid: 0a997531ef2a09cckunmfc27e25b4e0226 X-HM-MType: 1 X-HM-Spam-Status: e1kfGhgUHx5ZQUpXWQgPGg8OCBgUHx5ZQUlOS1dZFg8aDwILHllBWSg2Ly tZV1koWUFITzdXWS1ZQUlXWQ8JGhUIEh9ZQVlCQ0tMVktJQ0gaGBpNHkoZGFYVFAkWGhdVEwETFh oSFyQUDg9ZV1kYEgtZQVlKSkxVSkNPVUpJQlVKSE9ZV1kWGg8SFR0UWUFZT0tIVUpLSEpOTE5VSk tLVUpCS0tZBg++ DKIM-Signature: a=rsa-sha256; b=Wti8Khl09WilIY/Kt4OJjPDBGwcGXaCw+n0gqtJdKvcCeTP+jOulzXNVqjK8kwmjGJ1ZF8zM+5jrMHSmjWwDqLHSgw0HoLfQBZb1HBItN3+afVYw8Ejczy3tk3BDhtZ8omG21DBmtBIq8KwJh8rxyod14irEHFUTQlgadPRGtoY=; c=relaxed/relaxed; s=default; d=thundersoft.com; v=1; bh=aWAYbqoYVtppRStnG1G4tD44qpuBAMIK8fz0sA1UFI4=; h=date:mime-version:subject:message-id:from; Add device tree bindings for Black Sesame Technologies Arm SoC, it consists several SoC models like C1200, etc. Signed-off-by: Albert Yang Reviewed-by: Krzysztof Kozlowski --- Changes for v4: - remove Signed-off-by: Ge Gordon - add Reviewed-by Krzysztof Kozlowski info Changes for v3: - Add Signed-off-by: Ge Gordon Changes for v2: - Removed unnecessary pipe (`|`) in description - Dropped invalid `compatible` entry for standalone SoC - Removed root node (`$nodename: '/'`) definition --- Documentation/devicetree/bindings/arm/bst.yaml | 31 ++++++++++++++++++++++= ++++ 1 file changed, 31 insertions(+) diff --git a/Documentation/devicetree/bindings/arm/bst.yaml b/Documentation= /devicetree/bindings/arm/bst.yaml new file mode 100644 index 0000000000000000000000000000000000000000..a3a7f424fd57f23efeed9b076c2= 612ba672be3e2 --- /dev/null +++ b/Documentation/devicetree/bindings/arm/bst.yaml @@ -0,0 +1,31 @@ +# SPDX-License-Identifier: GPL-2.0-only OR BSD-2-Clause +%YAML 1.2 +--- +$id: http://devicetree.org/schemas/arm/bst.yaml# +$schema: http://devicetree.org/meta-schemas/core.yaml# + +title: BST platforms + +description: + Black Sesame Technologies (BST) is a semiconductor company that produces + automotive-grade system-on-chips (SoCs) for intelligent driving, focusing + on computer vision and AI capabilities. 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BST produces automotive-grade system-on-chips for intelligent driving, focusing on computer vision and AI capabilities. The BST C1200 family includes SoCs for ADAS and autonomous driving applications. Signed-off-by: Albert Yang --- Changes for v4: - remove Signed-off-by: Ge Gordon Changes for v3: - Reword subject from "for bst silicons" to "for Black Sesame Technologies SoCs" - drop unrelated whitespace hunk Changes for v2: - Placed the configuration entry in correct alphabetical order - Used generic family name (ARCH_BST) instead of SoC-specific naming - Followed upstream kernel naming and description conventions --- arch/arm64/Kconfig.platforms | 8 ++++++++ 1 file changed, 8 insertions(+) diff --git a/arch/arm64/Kconfig.platforms b/arch/arm64/Kconfig.platforms index a88f5ad9328c2ee13a0822782af6c83899273f14..8a870b213dee930861bab39dce2= df295c387cf89 100644 --- a/arch/arm64/Kconfig.platforms +++ b/arch/arm64/Kconfig.platforms @@ -112,6 +112,14 @@ config ARCH_BLAIZE help This enables support for the Blaize SoC family =20 +config ARCH_BST + bool "Black Sesame Technologies SoC Family" + help + This enables support for Black Sesame Technologies (BST) SoC family. + BST produces automotive-grade system-on-chips for intelligent driving, + focusing on computer vision and AI capabilities. The BST C1200 family + includes SoCs for ADAS and autonomous driving applications. + config ARCH_CIX bool "Cixtech SoC family" help --=20 2.43.0 From nobody Thu Oct 2 03:30:35 2025 Received: from mail-m155104.qiye.163.com (mail-m155104.qiye.163.com [101.71.155.104]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id A38F331196F; Tue, 23 Sep 2025 07:26:14 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=none smtp.client-ip=101.71.155.104 ARC-Seal: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1758612379; cv=none; b=kQPf+j3jfN6pXnQXKyCD2F2jyRnrRL4Nnh0K5deIdzCti3sV4xlcIcY1CzfyrAHjXQ1gGqQLz8hPd21xaaHXqBYTVSTN6ipIqIyQeBBMflaEuS69WT+5yklKjk477kuhRs/AH+IyTZ7Xq/fFEeJRxPQ/BFB31Ae15yFm/7JSDrw= ARC-Message-Signature: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1758612379; c=relaxed/simple; bh=D/w1Y1iVuxoaJKfCtX6pNsQnKymjUqB4eNMUUWKvWCY=; h=From:Date:Subject:MIME-Version:Content-Type:Message-Id:References: In-Reply-To:To:Cc; b=o+HIBvdWd/ihxosB5FvtpLK8mYj8UI8jR29U1u8tYzFEozvpTb10CeIzN3TDlo3+sqzRRocLkGJSPsghVvHch8i1kOnx3DpWrMs5vr0iYogl2dJp/G6mRAPKj1ZNjOUnIHJ7t15RsbTBLzlOAl834K2D9hjeRctb+yHijudOscM= ARC-Authentication-Results: i=1; smtp.subspace.kernel.org; dmarc=pass (p=none dis=none) header.from=thundersoft.com; spf=pass smtp.mailfrom=thundersoft.com; dkim=pass (1024-bit key) header.d=thundersoft.com header.i=@thundersoft.com header.b=mDWxXO5f; arc=none smtp.client-ip=101.71.155.104 Authentication-Results: smtp.subspace.kernel.org; dmarc=pass (p=none dis=none) header.from=thundersoft.com Authentication-Results: smtp.subspace.kernel.org; spf=pass smtp.mailfrom=thundersoft.com Authentication-Results: smtp.subspace.kernel.org; dkim=pass (1024-bit key) header.d=thundersoft.com header.i=@thundersoft.com header.b="mDWxXO5f" Received: from [127.0.1.1] (unknown [117.184.129.134]) by smtp.qiye.163.com (Hmail) with ESMTP id 23bdebfe3; Tue, 23 Sep 2025 14:10:33 +0800 (GMT+08:00) From: Albert Yang Date: Tue, 23 Sep 2025 14:10:10 +0800 Subject: [PATCH 4/9] dt-bindings: mmc: add binding for BST DWCMSHC SDHCI controller Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Content-Transfer-Encoding: quoted-printable Message-Id: <20250923-v4-patch-final-v1-4-2283ad7cbf88@thundersoft.com> References: <20250923-v4-patch-final-v1-0-2283ad7cbf88@thundersoft.com> In-Reply-To: <20250923-v4-patch-final-v1-0-2283ad7cbf88@thundersoft.com> To: Rob Herring , Krzysztof Kozlowski , Conor Dooley , Ge Gordon , BST Linux Kernel Upstream Group , Catalin Marinas , Will Deacon , Ulf Hansson , Adrian Hunter , Arnd Bergmann Cc: devicetree@vger.kernel.org, linux-kernel@vger.kernel.org, linux-arm-kernel@lists.infradead.org, linux-mmc@vger.kernel.org, soc@lists.linux.dev, Albert Yang X-Mailer: b4 0.14.2 X-Developer-Signature: v=1; a=ed25519-sha256; t=1758607828; l=3433; i=yangzh0906@thundersoft.com; s=20250814; h=from:subject:message-id; bh=D/w1Y1iVuxoaJKfCtX6pNsQnKymjUqB4eNMUUWKvWCY=; b=9y70kes2Rz0dOny17wbciJHU43o4HZRoaSvtxFBCTfTF8Op4ezQn9gcxOb/9g/ZNiWUhalM15 /1e4NP9405iBEucV5VDbo/AwX6oWNbK08gxPo3Jc9fit8GlVXsHzjIK X-Developer-Key: i=yangzh0906@thundersoft.com; a=ed25519; pk=bEcgALL9KpUg/m7zH44r50xa/re91dI9SA0vGV1/bu4= X-HM-Tid: 0a997531f9c209cckunmfc27e25b4e0298 X-HM-MType: 1 X-HM-Spam-Status: e1kfGhgUHx5ZQUpXWQgPGg8OCBgUHx5ZQUlOS1dZFg8aDwILHllBWSg2Ly tZV1koWUFITzdXWS1ZQUlXWQ8JGhUIEh9ZQVkZQkIYVh1PShpNSk0dSBoZHlYVFAkWGhdVEwETFh oSFyQUDg9ZV1kYEgtZQVlKSkxVSkNPVUpJQlVKSE9ZV1kWGg8SFR0UWUFZT0tIVUpLSU9PT0hVSk tLVUpCS0tZBg++ DKIM-Signature: a=rsa-sha256; b=mDWxXO5fUcYrzXAEpL6WHUPc1f8Y4Pa3BHfM/c7I4NxLWGD3shbVqN5OsblcVlLmcrFGBjHYKXHzgAAdhTnI8Ekci5CYMf+9zNK0eRVIkGLUHVYTxipu1cbbZ4j+RtywhMO0mpMzoKzjULkNTWR7wW+ZA5wN/rjhl99EQmwNRUI=; c=relaxed/relaxed; s=default; d=thundersoft.com; v=1; bh=kzr6ecyyae77VtZYq1ReJ86cHFdZjbBe3GMXfzbB9gc=; h=date:mime-version:subject:message-id:from; Add device tree binding documentation for the Black Sesame Technologies (BST) DWCMSHC SDHCI controller. This binding describes the required and optional properties for the bst,c1200-dwcmshc-sdhci compatible controller, including register layout, interrupts, bus width, clock configuration, and other controller-specific features. Signed-off-by: Albert Yang --- Changes for v4: - Remove Signed-off-by line for Ge Gordon - Change `$ref: mmc-controller.yaml#` to `$ref: sdhci-common.yaml#` - Change compatible string from `bst,c1200-dwcmshc-sdhci` to `bst,c1200-sdh= ci` Changes for v3: - Switch reg schema from maxItems to explicit items with per-entry descript= ions - Improve example: add irq.h include and wrap under a bus node with address= /size cells - Drop status =3D "disabled" from example; keep example concise - Add Signed-off-by: Ge Gordon Changes for v2: - Simplify description, remove redundant paragraphs - Update $schema to reference mmc-specific scheme - Correct compatible to add soc name (bst,c1200-dwcmshc-sdhci) - Remove all redundant property descriptions - Drop invalid mmc_crm_base/size properties, use reg for all address ranges - Clean up required properties to only essential entries - Standardize example DTS format, fix reg syntax and property ordering - Remove additionalProperties: true --- .../devicetree/bindings/mmc/bst,dwcmshc-sdhci.yaml | 70 ++++++++++++++++++= ++++ 1 file changed, 70 insertions(+) diff --git a/Documentation/devicetree/bindings/mmc/bst,dwcmshc-sdhci.yaml b= /Documentation/devicetree/bindings/mmc/bst,dwcmshc-sdhci.yaml new file mode 100644 index 0000000000000000000000000000000000000000..7f16e6db39690cb7621d167bf7b= c492f814ea693 --- /dev/null +++ b/Documentation/devicetree/bindings/mmc/bst,dwcmshc-sdhci.yaml @@ -0,0 +1,70 @@ +# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause) +%YAML 1.2 +--- +$id: http://devicetree.org/schemas/mmc/bst,dwcmshc-sdhci.yaml# +$schema: http://devicetree.org/meta-schemas/core.yaml# + +title: Black Sesame Technologies DWCMSHC SDHCI Controller + +maintainers: + - Ge Gordon + +allOf: + - $ref: sdhci-common.yaml# + +properties: + compatible: + const: bst,c1200-sdhci + + reg: + items: + - description: Core SDHCI registers + - description: CRM registers + + interrupts: + maxItems: 1 + + clocks: + maxItems: 1 + + clock-names: + items: + - const: core + + memory-region: + maxItems: 1 + + dma-coherent: true + +required: + - compatible + - reg + - interrupts + - clocks + - clock-names + +unevaluatedProperties: false + +examples: + - | + #include + #include + + bus { + #address-cells =3D <2>; + #size-cells =3D <2>; + + mmc@22200000 { + compatible =3D "bst,c1200-dwcmshc-sdhci"; + reg =3D <0x0 0x22200000 0x0 0x1000>, + <0x0 0x23006000 0x0 0x1000>; + interrupts =3D ; + clocks =3D <&clk_mmc>; + clock-names =3D "core"; + memory-region =3D <&mmc0_reserved>; + max-frequency =3D <200000000>; + bus-width =3D <8>; + non-removable; + dma-coherent; + }; + }; --=20 2.43.0 From nobody Thu Oct 2 03:30:35 2025 Received: from mail-m3286.qiye.163.com (mail-m3286.qiye.163.com [220.197.32.86]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id 576D631D379; Tue, 23 Sep 2025 08:32:59 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=none smtp.client-ip=220.197.32.86 ARC-Seal: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1758616383; cv=none; b=LYcxtkeP0nmgHpiQVi+HpBhb9RNhWtp8suqU6nBA9kRN0cQctZF1Qi3IUsSm2rxsFn+85TKChQZjRMow+Wx+74U9GAEC7U95DNdHM9/0aDmiTQkPSpE+15R7+nkDG/MZDp+vmWLFDtT0xodOe4DXcWcf4PUX7WKGRLJ3KG3Rszg= ARC-Message-Signature: i=1; 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Tue, 23 Sep 2025 14:10:34 +0800 (GMT+08:00) From: Albert Yang Date: Tue, 23 Sep 2025 14:10:11 +0800 Subject: [PATCH 5/9] mmc: sdhci: add Black Sesame Technologies BST C1200 controller driver Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Content-Transfer-Encoding: quoted-printable Message-Id: <20250923-v4-patch-final-v1-5-2283ad7cbf88@thundersoft.com> References: <20250923-v4-patch-final-v1-0-2283ad7cbf88@thundersoft.com> In-Reply-To: <20250923-v4-patch-final-v1-0-2283ad7cbf88@thundersoft.com> To: Rob Herring , Krzysztof Kozlowski , Conor Dooley , Ge Gordon , BST Linux Kernel Upstream Group , Catalin Marinas , Will Deacon , Ulf Hansson , Adrian Hunter , Arnd Bergmann Cc: devicetree@vger.kernel.org, linux-kernel@vger.kernel.org, linux-arm-kernel@lists.infradead.org, linux-mmc@vger.kernel.org, soc@lists.linux.dev, Albert Yang X-Mailer: b4 0.14.2 X-Developer-Signature: v=1; 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h=date:mime-version:subject:message-id:from; Add SDHCI controller driver for Black Sesame Technologies C1200 SoC. This driver supports the DWCMSHC SDHCI controller with BST-specific enhancements including: - Custom clock management and tuning - Power management support - BST-specific register configurations - Support for eMMC and SD card interfaces - Hardware limitation workaround for 32-bit DMA addressing The driver addresses specific hardware constraints where: - System memory uses 64-bit bus, eMMC controller uses 32-bit bus - eMMC controller cannot access memory through SMMU due to hardware bug - All system DRAM is configured outside 4GB boundary (ZONE_DMA32) - Uses SRAM-based bounce buffer within 32-bit address space Signed-off-by: Ge Gordon Signed-off-by: Albert Yang Acked-by: Arnd Bergmann --- Changes for v4: - Rename all functions from bst_* to sdhci_bst_* for better namespace consi= stency - Rename driver file from sdhci-of-bst-c1200.c to sdhci-of-bst.c - Rename dwcmshc_priv structure to sdhci_bst_priv for clarity - Update driver name from "sdhci-dwcmshc" to "sdhci-bst" throughout - Add comprehensive register bit mask definitions and named constants - Replace manual polling loops with read_poll_timeout() for clock stability - Add dedicated sdhci_bst_wait_int_clk() function for internal clock manage= ment - Completely rewrite power management with proper power-off handling - Enhance clock control with read-modify-write operations to avoid clobberi= ng - Add MBIU burst mode configuration based on power state - Improve error handling and cleanup in probe/remove functions - Simplify bounce buffer allocation and remove redundant MMC parameter adju= stments - Add SDHCI_QUIRK_BROKEN_ADMA quirk for hardware limitation - Replace ioread32/iowrite32 with readl/writel for consistency - Update copyright year and simplify license text - Improve tuning algorithm with clearer variable naming - Enhance register access patterns with proper bit field manipulation - Add power-off clock management to reduce idle power consumption - Add Acked-by: Arnd Bergmann Changes for v3: - Simplify dwcmshc_priv structure by removing unused fields - Improve helper functions with better encapsulation - Use devm_platform_ioremap_resource() for resource management - Update Kconfig description and alphabetical ordering - Clarify documentation on hardware limitations and bounce buffer approach - Remove duplicate sdhci_writew SDHCI_CLOCK_CONTROL Changes for v2: - Remove COMMON_CLK dependency from Kconfig (MMC_SDHCI_BST) - Add ARCH_BST || COMPILE_TEST dependency from Kconfig (MMC_SDHCI_BST) - Replace temporary ioremap with persistent mapping - Map CRM registers once during probe instead of per-access - Add proper cleanup in remove callback - Refactor bounce buffer allocation with simplified error handling - Remove unnecessary DMA configuration layers - Prune unused headers and legacy vendor debug code - Remove deprecated sdhci_bst_print_vendor() export - Convert internal functions to static scope - Standardize naming conventions (DRIVER_NAME, DEFAULT_MAX_FREQ) - Optimize clock configuration routines - Fix register access macros for EMMC_CTRL with proper offset calculation - Correct device tree compatibility string to "bst,c1200-dwcmshc-sdhci" - Add robust ioremap error checking - Improve bounce buffer allocation failure handling - Update MODULE_DESCRIPTION and AUTHOR fields - Add explanatory comments for hardware limitations - Remove redundant multi-host setup infrastructure - Fix build warnings from lkp (kernel test robot) --- drivers/mmc/host/Kconfig | 14 ++ drivers/mmc/host/Makefile | 1 + drivers/mmc/host/sdhci-of-bst.c | 544 ++++++++++++++++++++++++++++++++++++= ++++ 3 files changed, 559 insertions(+) diff --git a/drivers/mmc/host/Kconfig b/drivers/mmc/host/Kconfig index 7232de1c068873d9bccec0b3b43ece939cb84894..75c37be559d23bff773bbe3f018= b76c34ad710ca 100644 --- a/drivers/mmc/host/Kconfig +++ b/drivers/mmc/host/Kconfig @@ -429,6 +429,20 @@ config MMC_SDHCI_BCM_KONA =20 If you have a controller with this interface, say Y or M here. =20 +config MMC_SDHCI_BST + tristate "SDHCI support for Black Sesame Technologies BST C1200 controlle= r" + depends on ARCH_BST || COMPILE_TEST + depends on MMC_SDHCI_PLTFM + depends on OF + help + This selects the Secure Digital Host Controller Interface (SDHCI) + for Black Sesame Technologies BST C1200 SoC. The controller is + based on Synopsys DesignWare Cores Mobile Storage Controller but + requires platform-specific workarounds for hardware limitations. + + If you have a controller with this interface, say Y or M here. + If unsure, say N. + config MMC_SDHCI_F_SDH30 tristate "SDHCI support for Fujitsu Semiconductor F_SDH30" depends on MMC_SDHCI_PLTFM diff --git a/drivers/mmc/host/Makefile b/drivers/mmc/host/Makefile index 5057fea8afb696e210e465a6a2aafc68adad7854..ee412e6b84d6c91f80654e53d0a= 05b549d4b6171 100644 --- a/drivers/mmc/host/Makefile +++ b/drivers/mmc/host/Makefile @@ -13,6 +13,7 @@ obj-$(CONFIG_MMC_MXS) +=3D mxs-mmc.o obj-$(CONFIG_MMC_SDHCI) +=3D sdhci.o obj-$(CONFIG_MMC_SDHCI_UHS2) +=3D sdhci-uhs2.o obj-$(CONFIG_MMC_SDHCI_PCI) +=3D sdhci-pci.o +obj-$(CONFIG_MMC_SDHCI_BST) +=3D sdhci-of-bst.o sdhci-pci-y +=3D sdhci-pci-core.o sdhci-pci-o2micro.o sdhci-pci-arasan.o= \ sdhci-pci-dwc-mshc.o sdhci-pci-gli.o obj-$(CONFIG_MMC_SDHCI_ACPI) +=3D sdhci-acpi.o diff --git a/drivers/mmc/host/sdhci-of-bst.c b/drivers/mmc/host/sdhci-of-bs= t.c new file mode 100644 index 0000000000000000000000000000000000000000..b19b763f216a25f58d37c8e288a= 8aa791f1e20f7 --- /dev/null +++ b/drivers/mmc/host/sdhci-of-bst.c @@ -0,0 +1,544 @@ +// SPDX-License-Identifier: GPL-2.0+ +/* + * SDHCI driver for Black Sesame Technologies C1200 controller + * + * Copyright (c) 2025 Black Sesame Technologies + */ + +#include +#include +#include +#include +#include +#include +#include +#include +#include "sdhci.h" +#include "sdhci-pltfm.h" + +/* SDHCI standard register extensions */ +#define SDHCI_CLOCK_PLL_EN 0x0008 +#define SDHCI_TUNING_COUNT 0x20 +#define SDHCI_VENDOR_PTR_R 0xE8 + +/* Synopsys vendor specific registers */ +#define SDHC_EMMC_CTRL_R_OFFSET 0x2C +#define MBIU_CTRL 0x510 + +/* MBIU burst control bits */ +#define BURST_INCR16_EN BIT(3) +#define BURST_INCR8_EN BIT(2) +#define BURST_INCR4_EN BIT(1) +#define BURST_EN (BURST_INCR16_EN | BURST_INCR8_EN | BURST_INCR4_EN) +#define MBIU_BURST_MASK GENMASK(3, 0) + +/* CRM (Clock/Reset/Management) register offsets */ +#define SDEMMC_CRM_BCLK_DIV_CTRL 0x08 +#define SDEMMC_CRM_TIMER_DIV_CTRL 0x0C +#define SDEMMC_CRM_RX_CLK_CTRL 0x14 +#define SDEMMC_CRM_VOL_CTRL 0x1C +#define REG_WR_PROTECT 0x88 +#define DELAY_CHAIN_SEL 0x94 + +/* CRM register values and bit definitions */ +#define REG_WR_PROTECT_KEY 0x1234abcd +#define BST_VOL_STABLE_ON BIT(7) +#define BST_TIMER_DIV_MASK GENMASK(7, 0) +#define BST_TIMER_DIV_VAL 0x20 +#define BST_TIMER_LOAD_BIT BIT(8) +#define BST_BCLK_EN_BIT BIT(10) +#define BST_RX_UPDATE_BIT BIT(11) +#define BST_EMMC_CTRL_BIT2 BIT(2) + +/* Clock frequency limits */ +#define BST_DEFAULT_MAX_FREQ 2000000UL +#define BST_DEFAULT_MIN_FREQ 400000UL + +/* Clock control bit definitions */ +#define BST_CLOCK_DIV_MASK GENMASK(7, 0) +#define BST_CLOCK_DIV_SHIFT 8 +#define BST_BCLK_DIV_MASK GENMASK(9, 0) + +/* Clock frequency thresholds */ +#define BST_CLOCK_THRESHOLD_LOW 1500 + +/* Clock stability polling parameters */ +#define BST_CLK_STABLE_POLL_US 1000 /* Poll interval in microseconds */ +#define BST_CLK_STABLE_TIMEOUT_US 20000 /* Timeout for internal clock stab= ilization (us) */ + +struct sdhci_bst_priv { + void __iomem *crm_reg_base; +}; + +union sdhci_bst_rx_ctrl { + struct { + u32 rx_revert:1, + rx_clk_sel_sec:1, + rx_clk_div:4, + rx_clk_phase_inner:2, + rx_clk_sel_first:1, + rx_clk_phase_out:2, + rx_clk_en:1, + res0:20; + }; + u32 reg; +}; + +static u32 sdhci_bst_crm_read(struct sdhci_pltfm_host *pltfm_host, u32 off= set) +{ + struct sdhci_bst_priv *priv =3D sdhci_pltfm_priv(pltfm_host); + + return readl(priv->crm_reg_base + offset); +} + +static void sdhci_bst_crm_write(struct sdhci_pltfm_host *pltfm_host, u32 o= ffset, u32 value) +{ + struct sdhci_bst_priv *priv =3D sdhci_pltfm_priv(pltfm_host); + + writel(value, priv->crm_reg_base + offset); +} + +static int sdhci_bst_wait_int_clk(struct sdhci_host *host) +{ + u16 clk; + + if (read_poll_timeout(sdhci_readw, clk, (clk & SDHCI_CLOCK_INT_STABLE), + BST_CLK_STABLE_POLL_US, BST_CLK_STABLE_TIMEOUT_US, false, + host, SDHCI_CLOCK_CONTROL)) + return -EBUSY; + return 0; +} + +static unsigned int sdhci_bst_get_max_clock(struct sdhci_host *host) +{ + return BST_DEFAULT_MAX_FREQ; +} + +static unsigned int sdhci_bst_get_min_clock(struct sdhci_host *host) +{ + return BST_DEFAULT_MIN_FREQ; +} + +static void sdhci_bst_enable_clk(struct sdhci_host *host, unsigned int clk) +{ + struct sdhci_pltfm_host *pltfm_host; + unsigned int div; + u32 val; + union sdhci_bst_rx_ctrl rx_reg; + + pltfm_host =3D sdhci_priv(host); + if (clk =3D=3D 0) { + div =3D clk; + } else if (clk > BST_DEFAULT_MAX_FREQ) { + div =3D clk / 1000; + div =3D BST_DEFAULT_MAX_FREQ / div; + } else if (clk < BST_CLOCK_THRESHOLD_LOW) { + div =3D clk; + } else { + div =3D BST_DEFAULT_MAX_FREQ * 100; + div =3D div / clk; + div /=3D 100; + } + + clk =3D sdhci_readw(host, SDHCI_CLOCK_CONTROL); + clk &=3D ~SDHCI_CLOCK_CARD_EN; + sdhci_writew(host, clk, SDHCI_CLOCK_CONTROL); + + clk &=3D ~SDHCI_CLOCK_PLL_EN; + sdhci_writew(host, clk, SDHCI_CLOCK_CONTROL); + + val =3D sdhci_bst_crm_read(pltfm_host, SDEMMC_CRM_TIMER_DIV_CTRL); + val &=3D ~BST_TIMER_LOAD_BIT; + sdhci_bst_crm_write(pltfm_host, SDEMMC_CRM_TIMER_DIV_CTRL, val); + + val =3D sdhci_bst_crm_read(pltfm_host, SDEMMC_CRM_TIMER_DIV_CTRL); + val &=3D ~BST_TIMER_DIV_MASK; + val |=3D BST_TIMER_DIV_VAL; + sdhci_bst_crm_write(pltfm_host, SDEMMC_CRM_TIMER_DIV_CTRL, val); + + val =3D sdhci_bst_crm_read(pltfm_host, SDEMMC_CRM_TIMER_DIV_CTRL); + val |=3D BST_TIMER_LOAD_BIT; + sdhci_bst_crm_write(pltfm_host, SDEMMC_CRM_TIMER_DIV_CTRL, val); + + val =3D sdhci_bst_crm_read(pltfm_host, SDEMMC_CRM_RX_CLK_CTRL); + val &=3D ~BST_RX_UPDATE_BIT; + sdhci_bst_crm_write(pltfm_host, SDEMMC_CRM_RX_CLK_CTRL, val); + + rx_reg.reg =3D sdhci_bst_crm_read(pltfm_host, SDEMMC_CRM_RX_CLK_CTRL); + + rx_reg.rx_revert =3D 0; + rx_reg.rx_clk_sel_sec =3D 1; + rx_reg.rx_clk_div =3D 4; + rx_reg.rx_clk_phase_inner =3D 2; + rx_reg.rx_clk_sel_first =3D 0; + rx_reg.rx_clk_phase_out =3D 2; + + sdhci_bst_crm_write(pltfm_host, SDEMMC_CRM_RX_CLK_CTRL, rx_reg.reg); + + val =3D sdhci_bst_crm_read(pltfm_host, SDEMMC_CRM_RX_CLK_CTRL); + val |=3D BST_RX_UPDATE_BIT; + sdhci_bst_crm_write(pltfm_host, SDEMMC_CRM_RX_CLK_CTRL, val); + + /* Disable clock first */ + val =3D sdhci_bst_crm_read(pltfm_host, SDEMMC_CRM_BCLK_DIV_CTRL); + val &=3D ~BST_BCLK_EN_BIT; + sdhci_bst_crm_write(pltfm_host, SDEMMC_CRM_BCLK_DIV_CTRL, val); + + /* Setup clock divider */ + val =3D sdhci_bst_crm_read(pltfm_host, SDEMMC_CRM_BCLK_DIV_CTRL); + val &=3D ~BST_BCLK_DIV_MASK; + val |=3D div; + sdhci_bst_crm_write(pltfm_host, SDEMMC_CRM_BCLK_DIV_CTRL, val); + + /* Enable clock */ + val =3D sdhci_bst_crm_read(pltfm_host, SDEMMC_CRM_BCLK_DIV_CTRL); + val |=3D BST_BCLK_EN_BIT; + sdhci_bst_crm_write(pltfm_host, SDEMMC_CRM_BCLK_DIV_CTRL, val); + + /* RMW the clock divider bits to avoid clobbering other fields */ + clk =3D sdhci_readw(host, SDHCI_CLOCK_CONTROL); + clk &=3D ~(BST_CLOCK_DIV_MASK << BST_CLOCK_DIV_SHIFT); + clk |=3D (div & BST_CLOCK_DIV_MASK) << BST_CLOCK_DIV_SHIFT; + sdhci_writew(host, clk, SDHCI_CLOCK_CONTROL); + + clk =3D sdhci_readw(host, SDHCI_CLOCK_CONTROL); + clk |=3D SDHCI_CLOCK_PLL_EN; + sdhci_writew(host, clk, SDHCI_CLOCK_CONTROL); + + clk |=3D SDHCI_CLOCK_CARD_EN; + sdhci_writew(host, clk, SDHCI_CLOCK_CONTROL); + + clk |=3D SDHCI_CLOCK_INT_EN; + sdhci_writew(host, clk, SDHCI_CLOCK_CONTROL); +} + +static void sdhci_bst_set_clock(struct sdhci_host *host, unsigned int cloc= k) +{ + /* Turn off card/internal/PLL clocks when clock=3D=3D0 to avoid idle powe= r */ + u32 clk_reg =3D sdhci_readw(host, SDHCI_CLOCK_CONTROL); + + if (!clock) { + clk_reg &=3D ~(SDHCI_CLOCK_CARD_EN | SDHCI_CLOCK_INT_EN | SDHCI_CLOCK_PL= L_EN); + sdhci_writew(host, clk_reg, SDHCI_CLOCK_CONTROL); + return; + } + sdhci_bst_enable_clk(host, clock); +} + +/** + * sdhci_bst_reset - Reset the SDHCI host controller + * @host: SDHCI host controller + * @mask: Reset mask + * + * Performs a reset of the SDHCI host controller with special handling for= eMMC. + */ +static void sdhci_bst_reset(struct sdhci_host *host, u8 mask) +{ + u16 vendor_ptr, emmc_ctrl_reg; + u32 reg; + + if (host->mmc->caps2 & MMC_CAP2_NO_SD) { + vendor_ptr =3D sdhci_readw(host, SDHCI_VENDOR_PTR_R); + emmc_ctrl_reg =3D vendor_ptr + SDHC_EMMC_CTRL_R_OFFSET; + + reg =3D sdhci_readw(host, emmc_ctrl_reg); + reg &=3D ~BST_EMMC_CTRL_BIT2; + sdhci_writew(host, reg, emmc_ctrl_reg); + sdhci_reset(host, mask); + usleep_range(10, 20); + reg =3D sdhci_readw(host, emmc_ctrl_reg); + reg |=3D BST_EMMC_CTRL_BIT2; + sdhci_writew(host, reg, emmc_ctrl_reg); + } else { + sdhci_reset(host, mask); + } +} + +/** + * sdhci_bst_set_timeout - Set timeout value for commands + * @host: SDHCI host controller + * @cmd: MMC command + * + * Sets the timeout control register to maximum value (0xE). + */ +static void sdhci_bst_set_timeout(struct sdhci_host *host, struct mmc_comm= and *cmd) +{ + sdhci_writeb(host, 0xE, SDHCI_TIMEOUT_CONTROL); +} + +/** + * sdhci_bst_set_power - Set power mode and voltage + * @host: SDHCI host controller + * @mode: Power mode to set + * @vdd: Voltage to set + * + * Sets power mode and voltage, also configures MBIU control register. + */ +static void sdhci_bst_set_power(struct sdhci_host *host, unsigned char mod= e, + unsigned short vdd) +{ + struct sdhci_pltfm_host *pltfm_host =3D sdhci_priv(host); + u32 reg; + u32 val; + + sdhci_set_power(host, mode, vdd); + + if (mode =3D=3D MMC_POWER_OFF) { + /* Disable MBIU burst mode */ + reg =3D sdhci_readw(host, MBIU_CTRL); + reg &=3D ~BURST_EN; /* Clear all burst enable bits */ + sdhci_writew(host, reg, MBIU_CTRL); + + /* Disable CRM BCLK */ + val =3D sdhci_bst_crm_read(pltfm_host, SDEMMC_CRM_BCLK_DIV_CTRL); + val &=3D ~BST_BCLK_EN_BIT; + sdhci_bst_crm_write(pltfm_host, SDEMMC_CRM_BCLK_DIV_CTRL, val); + + /* Disable RX clock */ + val =3D sdhci_bst_crm_read(pltfm_host, SDEMMC_CRM_RX_CLK_CTRL); + val &=3D ~BST_RX_UPDATE_BIT; + sdhci_bst_crm_write(pltfm_host, SDEMMC_CRM_RX_CLK_CTRL, val); + + /* Turn off voltage stable power */ + val =3D sdhci_bst_crm_read(pltfm_host, SDEMMC_CRM_VOL_CTRL); + val &=3D ~BST_VOL_STABLE_ON; + sdhci_bst_crm_write(pltfm_host, SDEMMC_CRM_VOL_CTRL, val); + } else { + /* Configure burst mode only when powered on */ + reg =3D sdhci_readw(host, MBIU_CTRL); + reg &=3D ~MBIU_BURST_MASK; /* Clear burst related bits */ + reg |=3D BURST_EN; /* Enable burst mode for better bandwidth */ + sdhci_writew(host, reg, MBIU_CTRL); + } +} + +/** + * sdhci_bst_execute_tuning - Execute tuning procedure + * @host: SDHCI host controller + * @opcode: Opcode to use for tuning + * + * Performs tuning procedure by trying different values and selecting the = best one. + * + * Return: 0 on success, negative errno on failure + */ +static int sdhci_bst_execute_tuning(struct sdhci_host *host, u32 opcode) +{ + struct sdhci_pltfm_host *pltfm_host; + int ret =3D 0, error; + int first_start =3D -1, first_end =3D -1, best =3D 0; + int second_start =3D -1, second_end =3D -1, has_failure =3D 0; + int i; + + pltfm_host =3D sdhci_priv(host); + + for (i =3D 0; i < SDHCI_TUNING_COUNT; i++) { + /* Protected write */ + sdhci_bst_crm_write(pltfm_host, REG_WR_PROTECT, REG_WR_PROTECT_KEY); + /* Write tuning value */ + sdhci_bst_crm_write(pltfm_host, DELAY_CHAIN_SEL, (1ul << i) - 1); + + /* Wait for internal clock stable before tuning */ + if (sdhci_bst_wait_int_clk(host)) { + dev_err(mmc_dev(host->mmc), "Internal clock never stabilised\n"); + return -EBUSY; + } + + ret =3D mmc_send_tuning(host->mmc, opcode, &error); + if (ret !=3D 0) { + has_failure =3D 1; + } else { + if (has_failure =3D=3D 0) { + if (first_start =3D=3D -1) + first_start =3D i; + first_end =3D i; + } else { + if (second_start =3D=3D -1) + second_start =3D i; + second_end =3D i; + } + } + } + + /* Calculate best tuning value */ + if (first_end - first_start >=3D second_end - second_start) + best =3D ((first_end - first_start) >> 1) + first_start; + else + best =3D ((second_end - second_start) >> 1) + second_start; + + if (best < 0) + best =3D 0; + + sdhci_bst_crm_write(pltfm_host, DELAY_CHAIN_SEL, (1ul << best) - 1); + /* Confirm internal clock stable after setting best tuning value */ + if (sdhci_bst_wait_int_clk(host)) { + dev_err(mmc_dev(host->mmc), "Internal clock never stabilised\n"); + return -EBUSY; + } + + return 0; +} + +/** + * sdhci_bst_voltage_switch - Perform voltage switch + * @host: SDHCI host controller + * + * Enables voltage stable power. + */ +static void sdhci_bst_voltage_switch(struct sdhci_host *host) +{ + struct sdhci_pltfm_host *pltfm_host =3D sdhci_priv(host); + + /* Enable voltage stable power */ + sdhci_bst_crm_write(pltfm_host, SDEMMC_CRM_VOL_CTRL, BST_VOL_STABLE_ON); +} + +static const struct sdhci_ops sdhci_bst_ops =3D { + .set_clock =3D sdhci_bst_set_clock, + .set_bus_width =3D sdhci_set_bus_width, + .set_uhs_signaling =3D sdhci_set_uhs_signaling, + .get_min_clock =3D sdhci_bst_get_min_clock, + .get_max_clock =3D sdhci_bst_get_max_clock, + .reset =3D sdhci_bst_reset, + .set_power =3D sdhci_bst_set_power, + .set_timeout =3D sdhci_bst_set_timeout, + .platform_execute_tuning =3D sdhci_bst_execute_tuning, + .voltage_switch =3D sdhci_bst_voltage_switch, +}; + +static const struct sdhci_pltfm_data sdhci_bst_pdata =3D { + .ops =3D &sdhci_bst_ops, + .quirks =3D SDHCI_QUIRK_BROKEN_ADMA | + SDHCI_QUIRK_DELAY_AFTER_POWER | + SDHCI_QUIRK_CAP_CLOCK_BASE_BROKEN | + SDHCI_QUIRK_INVERTED_WRITE_PROTECT, + .quirks2 =3D SDHCI_QUIRK2_BROKEN_DDR50 | + SDHCI_QUIRK2_TUNING_WORK_AROUND | + SDHCI_QUIRK2_ACMD23_BROKEN, +}; + +static int sdhci_bst_alloc_bounce_buffer(struct sdhci_host *host) +{ + struct mmc_host *mmc =3D host->mmc; + unsigned int bounce_size; + int ret; + + /* Fixed SRAM bounce size to 32KB: verified config under 32-bit DMA addre= ssing limit */ + bounce_size =3D SZ_32K; + + ret =3D of_reserved_mem_device_init_by_idx(mmc_dev(mmc), mmc_dev(mmc)->of= _node, 0); + if (ret) { + dev_err(mmc_dev(mmc), "Failed to initialize reserved memory\n"); + return ret; + } + + host->bounce_buffer =3D dma_alloc_coherent(mmc_dev(mmc), bounce_size, + &host->bounce_addr, GFP_KERNEL); + if (!host->bounce_buffer) + return -ENOMEM; + + host->bounce_buffer_size =3D bounce_size; + + return 0; +} + +static int sdhci_bst_probe(struct platform_device *pdev) +{ + struct sdhci_pltfm_host *pltfm_host; + struct sdhci_host *host; + struct sdhci_bst_priv *priv; + int err; + + host =3D sdhci_pltfm_init(pdev, &sdhci_bst_pdata, sizeof(struct sdhci_bst= _priv)); + if (IS_ERR(host)) + return PTR_ERR(host); + + pltfm_host =3D sdhci_priv(host); + priv =3D sdhci_pltfm_priv(pltfm_host); /* Get platform private data */ + + err =3D mmc_of_parse(host->mmc); + if (err) + return err; + + sdhci_get_of_property(pdev); + + /* Get CRM registers from the second reg entry */ + priv->crm_reg_base =3D devm_platform_ioremap_resource(pdev, 1); + if (IS_ERR(priv->crm_reg_base)) { + err =3D PTR_ERR(priv->crm_reg_base); + return err; + } + + /* + * Silicon constraints for BST C1200: + * - System RAM base is 0x800000000 (above 32-bit addressable range) + * - The eMMC controller DMA engine is limited to 32-bit addressing + * - SMMU cannot be used on this path due to hardware design flaws + * - These are fixed in silicon and cannot be changed in software + * + * Bus/controller mapping: + * - No registers are available to reprogram the address mapping + * - The 32-bit DMA limit is a hard constraint of the controller IP + * + * Given these constraints, an SRAM-based bounce buffer in the 32-bit + * address space is required to enable eMMC DMA on this platform. + */ + err =3D sdhci_bst_alloc_bounce_buffer(host); + if (err) { + dev_err(&pdev->dev, "Failed to allocate bounce buffer: %d\n", err); + return err; + } + + err =3D sdhci_add_host(host); + if (err) + goto err_free_bounce_buffer; + + return 0; + +err_free_bounce_buffer: + if (host->bounce_buffer) { + dma_free_coherent(mmc_dev(host->mmc), host->bounce_buffer_size, + host->bounce_buffer, host->bounce_addr); + host->bounce_buffer =3D NULL; + } + of_reserved_mem_device_release(mmc_dev(host->mmc)); + + return err; +} + +static void sdhci_bst_remove(struct platform_device *pdev) +{ + struct sdhci_host *host =3D platform_get_drvdata(pdev); + + /* Free bounce buffer if allocated */ + if (host->bounce_buffer) { + dma_free_coherent(mmc_dev(host->mmc), host->bounce_buffer_size, + host->bounce_buffer, host->bounce_addr); + host->bounce_buffer =3D NULL; + } + + /* Release reserved memory */ + of_reserved_mem_device_release(mmc_dev(host->mmc)); + + /* Use platform helper for remove */ + sdhci_pltfm_remove(pdev); +} + +static const struct of_device_id sdhci_bst_ids[] =3D { + { .compatible =3D "bst,c1200-dwcmshc-sdhci" }, + {} +}; +MODULE_DEVICE_TABLE(of, sdhci_bst_ids); + +static struct platform_driver sdhci_bst_driver =3D { + .driver =3D { + .name =3D "sdhci-bst", + .of_match_table =3D sdhci_bst_ids, + }, + .probe =3D sdhci_bst_probe, + .remove =3D sdhci_bst_remove, +}; +module_platform_driver(sdhci_bst_driver); + +MODULE_DESCRIPTION("Black Sesame Technologies SDHCI driver (BST)"); +MODULE_AUTHOR("Black Sesame Technologies Co., Ltd."); +MODULE_LICENSE("GPL"); --=20 2.43.0 From nobody Thu Oct 2 03:30:35 2025 Received: from mail-m32118.qiye.163.com (mail-m32118.qiye.163.com [220.197.32.118]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id B7B8C30DD24; Tue, 23 Sep 2025 06:46:05 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=none smtp.client-ip=220.197.32.118 ARC-Seal: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1758609968; cv=none; b=Pzku2L/UuhcSmaG4sKqFpjMF8AKVZahJCybeYytsZDhKjxBoMnh6aQtrbWR2qazKzpPyCb4Fu8g8HN1WdkK2nY8mVCMZ6Dt1qGMAW2Sy7kjzJWM0/UxnhAPp9NmkfuJjIbSOmkxlCuCmEU0e4pJ1bhucB9ErtC9bkLtV4fnEBTo= ARC-Message-Signature: i=1; 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Tue, 23 Sep 2025 14:10:36 +0800 (GMT+08:00) From: Albert Yang Date: Tue, 23 Sep 2025 14:10:12 +0800 Subject: [PATCH 6/9] mmc: sdhci: allow drivers to pre-allocate bounce buffer Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Content-Transfer-Encoding: quoted-printable Message-Id: <20250923-v4-patch-final-v1-6-2283ad7cbf88@thundersoft.com> References: <20250923-v4-patch-final-v1-0-2283ad7cbf88@thundersoft.com> In-Reply-To: <20250923-v4-patch-final-v1-0-2283ad7cbf88@thundersoft.com> To: Rob Herring , Krzysztof Kozlowski , Conor Dooley , Ge Gordon , BST Linux Kernel Upstream Group , Catalin Marinas , Will Deacon , Ulf Hansson , Adrian Hunter , Arnd Bergmann Cc: devicetree@vger.kernel.org, linux-kernel@vger.kernel.org, linux-arm-kernel@lists.infradead.org, linux-mmc@vger.kernel.org, soc@lists.linux.dev, Albert Yang X-Mailer: b4 0.14.2 X-Developer-Signature: v=1; a=ed25519-sha256; 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In sdhci_allocate_bounce_buffer(), add an early path that respects a driver-provided pre-allocated bounce buffer (host->bounce_buffer). If the buffer is already allocated by the driver (e.g. coherent/SRAM buffer needed for platforms with 32-bit DMA constraints), just compute max_blocks from host->bounce_buffer_size and jump to the common "out" path to set mmc->max_*. This enables platform drivers to allocate the bounce buffer before sdhci_add_host(), avoiding starting the host without the buffer ready and aligning with the guidance from review. No functional change for drivers that do not pre-allocate the buffer. drivers/mmc/host/sdhci.c (sdhci_allocate_bounce_buffer): Handle pre-allocated bounce buffer and fall through to set mmc->max_*. Suggested-by: Adrian Hunter Link: https://lore.kernel.org/lkml/2b23bcb9-abc7-4667-b939-a19ecae935a2@int= el.com/ Signed-off-by: Albert Yang Acked-by: Adrian Hunter --- Changes for v4: - Add new patch by Suggested-by: Adrian Hunter --- drivers/mmc/host/sdhci.c | 7 +++++++ 1 file changed, 7 insertions(+) diff --git a/drivers/mmc/host/sdhci.c b/drivers/mmc/host/sdhci.c index 3a17821efa5ca92c6c29141d8fcb9ebf58355cc7..03fbe30cb205e16b924481caa44= f0979d230f380 100644 --- a/drivers/mmc/host/sdhci.c +++ b/drivers/mmc/host/sdhci.c @@ -4193,6 +4193,12 @@ static void sdhci_allocate_bounce_buffer(struct sdhc= i_host *host) unsigned int bounce_size; int ret; =20 + /* Drivers may have already allocated the buffer */ + if (host->bounce_buffer) { + bounce_size =3D host->bounce_buffer_size; + max_blocks =3D bounce_size / 512; + goto out; + } /* * Cap the bounce buffer at 64KB. Using a bigger bounce buffer * has diminishing returns, this is probably because SD/MMC @@ -4241,6 +4247,7 @@ static void sdhci_allocate_bounce_buffer(struct sdhci= _host *host) =20 host->bounce_buffer_size =3D bounce_size; =20 +out: /* Lie about this since we're bouncing */ mmc->max_segs =3D max_blocks; mmc->max_seg_size =3D bounce_size; --=20 2.43.0 From nobody Thu Oct 2 03:30:35 2025 Received: from mail-m3290.qiye.163.com (mail-m3290.qiye.163.com [220.197.32.90]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id 506AB1990A7; Tue, 23 Sep 2025 06:10:46 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=none smtp.client-ip=220.197.32.90 ARC-Seal: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1758607850; cv=none; b=E5MJPJpyt7wuvoFHgLjZWvfRKlaTqd5gHZcAneuItqWj40ZQE8lgJv0BUxib/PYwxZMylpdun7i7cfC7+BDqfqmOln4b1gYmg8iGDU1oDa4aXV1WLfgMPrL2pgCSPucMieTR2NTj1hkODTPNIgMoHVf4dfwVO9DkH+VbMebNYFo= ARC-Message-Signature: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1758607850; c=relaxed/simple; bh=6Om2WbeIVDWsvp3M13b/4u8GU7cNdXlbfg/+WQNQPgc=; h=From:Date:Subject:MIME-Version:Content-Type:Message-Id:References: In-Reply-To:To:Cc; b=Lv1ZHNSdmaI9IH+wSriYMKe/DkOlMSuUu8tqMRPn2IPRj7RUqzpwdHma09WL7fXPXXpTCorGvlOKAwgxa5XO4dITvNjVQex5mIgpgr89WlEZTAv23Yxg5sAiBBJ6nSc1NZrAJcgQUpd7S4XK0UpuCizWL+uVrzZWBaorFgep4pE= ARC-Authentication-Results: i=1; smtp.subspace.kernel.org; dmarc=pass (p=none dis=none) header.from=thundersoft.com; spf=pass smtp.mailfrom=thundersoft.com; dkim=pass (1024-bit key) header.d=thundersoft.com header.i=@thundersoft.com header.b=PxBbLtuq; arc=none smtp.client-ip=220.197.32.90 Authentication-Results: smtp.subspace.kernel.org; dmarc=pass (p=none dis=none) header.from=thundersoft.com Authentication-Results: smtp.subspace.kernel.org; spf=pass smtp.mailfrom=thundersoft.com Authentication-Results: smtp.subspace.kernel.org; dkim=pass (1024-bit key) header.d=thundersoft.com header.i=@thundersoft.com header.b="PxBbLtuq" Received: from [127.0.1.1] (unknown [117.184.129.134]) by smtp.qiye.163.com (Hmail) with ESMTP id 23bdec001; Tue, 23 Sep 2025 14:10:37 +0800 (GMT+08:00) From: Albert Yang Date: Tue, 23 Sep 2025 14:10:13 +0800 Subject: [PATCH 7/9] arm64: dts: bst: add support for Black Sesame Technologies C1200 CDCU1.0 board Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Content-Transfer-Encoding: quoted-printable Message-Id: <20250923-v4-patch-final-v1-7-2283ad7cbf88@thundersoft.com> References: <20250923-v4-patch-final-v1-0-2283ad7cbf88@thundersoft.com> In-Reply-To: <20250923-v4-patch-final-v1-0-2283ad7cbf88@thundersoft.com> To: Rob Herring , Krzysztof Kozlowski , Conor Dooley , Ge Gordon , BST Linux Kernel Upstream Group , Catalin Marinas , Will Deacon , Ulf Hansson , Adrian Hunter , Arnd Bergmann Cc: devicetree@vger.kernel.org, linux-kernel@vger.kernel.org, linux-arm-kernel@lists.infradead.org, linux-mmc@vger.kernel.org, soc@lists.linux.dev, Albert Yang X-Mailer: b4 0.14.2 X-Developer-Signature: v=1; a=ed25519-sha256; t=1758607828; l=7150; i=yangzh0906@thundersoft.com; s=20250814; h=from:subject:message-id; bh=6Om2WbeIVDWsvp3M13b/4u8GU7cNdXlbfg/+WQNQPgc=; b=8T7fIxj2geu2rwMom6GwylX9JLZEEmL1CziNr5UJRypzXX/ic+FXHrtwhuLcv0Q1j0qZv47Hm vcgzwed+H07A7LOuuMNXObeDOnAAPsxS3EJkJTGgmBxD+7dMDXm0p6S X-Developer-Key: i=yangzh0906@thundersoft.com; a=ed25519; pk=bEcgALL9KpUg/m7zH44r50xa/re91dI9SA0vGV1/bu4= X-HM-Tid: 0a9975320ab509cckunmfc27e25b4e0345 X-HM-MType: 1 X-HM-Spam-Status: e1kfGhgUHx5ZQUpXWQgPGg8OCBgUHx5ZQUlOS1dZFg8aDwILHllBWSg2Ly tZV1koWUFITzdXWS1ZQUlXWQ8JGhUIEh9ZQVlCH00dVkMfGElMSh1NQx1OGlYVFAkWGhdVEwETFh oSFyQUDg9ZV1kYEgtZQVlKSkxVSkNPVUpJQlVKSE9ZV1kWGg8SFR0UWUFZT0tIVUpLSU9PT0hVSk tLVUpCS0tZBg++ DKIM-Signature: a=rsa-sha256; b=PxBbLtuqRJBw1EWduNdiVCU44E7LHoAlnUToASDVhd8K6Kienw66ZmKjrnNy5oB64PcCiIfi4Ietq3niO1rIZzVrLmSxRPrjiZCobyGdNctSPVwtITdx9NJV3j9/1xJSkAwG2E7GNsRKTTJ3X/283yMqmdGKoLPYq2I7Ks+BnPI=; c=relaxed/relaxed; s=default; d=thundersoft.com; v=1; bh=D/wIjlORwMfAe2A8lh3D4l0PcZesLECFnhFcbmUELsc=; h=date:mime-version:subject:message-id:from; Add device tree support for the Black Sesame Technologies (BST) C1200 CDCU1.0 ADAS 4C2G platform. This platform is based on the BST C1200 SoC family. The changes include: - Adding a new BST device tree directory - Adding Makefile entries to build the BST platform device trees - Adding the device tree for the BST C1200 CDCU1.0 ADAS 4C2G board This board features a quad-core Cortex-A78 CPU, and various peripherals including UART, MMC, watchdog timer, and interrupt controller. Signed-off-by: Albert Yang --- Changes for v4: - Remove Signed-off-by line for Ge Gordon - Reorder device tree node properties for better consistency - CPU nodes: move `device_type` before `compatible`, add explicit `reg` val= ues - MMC node: change compatible from `bst,c1200-dwcmshc-sdhci` to `bst,c1200-= sdhci` - MMC node: remove `bus-width` and `non-removable` from SoC dtsi, move to b= oard dts - SoC node: reorder properties (`ranges` before address/size cells) - UART node: reorder properties (clock-frequency before interrupts) - GIC node: reorder properties for better readability - Timer node: reorder properties (always-on before interrupt-parent) - Board DTS: add `bus-width =3D <8>` and `non-removable` to MMC node - Board DTS: reorder MMC and UART node references Changes for v3: - Split defconfig enablement out into a dedicated defconfig patch - Refine memory description: consolidate ranges in memory node and delete u= nused memory ranges - Adjust the order of nodes - Remove mask of gic Changes for v2: - Reorganize memory map into discrete regions - Update MMC controller definition with split core/CRM register regions - Remove deprecated properties - Update compatible string - Standardize interrupt definitions and numeric formats - Remove reserved-memory node (superseded by bounce buffers) - Add root compatible string for platform identification - Add soc defconfig --- arch/arm64/boot/dts/Makefile | 1 + arch/arm64/boot/dts/bst/Makefile | 2 + .../boot/dts/bst/bstc1200-cdcu1.0-adas_4c2g.dts | 43 ++++++++ arch/arm64/boot/dts/bst/bstc1200.dtsi | 115 +++++++++++++++++= ++++ 4 files changed, 161 insertions(+) diff --git a/arch/arm64/boot/dts/Makefile b/arch/arm64/boot/dts/Makefile index b0844404eda1835d7f3112a1250dde74ac251c50..98ec8f1b76e4753257e8678c6db= 918053e9c528d 100644 --- a/arch/arm64/boot/dts/Makefile +++ b/arch/arm64/boot/dts/Makefile @@ -13,6 +13,7 @@ subdir-y +=3D axiado subdir-y +=3D bitmain subdir-y +=3D blaize subdir-y +=3D broadcom +subdir-y +=3D bst subdir-y +=3D cavium subdir-y +=3D cix subdir-y +=3D exynos diff --git a/arch/arm64/boot/dts/bst/Makefile b/arch/arm64/boot/dts/bst/Mak= efile new file mode 100644 index 0000000000000000000000000000000000000000..4c1b8b4cdad893df0cc47d81a64= d9cbc7a60a9dd --- /dev/null +++ b/arch/arm64/boot/dts/bst/Makefile @@ -0,0 +1,2 @@ +# SPDX-License-Identifier: GPL-2.0 +dtb-$(CONFIG_ARCH_BST) +=3D bstc1200-cdcu1.0-adas_4c2g.dtb diff --git a/arch/arm64/boot/dts/bst/bstc1200-cdcu1.0-adas_4c2g.dts b/arch/= arm64/boot/dts/bst/bstc1200-cdcu1.0-adas_4c2g.dts new file mode 100644 index 0000000000000000000000000000000000000000..178ad4bf4f0aacf831a61af07ad= 151a70e075749 --- /dev/null +++ b/arch/arm64/boot/dts/bst/bstc1200-cdcu1.0-adas_4c2g.dts @@ -0,0 +1,43 @@ +// SPDX-License-Identifier: GPL-2.0 +/dts-v1/; + +#include "bstc1200.dtsi" + +/ { + model =3D "BST C1200-96 CDCU1.0 4C2G"; + compatible =3D "bst,c1200-cdcu1.0-adas-4c2g", "bst,c1200"; + + chosen { + stdout-path =3D "serial0:115200n8"; + }; + + memory@810000000 { + device_type =3D "memory"; + reg =3D <0x8 0x10000000 0x0 0x30000000>, + <0x8 0xc0000000 0x1 0x0>, + <0xc 0x00000000 0x0 0x40000000>; + }; + + reserved-memory { + #address-cells =3D <2>; + #size-cells =3D <2>; + ranges; + + mmc0_reserved: mmc0-reserved@5160000 { + compatible =3D "shared-dma-pool"; + reg =3D <0x0 0x5160000 0x0 0x10000>; + no-map; + }; + }; +}; + +&mmc0 { + bus-width =3D <8>; + memory-region =3D <&mmc0_reserved>; + non-removable; + status =3D "okay"; +}; + +&uart0 { + status =3D "okay"; +}; diff --git a/arch/arm64/boot/dts/bst/bstc1200.dtsi b/arch/arm64/boot/dts/bs= t/bstc1200.dtsi new file mode 100644 index 0000000000000000000000000000000000000000..9660d8396e275945b27846c80dd= e79478c16ae76 --- /dev/null +++ b/arch/arm64/boot/dts/bst/bstc1200.dtsi @@ -0,0 +1,115 @@ +// SPDX-License-Identifier: GPL-2.0 +#include +#include + +/ { + compatible =3D "bst,c1200"; + #address-cells =3D <2>; + #size-cells =3D <2>; + + clk_mmc: clock-4000000 { + compatible =3D "fixed-clock"; + #clock-cells =3D <0>; + clock-frequency =3D <4000000>; + }; + + cpus { + #address-cells =3D <1>; + #size-cells =3D <0>; + + cpu@0 { + device_type =3D "cpu"; + compatible =3D "arm,cortex-a78"; + reg =3D <0x0>; + enable-method =3D "psci"; + next-level-cache =3D <&l2_cache>; + }; + + cpu@1 { + device_type =3D "cpu"; + compatible =3D "arm,cortex-a78"; + reg =3D <0x100>; + enable-method =3D "psci"; + next-level-cache =3D <&l2_cache>; + }; + + cpu@2 { + device_type =3D "cpu"; + compatible =3D "arm,cortex-a78"; + reg =3D <0x200>; + enable-method =3D "psci"; + next-level-cache =3D <&l2_cache>; + }; + + cpu@3 { + device_type =3D "cpu"; + compatible =3D "arm,cortex-a78"; + reg =3D <0x300>; + enable-method =3D "psci"; + next-level-cache =3D <&l2_cache>; + }; + + l2_cache: l2-cache { + compatible =3D "cache"; + cache-level =3D <2>; + cache-unified; + }; + }; + + psci { + compatible =3D "arm,psci-1.0"; + method =3D "smc"; + }; + + soc { + compatible =3D "simple-bus"; + ranges; + #address-cells =3D <2>; + #size-cells =3D <2>; + interrupt-parent =3D <&gic>; + + uart0: serial@20008000 { + compatible =3D "snps,dw-apb-uart"; + reg =3D <0x0 0x20008000 0x0 0x1000>; + clock-frequency =3D <25000000>; + interrupts =3D ; + reg-shift =3D <2>; + reg-io-width =3D <4>; + status =3D "disabled"; + }; + + mmc0: mmc@22200000 { + compatible =3D "bst,c1200-sdhci"; + reg =3D <0x0 0x22200000 0x0 0x1000>, + <0x0 0x23006000 0x0 0x1000>; + clocks =3D <&clk_mmc>; + clock-names =3D "core"; + dma-coherent; + interrupts =3D ; + max-frequency =3D <200000000>; + status =3D "disabled"; + }; + + gic: interrupt-controller@32800000 { + compatible =3D "arm,gic-v3"; + reg =3D <0x0 0x32800000 0x0 0x10000>, + <0x0 0x32880000 0x0 0x100000>; + ranges; + #address-cells =3D <2>; + #size-cells =3D <2>; + #interrupt-cells =3D <3>; + interrupt-controller; + interrupts =3D ; + }; + }; + + timer { + compatible =3D "arm,armv8-timer"; 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charset="utf-8" Content-Transfer-Encoding: quoted-printable Message-Id: <20250923-v4-patch-final-v1-8-2283ad7cbf88@thundersoft.com> References: <20250923-v4-patch-final-v1-0-2283ad7cbf88@thundersoft.com> In-Reply-To: <20250923-v4-patch-final-v1-0-2283ad7cbf88@thundersoft.com> To: Rob Herring , Krzysztof Kozlowski , Conor Dooley , Ge Gordon , BST Linux Kernel Upstream Group , Catalin Marinas , Will Deacon , Ulf Hansson , Adrian Hunter , Arnd Bergmann Cc: devicetree@vger.kernel.org, linux-kernel@vger.kernel.org, linux-arm-kernel@lists.infradead.org, linux-mmc@vger.kernel.org, soc@lists.linux.dev, Albert Yang X-Mailer: b4 0.14.2 X-Developer-Signature: v=1; a=ed25519-sha256; t=1758607828; l=1411; i=yangzh0906@thundersoft.com; s=20250814; h=from:subject:message-id; bh=GESOXygDFTo0+zjPMAAH/mMuZM8ehq9tb72d7ALilWc=; b=jr2tBq82ym4uCgrtKfh0RPngoe233C5kOI8cqHiK6YaQAnkIumkhjn+wfy/dleV1zGyi+yoYK /xcg0HO4FYtDabz8dwLcxjXLek+LaJzW2IgxIQ0gpaVSwWKdE/Y9RUV X-Developer-Key: i=yangzh0906@thundersoft.com; a=ed25519; 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h=date:mime-version:subject:message-id:from; Add a MAINTAINERS entry for Black Sesame Technologies (BST) ARM SoC support. This entry covers device tree bindings, drivers, and board files for BST SoCs, including MMC and platform support. Signed-off-by: Albert Yang --- Change for v4: - Changed file name: sdhci-of-bst-c1200.c to sdhci-of-bst.c - Changed title from "add and consolidate" to just "add" - Simplified commit message description - Removed Signed-off-by line for Ge Gordon Change for v3: - No changes Change for v2: - No changes --- MAINTAINERS | 10 ++++++++++ 1 file changed, 10 insertions(+) diff --git a/MAINTAINERS b/MAINTAINERS index cd7ff55b5d321752ac44c91d2d7e74de28e08960..685294ef3e2ecf124219b2c5eaf= b8cad25600652 100644 --- a/MAINTAINERS +++ b/MAINTAINERS @@ -2505,6 +2505,16 @@ S: Maintained F: Documentation/devicetree/bindings/arm/blaize.yaml F: arch/arm64/boot/dts/blaize/ =20 +ARM/BST SOC SUPPORT +M: Ge Gordon +R: BST Linux Kernel Upstream Group +L: linux-arm-kernel@lists.infradead.org (moderated for non-subscribers) +S: Maintained +F: Documentation/devicetree/bindings/arm/bst.yaml +F: Documentation/devicetree/bindings/mmc/bst,dwcmshc-sdhci.yaml +F: arch/arm64/boot/dts/bst/ +F: drivers/mmc/host/sdhci-of-bst.c + ARM/CALXEDA HIGHBANK ARCHITECTURE M: Andre Przywara L: linux-arm-kernel@lists.infradead.org (moderated for non-subscribers) --=20 2.43.0