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R. Silva" , Ulf Hansson Cc: kernel@collabora.com, dri-devel@lists.freedesktop.org, devicetree@vger.kernel.org, linux-kernel@vger.kernel.org, linux-arm-kernel@lists.infradead.org, linux-mediatek@lists.infradead.org, linux-hardening@vger.kernel.org, linux-pm@vger.kernel.org, Nicolas Frattaroli X-Mailer: b4 0.14.2 The Mali-based GPU on the MediaTek MT8196 SoC uses a separate MCU to control the power and frequency of the GPU. This is modelled as a power domain and clock provider. It lets us omit the OPP tables from the device tree, as those can now be enumerated at runtime from the MCU. Add the necessary schema logic to handle what this SoC expects in terms of clocks and power-domains. Signed-off-by: Nicolas Frattaroli --- .../bindings/gpu/arm,mali-valhall-csf.yaml | 40 ++++++++++++++++++= ++-- 1 file changed, 38 insertions(+), 2 deletions(-) diff --git a/Documentation/devicetree/bindings/gpu/arm,mali-valhall-csf.yam= l b/Documentation/devicetree/bindings/gpu/arm,mali-valhall-csf.yaml index 7ad5a3ffc5f5c753322eda9e74cc65de89d11c73..860691ce985e560536b6c515b82= 441ba6d367c46 100644 --- a/Documentation/devicetree/bindings/gpu/arm,mali-valhall-csf.yaml +++ b/Documentation/devicetree/bindings/gpu/arm,mali-valhall-csf.yaml @@ -45,7 +45,9 @@ properties: minItems: 1 items: - const: core - - const: coregroup + - enum: + - coregroup + - stacks - const: stacks =20 mali-supply: true @@ -92,7 +94,6 @@ required: - interrupts - interrupt-names - clocks - - mali-supply =20 additionalProperties: false =20 @@ -109,6 +110,29 @@ allOf: power-domains: maxItems: 1 power-domain-names: false + required: + - mali-supply + - if: + properties: + compatible: + contains: + const: mediatek,mt8196-mali + then: + properties: + mali-supply: false + sram-supply: false + operating-points-v2: false + power-domains: + maxItems: 1 + power-domain-names: false + clocks: + maxItems: 2 + clock-names: + items: + - const: core + - const: stacks + required: + - power-domains =20 examples: - | @@ -144,5 +168,17 @@ examples: }; }; }; + - | + gpu@48000000 { + compatible =3D "mediatek,mt8196-mali", "arm,mali-valhall-csf"; + reg =3D <0x48000000 0x480000>; + clocks =3D <&gpufreq 0>, <&gpufreq 1>; + clock-names =3D "core", "stacks"; + interrupts =3D , + , + ; + interrupt-names =3D "job", "mmu", "gpu"; + power-domains =3D <&gpufreq>; + }; =20 ... --=20 2.51.0 From nobody Thu Oct 2 03:27:33 2025 Received: from sender4-pp-f112.zoho.com (sender4-pp-f112.zoho.com [136.143.188.112]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id 36E26322773; Tue, 23 Sep 2025 11:40:56 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=pass smtp.client-ip=136.143.188.112 ARC-Seal: i=2; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1758627659; cv=pass; b=VZ52nYDKb9nxpUNKOejl3OEpX25CQPdZKyPqU0mu5StLPRQdiqxbVNPoGzmq5a3QpGmaQQQJK1Xx8t167nWJNgj7jPHam51CVn652yYI5+bex7HmNo2lx3W4NI9aFkg93aN2MGF0hSvPn3Mq3b90KktBmEWax76Jo+Zu4ApdDiA= ARC-Message-Signature: i=2; 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h=From:From:Date:Date:Subject:Subject:MIME-Version:Content-Type:Content-Transfer-Encoding:Message-Id:Message-Id:References:In-Reply-To:To:To:Cc:Cc:Reply-To; bh=949P4c7oqZxzyo32GRpJ63no7ggIJKiAuXyyVIYptoo=; b=T3FdaC/KTIftSH470aR/Ul2aZLxtVSbyowKqlyeWUei8rzdr/vNAVmtrijsvYiX0 RLGrX/xr7wOKh4jxeEVlLJu2VPbscCew+M9216HP89Dava1o4kWME24fh5sPU4lmmjq /10+uH05ldee9uBdsnlSAt468tPPkVjsTZ/DzX4E= Received: by mx.zohomail.com with SMTPS id 17586276323594.250542151723835; Tue, 23 Sep 2025 04:40:32 -0700 (PDT) From: Nicolas Frattaroli Date: Tue, 23 Sep 2025 13:39:55 +0200 Subject: [PATCH v4 2/8] dt-bindings: power: Add MT8196 GPU frequency control binding Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Content-Transfer-Encoding: quoted-printable Message-Id: <20250923-mt8196-gpufreq-v4-2-6cd63ade73d6@collabora.com> References: <20250923-mt8196-gpufreq-v4-0-6cd63ade73d6@collabora.com> In-Reply-To: <20250923-mt8196-gpufreq-v4-0-6cd63ade73d6@collabora.com> To: AngeloGioacchino Del Regno , Boris Brezillon , Jassi Brar , Chia-I Wu , Chen-Yu Tsai , Steven Price , Liviu Dudau , Maarten Lankhorst , Maxime Ripard , Thomas Zimmermann , David Airlie , Simona Vetter , Rob Herring , Krzysztof Kozlowski , Conor Dooley , Matthias Brugger , Kees Cook , "Gustavo A. R. Silva" , Ulf Hansson Cc: kernel@collabora.com, dri-devel@lists.freedesktop.org, devicetree@vger.kernel.org, linux-kernel@vger.kernel.org, linux-arm-kernel@lists.infradead.org, linux-mediatek@lists.infradead.org, linux-hardening@vger.kernel.org, linux-pm@vger.kernel.org, Nicolas Frattaroli X-Mailer: b4 0.14.2 On the MT8196 and MT6991 SoCs, the GPU power and frequency is controlled by some integration logic, referred to as "MFlexGraphics" by MediaTek, which comes in the form of an embedded controller running special-purpose firmware. This controller takes care of the regulators and PLL clock frequencies to squeeze the maximum amount of power out of the silicon. Add a binding which models it as a power domain. Signed-off-by: Nicolas Frattaroli --- .../bindings/power/mediatek,mt8196-gpufreq.yaml | 117 +++++++++++++++++= ++++ 1 file changed, 117 insertions(+) diff --git a/Documentation/devicetree/bindings/power/mediatek,mt8196-gpufre= q.yaml b/Documentation/devicetree/bindings/power/mediatek,mt8196-gpufreq.ya= ml new file mode 100644 index 0000000000000000000000000000000000000000..03721244a737ce0914a89cc0aed= d88fa3b6b2038 --- /dev/null +++ b/Documentation/devicetree/bindings/power/mediatek,mt8196-gpufreq.yaml @@ -0,0 +1,117 @@ +# SPDX-License-Identifier: GPL-2.0-only OR BSD-2-Clause +%YAML 1.2 +--- +$id: http://devicetree.org/schemas/power/mediatek,mt8196-gpufreq.yaml# +$schema: http://devicetree.org/meta-schemas/core.yaml# + +title: MediaTek MFlexGraphics Power and Frequency Controller + +maintainers: + - Nicolas Frattaroli + +description: | + A special-purpose embedded MCU to control power and frequency of GPU dev= ices + using MediaTek Flexible Graphics integration hardware. + +properties: + $nodename: + pattern: '^power-controller@[a-f0-9]+$' + + compatible: + enum: + - mediatek,mt8196-gpufreq + + reg: + items: + - description: GPR memory area + - description: RPC memory area + - description: SoC variant ID register + + reg-names: + items: + - const: gpr + - const: rpc + - const: hw-revision + + clocks: + items: + - description: main clock of the embedded controller (EB) + - description: core PLL + - description: stack 0 PLL + - description: stack 1 PLL + + clock-names: + items: + - const: eb + - const: core + - const: stack0 + - const: stack1 + + mboxes: + items: + - description: FastDVFS events + - description: frequency control + - description: sleep control + - description: timer control + - description: frequency hopping control + - description: hardware voter control + - description: FastDVFS control + + mbox-names: + items: + - const: fast-dvfs-event + - const: gpufreq + - const: sleep + - const: timer + - const: fhctl + - const: ccf + - const: fast-dvfs + + shmem: + $ref: /schemas/types.yaml#/definitions/phandle + description: phandle to the shared memory region of the GPUEB MCU + + "#clock-cells": + const: 1 + + "#power-domain-cells": + const: 0 + +required: + - compatible + - reg + - reg-names + - clocks + - clock-names + - mboxes + - mbox-names + - shmem + - "#clock-cells" + - "#power-domain-cells" + +additionalProperties: false + +examples: + - | + #include + + power-controller@4b09fd00 { + compatible =3D "mediatek,mt8196-gpufreq"; + reg =3D <0x4b09fd00 0x80>, + <0x4b800000 0x1000>, + <0x4b860128 0x4>; + reg-names =3D "gpr", "rpc", "hw-revision"; + clocks =3D <&topckgen CLK_TOP_MFG_EB>, + <&mfgpll CLK_MFG_AO_MFGPLL>, + <&mfgpll_sc0 CLK_MFGSC0_AO_MFGPLL_SC0>, + <&mfgpll_sc1 CLK_MFGSC1_AO_MFGPLL_SC1>; + clock-names =3D "eb", "core", "stack0", "stack1"; + mboxes =3D <&gpueb_mbox 0>, <&gpueb_mbox 1>, <&gpueb_mbox 2>, + <&gpueb_mbox 3>, <&gpueb_mbox 4>, <&gpueb_mbox 5>, + <&gpueb_mbox 7>; + mbox-names =3D "fast-dvfs-event", "gpufreq", "sleep", "timer", "fh= ctl", + "ccf", "fast-dvfs"; + shmem =3D <&gpufreq_shmem>; + #clock-cells =3D <1>; + #power-domain-cells =3D <0>; + }; --=20 2.51.0 From nobody Thu Oct 2 03:27:33 2025 Received: from sender4-pp-f112.zoho.com (sender4-pp-f112.zoho.com [136.143.188.112]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id 9FBBB322556; Tue, 23 Sep 2025 11:41:03 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; 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charset="utf-8" Content-Transfer-Encoding: quoted-printable Message-Id: <20250923-mt8196-gpufreq-v4-3-6cd63ade73d6@collabora.com> References: <20250923-mt8196-gpufreq-v4-0-6cd63ade73d6@collabora.com> In-Reply-To: <20250923-mt8196-gpufreq-v4-0-6cd63ade73d6@collabora.com> To: AngeloGioacchino Del Regno , Boris Brezillon , Jassi Brar , Chia-I Wu , Chen-Yu Tsai , Steven Price , Liviu Dudau , Maarten Lankhorst , Maxime Ripard , Thomas Zimmermann , David Airlie , Simona Vetter , Rob Herring , Krzysztof Kozlowski , Conor Dooley , Matthias Brugger , Kees Cook , "Gustavo A. R. Silva" , Ulf Hansson Cc: kernel@collabora.com, dri-devel@lists.freedesktop.org, devicetree@vger.kernel.org, linux-kernel@vger.kernel.org, linux-arm-kernel@lists.infradead.org, linux-mediatek@lists.infradead.org, linux-hardening@vger.kernel.org, linux-pm@vger.kernel.org, Nicolas Frattaroli X-Mailer: b4 0.14.2 This compatible is used for an SRAM section that's shared between the MT8196's application processor cores and the embedded GPUEB MCU that controls the GPU frequency. Through this SRAM section, things about the GPU frequency controller like the OPP table can be read. Reviewed-by: AngeloGioacchino Del Regno Acked-by: Rob Herring (Arm) Signed-off-by: Nicolas Frattaroli --- Documentation/devicetree/bindings/sram/sram.yaml | 1 + 1 file changed, 1 insertion(+) diff --git a/Documentation/devicetree/bindings/sram/sram.yaml b/Documentati= on/devicetree/bindings/sram/sram.yaml index 7c1337e159f2371401ae99313375656fff014ed4..6ba0dd6a66def11f56a1d5276d7= 397b655bff11e 100644 --- a/Documentation/devicetree/bindings/sram/sram.yaml +++ b/Documentation/devicetree/bindings/sram/sram.yaml @@ -89,6 +89,7 @@ patternProperties: - arm,juno-scp-shmem - arm,scmi-shmem - arm,scp-shmem + - mediatek,mt8196-gpufreq-sram - renesas,smp-sram - rockchip,rk3066-smp-sram - samsung,exynos4210-sysram --=20 2.51.0 From nobody Thu Oct 2 03:27:33 2025 Received: from sender4-pp-f112.zoho.com (sender4-pp-f112.zoho.com [136.143.188.112]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id 6A67332274C; Tue, 23 Sep 2025 11:41:12 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=pass smtp.client-ip=136.143.188.112 ARC-Seal: i=2; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1758627674; cv=pass; b=gZeG9dUHmuv71cTizpbPJntBTU+oCLuGUI9tgOtqGOGhBYKkitk2ZsTnpTbqYNWMpZJ7Lk+qaoLKd1NqMOEmMQ9czui34+0+QL8eGjhsUWrSU981x40s6Rkdmjp1rok4ZY/v7d6YU3BL6HQMks4YyGvlT7qpa5QRPydzbYRuRBc= ARC-Message-Signature: i=2; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1758627674; c=relaxed/simple; bh=UbcJcNEfDFTnnUBurIVh4FMqr8VGmK6aS7+NNyGZ6ZA=; h=From:Date:Subject:MIME-Version:Content-Type:Message-Id:References: In-Reply-To:To:Cc; b=Cof3mMLWPTaPiQw5IIqd5XChQdnU7ZmaXAf394Zj6grbiT5XGS6mV+9G8D107jqYtu1mDOtTOXMc26UrWMOhcGji6Xud2Ju4ekcJUBzF544yIDYsR8SHK0V/MCXM+6z9aseIOgIeOD0J7LA71WyqQ8DQbOgmiRnLf7j5uKLqDw4= ARC-Authentication-Results: i=2; smtp.subspace.kernel.org; dmarc=pass (p=none dis=none) header.from=collabora.com; spf=pass smtp.mailfrom=collabora.com; dkim=pass (1024-bit key) header.d=collabora.com header.i=nicolas.frattaroli@collabora.com header.b=AD6C5rBC; arc=pass smtp.client-ip=136.143.188.112 Authentication-Results: smtp.subspace.kernel.org; dmarc=pass (p=none dis=none) header.from=collabora.com Authentication-Results: smtp.subspace.kernel.org; spf=pass smtp.mailfrom=collabora.com Authentication-Results: smtp.subspace.kernel.org; dkim=pass (1024-bit key) header.d=collabora.com header.i=nicolas.frattaroli@collabora.com header.b="AD6C5rBC" ARC-Seal: i=1; a=rsa-sha256; t=1758627648; cv=none; d=zohomail.com; s=zohoarc; b=KWnyYstbYsqu77K0d6sbxLmGRGRAIaUQsQqMFjBgzeyqmWN2geANGC23t15HjFjgupdKgkZzzb3b/EX5HPQlekzjQGYq7oEprZTpoNW70u2WalKmoa4u1DoNHrzPI67qItMM5zEzDv1s00NyuGvAIZqvPyZM9/L6gl/+2sareHo= ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=zohomail.com; s=zohoarc; t=1758627648; h=Content-Type:Content-Transfer-Encoding:Cc:Cc:Date:Date:From:From:In-Reply-To:MIME-Version:Message-ID:References:Subject:Subject:To:To:Message-Id:Reply-To; bh=ZFDG+wvs2WG93zhT44NWUOfN2GowDDjPuUl1CMypSmk=; b=Lw5xSCfPH3ZqD+AR9NKK1N13JOiGO4QYs5gjfBEF1O4JZUEiXai2QhAmYbObi3VT8z1w/k0aDAngJcbzbs2FZwoOk6HTv5Qd38cyKQNRNXglSBEjypDRb8S1s+LMoLtHrYASPqbp1HlrVVQKSUAiPkpKfvCQMIay0q68bnjuZs0= ARC-Authentication-Results: i=1; mx.zohomail.com; dkim=pass header.i=collabora.com; spf=pass smtp.mailfrom=nicolas.frattaroli@collabora.com; dmarc=pass header.from= DKIM-Signature: v=1; a=rsa-sha256; q=dns/txt; c=relaxed/relaxed; t=1758627648; s=zohomail; d=collabora.com; i=nicolas.frattaroli@collabora.com; h=From:From:Date:Date:Subject:Subject:MIME-Version:Content-Type:Content-Transfer-Encoding:Message-Id:Message-Id:References:In-Reply-To:To:To:Cc:Cc:Reply-To; bh=ZFDG+wvs2WG93zhT44NWUOfN2GowDDjPuUl1CMypSmk=; b=AD6C5rBCb111C5q6cIOOqoSnnFCKHixwxfdqLbn/jSVTfCqY0Kw4/fMqIrCzW4pP ZHO9i+ofc3uI+YR+cOfnveSw6TL47Km5Qul1R+gMxX3UDCPB/hMbOU6LMXTC9+f7i4w YffG3l4P7cvp2uEw5PsXV+KlgXqdRLC3x2ca5aBI= Received: by mx.zohomail.com with SMTPS id 1758627645320914.7659430893929; Tue, 23 Sep 2025 04:40:45 -0700 (PDT) From: Nicolas Frattaroli Date: Tue, 23 Sep 2025 13:39:57 +0200 Subject: [PATCH v4 4/8] dt-bindings: mailbox: Add MT8196 GPUEB Mailbox Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Content-Transfer-Encoding: quoted-printable Message-Id: <20250923-mt8196-gpufreq-v4-4-6cd63ade73d6@collabora.com> References: <20250923-mt8196-gpufreq-v4-0-6cd63ade73d6@collabora.com> In-Reply-To: <20250923-mt8196-gpufreq-v4-0-6cd63ade73d6@collabora.com> To: AngeloGioacchino Del Regno , Boris Brezillon , Jassi Brar , Chia-I Wu , Chen-Yu Tsai , Steven Price , Liviu Dudau , Maarten Lankhorst , Maxime Ripard , Thomas Zimmermann , David Airlie , Simona Vetter , Rob Herring , Krzysztof Kozlowski , Conor Dooley , Matthias Brugger , Kees Cook , "Gustavo A. R. Silva" , Ulf Hansson Cc: kernel@collabora.com, dri-devel@lists.freedesktop.org, devicetree@vger.kernel.org, linux-kernel@vger.kernel.org, linux-arm-kernel@lists.infradead.org, linux-mediatek@lists.infradead.org, linux-hardening@vger.kernel.org, linux-pm@vger.kernel.org, Nicolas Frattaroli X-Mailer: b4 0.14.2 The MediaTek MT8196 SoC includes an embedded MCU referred to as "GPUEB", acting as glue logic to control power and frequency of the Mali GPU. This MCU runs special-purpose firmware for this use, and the main application processor communicates with it through a mailbox. Add a binding that describes this mailbox. Reviewed-by: AngeloGioacchino Del Regno Signed-off-by: Nicolas Frattaroli Reviewed-by: Rob Herring (Arm) --- .../mailbox/mediatek,mt8196-gpueb-mbox.yaml | 64 ++++++++++++++++++= ++++ 1 file changed, 64 insertions(+) diff --git a/Documentation/devicetree/bindings/mailbox/mediatek,mt8196-gpue= b-mbox.yaml b/Documentation/devicetree/bindings/mailbox/mediatek,mt8196-gpu= eb-mbox.yaml new file mode 100644 index 0000000000000000000000000000000000000000..ab5b780cb83a708a3897ca1a440= 131d97b56c3a6 --- /dev/null +++ b/Documentation/devicetree/bindings/mailbox/mediatek,mt8196-gpueb-mbox.= yaml @@ -0,0 +1,64 @@ +# SPDX-License-Identifier: GPL-2.0-only OR BSD-2-Clause +%YAML 1.2 +--- +$id: http://devicetree.org/schemas/mailbox/mediatek,mt8196-gpueb-mbox.yaml# +$schema: http://devicetree.org/meta-schemas/core.yaml# + +title: MediaTek MFlexGraphics GPUEB Mailbox Controller + +maintainers: + - Nicolas Frattaroli + +properties: + compatible: + enum: + - mediatek,mt8196-gpueb-mbox + + reg: + items: + - description: mailbox data registers + - description: mailbox control registers + + reg-names: + items: + - const: data + - const: ctl + + clocks: + items: + - description: main clock of the GPUEB MCU + + interrupts: + items: + - description: fires when a new message is received + + "#mbox-cells": + const: 1 + description: + The number of the mailbox channel. + +required: + - compatible + - reg + - reg-names + - clocks + - interrupts + - "#mbox-cells" + +additionalProperties: false + +examples: + - | + #include + #include + #include + + mailbox@4b09fd80 { + compatible =3D "mediatek,mt8196-gpueb-mbox"; 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Tue, 23 Sep 2025 04:40:51 -0700 (PDT) From: Nicolas Frattaroli Date: Tue, 23 Sep 2025 13:39:58 +0200 Subject: [PATCH v4 5/8] mailbox: add MediaTek GPUEB IPI mailbox Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Content-Transfer-Encoding: quoted-printable Message-Id: <20250923-mt8196-gpufreq-v4-5-6cd63ade73d6@collabora.com> References: <20250923-mt8196-gpufreq-v4-0-6cd63ade73d6@collabora.com> In-Reply-To: <20250923-mt8196-gpufreq-v4-0-6cd63ade73d6@collabora.com> To: AngeloGioacchino Del Regno , Boris Brezillon , Jassi Brar , Chia-I Wu , Chen-Yu Tsai , Steven Price , Liviu Dudau , Maarten Lankhorst , Maxime Ripard , Thomas Zimmermann , David Airlie , Simona Vetter , Rob Herring , Krzysztof Kozlowski , Conor Dooley , Matthias Brugger , Kees Cook , "Gustavo A. R. Silva" , Ulf Hansson Cc: kernel@collabora.com, dri-devel@lists.freedesktop.org, devicetree@vger.kernel.org, linux-kernel@vger.kernel.org, linux-arm-kernel@lists.infradead.org, linux-mediatek@lists.infradead.org, linux-hardening@vger.kernel.org, linux-pm@vger.kernel.org, Nicolas Frattaroli X-Mailer: b4 0.14.2 The MT8196 SoC uses an embedded MCU to control frequencies and power of the GPU. This controller is referred to as "GPUEB". It communicates to the application processor, among other ways, through a mailbox. The mailbox exposes one interrupt, which appears to only be fired when a response is received, rather than a transaction is completed. For us, this means we unfortunately need to poll for txdone. The mailbox also requires the EB clock to be on when touching any of the mailbox registers. Add a simple driver for it based on the common mailbox framework. Signed-off-by: Nicolas Frattaroli Reviewed-by: AngeloGioacchino Del Regno --- drivers/mailbox/Kconfig | 10 ++ drivers/mailbox/Makefile | 2 + drivers/mailbox/mtk-gpueb-mailbox.c | 318 ++++++++++++++++++++++++++++++++= ++++ 3 files changed, 330 insertions(+) diff --git a/drivers/mailbox/Kconfig b/drivers/mailbox/Kconfig index 02432d4a5ccd46a16156a09c7f277fb03e4013f5..2016defda1fabb5c0fcc8078f84= a52d4e4e00167 100644 --- a/drivers/mailbox/Kconfig +++ b/drivers/mailbox/Kconfig @@ -294,6 +294,16 @@ config MTK_CMDQ_MBOX critical time limitation, such as updating display configuration during the vblank. =20 +config MTK_GPUEB_MBOX + tristate "MediaTek GPUEB Mailbox Support" + depends on ARCH_MEDIATEK || COMPILE_TEST + help + The MediaTek GPUEB mailbox is used to communicate with the embedded + controller in charge of GPU frequency and power management on some + MediaTek SoCs, such as the MT8196. + Say Y or m here if you want to support the MT8196 SoC in your kernel + build. + config ZYNQMP_IPI_MBOX tristate "Xilinx ZynqMP IPI Mailbox" depends on ARCH_ZYNQMP && OF diff --git a/drivers/mailbox/Makefile b/drivers/mailbox/Makefile index 98a68f838486eed117d24296138bf59fda3f92e4..564d06e71313e6d1972e4a6036e= 1e78c8c7ec450 100644 --- a/drivers/mailbox/Makefile +++ b/drivers/mailbox/Makefile @@ -63,6 +63,8 @@ obj-$(CONFIG_MTK_ADSP_MBOX) +=3D mtk-adsp-mailbox.o =20 obj-$(CONFIG_MTK_CMDQ_MBOX) +=3D mtk-cmdq-mailbox.o =20 +obj-$(CONFIG_MTK_GPUEB_MBOX) +=3D mtk-gpueb-mailbox.o + obj-$(CONFIG_ZYNQMP_IPI_MBOX) +=3D zynqmp-ipi-mailbox.o =20 obj-$(CONFIG_SUN6I_MSGBOX) +=3D sun6i-msgbox.o diff --git a/drivers/mailbox/mtk-gpueb-mailbox.c b/drivers/mailbox/mtk-gpue= b-mailbox.c new file mode 100644 index 0000000000000000000000000000000000000000..d388418349dfb70f6aff4756fc9= a368c2325135f --- /dev/null +++ b/drivers/mailbox/mtk-gpueb-mailbox.c @@ -0,0 +1,318 @@ +// SPDX-License-Identifier: GPL-2.0-only +/* + * MediaTek GPUEB mailbox driver for SoCs such as the MT8196 + * + * Copyright (C) 2025, Collabora Ltd. + * + * Developers harmed in the making of this driver: + * - Nicolas Frattaroli + */ + +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include + +#define GPUEB_MBOX_CTL_TX_STS 0x00 +#define GPUEB_MBOX_CTL_IRQ_SET 0x04 +#define GPUEB_MBOX_CTL_IRQ_CLR 0x74 +#define GPUEB_MBOX_CTL_RX_STS 0x78 + +#define GPUEB_MBOX_FULL BIT(0) /* i.e. we've received data */ +#define GPUEB_MBOX_BLOCKED BIT(1) /* i.e. the channel is shutdown */ + +#define GPUEB_MBOX_MAX_RX_SIZE 32 /* in bytes */ + +struct mtk_gpueb_mbox { + struct device *dev; + struct clk *clk; + void __iomem *mbox_mmio; + void __iomem *mbox_ctl; + struct mbox_controller mbox; + struct mtk_gpueb_mbox_chan *ch; + int irq; + const struct mtk_gpueb_mbox_variant *v; +}; + +/** + * struct mtk_gpueb_mbox_chan - per-channel runtime data + * @ebm: pointer to the parent &struct mtk_gpueb_mbox mailbox + * @full_name: descriptive name of channel for IRQ subsystem + * @num: channel number, starting at 0 + * @rx_status: signifies whether channel reception is turned off, or full + * @c: pointer to the constant &struct mtk_gpueb_mbox_chan_desc channel da= ta + */ +struct mtk_gpueb_mbox_chan { + struct mtk_gpueb_mbox *ebm; + char *full_name; + u8 num; + atomic_t rx_status; + const struct mtk_gpueb_mbox_chan_desc *c; +}; + +/** + * struct mtk_gpueb_mbox_chan_desc - per-channel constant data + * @name: name of this channel + * @num: index of this channel, starting at 0 + * @tx_offset: byte offset measured from mmio base for outgoing data + * @tx_len: size, in bytes, of the outgoing data on this channel + * @rx_offset: bytes offset measured from mmio base for incoming data + * @rx_len: size, in bytes, of the incoming data on this channel + */ +struct mtk_gpueb_mbox_chan_desc { + const char *name; + const u8 num; + const u16 tx_offset; + const u8 tx_len; + const u16 rx_offset; + const u8 rx_len; +}; + +struct mtk_gpueb_mbox_variant { + const u8 num_channels; + const struct mtk_gpueb_mbox_chan_desc channels[] __counted_by(num_channel= s); +}; + +/** + * mtk_gpueb_mbox_read_rx - read RX buffer from MMIO into channel's RX buf= fer + * @buf: buffer to read into + * @chan: pointer to the channel to read + */ +static void mtk_gpueb_mbox_read_rx(void *buf, struct mtk_gpueb_mbox_chan *= chan) +{ + memcpy_fromio(buf, chan->ebm->mbox_mmio + chan->c->rx_offset, chan->c->rx= _len); +} + +static irqreturn_t mtk_gpueb_mbox_isr(int irq, void *data) +{ + struct mtk_gpueb_mbox_chan *ch =3D data; + u32 rx_sts; + + rx_sts =3D readl(ch->ebm->mbox_ctl + GPUEB_MBOX_CTL_RX_STS); + + if (rx_sts & BIT(ch->num)) { + if (!atomic_cmpxchg(&ch->rx_status, 0, GPUEB_MBOX_FULL | GPUEB_MBOX_BLOC= KED)) + return IRQ_WAKE_THREAD; + } + + return IRQ_NONE; +} + +static irqreturn_t mtk_gpueb_mbox_thread(int irq, void *data) +{ + struct mtk_gpueb_mbox_chan *ch =3D data; + u8 buf[GPUEB_MBOX_MAX_RX_SIZE] =3D {}; + int status; + + status =3D atomic_cmpxchg(&ch->rx_status, GPUEB_MBOX_FULL | GPUEB_MBOX_BL= OCKED, + GPUEB_MBOX_FULL); + if (status =3D=3D (GPUEB_MBOX_FULL | GPUEB_MBOX_BLOCKED)) { + mtk_gpueb_mbox_read_rx(buf, ch); + writel(BIT(ch->num), ch->ebm->mbox_ctl + GPUEB_MBOX_CTL_IRQ_CLR); + mbox_chan_received_data(&ch->ebm->mbox.chans[ch->num], buf); + atomic_set(&ch->rx_status, 0); + return IRQ_HANDLED; + } + + return IRQ_NONE; +} + +static int mtk_gpueb_mbox_send_data(struct mbox_chan *chan, void *data) +{ + struct mtk_gpueb_mbox_chan *ch =3D chan->con_priv; + u32 *values =3D data; + int i; + + if (atomic_read(&ch->rx_status)) + return -EBUSY; + + /* + * We don't want any fancy nonsense, just write the 32-bit values in + * order. memcpy_toio/__iowrite32_copy don't work here, as they may use + * writes of different sizes or memory ordering characteristics depending + * on the architecture, alignment and the current phase of the moon. + */ + for (i =3D 0; i < ch->c->tx_len; i +=3D 4) + writel(values[i / 4], ch->ebm->mbox_mmio + ch->c->tx_offset + i); + + writel(BIT(ch->num), ch->ebm->mbox_ctl + GPUEB_MBOX_CTL_IRQ_SET); + + return 0; +} + +static int mtk_gpueb_mbox_startup(struct mbox_chan *chan) +{ + struct mtk_gpueb_mbox_chan *ch =3D chan->con_priv; + int ret; + + atomic_set(&ch->rx_status, 0); + + ret =3D clk_enable(ch->ebm->clk); + if (ret) { + dev_err(ch->ebm->dev, "Failed to enable EB clock: %pe\n", + ERR_PTR(ret)); + goto err_block; + } + + writel(BIT(ch->num), ch->ebm->mbox_ctl + GPUEB_MBOX_CTL_IRQ_CLR); + + ret =3D devm_request_threaded_irq(ch->ebm->dev, ch->ebm->irq, mtk_gpueb_m= box_isr, + mtk_gpueb_mbox_thread, IRQF_SHARED | IRQF_ONESHOT, + ch->full_name, ch); + if (ret) { + dev_err(ch->ebm->dev, "Failed to request IRQ: %pe\n", + ERR_PTR(ret)); + goto err_unclk; + } + + return 0; + +err_unclk: + clk_disable(ch->ebm->clk); +err_block: + atomic_set(&ch->rx_status, GPUEB_MBOX_BLOCKED); + + return ret; +} + +static void mtk_gpueb_mbox_shutdown(struct mbox_chan *chan) +{ + struct mtk_gpueb_mbox_chan *ch =3D chan->con_priv; + + atomic_set(&ch->rx_status, GPUEB_MBOX_BLOCKED); + + devm_free_irq(ch->ebm->dev, ch->ebm->irq, ch); + + clk_disable(ch->ebm->clk); +} + +static bool mtk_gpueb_mbox_last_tx_done(struct mbox_chan *chan) +{ + struct mtk_gpueb_mbox_chan *ch =3D chan->con_priv; + + return !(readl(ch->ebm->mbox_ctl + GPUEB_MBOX_CTL_TX_STS) & BIT(ch->num)); +} + +const struct mbox_chan_ops mtk_gpueb_mbox_ops =3D { + .send_data =3D mtk_gpueb_mbox_send_data, + .startup =3D mtk_gpueb_mbox_startup, + .shutdown =3D mtk_gpueb_mbox_shutdown, + .last_tx_done =3D mtk_gpueb_mbox_last_tx_done, +}; + +static int mtk_gpueb_mbox_probe(struct platform_device *pdev) +{ + struct mtk_gpueb_mbox_chan *ch; + struct mtk_gpueb_mbox *ebm; + unsigned int i; + + ebm =3D devm_kzalloc(&pdev->dev, sizeof(*ebm), GFP_KERNEL); + if (!ebm) + return -ENOMEM; + + ebm->dev =3D &pdev->dev; + ebm->v =3D of_device_get_match_data(ebm->dev); + + ebm->irq =3D platform_get_irq(pdev, 0); + if (ebm->irq < 0) + return ebm->irq; + + ebm->clk =3D devm_clk_get_prepared(ebm->dev, NULL); + if (IS_ERR(ebm->clk)) + return dev_err_probe(ebm->dev, PTR_ERR(ebm->clk), + "Failed to get 'eb' clock\n"); + + ebm->mbox_mmio =3D devm_platform_ioremap_resource(pdev, 0); + if (IS_ERR(ebm->mbox_mmio)) + return dev_err_probe(ebm->dev, PTR_ERR(ebm->mbox_mmio), + "Couldn't map mailbox data registers\n"); + + ebm->mbox_ctl =3D devm_platform_ioremap_resource(pdev, 1); + if (IS_ERR(ebm->mbox_ctl)) + return dev_err_probe( + ebm->dev, PTR_ERR(ebm->mbox_ctl), + "Couldn't map mailbox control registers\n"); + + ebm->ch =3D devm_kmalloc_array(ebm->dev, ebm->v->num_channels, + sizeof(*ebm->ch), GFP_KERNEL); + if (!ebm->ch) + return -ENOMEM; + + ebm->mbox.chans =3D devm_kcalloc(ebm->dev, ebm->v->num_channels, + sizeof(struct mbox_chan), GFP_KERNEL); + if (!ebm->mbox.chans) + return -ENOMEM; + + for (i =3D 0; i < ebm->v->num_channels; i++) { + ch =3D &ebm->ch[i]; + ch->c =3D &ebm->v->channels[i]; + if (ch->c->rx_len > GPUEB_MBOX_MAX_RX_SIZE) { + dev_err(ebm->dev, "Channel %s RX size (%d) too large\n", + ch->c->name, ch->c->rx_len); + return -EINVAL; + } + ch->full_name =3D devm_kasprintf(ebm->dev, GFP_KERNEL, "%s:%s", + dev_name(ebm->dev), ch->c->name); + if (!ch->full_name) + return -ENOMEM; + + ch->ebm =3D ebm; + ch->num =3D i; + spin_lock_init(&ebm->mbox.chans[i].lock); + ebm->mbox.chans[i].con_priv =3D ch; + atomic_set(&ch->rx_status, GPUEB_MBOX_BLOCKED); + } + + ebm->mbox.dev =3D ebm->dev; + ebm->mbox.num_chans =3D ebm->v->num_channels; + ebm->mbox.txdone_poll =3D true; + ebm->mbox.txpoll_period =3D 0; /* minimum hrtimer interval */ + ebm->mbox.ops =3D &mtk_gpueb_mbox_ops; + + dev_set_drvdata(ebm->dev, ebm); + + return devm_mbox_controller_register(ebm->dev, &ebm->mbox); +} + +static const struct mtk_gpueb_mbox_variant mtk_gpueb_mbox_mt8196 =3D { + .num_channels =3D 12, + .channels =3D { + { "fast-dvfs-event", 0, 0x0000, 16, 0x00e0, 16 }, + { "gpufreq", 1, 0x0010, 32, 0x00f0, 32 }, + { "sleep", 2, 0x0030, 12, 0x0110, 4 }, + { "timer", 3, 0x003c, 24, 0x0114, 4 }, + { "fhctl", 4, 0x0054, 36, 0x0118, 4 }, + { "ccf", 5, 0x0078, 16, 0x011c, 16 }, + { "gpumpu", 6, 0x0088, 24, 0x012c, 4 }, + { "fast-dvfs", 7, 0x00a0, 24, 0x0130, 24 }, + { "ipir-c-met", 8, 0x00b8, 4, 0x0148, 16 }, + { "ipis-c-met", 9, 0x00bc, 16, 0x0158, 4 }, + { "brisket", 10, 0x00cc, 16, 0x015c, 16 }, + { "ppb", 11, 0x00dc, 4, 0x016c, 4 }, + }, +}; + +static const struct of_device_id mtk_gpueb_mbox_of_ids[] =3D { + { .compatible =3D "mediatek,mt8196-gpueb-mbox", .data =3D &mtk_gpueb_mbox= _mt8196 }, + { /* Sentinel */ } +}; +MODULE_DEVICE_TABLE(of, mtk_gpueb_mbox_of_ids); + +static struct platform_driver mtk_gpueb_mbox_drv =3D { + .probe =3D mtk_gpueb_mbox_probe, + .driver =3D { + .name =3D "mtk-gpueb-mbox", + .of_match_table =3D mtk_gpueb_mbox_of_ids, + } +}; +module_platform_driver(mtk_gpueb_mbox_drv); + +MODULE_AUTHOR("Nicolas Frattaroli "); +MODULE_DESCRIPTION("MediaTek GPUEB mailbox driver"); +MODULE_LICENSE("GPL"); --=20 2.51.0 From nobody Thu Oct 2 03:27:33 2025 Received: from sender4-pp-f112.zoho.com (sender4-pp-f112.zoho.com [136.143.188.112]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id 39068322C95; Tue, 23 Sep 2025 11:41:25 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=pass smtp.client-ip=136.143.188.112 ARC-Seal: i=2; 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charset="utf-8" Content-Transfer-Encoding: quoted-printable Message-Id: <20250923-mt8196-gpufreq-v4-6-6cd63ade73d6@collabora.com> References: <20250923-mt8196-gpufreq-v4-0-6cd63ade73d6@collabora.com> In-Reply-To: <20250923-mt8196-gpufreq-v4-0-6cd63ade73d6@collabora.com> To: AngeloGioacchino Del Regno , Boris Brezillon , Jassi Brar , Chia-I Wu , Chen-Yu Tsai , Steven Price , Liviu Dudau , Maarten Lankhorst , Maxime Ripard , Thomas Zimmermann , David Airlie , Simona Vetter , Rob Herring , Krzysztof Kozlowski , Conor Dooley , Matthias Brugger , Kees Cook , "Gustavo A. R. Silva" , Ulf Hansson Cc: kernel@collabora.com, dri-devel@lists.freedesktop.org, devicetree@vger.kernel.org, linux-kernel@vger.kernel.org, linux-arm-kernel@lists.infradead.org, linux-mediatek@lists.infradead.org, linux-hardening@vger.kernel.org, linux-pm@vger.kernel.org, Nicolas Frattaroli X-Mailer: b4 0.14.2 As it stands, panthor keeps a cached current frequency value for when it wants to retrieve it. This doesn't work well for when things might switch frequency without panthor's knowledge. Instead, implement the get_cur_freq operation, and expose it through a helper function to the rest of panthor. Reviewed-by: Steven Price Reviewed-by: AngeloGioacchino Del Regno Signed-off-by: Nicolas Frattaroli --- drivers/gpu/drm/panthor/panthor_devfreq.c | 33 +++++++++++++++++++++++++++= ---- drivers/gpu/drm/panthor/panthor_devfreq.h | 2 ++ drivers/gpu/drm/panthor/panthor_device.h | 3 --- drivers/gpu/drm/panthor/panthor_drv.c | 4 +++- 4 files changed, 34 insertions(+), 8 deletions(-) diff --git a/drivers/gpu/drm/panthor/panthor_devfreq.c b/drivers/gpu/drm/pa= nthor/panthor_devfreq.c index 3686515d368db5bb329f4858d4a7247a4957cc24..8903f60c0a3f06313ac2008791c= 210ff32b6bd52 100644 --- a/drivers/gpu/drm/panthor/panthor_devfreq.c +++ b/drivers/gpu/drm/panthor/panthor_devfreq.c @@ -62,7 +62,6 @@ static void panthor_devfreq_update_utilization(struct pan= thor_devfreq *pdevfreq) static int panthor_devfreq_target(struct device *dev, unsigned long *freq, u32 flags) { - struct panthor_device *ptdev =3D dev_get_drvdata(dev); struct dev_pm_opp *opp; int err; =20 @@ -72,8 +71,6 @@ static int panthor_devfreq_target(struct device *dev, uns= igned long *freq, dev_pm_opp_put(opp); =20 err =3D dev_pm_opp_set_rate(dev, *freq); - if (!err) - ptdev->current_frequency =3D *freq; =20 return err; } @@ -115,11 +112,21 @@ static int panthor_devfreq_get_dev_status(struct devi= ce *dev, return 0; } =20 +static int panthor_devfreq_get_cur_freq(struct device *dev, unsigned long = *freq) +{ + struct panthor_device *ptdev =3D dev_get_drvdata(dev); + + *freq =3D clk_get_rate(ptdev->clks.core); + + return 0; +} + static struct devfreq_dev_profile panthor_devfreq_profile =3D { .timer =3D DEVFREQ_TIMER_DELAYED, .polling_ms =3D 50, /* ~3 frames */ .target =3D panthor_devfreq_target, .get_dev_status =3D panthor_devfreq_get_dev_status, + .get_cur_freq =3D panthor_devfreq_get_cur_freq, }; =20 int panthor_devfreq_init(struct panthor_device *ptdev) @@ -198,7 +205,6 @@ int panthor_devfreq_init(struct panthor_device *ptdev) return PTR_ERR(opp); =20 panthor_devfreq_profile.initial_freq =3D cur_freq; - ptdev->current_frequency =3D cur_freq; =20 /* * Set the recommend OPP this will enable and configure the regulator @@ -296,3 +302,22 @@ void panthor_devfreq_record_idle(struct panthor_device= *ptdev) =20 spin_unlock_irqrestore(&pdevfreq->lock, irqflags); } + +unsigned long panthor_devfreq_get_freq(struct panthor_device *ptdev) +{ + struct panthor_devfreq *pdevfreq =3D ptdev->devfreq; + unsigned long freq =3D 0; + int ret; + + if (!pdevfreq || !pdevfreq->devfreq) + return 0; + + if (pdevfreq->devfreq->profile->get_cur_freq) { + ret =3D pdevfreq->devfreq->profile->get_cur_freq(ptdev->base.dev, + &freq); + if (ret) + return 0; + } + + return freq; +} diff --git a/drivers/gpu/drm/panthor/panthor_devfreq.h b/drivers/gpu/drm/pa= nthor/panthor_devfreq.h index b7631de695f7d79456478c87e8af5dc47673cd1d..f8e29e02f66cb3281ed4bb4c75c= da9bd4df82b92 100644 --- a/drivers/gpu/drm/panthor/panthor_devfreq.h +++ b/drivers/gpu/drm/panthor/panthor_devfreq.h @@ -18,4 +18,6 @@ void panthor_devfreq_suspend(struct panthor_device *ptdev= ); void panthor_devfreq_record_busy(struct panthor_device *ptdev); void panthor_devfreq_record_idle(struct panthor_device *ptdev); =20 +unsigned long panthor_devfreq_get_freq(struct panthor_device *ptdev); + #endif /* __PANTHOR_DEVFREQ_H__ */ diff --git a/drivers/gpu/drm/panthor/panthor_device.h b/drivers/gpu/drm/pan= thor/panthor_device.h index 9f0649ecfc4fc697a21a8b2fc4dd89c8ecf298df..f32c1868bf6d782d99df9dbd0ba= bcea049c917e0 100644 --- a/drivers/gpu/drm/panthor/panthor_device.h +++ b/drivers/gpu/drm/panthor/panthor_device.h @@ -214,9 +214,6 @@ struct panthor_device { /** @profile_mask: User-set profiling flags for job accounting. */ u32 profile_mask; =20 - /** @current_frequency: Device clock frequency at present. Set by DVFS*/ - unsigned long current_frequency; - /** @fast_rate: Maximum device clock frequency. Set by DVFS */ unsigned long fast_rate; =20 diff --git a/drivers/gpu/drm/panthor/panthor_drv.c b/drivers/gpu/drm/pantho= r/panthor_drv.c index ea4a37b566a8b215f2b7a09c333a696f1dcdb58f..4d59d94c353c3ca76f4b98a411c= 8f8284efafd08 100644 --- a/drivers/gpu/drm/panthor/panthor_drv.c +++ b/drivers/gpu/drm/panthor/panthor_drv.c @@ -25,6 +25,7 @@ #include #include =20 +#include "panthor_devfreq.h" #include "panthor_device.h" #include "panthor_fw.h" #include "panthor_gem.h" @@ -1519,7 +1520,8 @@ static void panthor_gpu_show_fdinfo(struct panthor_de= vice *ptdev, drm_printf(p, "drm-cycles-panthor:\t%llu\n", pfile->stats.cycles); =20 drm_printf(p, "drm-maxfreq-panthor:\t%lu Hz\n", ptdev->fast_rate); - drm_printf(p, "drm-curfreq-panthor:\t%lu Hz\n", ptdev->current_frequency); + drm_printf(p, "drm-curfreq-panthor:\t%lu Hz\n", + panthor_devfreq_get_freq(ptdev)); } =20 static void panthor_show_internal_memory_stats(struct drm_printer *p, stru= ct drm_file *file) --=20 2.51.0 From nobody Thu Oct 2 03:27:33 2025 Received: from sender4-pp-f112.zoho.com (sender4-pp-f112.zoho.com [136.143.188.112]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id ECE23322541; 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charset="utf-8" Content-Transfer-Encoding: quoted-printable Message-Id: <20250923-mt8196-gpufreq-v4-7-6cd63ade73d6@collabora.com> References: <20250923-mt8196-gpufreq-v4-0-6cd63ade73d6@collabora.com> In-Reply-To: <20250923-mt8196-gpufreq-v4-0-6cd63ade73d6@collabora.com> To: AngeloGioacchino Del Regno , Boris Brezillon , Jassi Brar , Chia-I Wu , Chen-Yu Tsai , Steven Price , Liviu Dudau , Maarten Lankhorst , Maxime Ripard , Thomas Zimmermann , David Airlie , Simona Vetter , Rob Herring , Krzysztof Kozlowski , Conor Dooley , Matthias Brugger , Kees Cook , "Gustavo A. R. Silva" , Ulf Hansson Cc: kernel@collabora.com, dri-devel@lists.freedesktop.org, devicetree@vger.kernel.org, linux-kernel@vger.kernel.org, linux-arm-kernel@lists.infradead.org, linux-mediatek@lists.infradead.org, linux-hardening@vger.kernel.org, linux-pm@vger.kernel.org, Nicolas Frattaroli X-Mailer: b4 0.14.2 On SoCs where the GPU's power-domain is in charge of setting performance levels, the OPP table of the GPU node will have already been populated during said power-domain's attach_dev operation. To avoid initialising an OPP table twice, only set the OPP regulator and the OPPs from DT if there's no OPP table present. Signed-off-by: Nicolas Frattaroli --- drivers/gpu/drm/panthor/panthor_devfreq.c | 24 +++++++++++++++--------- 1 file changed, 15 insertions(+), 9 deletions(-) diff --git a/drivers/gpu/drm/panthor/panthor_devfreq.c b/drivers/gpu/drm/pa= nthor/panthor_devfreq.c index 8903f60c0a3f06313ac2008791c210ff32b6bd52..4ec46a67db7d4331ac31a249e41= ee19378cd411e 100644 --- a/drivers/gpu/drm/panthor/panthor_devfreq.c +++ b/drivers/gpu/drm/panthor/panthor_devfreq.c @@ -143,6 +143,7 @@ int panthor_devfreq_init(struct panthor_device *ptdev) struct panthor_devfreq *pdevfreq; struct dev_pm_opp *opp; unsigned long cur_freq; + struct opp_table *t; unsigned long freq =3D ULONG_MAX; int ret; =20 @@ -152,17 +153,22 @@ int panthor_devfreq_init(struct panthor_device *ptdev) =20 ptdev->devfreq =3D pdevfreq; =20 - ret =3D devm_pm_opp_set_regulators(dev, reg_names); - if (ret) { - if (ret !=3D -EPROBE_DEFER) - DRM_DEV_ERROR(dev, "Couldn't set OPP regulators\n"); + t =3D dev_pm_opp_get_opp_table(dev); + if (IS_ERR_OR_NULL(t)) { + ret =3D devm_pm_opp_set_regulators(dev, reg_names); + if (ret) { + if (ret !=3D -EPROBE_DEFER) + DRM_DEV_ERROR(dev, "Couldn't set OPP regulators\n"); =20 - return ret; - } + return ret; + } =20 - ret =3D devm_pm_opp_of_add_table(dev); - if (ret) - return ret; + ret =3D devm_pm_opp_of_add_table(dev); + if (ret) + return ret; + } else { + dev_pm_opp_put_opp_table(t); + } =20 spin_lock_init(&pdevfreq->lock); =20 --=20 2.51.0 From nobody Thu Oct 2 03:27:33 2025 Received: from sender4-pp-f112.zoho.com (sender4-pp-f112.zoho.com [136.143.188.112]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id 34FB2322773; Tue, 23 Sep 2025 11:41:39 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=pass smtp.client-ip=136.143.188.112 ARC-Seal: i=2; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1758627703; cv=pass; b=txQhFTfvNyFTfmMWEkiAP42P0EYR/kWRbVpTIJBgXdWtN1J5U1yVFeCGpMYLKl8uLia3etbI2eSDmUaJBkr9AUgiO7sZ2UO+kO4gn7XiF3WAud/RYXIDzIQKAZ4so30TgEataiuKUrC0vwHBx0HVbSIKv3CX7MDYcsxQjNXlY4Y= ARC-Message-Signature: i=2; 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h=From:From:Date:Date:Subject:Subject:MIME-Version:Content-Type:Content-Transfer-Encoding:Message-Id:Message-Id:References:In-Reply-To:To:To:Cc:Cc:Reply-To; bh=HYKeHHm6NsgBv+iw3ceRO3055kcHfkYzP5Udx2VlZbo=; b=fQgJmqD4Q4kqT7A7y5ZyPi7lqhxv/ZJFfWKedpxv+lZfL3TvkWPoyL2aXBVxj0hH UopYS6AtkP7Yknp6OHFx3e0caSs2aWkEOkXyGTeDrxbujNzmlWazZlvctlxjSpOI0dK nWvfqJvGCKkMuKcMuebBHT2bLv3hXN90Nj8PXeUo= Received: by mx.zohomail.com with SMTPS id 1758627671505460.9892284202813; Tue, 23 Sep 2025 04:41:11 -0700 (PDT) From: Nicolas Frattaroli Date: Tue, 23 Sep 2025 13:40:01 +0200 Subject: [PATCH v4 8/8] pmdomain: mediatek: Add support for MFlexGraphics Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Content-Transfer-Encoding: quoted-printable Message-Id: <20250923-mt8196-gpufreq-v4-8-6cd63ade73d6@collabora.com> References: <20250923-mt8196-gpufreq-v4-0-6cd63ade73d6@collabora.com> In-Reply-To: <20250923-mt8196-gpufreq-v4-0-6cd63ade73d6@collabora.com> To: AngeloGioacchino Del Regno , Boris Brezillon , Jassi Brar , Chia-I Wu , Chen-Yu Tsai , Steven Price , Liviu Dudau , Maarten Lankhorst , Maxime Ripard , Thomas Zimmermann , David Airlie , Simona Vetter , Rob Herring , Krzysztof Kozlowski , Conor Dooley , Matthias Brugger , Kees Cook , "Gustavo A. R. Silva" , Ulf Hansson Cc: kernel@collabora.com, dri-devel@lists.freedesktop.org, devicetree@vger.kernel.org, linux-kernel@vger.kernel.org, linux-arm-kernel@lists.infradead.org, linux-mediatek@lists.infradead.org, linux-hardening@vger.kernel.org, linux-pm@vger.kernel.org, Nicolas Frattaroli X-Mailer: b4 0.14.2 Various MediaTek SoCs use GPU integration silicon named "MFlexGraphics" by MediaTek. On the MT8196 and MT6991 SoCs, interacting with this integration silicon is required to power on the GPU. This glue silicon is in the form of an embedded microcontroller running special-purpose firmware, which autonomously adjusts clocks and regulators. Implement a driver, modelled as a pmdomain driver with a set_performance_state operation, to support these SoCs. The driver also exposes the actual achieved clock rate, as read back from the MCU, as common clock framework clocks, by acting as a clock provider as well. Signed-off-by: Nicolas Frattaroli --- drivers/pmdomain/mediatek/Kconfig | 16 + drivers/pmdomain/mediatek/Makefile | 1 + drivers/pmdomain/mediatek/mtk-mfg-pmdomain.c | 928 +++++++++++++++++++++++= ++++ 3 files changed, 945 insertions(+) diff --git a/drivers/pmdomain/mediatek/Kconfig b/drivers/pmdomain/mediatek/= Kconfig index 0e34a517ab7d5a867bebaab11c0d866282a15e45..2abf78c85d017b1e3526b41c81f= 274f78d581fd0 100644 --- a/drivers/pmdomain/mediatek/Kconfig +++ b/drivers/pmdomain/mediatek/Kconfig @@ -26,6 +26,22 @@ config MTK_SCPSYS_PM_DOMAINS Control Processor System (SCPSYS) has several power management related tasks in the system. =20 +config MTK_MFG_PM_DOMAIN + tristate "MediaTek MFlexGraphics power domain" + default ARCH_MEDIATEK + depends on PM + depends on OF + depends on COMMON_CLK + select PM_GENERIC_DOMAINS + imply MTK_GPUEB_MBOX + help + Say y or m here to enable the power domains driver for MediaTek + MFlexGraphics. This driver allows for power and frequency control of + GPUs on MediaTek SoCs such as the MT8196 or MT6991. + + This driver is required for the Mali GPU to work at all on MT8196 and + MT6991. + config AIROHA_CPU_PM_DOMAIN tristate "Airoha CPU power domain" default ARCH_AIROHA diff --git a/drivers/pmdomain/mediatek/Makefile b/drivers/pmdomain/mediatek= /Makefile index 18ba92e3c418154e1d428dbc6b59b97b26056d98..b424f1ed867604393b3ff963648= 55363aedaa40c 100644 --- a/drivers/pmdomain/mediatek/Makefile +++ b/drivers/pmdomain/mediatek/Makefile @@ -1,4 +1,5 @@ # SPDX-License-Identifier: GPL-2.0-only +obj-$(CONFIG_MTK_MFG_PM_DOMAIN) +=3D mtk-mfg-pmdomain.o obj-$(CONFIG_MTK_SCPSYS) +=3D mtk-scpsys.o obj-$(CONFIG_MTK_SCPSYS_PM_DOMAINS) +=3D mtk-pm-domains.o obj-$(CONFIG_AIROHA_CPU_PM_DOMAIN) +=3D airoha-cpu-pmdomain.o diff --git a/drivers/pmdomain/mediatek/mtk-mfg-pmdomain.c b/drivers/pmdomai= n/mediatek/mtk-mfg-pmdomain.c new file mode 100644 index 0000000000000000000000000000000000000000..3148796a6b8aea9958c424f695e= fb7d8af23b7ce --- /dev/null +++ b/drivers/pmdomain/mediatek/mtk-mfg-pmdomain.c @@ -0,0 +1,928 @@ +// SPDX-License-Identifier: GPL-2.0-only +/* + * Driver for MediaTek MFlexGraphics Devices + * + * Copyright (C) 2025, Collabora Ltd. + */ + +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include + +#define GPR_LP_STATE 0x0028 +#define EB_ON_SUSPEND 0x0 +#define EB_ON_RESUME 0x1 +#define GPR_IPI_MAGIC 0x34 + +#define RPC_PWR_CON 0x0504 +#define PWR_ACK_M GENMASK(31, 30) +#define RPC_DUMMY_REG_2 0x0658 +#define RPC_GHPM_CFG0_CON 0x0800 +#define GHPM_ENABLE_M BIT(0) +#define GHPM_ON_SEQ_M BIT(2) +#define RPC_GHPM_RO0_CON 0x09A4 +#define GHPM_STATE_M GENMASK(7, 0) +#define GHPM_PWR_STATE_M BIT(16) + +#define GF_REG_MAGIC 0x0000 +#define GF_REG_GPU_OPP_IDX 0x0004 +#define GF_REG_STK_OPP_IDX 0x0008 +#define GF_REG_GPU_OPP_NUM 0x000c +#define GF_REG_STK_OPP_NUM 0x0010 +#define GF_REG_GPU_OPP_SNUM 0x0014 +#define GF_REG_STK_OPP_SNUM 0x0018 +#define GF_REG_POWER_COUNT 0x001c +#define GF_REG_BUCK_COUNT 0x0020 +#define GF_REG_MTCMOS_COUNT 0x0024 +#define GF_REG_CG_COUNT 0x0028 /* CG =3D Clock Gate? */ +#define GF_REG_ACTIVE_COUNT 0x002C +#define GF_REG_TEMP_RAW 0x0030 +#define GF_REG_TEMP_NORM_GPU 0x0034 +#define GF_REG_TEMP_HIGH_GPU 0x0038 +#define GF_REG_TEMP_NORM_STK 0x003C +#define GF_REG_TEMP_HIGH_STK 0x0040 +#define GF_REG_FREQ_CUR_GPU 0x0044 +#define GF_REG_FREQ_CUR_STK 0x0048 +#define GF_REG_FREQ_OUT_GPU 0x004C /* Guess: actual achieved freq */ +#define GF_REG_FREQ_OUT_STK 0x0050 /* Guess: actual achieved freq */ +#define GF_REG_FREQ_METER_GPU 0x0054 /* Seems unused, always 0 */ +#define GF_REG_FREQ_METER_STK 0x0058 /* Seems unused, always 0 */ +#define GF_REG_VOLT_CUR_GPU 0x005C /* in tens of microvolts */ +#define GF_REG_VOLT_CUR_STK 0x0060 /* in tens of microvolts */ +#define GF_REG_VOLT_CUR_GPU_SRAM 0x0064 +#define GF_REG_VOLT_CUR_STK_SRAM 0x0068 +#define GF_REG_VOLT_CUR_GPU_REG 0x006C /* Seems unused, always 0 */ +#define GF_REG_VOLT_CUR_STK_REG 0x0070 /* Seems unused, always 0 */ +#define GF_REG_VOLT_CUR_GPU_REG_SRAM 0x0074 +#define GF_REG_VOLT_CUR_STK_REG_SRAM 0x0078 +#define GF_REG_PWR_CUR_GPU 0x007C /* in milliwatts */ +#define GF_REG_PWR_CUR_STK 0x0080 /* in milliwatts */ +#define GF_REG_PWR_MAX_GPU 0x0084 /* in milliwatts */ +#define GF_REG_PWR_MAX_STK 0x0088 /* in milliwatts */ +#define GF_REG_PWR_MIN_GPU 0x008C /* in milliwatts */ +#define GF_REG_PWR_MIN_STK 0x0090 /* in milliwatts */ +#define GF_REG_LEAKAGE_RT_GPU 0x0094 /* Unknown */ +#define GF_REG_LEAKAGE_RT_STK 0x0098 /* Unknown */ +#define GF_REG_LEAKAGE_RT_SRAM 0x009C /* Unknown */ +#define GF_REG_LEAKAGE_HT_GPU 0x00A0 /* Unknown */ +#define GF_REG_LEAKAGE_HT_STK 0x00A4 /* Unknown */ +#define GF_REG_LEAKAGE_HT_SRAM 0x00A8 /* Unknown */ +#define GF_REG_VOLT_DAC_LOW_GPU 0x00AC /* Seems unused, always 0 */ +#define GF_REG_VOLT_DAC_LOW_STK 0x00B0 /* Seems unused, always 0 */ +#define GF_REG_OPP_CUR_CEIL 0x00B4 +#define GF_REG_OPP_CUR_FLOOR 0x00B8 +#define GF_REG_OPP_CUR_LIMITER_CEIL 0x00BC +#define GF_REG_OPP_CUR_LIMITER_FLOOR 0x00C0 +#define GF_REG_OPP_PRIORITY_CEIL 0x00C4 +#define GF_REG_OPP_PRIORITY_FLOOR 0x00C8 +#define GF_REG_PWR_CTL 0x00CC +#define GF_REG_ACTIVE_SLEEP_CTL 0x00D0 +#define GF_REG_DVFS_STATE 0x00D4 +#define GF_REG_SHADER_PRESENT 0x00D8 +#define GF_REG_ASENSOR_ENABLE 0x00DC +#define GF_REG_AGING_LOAD 0x00E0 +#define GF_REG_AGING_MARGIN 0x00E4 +#define GF_REG_AVS_ENABLE 0x00E8 +#define GF_REG_AVS_MARGIN 0x00EC +#define GF_REG_CHIP_TYPE 0x00F0 +#define GF_REG_SB_VERSION 0x00F4 +#define GF_REG_PTP_VERSION 0x00F8 +#define GF_REG_DBG_VERSION 0x00FC +#define GF_REG_KDBG_VERSION 0x0100 +#define GF_REG_GPM1_MODE 0x0104 +#define GF_REG_GPM3_MODE 0x0108 +#define GF_REG_DFD_MODE 0x010C +#define GF_REG_DUAL_BUCK 0x0110 +#define GF_REG_SEGMENT_ID 0x0114 +#define GF_REG_POWER_TIME_H 0x0118 +#define GF_REG_POWER_TIME_L 0x011C +#define GF_REG_PWR_STATUS 0x0120 +#define GF_REG_STRESS_TEST 0x0124 +#define GF_REG_TEST_MODE 0x0128 +#define GF_REG_IPS_MODE 0x012C +#define GF_REG_TEMP_COMP_MODE 0x0130 +#define GF_REG_HT_TEMP_COMP_MODE 0x0134 +#define GF_REG_PWR_TRACKER_MODE 0x0138 +#define GF_REG_OPP_TABLE_GPU 0x0314 +#define GF_REG_OPP_TABLE_STK 0x09A4 +#define GF_REG_OPP_TABLE_GPU_S 0x1034 +#define GF_REG_OPP_TABLE_STK_S 0x16c4 +#define GF_REG_LIMIT_TABLE 0x1d54 +#define GF_REG_GPM3_TABLE 0x223C + +#define MFG_MT8196_E2_ID 0x101 +#define GPUEB_SLEEP_MAGIC 0x55667788UL +#define GPUEB_SRAM_MAGIC 0xBABADADAUL + +#define GPUEB_TIMEOUT_US 10000UL +#define GPUEB_POLL_US 50 + +#define MAX_OPP_NUM 70 + +#define GPUEB_MBOX_MAX_RX_SIZE 32 /* in bytes */ + +/* + * This enum is part of the ABI of the GPUEB firmware. Don't change the + * numbering, as you would wreak havoc. + */ +enum mtk_mfg_ipi_cmd { + CMD_INIT_SHARED_MEM =3D 0, + CMD_GET_FREQ_BY_IDX =3D 1, + CMD_GET_POWER_BY_IDX =3D 2, + CMD_GET_OPPIDX_BY_FREQ =3D 3, + CMD_GET_LEAKAGE_POWER =3D 4, + CMD_SET_LIMIT =3D 5, + CMD_POWER_CONTROL =3D 6, + CMD_ACTIVE_SLEEP_CONTROL =3D 7, + CMD_COMMIT =3D 8, + CMD_DUAL_COMMIT =3D 9, + CMD_PDCA_CONFIG =3D 10, + CMD_UPDATE_DEBUG_OPP_INFO =3D 11, + CMD_SWITCH_LIMIT =3D 12, + CMD_FIX_TARGET_OPPIDX =3D 13, + CMD_FIX_DUAL_TARGET_OPPIDX =3D 14, + CMD_FIX_CUSTOM_FREQ_VOLT =3D 15, + CMD_FIX_DUAL_CUSTOM_FREQ_VOLT =3D 16, + CMD_SET_MFGSYS_CONFIG =3D 17, + CMD_MSSV_COMMIT =3D 18, + CMD_NUM =3D 19, +}; + +/* + * This struct is part of the ABI of the GPUEB firmware. Changing it, or + * reordering fields in it, will break things, so don't do it. Thank you. + */ +struct __packed mtk_mfg_ipi_msg { + __le32 magic; + __le32 cmd; + __le32 target; + /* + * Downstream relies on the compiler to implicitly add the following + * padding, as it declares the struct as non-packed. + */ + __le32 reserved; + union { + s32 __bitwise oppidx; + s32 __bitwise return_value; + __le32 freq; + __le32 volt; + __le32 power; + __le32 power_state; + __le32 mode; + __le32 value; + struct { + __le64 base; + __le32 size; + } shared_mem; + struct { + __le32 freq; + __le32 volt; + } custom; + struct { + __le32 limiter; + s32 __bitwise ceiling_info; + s32 __bitwise floor_info; + } set_limit; + struct { + __le32 target; + __le32 val; + } mfg_cfg; + struct { + __le32 target; + __le32 val; + } mssv; + struct { + s32 __bitwise gpu_oppidx; + s32 __bitwise stack_oppidx; + } dual_commit; + struct { + __le32 fgpu; + __le32 vgpu; + __le32 fstack; + __le32 vstack; + } dual_custom; + } u; +}; + +struct __packed mtk_mfg_ipi_sleep_msg { + __le32 event; + __le32 state; + __le32 magic; +}; + +/** + * struct mtk_mfg_opp_entry - OPP table entry from firmware + * @freq_khz: The operating point's frequency in kilohertz + * @voltage_core: The operating point's core voltage in tens of microvolts + * @voltage_sram: The operating point's SRAM voltage in tens of microvolts + * @posdiv: exponent of base 2 for PLL frequency divisor used for this OPP + * @voltage_margin: Number of tens of microvolts the voltage can be unders= hot + * @power_mw: estimate of power usage at this operating point, in milliwat= ts + * + * This struct is part of the ABI with the EB firmware. Do not change it. + */ +struct __packed mtk_mfg_opp_entry { + __le32 freq_khz; + __le32 voltage_core; + __le32 voltage_sram; + __le32 posdiv; + __le32 voltage_margin; + __le32 power_mw; +}; + +struct mtk_mfg_mbox { + struct mbox_client cl; + struct completion rx_done; + struct mtk_mfg *mfg; + struct mbox_chan *ch; + void *rx_data; +}; + +struct mtk_mfg { + struct generic_pm_domain pd; + struct platform_device *pdev; + struct clk *clk_eb; + struct clk_bulk_data *gpu_clks; + struct clk_hw clk_core_hw; + struct clk_hw clk_stack_hw; + struct regulator_bulk_data *gpu_regs; + void __iomem *rpc; + void __iomem *gpr; + void __iomem *sram; + phys_addr_t sram_phys; + unsigned int sram_size; + unsigned int ghpm_en_reg; + u32 ipi_magic; + unsigned int num_opps; + unsigned int num_unique_gpu_opps; + struct dev_pm_opp_data *gpu_opps; + struct mtk_mfg_mbox *gf_mbox; + struct mtk_mfg_mbox *slp_mbox; + int last_opp; + const struct mtk_mfg_variant *variant; +}; + +struct mtk_mfg_variant { + const char *const *clk_names; + unsigned int num_clks; + const char *const *regulator_names; + unsigned int num_regulators; + /** @turbo_below: opp indices below this value are considered turbo */ + unsigned int turbo_below; + int (*init)(struct mtk_mfg *mfg); +}; + +static inline struct mtk_mfg *mtk_mfg_from_genpd(struct generic_pm_domain = *pd) +{ + return container_of(pd, struct mtk_mfg, pd); +} + +static inline void mtk_mfg_update_reg_bits(void __iomem *addr, u32 mask, u= 32 val) +{ + writel((readl(addr) & ~mask) | (val & mask), addr); +} + +static unsigned long mtk_mfg_recalc_rate_gpu(struct clk_hw *hw, + unsigned long parent_rate) +{ + struct mtk_mfg *mfg =3D container_of(hw, struct mtk_mfg, clk_core_hw); + + return readl(mfg->sram + GF_REG_FREQ_OUT_GPU) * 1000UL; +} + +static unsigned long mtk_mfg_recalc_rate_stack(struct clk_hw *hw, + unsigned long parent_rate) +{ + struct mtk_mfg *mfg =3D container_of(hw, struct mtk_mfg, clk_stack_hw); + + return readl(mfg->sram + GF_REG_FREQ_OUT_STK) * 1000UL; +} + +static const struct clk_ops mtk_mfg_clk_gpu_ops =3D { + .recalc_rate =3D mtk_mfg_recalc_rate_gpu, +}; + +static const struct clk_ops mtk_mfg_clk_stack_ops =3D { + .recalc_rate =3D mtk_mfg_recalc_rate_stack, +}; + +static const struct clk_init_data mtk_mfg_clk_gpu_init =3D { + .name =3D "gpu-core", + .ops =3D &mtk_mfg_clk_gpu_ops, + .flags =3D CLK_GET_RATE_NOCACHE, +}; + +static const struct clk_init_data mtk_mfg_clk_stack_init =3D { + .name =3D "gpu-stack", + .ops =3D &mtk_mfg_clk_stack_ops, + .flags =3D CLK_GET_RATE_NOCACHE, +}; + +static int mtk_mfg_eb_on(struct mtk_mfg *mfg) +{ + struct device *dev =3D &mfg->pdev->dev; + u32 val; + int ret; + + /* + * If MFG is already on from e.g. the bootloader, we should skip doing + * the power-on sequence, as it wouldn't work without powering it off + * first. + */ + if ((readl(mfg->rpc + RPC_PWR_CON) & PWR_ACK_M) =3D=3D PWR_ACK_M) + return 0; + + ret =3D readl_poll_timeout(mfg->rpc + RPC_GHPM_RO0_CON, val, + !(val & (GHPM_PWR_STATE_M | GHPM_STATE_M)), + GPUEB_POLL_US, GPUEB_TIMEOUT_US); + if (ret) { + dev_err(dev, "timed out waiting for EB to power on\n"); + return ret; + } + + mtk_mfg_update_reg_bits(mfg->rpc + mfg->ghpm_en_reg, GHPM_ENABLE_M, + GHPM_ENABLE_M); + + mtk_mfg_update_reg_bits(mfg->rpc + RPC_GHPM_CFG0_CON, GHPM_ON_SEQ_M, 0); + mtk_mfg_update_reg_bits(mfg->rpc + RPC_GHPM_CFG0_CON, GHPM_ON_SEQ_M, + GHPM_ON_SEQ_M); + + mtk_mfg_update_reg_bits(mfg->rpc + mfg->ghpm_en_reg, GHPM_ENABLE_M, 0); + + + ret =3D readl_poll_timeout(mfg->rpc + RPC_PWR_CON, val, + (val & PWR_ACK_M) =3D=3D PWR_ACK_M, + GPUEB_POLL_US, GPUEB_TIMEOUT_US); + if (ret) { + dev_err(dev, "timed out waiting for EB power ack, val =3D 0x%X\n", + val); + return ret; + } + + ret =3D readl_poll_timeout(mfg->gpr + GPR_LP_STATE, val, + (val =3D=3D EB_ON_RESUME), + GPUEB_POLL_US, GPUEB_TIMEOUT_US); + if (ret) { + dev_err(dev, "timed out waiting for EB to resume, status =3D 0x%X\n", va= l); + return ret; + } + + return 0; +} + +static int mtk_mfg_eb_off(struct mtk_mfg *mfg) +{ + struct device *dev =3D &mfg->pdev->dev; + struct mtk_mfg_ipi_sleep_msg msg =3D { + .event =3D 0, + .state =3D 0, + .magic =3D GPUEB_SLEEP_MAGIC + }; + u32 val; + int ret; + + ret =3D mbox_send_message(mfg->slp_mbox->ch, &msg); + if (ret < 0) { + dev_err(dev, "Cannot send sleep command: %pe\n", ERR_PTR(ret)); + return ret; + } + + ret =3D readl_poll_timeout(mfg->rpc + RPC_PWR_CON, val, + !(val & PWR_ACK_M), GPUEB_POLL_US, + GPUEB_TIMEOUT_US); + + if (ret) + dev_err(dev, "timed out waiting for EB to power off, val=3D0x%08X\n", + val); + + return ret; +} + +static int mtk_mfg_send_ipi(struct mtk_mfg *mfg, struct mtk_mfg_ipi_msg *m= sg) +{ + struct device *dev =3D &mfg->pdev->dev; + unsigned long wait; + int ret; + + msg->magic =3D mfg->ipi_magic; + + ret =3D mbox_send_message(mfg->gf_mbox->ch, msg); + if (ret < 0) { + dev_err(dev, "Cannot send GPUFreq IPI command: %pe\n", ERR_PTR(ret)); + return ret; + } + + wait =3D wait_for_completion_timeout(&mfg->gf_mbox->rx_done, msecs_to_jif= fies(500)); + if (!wait) + return -ETIMEDOUT; + + msg =3D mfg->gf_mbox->rx_data; + + if (msg->u.return_value < 0) { + dev_err(dev, "IPI return: %d\n", msg->u.return_value); + return -EPROTO; + } + + return 0; +} + +static int mtk_mfg_init_shared_mem(struct mtk_mfg *mfg) +{ + struct device *dev =3D &mfg->pdev->dev; + struct mtk_mfg_ipi_msg msg =3D {}; + int ret; + + dev_dbg(dev, "clearing GPUEB sram, 0x%X bytes\n", mfg->sram_size); + memset_io(mfg->sram, 0, mfg->sram_size); + + msg.cmd =3D CMD_INIT_SHARED_MEM; + msg.u.shared_mem.base =3D mfg->sram_phys; + msg.u.shared_mem.size =3D mfg->sram_size; + + ret =3D mtk_mfg_send_ipi(mfg, &msg); + if (ret) + return ret; + + if (readl(mfg->sram) !=3D GPUEB_SRAM_MAGIC) { + dev_err(dev, "EB did not initialise SRAM correctly\n"); + return -EIO; + } + + return 0; +} + +static int mtk_mfg_power_control(struct mtk_mfg *mfg, bool enabled) +{ + struct mtk_mfg_ipi_msg msg =3D {}; + + msg.cmd =3D CMD_POWER_CONTROL; + msg.u.power_state =3D enabled ? 1 : 0; + + return mtk_mfg_send_ipi(mfg, &msg); +} + +static int mtk_mfg_set_oppidx(struct mtk_mfg *mfg, unsigned int opp_idx) +{ + struct mtk_mfg_ipi_msg msg =3D {}; + int ret; + + if (opp_idx >=3D mfg->num_opps) + return -EINVAL; + + if (mfg->last_opp =3D=3D opp_idx) + return 0; + + msg.cmd =3D CMD_FIX_TARGET_OPPIDX; + msg.u.oppidx =3D opp_idx; + + ret =3D mtk_mfg_send_ipi(mfg, &msg); + if (ret) { + dev_err(&mfg->pdev->dev, "Failed to set OPP %u: %pe\n", + opp_idx, ERR_PTR(ret)); + return ret; + } + + mfg->last_opp =3D opp_idx; + + return 0; +} + +static int mtk_mfg_read_opp_tables(struct mtk_mfg *mfg) +{ + struct device *dev =3D &mfg->pdev->dev; + struct mtk_mfg_opp_entry e =3D {}; + unsigned int i; + unsigned long long last_freq; + + mfg->num_opps =3D readl(mfg->sram + GF_REG_GPU_OPP_NUM); + + if (mfg->num_opps > MAX_OPP_NUM || mfg->num_opps =3D=3D 0) { + dev_err(dev, "OPP count (%u) out of range %u >=3D count > 0\n", + mfg->num_opps, MAX_OPP_NUM); + return -EINVAL; + } + + mfg->gpu_opps =3D devm_kcalloc(dev, mfg->num_opps, + sizeof(struct dev_pm_opp_data), GFP_KERNEL); + if (!mfg->gpu_opps) + return -ENOMEM; + + for (i =3D 0; i < mfg->num_opps; i++) { + memcpy_fromio(&e, mfg->sram + GF_REG_OPP_TABLE_GPU + i * sizeof(e), + sizeof(e)); + if (mem_is_zero(&e, sizeof(e))) { + dev_err(dev, "ran into an empty GPU OPP at index %u\n", + i); + return -EINVAL; + } + mfg->gpu_opps[i].freq =3D e.freq_khz * 1000ULL; + mfg->gpu_opps[i].u_volt =3D e.voltage_core * 10; + mfg->gpu_opps[i].level =3D i; + if (i < mfg->variant->turbo_below) + mfg->gpu_opps[i].turbo =3D true; + + if (!last_freq || mfg->gpu_opps[i].freq !=3D last_freq) + mfg->num_unique_gpu_opps++; + + last_freq =3D mfg->gpu_opps[i].freq; + } + + return 0; +} + +static const char *const mtk_mfg_mt8196_clk_names[] =3D { + "core", + "stack0", + "stack1", +}; + +static const char *const mtk_mfg_mt8196_regulators[] =3D { + "core", + "stack", + "sram", +}; + +static int mtk_mfg_mt8196_init(struct mtk_mfg *mfg) +{ + void __iomem *e2_base; + + e2_base =3D devm_platform_ioremap_resource_byname(mfg->pdev, "hw-revision= "); + if (IS_ERR(e2_base)) + return dev_err_probe(&mfg->pdev->dev, PTR_ERR(e2_base), + "Couldn't get hw-revision register\n"); + + if (readl(e2_base) =3D=3D MFG_MT8196_E2_ID) + mfg->ghpm_en_reg =3D RPC_DUMMY_REG_2; + else + mfg->ghpm_en_reg =3D RPC_GHPM_CFG0_CON; + + return 0; +}; + +static const struct mtk_mfg_variant mtk_mfg_mt8196_variant =3D { + .clk_names =3D mtk_mfg_mt8196_clk_names, + .num_clks =3D ARRAY_SIZE(mtk_mfg_mt8196_clk_names), + .regulator_names =3D mtk_mfg_mt8196_regulators, + .num_regulators =3D ARRAY_SIZE(mtk_mfg_mt8196_regulators), + .turbo_below =3D 7, + .init =3D mtk_mfg_mt8196_init, +}; + +static void mtk_mfg_mbox_rx_callback(struct mbox_client *cl, void *mssg) +{ + struct mtk_mfg_mbox *mb =3D container_of(cl, struct mtk_mfg_mbox, cl); + + if (mb->rx_data) + mb->rx_data =3D memcpy(mb->rx_data, mssg, GPUEB_MBOX_MAX_RX_SIZE); + complete(&mb->rx_done); +} + +static int mtk_mfg_attach_dev(struct generic_pm_domain *pd, struct device = *dev) +{ + struct mtk_mfg *mfg =3D mtk_mfg_from_genpd(pd); + struct dev_pm_opp_data *opps =3D mfg->gpu_opps; + int i, ret; + + for (i =3D mfg->num_opps - 1; i >=3D 0; i--) { + if ((i =3D=3D mfg->num_opps - 1) || (opps[i].freq !=3D opps[i + 1].freq)= ) { + ret =3D dev_pm_opp_add_dynamic(dev, &opps[i]); + if (ret) { + dev_err(dev, "Failed to add OPP level %u from PD %s\n", + opps[i].level, pd->name); + dev_pm_opp_remove_all_dynamic(dev); + return ret; + } + } + } + + return 0; +} + +static void mtk_mfg_detach_dev(struct generic_pm_domain *pd, struct device= *dev) +{ + dev_pm_opp_remove_all_dynamic(dev); +} + +static int mtk_mfg_set_performance(struct generic_pm_domain *pd, + unsigned int state) +{ + struct mtk_mfg *mfg =3D mtk_mfg_from_genpd(pd); + + /* + * Occasionally, we're asked to set OPPs when we're off. This will fail, + * so don't do it at all. We do foo !=3D GENPD_STATE_ON instead of !foo + * as to not depend on the actual value of the enum. + */ + if (mfg->pd.status !=3D GENPD_STATE_ON) + return 0; + + return mtk_mfg_set_oppidx(mfg, state); +} + +static int mtk_mfg_power_on(struct generic_pm_domain *pd) +{ + struct mtk_mfg *mfg =3D mtk_mfg_from_genpd(pd); + int ret; + + ret =3D regulator_bulk_enable(mfg->variant->num_regulators, + mfg->gpu_regs); + if (ret) + return ret; + + ret =3D clk_prepare_enable(mfg->clk_eb); + if (ret) + goto err_disable_regulators; + + ret =3D clk_bulk_prepare_enable(mfg->variant->num_clks, mfg->gpu_clks); + if (ret) + goto err_disable_eb_clk; + + ret =3D mtk_mfg_eb_on(mfg); + if (ret) + goto err_disable_clks; + + ret =3D mtk_mfg_power_control(mfg, true); + if (ret) + goto err_eb_off; + + return 0; + +err_eb_off: + mtk_mfg_eb_off(mfg); +err_disable_clks: + clk_bulk_disable_unprepare(mfg->variant->num_clks, mfg->gpu_clks); +err_disable_eb_clk: + clk_disable_unprepare(mfg->clk_eb); +err_disable_regulators: + regulator_bulk_disable(mfg->variant->num_regulators, mfg->gpu_regs); + + return ret; +} + +static int mtk_mfg_power_off(struct generic_pm_domain *pd) +{ + struct mtk_mfg *mfg =3D mtk_mfg_from_genpd(pd); + struct device *dev =3D &mfg->pdev->dev; + int ret; + + ret =3D mtk_mfg_power_control(mfg, false); + if (ret) { + dev_err(dev, "power_control failed: %pe\n", ERR_PTR(ret)); + return ret; + } + ret =3D mtk_mfg_eb_off(mfg); + if (ret) { + dev_err(dev, "eb_off failed: %pe\n", ERR_PTR(ret)); + return ret; + } + mfg->last_opp =3D -1; + clk_bulk_disable_unprepare(mfg->variant->num_clks, mfg->gpu_clks); + clk_disable_unprepare(mfg->clk_eb); + ret =3D regulator_bulk_disable(mfg->variant->num_regulators, mfg->gpu_reg= s); + + return ret; +} + +static int mtk_mfg_init_mbox(struct mtk_mfg *mfg) +{ + struct device *dev =3D &mfg->pdev->dev; + struct mtk_mfg_mbox *gf; + struct mtk_mfg_mbox *slp; + + gf =3D devm_kzalloc(dev, sizeof(*gf), GFP_KERNEL); + if (!gf) + return -ENOMEM; + + slp =3D devm_kzalloc(dev, sizeof(*slp), GFP_KERNEL); + if (!slp) + return -ENOMEM; + + gf->mfg =3D mfg; + init_completion(&gf->rx_done); + gf->cl.dev =3D dev; + gf->cl.rx_callback =3D mtk_mfg_mbox_rx_callback; + gf->cl.tx_tout =3D GPUEB_TIMEOUT_US / USEC_PER_MSEC; + gf->rx_data =3D devm_kzalloc(dev, GPUEB_MBOX_MAX_RX_SIZE, GFP_KERNEL); + if (!gf->rx_data) + return -ENOMEM; + gf->ch =3D mbox_request_channel_byname(&gf->cl, "gpufreq"); + if (IS_ERR(gf->ch)) + return PTR_ERR(gf->ch); + + mfg->gf_mbox =3D gf; + + slp->mfg =3D mfg; + init_completion(&slp->rx_done); + slp->cl.dev =3D dev; + slp->cl.tx_tout =3D GPUEB_TIMEOUT_US / USEC_PER_MSEC; + slp->cl.tx_block =3D true; + slp->ch =3D mbox_request_channel_byname(&slp->cl, "sleep"); + if (IS_ERR(slp->ch)) + return PTR_ERR(slp->ch); + + mfg->slp_mbox =3D slp; + + return 0; +} + +static int mtk_mfg_init_clk_provider(struct mtk_mfg *mfg) +{ + struct device *dev =3D &mfg->pdev->dev; + struct clk_hw_onecell_data *clk_data; + int ret; + + clk_data =3D devm_kzalloc(dev, struct_size(clk_data, hws, 2), GFP_KERNEL); + if (!clk_data) + return -ENOMEM; + + clk_data->num =3D 2; + + mfg->clk_core_hw.init =3D &mtk_mfg_clk_gpu_init; + mfg->clk_stack_hw.init =3D &mtk_mfg_clk_stack_init; + + ret =3D devm_clk_hw_register(dev, &mfg->clk_core_hw); + if (ret) + return dev_err_probe(dev, ret, "Couldn't register GPU core clock\n"); + + ret =3D devm_clk_hw_register(dev, &mfg->clk_stack_hw); + if (ret) + return dev_err_probe(dev, ret, "Couldn't register GPU stack clock\n"); + + clk_data->hws[0] =3D &mfg->clk_core_hw; + clk_data->hws[1] =3D &mfg->clk_stack_hw; + + ret =3D devm_of_clk_add_hw_provider(dev, of_clk_hw_onecell_get, clk_data); + if (ret) + return dev_err_probe(dev, ret, "Couldn't register clock provider\n"); + + return 0; +} + +static const struct of_device_id mtk_mfg_of_match[] =3D { + { .compatible =3D "mediatek,mt8196-gpufreq", .data =3D &mtk_mfg_mt8196_va= riant }, + {} +}; +MODULE_DEVICE_TABLE(of, mtk_mfg_of_match); + +static int mtk_mfg_probe(struct platform_device *pdev) +{ + struct device_node *shmem __free(device_node); + struct mtk_mfg *mfg; + struct device *dev =3D &pdev->dev; + const struct mtk_mfg_variant *data =3D of_device_get_match_data(dev); + struct resource res; + int ret, i; + + mfg =3D devm_kzalloc(dev, sizeof(*mfg), GFP_KERNEL); + if (!mfg) + return -ENOMEM; + + mfg->pdev =3D pdev; + mfg->variant =3D data; + + dev_set_drvdata(dev, mfg); + + mfg->gpr =3D devm_platform_ioremap_resource_byname(pdev, "gpr"); + if (IS_ERR(mfg->gpr)) + return dev_err_probe(dev, PTR_ERR(mfg->gpr), + "Could not retrieve GPR MMIO registers\n"); + + mfg->rpc =3D devm_platform_ioremap_resource_byname(pdev, "rpc"); + if (IS_ERR(mfg->rpc)) + return dev_err_probe(dev, PTR_ERR(mfg->rpc), + "Could not retrieve RPC MMIO registers\n"); + + mfg->clk_eb =3D devm_clk_get(dev, "eb"); + if (IS_ERR(mfg->clk_eb)) + return dev_err_probe(dev, PTR_ERR(mfg->clk_eb), + "Could not get 'eb' clock\n"); + + mfg->gpu_clks =3D devm_kcalloc(dev, data->num_clks, sizeof(*mfg->gpu_clks= ), + GFP_KERNEL); + if (!mfg->gpu_clks) + return -ENOMEM; + + for (i =3D 0; i < data->num_clks; i++) + mfg->gpu_clks[i].id =3D data->clk_names[i]; + + ret =3D devm_clk_bulk_get(dev, data->num_clks, mfg->gpu_clks); + if (ret) + return dev_err_probe(dev, ret, "couldn't get GPU clocks\n"); + + mfg->gpu_regs =3D devm_kcalloc(dev, data->num_regulators, + sizeof(*mfg->gpu_regs), GFP_KERNEL); + if (!mfg->gpu_regs) + return -ENOMEM; + + for (i =3D 0; i < data->num_regulators; i++) + mfg->gpu_regs[i].supply =3D data->regulator_names[i]; + + ret =3D devm_regulator_bulk_get(dev, data->num_regulators, mfg->gpu_regs); + if (ret) + return dev_err_probe(dev, ret, "couldn't get GPU regulators\n"); + + shmem =3D of_parse_phandle(dev->of_node, "shmem", 0); + if (!shmem) + return dev_err_probe(dev, -ENODEV, "Could not get 'shmem'\n"); + + ret =3D of_address_to_resource(shmem, 0, &res); + if (ret) + return dev_err_probe(dev, ret, + "failed to get GPUEB shared memory\n"); + + mfg->sram =3D devm_ioremap(dev, res.start, resource_size(&res)); + if (!mfg->sram) + return dev_err_probe(dev, -EADDRNOTAVAIL, + "failed to ioremap GPUEB sram\n"); + mfg->sram_size =3D resource_size(&res); + mfg->sram_phys =3D res.start; + + if (data->init) { + ret =3D data->init(mfg); + if (ret) + return dev_err_probe(dev, ret, "Variant init failed\n"); + } + + mfg->pd.name =3D dev_name(dev); + mfg->pd.attach_dev =3D mtk_mfg_attach_dev; + mfg->pd.detach_dev =3D mtk_mfg_detach_dev; + mfg->pd.power_off =3D mtk_mfg_power_off; + mfg->pd.power_on =3D mtk_mfg_power_on; + mfg->pd.set_performance_state =3D mtk_mfg_set_performance; + mfg->pd.flags =3D GENPD_FLAG_OPP_TABLE_FW; + pm_genpd_init(&mfg->pd, NULL, false); + + ret =3D clk_prepare_enable(mfg->clk_eb); + if (ret) + return dev_err_probe(dev, ret, "failed to turn on EB clock\n"); + mfg->ipi_magic =3D readl(mfg->gpr + GPR_IPI_MAGIC); + /* Downstream does this, don't know why. */ + writel(0x0, mfg->gpr + GPR_IPI_MAGIC); + + ret =3D mtk_mfg_init_mbox(mfg); + if (ret) { + ret =3D dev_err_probe(dev, ret, "Couldn't initialise mailbox\n"); + goto out; + } + + mfg->last_opp =3D -1; + + ret =3D mtk_mfg_power_on(&mfg->pd); + clk_disable_unprepare(mfg->clk_eb); + if (ret) + return dev_err_probe(dev, ret, "Failed to power on MFG\n"); + + ret =3D mtk_mfg_init_shared_mem(mfg); + if (ret) { + dev_err(dev, "Couldn't initialize EB SRAM: %pe\n", ERR_PTR(ret)); + goto out; + } + + ret =3D mtk_mfg_read_opp_tables(mfg); + if (ret) { + dev_err(dev, "Error reading OPP tables from EB: %pe\n", + ERR_PTR(ret)); + goto out; + } + + ret =3D mtk_mfg_init_clk_provider(mfg); + if (ret) + goto out; + + ret =3D of_genpd_add_provider_simple(pdev->dev.of_node, &mfg->pd); + if (ret) { + ret =3D dev_err_probe(dev, ret, "Failed to add pmdomain provider\n"); + goto out; + } + + return 0; + +out: + mtk_mfg_power_off(&mfg->pd); + return ret; +} + +static struct platform_driver mtk_mfg_driver =3D { + .driver =3D { + .name =3D "mtk-mfg-pmdomain", + .of_match_table =3D mtk_mfg_of_match, + }, + .probe =3D mtk_mfg_probe, +}; +module_platform_driver(mtk_mfg_driver); + +MODULE_AUTHOR("Nicolas Frattaroli "); +MODULE_DESCRIPTION("MediaTek MFlexGraphics Power Domain Driver"); +MODULE_LICENSE("GPL"); --=20 2.51.0