From nobody Thu Oct 2 06:14:58 2025 Received: from smtpout-04.galae.net (smtpout-04.galae.net [185.171.202.116]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id 06D6F2E7BAE; Mon, 22 Sep 2025 15:27:17 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=none smtp.client-ip=185.171.202.116 ARC-Seal: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1758554839; cv=none; b=Gwt28CV3v9JGWsbjj7JQdHDRWdCTEqANxloRJhk7QUdxvxa778VEr6OStGdPyW2+NMpv12GKTZmg4W9wVgC3t7FmGnRYDCRnNf6f2ZhlrmkVJrp3fwD1jCJiCWm5nJx+n3JoGZZN3Y8MpODQo4a/+3DeeEG9dqeed85MyAa5qj0= ARC-Message-Signature: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1758554839; c=relaxed/simple; bh=eilL7EMcxkFrk7yqkv5eRAaBBjlspJGLuN94fFROlHQ=; h=From:To:Cc:Subject:Date:Message-ID:In-Reply-To:References: MIME-Version; b=TMPH3QS9ikvrI+jgpsYG9P+Hd8EqKLyJ83iLZncY5hLJ8Gs1OTHwaGjXNM80GDtuWlkn0tOFcmEaUnOyF4/LdAYSVHughiHs7YO+QPTPjZcrgsF8B302hvtN4M0oNK9rspXYFNYtb2LLlF+gtNpxAfHqtJWQ3H3r3/qBx3xsQp0= ARC-Authentication-Results: i=1; smtp.subspace.kernel.org; dmarc=pass (p=reject dis=none) header.from=bootlin.com; spf=pass smtp.mailfrom=bootlin.com; dkim=pass (2048-bit key) header.d=bootlin.com header.i=@bootlin.com header.b=xY9gh6OL; arc=none smtp.client-ip=185.171.202.116 Authentication-Results: smtp.subspace.kernel.org; dmarc=pass (p=reject dis=none) header.from=bootlin.com Authentication-Results: smtp.subspace.kernel.org; spf=pass smtp.mailfrom=bootlin.com Authentication-Results: smtp.subspace.kernel.org; dkim=pass (2048-bit key) header.d=bootlin.com header.i=@bootlin.com header.b="xY9gh6OL" Received: from smtpout-01.galae.net (smtpout-01.galae.net [212.83.139.233]) by smtpout-04.galae.net (Postfix) with ESMTPS id 6C1CAC8EC47; Mon, 22 Sep 2025 15:26:59 +0000 (UTC) Received: from mail.galae.net (mail.galae.net [212.83.136.155]) by smtpout-01.galae.net (Postfix) with ESMTPS id 6D29060635; Mon, 22 Sep 2025 15:27:16 +0000 (UTC) Received: from [127.0.0.1] (localhost [127.0.0.1]) by localhost (Mailerdaemon) with ESMTPSA id 756B7102F1965; Mon, 22 Sep 2025 17:27:12 +0200 (CEST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=bootlin.com; s=dkim; t=1758554835; h=from:subject:date:message-id:to:cc:mime-version: content-transfer-encoding:in-reply-to:references; bh=tmBBrQpk6eRci8IPSFdygrTLGby6api2PRo6vkAg8M4=; b=xY9gh6OLGG5sTnftGqTr4AzWBr2eYzjc7zw5MKL02SGtIebpPHosTxy3Z+Xx3LohD+FUEu NY3Y/paHj6mspUkdYyzfDuSB3ESpt1gavJjt6wvi9Xi2U+wZdJts5+cllVEuEemFQDQGyV +3g5ICWUPAAeoZ3M/HA7MSKyBPXXCwO4csEYUtcycOl+ps6m2/CmxK3q3PscTsALPZX5sl G5q1kYiobnPr8ssFEGIVOCeq1P7iCjxz/WpOW8QxrmqaDImtrne8N+w3yB8dZzKuT8N8H+ jz69cZfn3FbtvdtwcQ9rkTdWroDWS1uihACzImgcCta4+/rySUMfbD0oZDowng== From: "Herve Codina (Schneider Electric)" To: Thomas Gleixner , Wolfram Sang , Hoan Tran , Linus Walleij , Bartosz Golaszewski , Rob Herring , Krzysztof Kozlowski , Conor Dooley , Geert Uytterhoeven , Magnus Damm , Saravana Kannan , Serge Semin , Herve Codina Cc: Phil Edworthy , linux-gpio@vger.kernel.org, devicetree@vger.kernel.org, linux-kernel@vger.kernel.org, linux-renesas-soc@vger.kernel.org, Pascal Eberhard , Miquel Raynal , Thomas Petazzoni Subject: [PATCH v4 8/8] ARM: dts: r9a06g032: Add support for GPIO interrupts Date: Mon, 22 Sep 2025 17:26:39 +0200 Message-ID: <20250922152640.154092-9-herve.codina@bootlin.com> X-Mailer: git-send-email 2.51.0 In-Reply-To: <20250922152640.154092-1-herve.codina@bootlin.com> References: <20250922152640.154092-1-herve.codina@bootlin.com> Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable X-Last-TLS-Session-Version: TLSv1.3 Content-Type: text/plain; charset="utf-8" In the RZ/N1 SoC, the GPIO interrupts are multiplexed using the GPIO Interrupt Multiplexer. Add the multiplexer node and connect GPIO interrupt lines to the multiplexer. The interrupt-map available in the multiplexer node has to be updated in dts files depending on the GPIO usage. Indeed, the usage of an interrupt for a GPIO is board dependent. Up to 8 GPIOs can be used as an interrupt line (one per multiplexer output interrupt). Signed-off-by: Herve Codina (Schneider Electric) Reviewed-by: Bartosz Golaszewski --- arch/arm/boot/dts/renesas/r9a06g032.dtsi | 43 ++++++++++++++++++++++++ 1 file changed, 43 insertions(+) diff --git a/arch/arm/boot/dts/renesas/r9a06g032.dtsi b/arch/arm/boot/dts/r= enesas/r9a06g032.dtsi index da977cdd8487..bd8160887091 100644 --- a/arch/arm/boot/dts/renesas/r9a06g032.dtsi +++ b/arch/arm/boot/dts/renesas/r9a06g032.dtsi @@ -534,6 +534,14 @@ gpio0a: gpio-port@0 { #gpio-cells =3D <2>; snps,nr-gpios =3D <32>; reg =3D <0>; + + interrupt-controller; + interrupt-parent =3D <&gpioirqmux>; + interrupts =3D < 0 1 2 3 4 5 6 7 + 8 9 10 11 12 13 14 15 + 16 17 18 19 20 21 22 23 + 24 25 26 27 28 29 30 31 >; + #interrupt-cells =3D <2>; }; =20 /* GPIO0b[0..1] connected to pins GPIO1..2 */ @@ -576,6 +584,14 @@ gpio1a: gpio-port@0 { #gpio-cells =3D <2>; snps,nr-gpios =3D <32>; reg =3D <0>; + + interrupt-controller; + interrupt-parent =3D <&gpioirqmux>; + interrupts =3D < 32 33 34 35 36 37 38 39 + 40 41 42 43 44 45 46 47 + 48 49 50 51 52 53 54 55 + 56 57 58 59 60 61 62 63 >; + #interrupt-cells =3D <2>; }; =20 /* GPIO1b[0..1] connected to pins GPIO55..56 */ @@ -608,6 +624,14 @@ gpio2a: gpio-port@0 { #gpio-cells =3D <2>; snps,nr-gpios =3D <32>; reg =3D <0>; + + interrupt-controller; + interrupt-parent =3D <&gpioirqmux>; + interrupts =3D < 64 65 66 67 68 69 70 71 + 72 73 74 75 76 77 78 79 + 80 81 82 83 84 85 86 87 + 88 89 90 91 92 93 94 95 >; + #interrupt-cells =3D <2>; }; =20 /* GPIO2b[0..9] connected to pins GPIO160..169 */ @@ -620,6 +644,25 @@ gpio2b: gpio-port@1 { }; }; =20 + gpioirqmux: interrupt-controller@51000480 { + compatible =3D "renesas,r9a06g032-gpioirqmux", "renesas,rzn1-gpioirqmux= "; + reg =3D <0x51000480 0x20>; + #interrupt-cells =3D <1>; + #address-cells =3D <0>; + interrupt-map-mask =3D <0x7f>; + + /* + * interrupt-map has to be updated according to GPIO + * usage. The src irq (0 field) has to be updated with + * the needed GPIO interrupt number. + * More items can be added (up to 8). Those items must + * define one GIC interrupt line among 103 to 110. + */ + interrupt-map =3D <0 &gic GIC_SPI 103 IRQ_TYPE_LEVEL_HIGH>; + + status =3D "disabled"; + }; + can0: can@52104000 { compatible =3D "renesas,r9a06g032-sja1000", "renesas,rzn1-sja1000"; reg =3D <0x52104000 0x800>; --=20 2.51.0