From nobody Thu Oct 2 04:49:34 2025 Received: from smtp.kernel.org (aws-us-west-2-korg-mail-1.web.codeaurora.org [10.30.226.201]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id 8567F1F8AC8; Mon, 22 Sep 2025 14:26:16 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=none smtp.client-ip=10.30.226.201 ARC-Seal: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1758551176; cv=none; b=d6dh7p7tddpseGQis1QTd4U9l+uCODQnkE9vpx2WnXeaUWT+j5EzFo4+IjHVBP31TDXvLu2eLA4MCy7KKxNEj9q/rF/DcupkDdIOuGL/63PlACTkAjul98XjHpPK0IGgmIGGorMAj6Lp/Tbd7tqO80r/H3GAu6HIpeP8vthJ8SM= ARC-Message-Signature: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1758551176; c=relaxed/simple; bh=CEK8yHPxJKhWjl3RH+TVpm29Wny+6IBKlzfazln71jo=; h=From:To:Cc:Subject:Date:Message-ID:MIME-Version; b=MCj6prvJptoNRmn+Lmm3GhRce3Vz49hPED9LpN9gK34qI/PolHyheQgyS1k0Kff+4ml3GtXRunUJyZIYir1y89j4fpIK8Feu2NQvGZErhCdkXkBVreyYorESi8zgZBfLsP8CrbntT74I1mPlqdprM/8beiMcW5szT8rJFF5+MoY= ARC-Authentication-Results: i=1; smtp.subspace.kernel.org; dkim=pass (2048-bit key) header.d=kernel.org header.i=@kernel.org header.b=n+6J3Ylk; arc=none smtp.client-ip=10.30.226.201 Authentication-Results: smtp.subspace.kernel.org; dkim=pass (2048-bit key) header.d=kernel.org header.i=@kernel.org header.b="n+6J3Ylk" Received: by smtp.kernel.org (Postfix) with ESMTPSA id 7BFC1C4CEF0; Mon, 22 Sep 2025 14:26:13 +0000 (UTC) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=kernel.org; s=k20201202; t=1758551176; bh=CEK8yHPxJKhWjl3RH+TVpm29Wny+6IBKlzfazln71jo=; h=From:To:Cc:Subject:Date:From; b=n+6J3YlkzS+dsKSUT5df0ZjUzucjalYcUGdQcyRUwxogpDUpe+d7y7RjK6MQCMNNB nwUgfy4ceEHu/0znn+stF8hwdhzHL3e3MXSUnHwq4Dv1h9jz0+Dq8G2R+5Z5+ZO1CN 0P4cpIqGlRbttm/xNQK0AIUT89fC7Qo6q06CfBTQk7enmhONfPKq14A1WmPgKXYNC5 p7HTBnd4+KMvUdPG4WN78zOXUzrzeNeLasVDPAqLfuFUdR5LQd6cITHaeILLsIYUEn lO+RjtVNYV6MJZWh87KxH5Uxk/E4vKe87ohb5Im1wW+Ot1TSvRD14PbxUms4bge3y0 LWoXby9vxGUkg== From: Lorenzo Pieralisi To: linux-kernel@vger.kernel.org Cc: linux-arm-kernel@lists.infradead.org, devicetree@vger.kernel.org, Sascha Bischoff , Thomas Gleixner , Rob Herring , Marc Zyngier Subject: [PATCH] irqchip/gic-v5: Add PCI bus msi-parent property handling Date: Mon, 22 Sep 2025 16:26:10 +0200 Message-ID: <20250922142610.80200-1-lpieralisi@kernel.org> X-Mailer: git-send-email 2.48.0 Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Content-Type: text/plain; charset="utf-8" In some legacy platforms the MSI controller for a PCI host bridge is identified by an msi-parent property whose phandle points at an MSI controller node with no #msi-cells property, that implicitly means #msi-cells =3D=3D 0. For such platforms, mapping a device ID and retrieving the MSI controller node becomes simply a matter of checking whether in the device hierarchy there is an msi-parent property pointing at an MSI controller node with such characteristics. Add a helper function to its_v5_pci_msi_prepare() to check the msi-parent property in addition to msi-map and retrieve the MSI controller node (with a 1:1 ID deviceID-IN<->deviceID-OUT mapping) to provide support for deviceID mapping and MSI controller node retrieval for such platforms. Fixes: 57d72196dfc8 ("irqchip/gic-v5: Add GICv5 ITS support") Signed-off-by: Lorenzo Pieralisi Cc: Sascha Bischoff Cc: Thomas Gleixner Cc: Rob Herring Cc: Marc Zyngier Tested-by: Sascha Bischoff --- Follow-up to [1] in that it is a fix and too risky to fix generic OF code at this stage of development since it might affect other platforms. Apply a fix to GIC ITS v5 MSI parent code - follow-up will clean up the msi-parent parsing in the kernel tree. [1] https://lore.kernel.org/lkml/20250916091858.257868-1-lpieralisi@kernel.= org/ drivers/irqchip/irq-gic-its-msi-parent.c | 34 ++++++++++++++++++++++-- 1 file changed, 32 insertions(+), 2 deletions(-) diff --git a/drivers/irqchip/irq-gic-its-msi-parent.c b/drivers/irqchip/irq= -gic-its-msi-parent.c index eb1473f1448a..198fb4e9a22d 100644 --- a/drivers/irqchip/irq-gic-its-msi-parent.c +++ b/drivers/irqchip/irq-gic-its-msi-parent.c @@ -101,6 +101,33 @@ static int its_pci_msi_prepare(struct irq_domain *doma= in, struct device *dev, return msi_info->ops->msi_prepare(domain->parent, dev, nvec, info); } =20 +static int its_v5_get_msi_parent(struct device *dev, struct device_node **= msi_np) +{ + struct of_phandle_args out_msi; + struct device *parent_dev; + int ret; + + /* + * Walk up the device parent links looking for one with a + * "msi-parent" property. + */ + for (parent_dev =3D dev; parent_dev; parent_dev =3D parent_dev->parent) { + ret =3D of_parse_phandle_with_optional_args(parent_dev->of_node, "msi-pa= rent", + "#msi-cells", + 0, &out_msi); + if (!ret) { + if (!out_msi.args_count) { + /* Return with a node reference held */ + *msi_np =3D out_msi.np; + return 0; + } + of_node_put(out_msi.np); + } + } + + return -ENODEV; +} + static int its_v5_pci_msi_prepare(struct irq_domain *domain, struct device= *dev, int nvec, msi_alloc_info_t *info) { @@ -117,8 +144,11 @@ static int its_v5_pci_msi_prepare(struct irq_domain *d= omain, struct device *dev, pdev =3D to_pci_dev(dev); =20 rid =3D pci_msi_map_rid_ctlr_node(pdev, &msi_node); - if (!msi_node) - return -ENODEV; + if (!msi_node) { + ret =3D its_v5_get_msi_parent(&pdev->dev, &msi_node); + if (ret) + return ret; + } =20 ret =3D its_translate_frame_address(msi_node, &pa); if (ret) --=20 2.48.0