From nobody Thu Oct 2 06:29:52 2025 Received: from smtp.kernel.org (aws-us-west-2-korg-mail-1.web.codeaurora.org [10.30.226.201]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id 0D2C93054F8; Mon, 22 Sep 2025 08:28:51 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=none smtp.client-ip=10.30.226.201 ARC-Seal: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1758529731; cv=none; b=E+V4VsRU/Bbd+wzH65TaLNs8Dkcp9j2QohOHCDiIqPwvcBVWchgwTszpBItXYhXZl4LfEkrhFFkoo8Ttxv8hCKUpYo4eJuuv/cEEezfvxxiWNp1dSdncr+kzLftrCNQk6VqxZFhAbKD5Gt5T3HUPmgMaYJUkFA2U3IStH20mTro= ARC-Message-Signature: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1758529731; c=relaxed/simple; bh=tS9i8aN1hYglqnYWNWW11cQTPh7t9Qg/dLKIcWSR4ZQ=; h=From:To:Cc:Subject:Date:Message-ID:In-Reply-To:References: MIME-Version; b=op1drhDtGPXTUT4q+T53HVTxj9qOBFmA7QUihp5b3PdBWZgx1a9NSEjuzFRdNAdl6r6EcfEmBQ3mAtJEJXPmFHvQTSUGMrVqtpTnRhboBNL1IpG8NLSBUkj2tjqaNe4Srb9ZGeqa0eXl9BK0+8ffcLEfEnnOjLbd5FwrYyo7WXQ= ARC-Authentication-Results: i=1; smtp.subspace.kernel.org; dkim=pass (2048-bit key) header.d=kernel.org header.i=@kernel.org header.b=lHJ5PRh7; arc=none smtp.client-ip=10.30.226.201 Authentication-Results: smtp.subspace.kernel.org; dkim=pass (2048-bit key) header.d=kernel.org header.i=@kernel.org header.b="lHJ5PRh7" Received: by smtp.kernel.org (Postfix) with ESMTPSA id E17C8C4CEF5; Mon, 22 Sep 2025 08:28:50 +0000 (UTC) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=kernel.org; s=k20201202; t=1758529730; bh=tS9i8aN1hYglqnYWNWW11cQTPh7t9Qg/dLKIcWSR4ZQ=; h=From:To:Cc:Subject:Date:In-Reply-To:References:From; b=lHJ5PRh7Ux8PJQOWAn4d/Lp9A0Hs+pg/NiaxkK9RMYJSmj/+imhD4Q0cMEnZS78FZ ODJdeKP3XzYggV8qOadOgH9Ptig2AU9AmrHhj9utUUHaylwa14n3iluhWrDz38hRGu uu1Pzk1gs8lhfrUPoYllNnBLk08KqZSrp0HZq5OSI432QwC/xUngD6dW8swhNrfPHc EzUbYqoFv0t5WCO2EWh/auYx2KvUjdBjR1wBeWg2m+nb3KKi4AZ6Tyq/itLJ27PLZx mabvJuICtlbgpb4doshTGd9lFb72qHAMDZhFbmpBlpuT9k2NNGmMe+jAHe9+OJ9ZI3 ibdwEi+0QoNNg== Received: from sofa.misterjones.org ([185.219.108.64] helo=valley-girl.lan) by disco-boy.misterjones.org with esmtpsa (TLS1.3) tls TLS_ECDHE_RSA_WITH_AES_256_GCM_SHA384 (Exim 4.98.2) (envelope-from ) id 1v0buj-00000008Kds-0Thb; Mon, 22 Sep 2025 08:28:49 +0000 From: Marc Zyngier To: linux-kernel@vger.kernel.org, linux-arm-kernel@lists.infradead.org, linux-acpi@vger.kernel.org Cc: Thomas Gleixner , Mark Rutland , Will Deacon , "Rafael J. Wysocki" , Rob Herring , Saravana Kannan , Greg Kroah-Hartman , Sven Peter , Janne Grunau , Suzuki K Poulose , James Clark , Jonathan Cameron Subject: [PATCH v3 26/26] perf: arm_pmu: Kill last use of per-CPU cpu_armpmu pointer Date: Mon, 22 Sep 2025 09:28:33 +0100 Message-ID: <20250922082833.2038905-27-maz@kernel.org> X-Mailer: git-send-email 2.47.3 In-Reply-To: <20250922082833.2038905-1-maz@kernel.org> References: <20250922082833.2038905-1-maz@kernel.org> Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable X-SA-Exim-Connect-IP: 185.219.108.64 X-SA-Exim-Rcpt-To: linux-kernel@vger.kernel.org, linux-arm-kernel@lists.infradead.org, linux-acpi@vger.kernel.org, tglx@linutronix.de, mark.rutland@arm.com, will@kernel.org, rafael@kernel.org, robh@kernel.org, saravanak@google.com, gregkh@linuxfoundation.org, sven@kernel.org, j@jannau.net, suzuki.poulose@arm.com, james.clark@linaro.org, jonathan.cameron@huawei.com X-SA-Exim-Mail-From: maz@kernel.org X-SA-Exim-Scanned: No (on disco-boy.misterjones.org); SAEximRunCond expanded to false Content-Type: text/plain; charset="utf-8" Having removed the use of the cpu_armpmu per-CPU variable from the interrupt handling, the only user left is the BRBE scheduler hook. It is easy to drop the use of this variable by following the pointer to the generic PMU structure, and get the arm_pmu structure from there. Perform the conversion and kill cpu_armpmu altogether. Suggested-by: Will Deacon Signed-off-by: Marc Zyngier --- drivers/perf/arm_pmu.c | 5 ----- drivers/perf/arm_pmuv3.c | 2 +- include/linux/perf/arm_pmu.h | 2 -- 3 files changed, 1 insertion(+), 8 deletions(-) diff --git a/drivers/perf/arm_pmu.c b/drivers/perf/arm_pmu.c index 959ceb3d1f556..f7abd13339630 100644 --- a/drivers/perf/arm_pmu.c +++ b/drivers/perf/arm_pmu.c @@ -104,7 +104,6 @@ static const struct pmu_irq_ops percpu_pmunmi_ops =3D { .free_pmuirq =3D armpmu_free_percpu_pmunmi }; =20 -DEFINE_PER_CPU(struct arm_pmu *, cpu_armpmu); static DEFINE_PER_CPU(int, cpu_irq); static DEFINE_PER_CPU(const struct pmu_irq_ops *, cpu_irq_ops); =20 @@ -725,8 +724,6 @@ static int arm_perf_starting_cpu(unsigned int cpu, stru= ct hlist_node *node) if (pmu->reset) pmu->reset(pmu); =20 - per_cpu(cpu_armpmu, cpu) =3D pmu; - irq =3D armpmu_get_cpu_irq(pmu, cpu); if (irq) per_cpu(cpu_irq_ops, cpu)->enable_pmuirq(irq); @@ -746,8 +743,6 @@ static int arm_perf_teardown_cpu(unsigned int cpu, stru= ct hlist_node *node) if (irq) per_cpu(cpu_irq_ops, cpu)->disable_pmuirq(irq); =20 - per_cpu(cpu_armpmu, cpu) =3D NULL; - return 0; } =20 diff --git a/drivers/perf/arm_pmuv3.c b/drivers/perf/arm_pmuv3.c index f6d7bab5d555c..2dee2d928aaef 100644 --- a/drivers/perf/arm_pmuv3.c +++ b/drivers/perf/arm_pmuv3.c @@ -1039,7 +1039,7 @@ static int armv8pmu_user_event_idx(struct perf_event = *event) static void armv8pmu_sched_task(struct perf_event_pmu_context *pmu_ctx, struct task_struct *task, bool sched_in) { - struct arm_pmu *armpmu =3D *this_cpu_ptr(&cpu_armpmu); + struct arm_pmu *armpmu =3D to_arm_pmu(pmu_ctx->pmu); struct pmu_hw_events *hw_events =3D this_cpu_ptr(armpmu->hw_events); =20 if (!hw_events->branch_users) diff --git a/include/linux/perf/arm_pmu.h b/include/linux/perf/arm_pmu.h index 6690bd77aa4ee..bab26a7d79f4c 100644 --- a/include/linux/perf/arm_pmu.h +++ b/include/linux/perf/arm_pmu.h @@ -132,8 +132,6 @@ struct arm_pmu { =20 #define to_arm_pmu(p) (container_of(p, struct arm_pmu, pmu)) =20 -DECLARE_PER_CPU(struct arm_pmu *, cpu_armpmu); - u64 armpmu_event_update(struct perf_event *event); =20 int armpmu_event_set_period(struct perf_event *event); --=20 2.47.3