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charset="utf-8" Update the HAMOA-IOT-SOM device tree to enable PCIe 3 support. Add perst wake and clkreq sideband signals and required regulators in PCIe3 controller and PHY device tree node. Signed-off-by: Ziyue Zhang --- arch/arm64/boot/dts/qcom/hamoa-iot-som.dtsi | 70 +++++++++++++++++++++ 1 file changed, 70 insertions(+) diff --git a/arch/arm64/boot/dts/qcom/hamoa-iot-som.dtsi b/arch/arm64/boot/= dts/qcom/hamoa-iot-som.dtsi index 0c8ae34c1f37..7486204a4a46 100644 --- a/arch/arm64/boot/dts/qcom/hamoa-iot-som.dtsi +++ b/arch/arm64/boot/dts/qcom/hamoa-iot-som.dtsi @@ -390,6 +390,53 @@ &gpu_zap_shader { firmware-name =3D "qcom/x1e80100/gen70500_zap.mbn"; }; =20 +&pm8550ve_8_gpios { + pcie_x8_12v: pcie-12v-default-state { + pins =3D "gpio8"; + function =3D "normal"; + output-enable; + output-high; + bias-pull-down; + power-source =3D <0>; + }; +}; + +&pmc8380_3_gpios { + pm_sde7_aux_3p3_en: pcie-aux-3p3-default-state { + pins =3D "gpio8"; + function =3D "normal"; + output-enable; + output-high; + bias-pull-down; + power-source =3D <0>; + }; + + pm_sde7_main_3p3_en: pcie-main-3p3-default-state { + pins =3D "gpio6"; + function =3D "normal"; + output-enable; + output-high; + bias-pull-down; + power-source =3D <0>; + }; +}; + +&pcie3 { + pinctrl-names =3D "default"; + pinctrl-0 =3D <&pcie3_default>; + perst-gpios =3D <&tlmm 143 GPIO_ACTIVE_LOW>; + wake-gpios =3D <&tlmm 145 GPIO_ACTIVE_LOW>; + + status =3D "okay"; +}; + +&pcie3_phy { + vdda-phy-supply =3D <&vreg_l3c_0p8>; + vdda-pll-supply =3D <&vreg_l3e_1p2>; + + status =3D "okay"; +}; + &pcie4 { perst-gpios =3D <&tlmm 146 GPIO_ACTIVE_LOW>; wake-gpios =3D <&tlmm 148 GPIO_ACTIVE_LOW>; @@ -471,6 +518,29 @@ &tlmm { gpio-reserved-ranges =3D <34 2>, /* TPM LP & INT */ <44 4>; /* SPI (TPM) */ =20 + pcie3_default: pcie3-default-state { + clkreq-n-pins { + pins =3D "gpio144"; + function =3D "pcie3_clk"; + drive-strength =3D <2>; + bias-pull-up; + }; + + perst-n-pins { + pins =3D "gpio143"; + function =3D "gpio"; + drive-strength =3D <2>; + bias-pull-down; + }; + + wake-n-pins { + pins =3D "gpio145"; + function =3D "gpio"; + drive-strength =3D <2>; + bias-pull-up; + }; + }; + pcie4_default: pcie4-default-state { clkreq-n-pins { pins =3D "gpio147"; --=20 2.34.1