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charset="utf-8" Update the HAMOA-IOT-SOM device tree to enable PCIe 5 support. Add perst wake and clkreq sideband signals and required regulators in PCIe5 controller and PHY device tree node. Signed-off-by: Ziyue Zhang --- arch/arm64/boot/dts/qcom/hamoa-iot-som.dtsi | 40 +++++++++++++++++++++ 1 file changed, 40 insertions(+) diff --git a/arch/arm64/boot/dts/qcom/hamoa-iot-som.dtsi b/arch/arm64/boot/= dts/qcom/hamoa-iot-som.dtsi index 1aead50b8920..0c8ae34c1f37 100644 --- a/arch/arm64/boot/dts/qcom/hamoa-iot-som.dtsi +++ b/arch/arm64/boot/dts/qcom/hamoa-iot-som.dtsi @@ -407,6 +407,23 @@ &pcie4_phy { status =3D "okay"; }; =20 +&pcie5 { + perst-gpios =3D <&tlmm 149 GPIO_ACTIVE_LOW>; + wake-gpios =3D <&tlmm 151 GPIO_ACTIVE_LOW>; + + pinctrl-0 =3D <&pcie5_default>; + pinctrl-names =3D "default"; + + status =3D "okay"; +}; + +&pcie5_phy { + vdda-phy-supply =3D <&vreg_l3i_0p8>; + vdda-pll-supply =3D <&vreg_l3e_1p2>; + + status =3D "okay"; +}; + &pcie6a { perst-gpios =3D <&tlmm 152 GPIO_ACTIVE_LOW>; wake-gpios =3D <&tlmm 154 GPIO_ACTIVE_LOW>; @@ -477,6 +494,29 @@ wake-n-pins { }; }; =20 + pcie5_default: pcie5-default-state { + clkreq-n-pins { + pins =3D "gpio150"; + function =3D "pcie5_clk"; + drive-strength =3D <2>; + bias-pull-up; + }; + + perst-n-pins { + pins =3D "gpio149"; + function =3D "gpio"; + drive-strength =3D <2>; + bias-disable; + }; + + wake-n-pins { + pins =3D "gpio151"; + function =3D "gpio"; + drive-strength =3D <2>; + bias-pull-up; + }; + }; + pcie6a_default: pcie6a-default-state { clkreq-n-pins { pins =3D "gpio153"; --=20 2.34.1 From nobody Thu Oct 2 05:03:33 2025 Received: from mx0b-0031df01.pphosted.com (mx0b-0031df01.pphosted.com [205.220.180.131]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id BA77D2F83C4; Mon, 22 Sep 2025 07:55:32 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=none smtp.client-ip=205.220.180.131 ARC-Seal: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1758527734; cv=none; b=aUj2vfzzuK9Ugg9hU0FdbFWQiSNIR/i3GQ/LyJHHkzAYZWcKl5YPinmdCAQOAyv8qxEwNE6jjV0tMqbAgyIZVSPmVd3VJ/9tp/WL0ln7A4rU8IUzMLH3nnFsy2QxMRH94OLSiK+QZBemTTIQw3ZmmTgfmxW485qg83SAuLKwUQE= ARC-Message-Signature: i=1; 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charset="utf-8" Specify the vddpe-3v3-supply regulator for PCIe5 using &vreg_wwan to ensure proper power configuration. Signed-off-by: Ziyue Zhang --- arch/arm64/boot/dts/qcom/hamoa-iot-evk.dts | 4 ++++ 1 file changed, 4 insertions(+) diff --git a/arch/arm64/boot/dts/qcom/hamoa-iot-evk.dts b/arch/arm64/boot/d= ts/qcom/hamoa-iot-evk.dts index df8d6e5c1f45..f0e4abbcc1ac 100644 --- a/arch/arm64/boot/dts/qcom/hamoa-iot-evk.dts +++ b/arch/arm64/boot/dts/qcom/hamoa-iot-evk.dts @@ -832,6 +832,10 @@ &mdss_dp3_phy { status =3D "okay"; }; =20 +&pcie5 { + vddpe-3v3-supply =3D <&vreg_wwan>; +}; + &pcie6a { vddpe-3v3-supply =3D <&vreg_nvme>; }; --=20 2.34.1 From nobody Thu Oct 2 05:03:33 2025 Received: from mx0b-0031df01.pphosted.com (mx0b-0031df01.pphosted.com [205.220.180.131]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id 043032F7AA1; Mon, 22 Sep 2025 07:55:37 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=none smtp.client-ip=205.220.180.131 ARC-Seal: i=1; a=rsa-sha256; d=subspace.kernel.org; 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charset="utf-8" Update the HAMOA-IOT-SOM device tree to enable PCIe 3 support. Add perst wake and clkreq sideband signals and required regulators in PCIe3 controller and PHY device tree node. Signed-off-by: Ziyue Zhang --- arch/arm64/boot/dts/qcom/hamoa-iot-som.dtsi | 70 +++++++++++++++++++++ 1 file changed, 70 insertions(+) diff --git a/arch/arm64/boot/dts/qcom/hamoa-iot-som.dtsi b/arch/arm64/boot/= dts/qcom/hamoa-iot-som.dtsi index 0c8ae34c1f37..7486204a4a46 100644 --- a/arch/arm64/boot/dts/qcom/hamoa-iot-som.dtsi +++ b/arch/arm64/boot/dts/qcom/hamoa-iot-som.dtsi @@ -390,6 +390,53 @@ &gpu_zap_shader { firmware-name =3D "qcom/x1e80100/gen70500_zap.mbn"; }; =20 +&pm8550ve_8_gpios { + pcie_x8_12v: pcie-12v-default-state { + pins =3D "gpio8"; + function =3D "normal"; + output-enable; + output-high; + bias-pull-down; + power-source =3D <0>; + }; +}; + +&pmc8380_3_gpios { + pm_sde7_aux_3p3_en: pcie-aux-3p3-default-state { + pins =3D "gpio8"; + function =3D "normal"; + output-enable; + output-high; + bias-pull-down; + power-source =3D <0>; + }; + + pm_sde7_main_3p3_en: pcie-main-3p3-default-state { + pins =3D "gpio6"; + function =3D "normal"; + output-enable; + output-high; + bias-pull-down; + power-source =3D <0>; + }; +}; + +&pcie3 { + pinctrl-names =3D "default"; + pinctrl-0 =3D <&pcie3_default>; + perst-gpios =3D <&tlmm 143 GPIO_ACTIVE_LOW>; + wake-gpios =3D <&tlmm 145 GPIO_ACTIVE_LOW>; + + status =3D "okay"; +}; + +&pcie3_phy { + vdda-phy-supply =3D <&vreg_l3c_0p8>; + vdda-pll-supply =3D <&vreg_l3e_1p2>; + + status =3D "okay"; +}; + &pcie4 { perst-gpios =3D <&tlmm 146 GPIO_ACTIVE_LOW>; wake-gpios =3D <&tlmm 148 GPIO_ACTIVE_LOW>; @@ -471,6 +518,29 @@ &tlmm { gpio-reserved-ranges =3D <34 2>, /* TPM LP & INT */ <44 4>; /* SPI (TPM) */ =20 + pcie3_default: pcie3-default-state { + clkreq-n-pins { + pins =3D "gpio144"; + function =3D "pcie3_clk"; + drive-strength =3D <2>; + bias-pull-up; + }; + + perst-n-pins { + pins =3D "gpio143"; + function =3D "gpio"; + drive-strength =3D <2>; + bias-pull-down; + }; + + wake-n-pins { + pins =3D "gpio145"; + function =3D "gpio"; + drive-strength =3D <2>; + bias-pull-up; + }; + }; + pcie4_default: pcie4-default-state { clkreq-n-pins { pins =3D "gpio147"; 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Mon, 22 Sep 2025 07:55:18 +0000 (GMT) Received: from pps.filterd (APTAIPPMTA02.qualcomm.com [127.0.0.1]) by APTAIPPMTA02.qualcomm.com (8.18.1.2/8.18.1.2) with ESMTP id 58M7tGKv022236; Mon, 22 Sep 2025 07:55:16 GMT Received: from pps.reinject (localhost [127.0.0.1]) by APTAIPPMTA02.qualcomm.com (PPS) with ESMTPS id 499nbm0544-1 (version=TLSv1.2 cipher=ECDHE-RSA-AES256-GCM-SHA384 bits=256 verify=NOT); Mon, 22 Sep 2025 07:55:16 +0000 Received: from APTAIPPMTA02.qualcomm.com (APTAIPPMTA02.qualcomm.com [127.0.0.1]) by pps.reinject (8.17.1.5/8.17.1.5) with ESMTP id 58M7tGWr022219; Mon, 22 Sep 2025 07:55:16 GMT Received: from cse-cd02-lnx.ap.qualcomm.com (cse-cd02-lnx.qualcomm.com [10.64.75.246]) by APTAIPPMTA02.qualcomm.com (PPS) with ESMTPS id 58M7tFNA022211 (version=TLSv1.2 cipher=ECDHE-RSA-AES256-GCM-SHA384 bits=256 verify=NOT); Mon, 22 Sep 2025 07:55:16 +0000 Received: by cse-cd02-lnx.ap.qualcomm.com (Postfix, from userid 4438065) id 94A51B75; Mon, 22 Sep 2025 15:55:14 +0800 (CST) From: Ziyue Zhang To: andersson@kernel.org, konradybcio@kernel.org, robh@kernel.org, krzk+dt@kernel.org, conor+dt@kernel.org, jingoohan1@gmail.com, mani@kernel.org, lpieralisi@kernel.org, kwilczynski@kernel.org, bhelgaas@google.com, johan+linaro@kernel.org, vkoul@kernel.org, kishon@kernel.org, neil.armstrong@linaro.org, abel.vesa@linaro.org, kw@linux.com Cc: linux-arm-msm@vger.kernel.org, devicetree@vger.kernel.org, linux-kernel@vger.kernel.org, linux-pci@vger.kernel.org, linux-phy@lists.infradead.org, qiang.yu@oss.qualcomm.com, quic_krichai@quicinc.com, quic_vbadigan@quicinc.com, Ziyue Zhang Subject: [PATCH v1 4/4] arm64: dts: qcom: Add PCIe 3 regulators for HAMOA-IOT-EVK board Date: Mon, 22 Sep 2025 15:55:09 +0800 Message-Id: <20250922075509.3288419-5-ziyue.zhang@oss.qualcomm.com> X-Mailer: git-send-email 2.34.1 In-Reply-To: <20250922075509.3288419-1-ziyue.zhang@oss.qualcomm.com> References: <20250922075509.3288419-1-ziyue.zhang@oss.qualcomm.com> Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable X-QCInternal: smtphost X-QCInternal: smtphost X-Proofpoint-Virus-Version: vendor=nai engine=6200 definitions=5800 signatures=585085 X-Proofpoint-Virus-Version: vendor=nai engine=6200 definitions=5800 signatures=585085 X-Proofpoint-ORIG-GUID: aBUZXnnV_fE_VZYTCwY3WSSvAYgy6VeK X-Proofpoint-GUID: aBUZXnnV_fE_VZYTCwY3WSSvAYgy6VeK X-Authority-Analysis: v=2.4 cv=No/Rc9dJ c=1 sm=1 tr=0 ts=68d100e6 cx=c_pps a=nuhDOHQX5FNHPW3J6Bj6AA==:117 a=nuhDOHQX5FNHPW3J6Bj6AA==:17 a=yJojWOMRYYMA:10 a=EUspDBNiAAAA:8 a=XGVIsFbTfmVoesHaU64A:9 X-Proofpoint-Spam-Details-Enc: AW1haW4tMjUwOTIwMDAzNyBTYWx0ZWRfX8E4vrbO/8oDx FNvruL/3cP+CPAtbd0ywJLsjSn8afhCbeK7UvKaWe7/P4T9kgtrPmxAEDzkWNlzA762KeUtwH9Q WbLdknkYrNgyULr5YrTZFr+KSvgycVJkClynLGhv+KnuzJm8yziTUNQZ+PE29lYDm2vWu+H4ah9 1QgIS6lE5TjqwCu8RedFog9gOQBzjUc7ZP468QbM+8NrjLw12VLT03VTNo0RA3tiWj+pMh2WM/4 95s+MhWamuhuo8szwNo2GnQeE2i9qxCUJYMmq5oNajo0f302OkUSbvuEtP+SYIcUwwV61oFWwHx LrYQ1HRL20LIuB3TACYfZUlKiATiICv15wfw2YK+/qkrTS/QUq4rLIV5oXTole19aFst641Vlvz EkVKgsK7 X-Proofpoint-Virus-Version: vendor=baseguard engine=ICAP:2.0.293,Aquarius:18.0.1117,Hydra:6.1.9,FMLib:17.12.80.40 definitions=2025-09-22_01,2025-09-19_01,2025-03-28_01 X-Proofpoint-Spam-Details: rule=outbound_notspam policy=outbound score=0 clxscore=1015 spamscore=0 suspectscore=0 adultscore=0 malwarescore=0 phishscore=0 bulkscore=0 priorityscore=1501 impostorscore=0 classifier=typeunknown authscore=0 authtc= authcc= route=outbound adjust=0 reason=mlx scancount=1 engine=8.19.0-2507300000 definitions=main-2509200037 Content-Type: text/plain; charset="utf-8" Specify the vddpe-3v3-supply regulator for PCIe3 using &vreg_wwan to ensure proper power configuration.Describe the voltage rails of the x8 PCI slots for PCIe3 port. Signed-off-by: Ziyue Zhang --- arch/arm64/boot/dts/qcom/hamoa-iot-evk.dts | 48 ++++++++++++++++++++++ 1 file changed, 48 insertions(+) diff --git a/arch/arm64/boot/dts/qcom/hamoa-iot-evk.dts b/arch/arm64/boot/d= ts/qcom/hamoa-iot-evk.dts index f0e4abbcc1ac..0eb85d6cf4e9 100644 --- a/arch/arm64/boot/dts/qcom/hamoa-iot-evk.dts +++ b/arch/arm64/boot/dts/qcom/hamoa-iot-evk.dts @@ -414,6 +414,48 @@ vreg_wwan: regulator-wwan { regulator-boot-on; }; =20 + vreg_pcie_12v: regulator-pcie-12v { + compatible =3D "regulator-fixed"; + + regulator-name =3D "VREG_PCIE_12V"; + regulator-min-microvolt =3D <12000000>; + regulator-max-microvolt =3D <12000000>; + + gpio =3D <&pm8550ve_8_gpios 8 GPIO_ACTIVE_HIGH>; + enable-active-high; + + pinctrl-0 =3D <&pcie_x8_12v>; + pinctrl-names =3D "default"; + }; + + vreg_pcie_3v3_aux: regulator-pcie-3v3-aux { + compatible =3D "regulator-fixed"; + + regulator-name =3D "VREG_PCIE_3P3_AUX"; + regulator-min-microvolt =3D <3300000>; + regulator-max-microvolt =3D <3300000>; + + gpio =3D <&pmc8380_3_gpios 8 GPIO_ACTIVE_HIGH>; + enable-active-high; + + pinctrl-0 =3D <&pm_sde7_aux_3p3_en>; + pinctrl-names =3D "default"; + }; + + vreg_pcie_3v3: regulator-pcie-3v3 { + compatible =3D "regulator-fixed"; + + regulator-name =3D "VREG_PCIE_3P3"; + regulator-min-microvolt =3D <3300000>; + regulator-max-microvolt =3D <3300000>; + + gpio =3D <&pmc8380_3_gpios 6 GPIO_ACTIVE_HIGH>; + enable-active-high; + + pinctrl-0 =3D <&pm_sde7_main_3p3_en>; + pinctrl-names =3D "default"; +}; + sound { compatible =3D "qcom,x1e80100-sndcard"; model =3D "X1E80100-EVK"; @@ -832,6 +874,12 @@ &mdss_dp3_phy { status =3D "okay"; }; =20 +&pcie3_port { + vpcie12v-supply =3D <&vreg_pcie_12v>; + vpcie3v3-supply =3D <&vreg_pcie_3v3>; + vpcie3v3aux-supply =3D <&vreg_pcie_3v3_aux>; +}; + &pcie5 { vddpe-3v3-supply =3D <&vreg_wwan>; }; --=20 2.34.1