From nobody Thu Oct 2 06:34:33 2025 Received: from lelvem-ot02.ext.ti.com (lelvem-ot02.ext.ti.com [198.47.23.235]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id B93E82F5326; Mon, 22 Sep 2025 07:13:11 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=none smtp.client-ip=198.47.23.235 ARC-Seal: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1758525193; cv=none; b=SaFQeTaswUPhjSSW7ev4uUD8504RaDyO7jXaUrnbiHnTNpcFLfQOjW8WUraWm3BAm+4oZXUsS9mXsbP51zu5iCh7av0bAem85LsvZiUC9cIUC6Ex0xflhHp/XnHimBcc4D3pJIdO+zhd5ogg31p06eW6Vbsn4Yq6OkfYFbXqZrQ= ARC-Message-Signature: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1758525193; c=relaxed/simple; bh=8KWHhTidiH2urEGsosGJ5Pg5i2u+LScKUBz6+Sgsu3M=; h=From:To:CC:Subject:Date:Message-ID:In-Reply-To:References: MIME-Version:Content-Type; b=KvqO2LoI4RtzqMsVUPmARo0RRjl6w6AznnY1yHRyEZZvdZLzN2EG3Q5oFH/GGgtlN1Y1iUBrqxrfTIGm4V01axbsOlOsAqNRFS0u809qfE5sTfJSaeeXxI4XFfl3oQmJUI9OmWNw/dFMcDkPtdh/xA4b35Zb7ofmDWGDPXVy0TI= ARC-Authentication-Results: i=1; smtp.subspace.kernel.org; dmarc=pass (p=quarantine dis=none) header.from=ti.com; spf=pass smtp.mailfrom=ti.com; dkim=pass (1024-bit key) header.d=ti.com header.i=@ti.com header.b=jjnmwLYu; arc=none smtp.client-ip=198.47.23.235 Authentication-Results: smtp.subspace.kernel.org; dmarc=pass (p=quarantine dis=none) header.from=ti.com Authentication-Results: smtp.subspace.kernel.org; spf=pass smtp.mailfrom=ti.com Authentication-Results: smtp.subspace.kernel.org; dkim=pass (1024-bit key) header.d=ti.com header.i=@ti.com header.b="jjnmwLYu" Received: from fllvem-sh04.itg.ti.com ([10.64.41.54]) by lelvem-ot02.ext.ti.com (8.15.2/8.15.2) with ESMTP id 58M7CgWu1200448; Mon, 22 Sep 2025 02:12:42 -0500 DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=ti.com; s=ti-com-17Q1; t=1758525162; bh=8rj79GWsNpW2CQ2ZrT1cmfk62tg9m6ghIwphYqlalKQ=; h=From:To:CC:Subject:Date:In-Reply-To:References; b=jjnmwLYutk5dyJu+pFCFUwtheIr+TFK6STk9pnJbSwx080SkIWuzoVbL9dk/6CdvG hNwozCUzzP7jEXJ1DFQcCvw6/SOArywSNvMIx64QukX57bHd2CfCKtmZ8b6dTfYQnC d3iGsFOgkl9SHuZNtuEvhHwhxDcYPalKna26Zhiw= Received: from DLEE115.ent.ti.com (dlee115.ent.ti.com [157.170.170.26]) by fllvem-sh04.itg.ti.com (8.18.1/8.18.1) with ESMTPS id 58M7CgPT1800438 (version=TLSv1.2 cipher=ECDHE-RSA-AES128-SHA256 bits=128 verify=FAIL); Mon, 22 Sep 2025 02:12:42 -0500 Received: from DLEE209.ent.ti.com (157.170.170.98) by DLEE115.ent.ti.com (157.170.170.26) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_128_CBC_SHA256_P256) id 15.1.2507.55; Mon, 22 Sep 2025 02:12:42 -0500 Received: from lelvem-mr05.itg.ti.com (10.180.75.9) by DLEE209.ent.ti.com (157.170.170.98) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_256_GCM_SHA384) id 15.2.2562.20 via Frontend Transport; Mon, 22 Sep 2025 02:12:42 -0500 Received: from uda0492258.dhcp.ti.com (uda0492258.dhcp.ti.com [172.24.231.84]) by lelvem-mr05.itg.ti.com (8.18.1/8.18.1) with ESMTP id 58M7CN0T2369246; Mon, 22 Sep 2025 02:12:36 -0500 From: Siddharth Vadapalli To: , , , , , , , , , , , , , , , <18255117159@163.com>, , CC: , , , , Subject: [PATCH v3 2/4] PCI: dwc: Export dw_pcie_allocate_domains() and dw_pcie_ep_raise_msix_irq() Date: Mon, 22 Sep 2025 12:42:14 +0530 Message-ID: <20250922071222.2814937-3-s-vadapalli@ti.com> X-Mailer: git-send-email 2.43.0 In-Reply-To: <20250922071222.2814937-1-s-vadapalli@ti.com> References: <20250922071222.2814937-1-s-vadapalli@ti.com> Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable X-C2ProcessedOrg: 333ef613-75bf-4e12-a4b1-8e3623f5dcea Content-Type: text/plain; charset="utf-8" The pci-keystone.c driver uses the functions 'dw_pcie_allocate_domains()' and 'dw_pcie_ep_raise_msix_irq()'. In preparation for enabling the pci-keystone.c driver to be built as a loadable module, export them. Signed-off-by: Siddharth Vadapalli --- This patch is a combination of patches 02/10 and 04/10 of the v2 series: 02/10: https://lore.kernel.org/r/20250912122356.3326888-3-s-vadapalli@ti.co= m/ 04/10: https://lore.kernel.org/r/20250912122356.3326888-5-s-vadapalli@ti.co= m/ Except for merging the patches of the v2 series together, and updating the commit message, no other changes have been made to get to this v3 patch. drivers/pci/controller/dwc/pcie-designware-ep.c | 1 + drivers/pci/controller/dwc/pcie-designware-host.c | 1 + 2 files changed, 2 insertions(+) diff --git a/drivers/pci/controller/dwc/pcie-designware-ep.c b/drivers/pci/= controller/dwc/pcie-designware-ep.c index 7f2112c2fb21..19571ac2b961 100644 --- a/drivers/pci/controller/dwc/pcie-designware-ep.c +++ b/drivers/pci/controller/dwc/pcie-designware-ep.c @@ -797,6 +797,7 @@ int dw_pcie_ep_raise_msix_irq(struct dw_pcie_ep *ep, u8= func_no, =20 return 0; } +EXPORT_SYMBOL_GPL(dw_pcie_ep_raise_msix_irq); =20 /** * dw_pcie_ep_cleanup - Cleanup DWC EP resources after fundamental reset diff --git a/drivers/pci/controller/dwc/pcie-designware-host.c b/drivers/pc= i/controller/dwc/pcie-designware-host.c index 952f8594b501..3cc83d921376 100644 --- a/drivers/pci/controller/dwc/pcie-designware-host.c +++ b/drivers/pci/controller/dwc/pcie-designware-host.c @@ -229,6 +229,7 @@ int dw_pcie_allocate_domains(struct dw_pcie_rp *pp) =20 return 0; } +EXPORT_SYMBOL_GPL(dw_pcie_allocate_domains); =20 void dw_pcie_free_msi(struct dw_pcie_rp *pp) { --=20 2.43.0