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charset="utf-8" From: Jackson Lee SError of kernel panic rarely happened while testing fluster. The root cause was to enter suspend mode because timeout of autosuspend delay happened. [ 48.834439] SError Interrupt on CPU0, code 0x00000000bf000000 -- SError [ 48.834455] CPU: 0 UID: 0 PID: 1067 Comm: v4l2h265dec0:sr Not tainted 6.= 12.9-gc9e21a1ebd75-dirty #7 [ 48.834461] Hardware name: ti Texas Instruments J721S2 EVM/Texas Instrum= ents J721S2 EVM, BIOS 2025.01-00345-gbaf3aaa8ecfa 01/01/2025 [ 48.834464] pstate: 20000005 (nzCv daif -PAN -UAO -TCO -DIT -SSBS BTYPE= =3D--) [ 48.834468] pc : wave5_dec_clr_disp_flag+0x40/0x80 [wave5] [ 48.834488] lr : wave5_dec_clr_disp_flag+0x40/0x80 [wave5] [ 48.834495] sp : ffff8000856e3a30 [ 48.834497] x29: ffff8000856e3a30 x28: ffff0008093f6010 x27: ffff0008091= 58130 [ 48.834504] x26: 0000000000000000 x25: ffff00080b625000 x24: ffff000804a= 9ba80 [ 48.834509] x23: ffff000802343028 x22: ffff000809158150 x21: ffff0008022= 18000 [ 48.834513] x20: ffff0008093f6000 x19: ffff0008093f6000 x18: 00000000000= 00000 [ 48.834518] x17: 0000000000000000 x16: 0000000000000000 x15: 0000ffff740= 09618 [ 48.834523] x14: 000000010000000c x13: 0000000000000000 x12: 00000000000= 00000 [ 48.834527] x11: ffffffffffffffff x10: ffffffffffffffff x9 : ffff0008023= 43028 [ 48.834532] x8 : ffff00080b6252a0 x7 : 0000000000000038 x6 : 00000000000= 00000 [ 48.834536] x5 : ffff00080b625060 x4 : 0000000000000000 x3 : 00000000000= 00000 [ 48.834541] x2 : 0000000000000000 x1 : ffff800084bf0118 x0 : ffff800084b= f0000 [ 48.834547] Kernel panic - not syncing: Asynchronous SError Interrupt [ 48.834549] CPU: 0 UID: 0 PID: 1067 Comm: v4l2h265dec0:sr Not tainted 6.= 12.9-gc9e21a1ebd75-dirty #7 [ 48.834554] Hardware name: ti Texas Instruments J721S2 EVM/Texas Instrum= ents J721S2 EVM, BIOS 2025.01-00345-gbaf3aaa8ecfa 01/01/2025 [ 48.834556] Call trace: [ 48.834559] dump_backtrace+0x94/0xec [ 48.834574] show_stack+0x18/0x24 [ 48.834579] dump_stack_lvl+0x38/0x90 [ 48.834585] dump_stack+0x18/0x24 [ 48.834588] panic+0x35c/0x3e0 [ 48.834592] nmi_panic+0x40/0x8c [ 48.834595] arm64_serror_panic+0x64/0x70 [ 48.834598] do_serror+0x3c/0x78 [ 48.834601] el1h_64_error_handler+0x34/0x4c [ 48.834605] el1h_64_error+0x64/0x68 [ 48.834608] wave5_dec_clr_disp_flag+0x40/0x80 [wave5] [ 48.834615] wave5_vpu_dec_clr_disp_flag+0x54/0x80 [wave5] [ 48.834622] wave5_vpu_dec_buf_queue+0x19c/0x1a0 [wave5] [ 48.834628] __enqueue_in_driver+0x3c/0x74 [videobuf2_common] [ 48.834639] vb2_core_qbuf+0x508/0x61c [videobuf2_common] [ 48.834646] vb2_qbuf+0xa4/0x168 [videobuf2_v4l2] [ 48.834656] v4l2_m2m_qbuf+0x80/0x238 [v4l2_mem2mem] [ 48.834666] v4l2_m2m_ioctl_qbuf+0x18/0x24 [v4l2_mem2mem] [ 48.834673] v4l_qbuf+0x48/0x5c [videodev] [ 48.834704] __video_do_ioctl+0x180/0x3f0 [videodev] [ 48.834725] video_usercopy+0x2ec/0x68c [videodev] [ 48.834745] video_ioctl2+0x18/0x24 [videodev] [ 48.834766] v4l2_ioctl+0x40/0x60 [videodev] [ 48.834786] __arm64_sys_ioctl+0xa8/0xec [ 48.834793] invoke_syscall+0x44/0x100 [ 48.834800] el0_svc_common.constprop.0+0xc0/0xe0 [ 48.834804] do_el0_svc+0x1c/0x28 [ 48.834809] el0_svc+0x30/0xd0 [ 48.834813] el0t_64_sync_handler+0xc0/0xc4 [ 48.834816] el0t_64_sync+0x190/0x194 [ 48.834820] SMP: stopping secondary CPUs [ 48.834831] Kernel Offset: disabled [ 48.834833] CPU features: 0x08,00002002,80200000,4200421b [ 48.834837] Memory Limit: none [ 49.161404] ---[ end Kernel panic - not syncing: Asynchronous SError Int= errupt ]--- Fixes: 2092b3833487 ("media: chips-media: wave5: Support runtime suspend/re= sume") Signed-off-by: Jackson Lee Signed-off-by: Nas Chung Reviewed-by: Nicolas Dufresne --- .../platform/chips-media/wave5/wave5-vpu-dec.c | 3 --- .../platform/chips-media/wave5/wave5-vpu-enc.c | 3 --- .../media/platform/chips-media/wave5/wave5-vpu.c | 2 +- .../platform/chips-media/wave5/wave5-vpuapi.c | 15 --------------- 4 files changed, 1 insertion(+), 22 deletions(-) diff --git a/drivers/media/platform/chips-media/wave5/wave5-vpu-dec.c b/dri= vers/media/platform/chips-media/wave5/wave5-vpu-dec.c index 72af0faa3ef2..1df78e427c6a 100644 --- a/drivers/media/platform/chips-media/wave5/wave5-vpu-dec.c +++ b/drivers/media/platform/chips-media/wave5/wave5-vpu-dec.c @@ -1829,9 +1829,6 @@ static int wave5_vpu_open_dec(struct file *filp) if (ret) goto cleanup_inst; =20 - if (list_empty(&dev->instances)) - pm_runtime_use_autosuspend(inst->dev->dev); - list_add_tail(&inst->list, &dev->instances); =20 mutex_unlock(&dev->dev_lock); diff --git a/drivers/media/platform/chips-media/wave5/wave5-vpu-enc.c b/dri= vers/media/platform/chips-media/wave5/wave5-vpu-enc.c index 506d6c6166a6..d2b047706626 100644 --- a/drivers/media/platform/chips-media/wave5/wave5-vpu-enc.c +++ b/drivers/media/platform/chips-media/wave5/wave5-vpu-enc.c @@ -1773,9 +1773,6 @@ static int wave5_vpu_open_enc(struct file *filp) if (ret) goto cleanup_inst; =20 - if (list_empty(&dev->instances)) - pm_runtime_use_autosuspend(inst->dev->dev); - list_add_tail(&inst->list, &dev->instances); =20 mutex_unlock(&dev->dev_lock); diff --git a/drivers/media/platform/chips-media/wave5/wave5-vpu.c b/drivers= /media/platform/chips-media/wave5/wave5-vpu.c index e1715d3f43b0..b3c633dd3df1 100644 --- a/drivers/media/platform/chips-media/wave5/wave5-vpu.c +++ b/drivers/media/platform/chips-media/wave5/wave5-vpu.c @@ -322,7 +322,7 @@ static int wave5_vpu_probe(struct platform_device *pdev) dev_info(&pdev->dev, "Product Code: 0x%x\n", dev->product_code); dev_info(&pdev->dev, "Firmware Revision: %u\n", fw_revision); =20 - pm_runtime_set_autosuspend_delay(&pdev->dev, 100); + pm_runtime_set_autosuspend_delay(&pdev->dev, 500); pm_runtime_use_autosuspend(&pdev->dev); pm_runtime_enable(&pdev->dev); wave5_vpu_sleep_wake(&pdev->dev, true, NULL, 0); diff --git a/drivers/media/platform/chips-media/wave5/wave5-vpuapi.c b/driv= ers/media/platform/chips-media/wave5/wave5-vpuapi.c index e5e879a13e8b..e94d6ebc9f81 100644 --- a/drivers/media/platform/chips-media/wave5/wave5-vpuapi.c +++ b/drivers/media/platform/chips-media/wave5/wave5-vpuapi.c @@ -207,8 +207,6 @@ int wave5_vpu_dec_close(struct vpu_instance *inst, u32 = *fail_res) int retry =3D 0; struct vpu_device *vpu_dev =3D inst->dev; int i; - int inst_count =3D 0; - struct vpu_instance *inst_elm; =20 *fail_res =3D 0; if (!inst->codec_info) @@ -250,11 +248,6 @@ int wave5_vpu_dec_close(struct vpu_instance *inst, u32= *fail_res) =20 wave5_vdi_free_dma_memory(vpu_dev, &p_dec_info->vb_task); =20 - list_for_each_entry(inst_elm, &vpu_dev->instances, list) - inst_count++; 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charset="utf-8" From: Jackson Lee When multi instances are created/destroyed, many interrupts happens and structures for decoder are removed. "struct vpu_instance" this structure is shared for all flow in the decoder, so if the structure is not protected by lock, Null dereference could happens sometimes. IRQ Handler was spilt to two phases and Lock was added as well. Fixes: 9707a6254a8a ("media: chips-media: wave5: Add the v4l2 layer") Signed-off-by: Jackson Lee Signed-off-by: Nas Chung --- .../platform/chips-media/wave5/wave5-helper.c | 28 +++++- .../platform/chips-media/wave5/wave5-helper.h | 1 + .../chips-media/wave5/wave5-vpu-dec.c | 5 + .../chips-media/wave5/wave5-vpu-enc.c | 5 + .../platform/chips-media/wave5/wave5-vpu.c | 96 +++++++++++++++++-- .../platform/chips-media/wave5/wave5-vpuapi.h | 6 ++ 6 files changed, 130 insertions(+), 11 deletions(-) diff --git a/drivers/media/platform/chips-media/wave5/wave5-helper.c b/driv= ers/media/platform/chips-media/wave5/wave5-helper.c index f03ad9c0de22..53a0ac068c2e 100644 --- a/drivers/media/platform/chips-media/wave5/wave5-helper.c +++ b/drivers/media/platform/chips-media/wave5/wave5-helper.c @@ -27,6 +27,11 @@ const char *state_to_str(enum vpu_instance_state state) } } =20 +int wave5_kfifo_alloc(struct vpu_instance *inst) +{ + return kfifo_alloc(&inst->irq_status, 16 * sizeof(int), GFP_KERNEL); +} + void wave5_cleanup_instance(struct vpu_instance *inst, struct file *filp) { int i; @@ -49,7 +54,7 @@ void wave5_cleanup_instance(struct vpu_instance *inst, st= ruct file *filp) v4l2_fh_del(&inst->v4l2_fh, filp); v4l2_fh_exit(&inst->v4l2_fh); } - list_del_init(&inst->list); + kfifo_free(&inst->irq_status); ida_free(&inst->dev->inst_ida, inst->id); kfree(inst->codec_info); kfree(inst); @@ -61,8 +66,29 @@ int wave5_vpu_release_device(struct file *filp, { struct vpu_instance *inst =3D file_to_vpu_inst(filp); int ret =3D 0; + unsigned long flags; =20 v4l2_m2m_ctx_release(inst->v4l2_fh.m2m_ctx); + /* + * To prevent Null reference exception, the existing irq handler were + * separated to two modules. + * One is to queue interrupt reason into the irq handler, + * the other is irq_thread to call the wave5_vpu_dec_finish_decode + * to get decoded frame. + * The list of instances should be protected between all flow of the + * decoding process, but to protect the list in the irq_handler, spin lock + * should be used, and mutex should be used in the irq_thread because spi= n lock + * is not able to be used because mutex is already being used + * in the wave5_vpu_dec_finish_decode. + * So the spin lock and mutex were used to protect the list in the releas= e function. + */ + ret =3D mutex_lock_interruptible(&inst->dev->irq_lock); + if (ret) + return ret; + spin_lock_irqsave(&inst->dev->irq_spinlock, flags); + list_del_init(&inst->list); + spin_unlock_irqrestore(&inst->dev->irq_spinlock, flags); + mutex_unlock(&inst->dev->irq_lock); if (inst->state !=3D VPU_INST_STATE_NONE) { u32 fail_res; =20 diff --git a/drivers/media/platform/chips-media/wave5/wave5-helper.h b/driv= ers/media/platform/chips-media/wave5/wave5-helper.h index 976a402e426f..d61fdbda359d 100644 --- a/drivers/media/platform/chips-media/wave5/wave5-helper.h +++ b/drivers/media/platform/chips-media/wave5/wave5-helper.h @@ -33,4 +33,5 @@ void wave5_update_pix_fmt(struct v4l2_pix_format_mplane *= pix_mp, unsigned int width, unsigned int height, const struct v4l2_frmsize_stepwise *frmsize); +int wave5_kfifo_alloc(struct vpu_instance *inst); #endif diff --git a/drivers/media/platform/chips-media/wave5/wave5-vpu-dec.c b/dri= vers/media/platform/chips-media/wave5/wave5-vpu-dec.c index 1df78e427c6a..a3a135946078 100644 --- a/drivers/media/platform/chips-media/wave5/wave5-vpu-dec.c +++ b/drivers/media/platform/chips-media/wave5/wave5-vpu-dec.c @@ -1810,6 +1810,11 @@ static int wave5_vpu_open_dec(struct file *filp) inst->xfer_func =3D V4L2_XFER_FUNC_DEFAULT; =20 init_completion(&inst->irq_done); + ret =3D wave5_kfifo_alloc(inst); + if (ret) { + dev_err(inst->dev->dev, "failed to allocate fifo\n"); + goto cleanup_inst; + } =20 inst->id =3D ida_alloc(&inst->dev->inst_ida, GFP_KERNEL); if (inst->id < 0) { diff --git a/drivers/media/platform/chips-media/wave5/wave5-vpu-enc.c b/dri= vers/media/platform/chips-media/wave5/wave5-vpu-enc.c index d2b047706626..f84146aa4915 100644 --- a/drivers/media/platform/chips-media/wave5/wave5-vpu-enc.c +++ b/drivers/media/platform/chips-media/wave5/wave5-vpu-enc.c @@ -1759,6 +1759,11 @@ static int wave5_vpu_open_enc(struct file *filp) inst->frame_rate =3D 30; =20 init_completion(&inst->irq_done); + ret =3D wave5_kfifo_alloc(inst); + if (ret) { + dev_err(inst->dev->dev, "failed to allocate fifo\n"); + goto cleanup_inst; + } =20 inst->id =3D ida_alloc(&inst->dev->inst_ida, GFP_KERNEL); if (inst->id < 0) { diff --git a/drivers/media/platform/chips-media/wave5/wave5-vpu.c b/drivers= /media/platform/chips-media/wave5/wave5-vpu.c index b3c633dd3df1..c00595b43bd3 100644 --- a/drivers/media/platform/chips-media/wave5/wave5-vpu.c +++ b/drivers/media/platform/chips-media/wave5/wave5-vpu.c @@ -51,8 +51,11 @@ static void wave5_vpu_handle_irq(void *dev_id) u32 seq_done; u32 cmd_done; u32 irq_reason; - struct vpu_instance *inst; + u32 irq_subreason; + struct vpu_instance *inst, *tmp; struct vpu_device *dev =3D dev_id; + int val; + unsigned long flags; =20 irq_reason =3D wave5_vdi_read_register(dev, W5_VPU_VINT_REASON); seq_done =3D wave5_vdi_read_register(dev, W5_RET_SEQ_DONE_INSTANCE_INFO); @@ -60,7 +63,8 @@ static void wave5_vpu_handle_irq(void *dev_id) wave5_vdi_write_register(dev, W5_VPU_VINT_REASON_CLR, irq_reason); wave5_vdi_write_register(dev, W5_VPU_VINT_CLEAR, 0x1); =20 - list_for_each_entry(inst, &dev->instances, list) { + spin_lock_irqsave(&dev->irq_spinlock, flags); + list_for_each_entry_safe(inst, tmp, &dev->instances, list) { =20 if (irq_reason & BIT(INT_WAVE5_INIT_SEQ) || irq_reason & BIT(INT_WAVE5_ENC_SET_PARAM)) { @@ -82,22 +86,54 @@ static void wave5_vpu_handle_irq(void *dev_id) irq_reason & BIT(INT_WAVE5_ENC_PIC)) { if (cmd_done & BIT(inst->id)) { cmd_done &=3D ~BIT(inst->id); - wave5_vdi_write_register(dev, W5_RET_QUEUE_CMD_DONE_INST, - cmd_done); - inst->ops->finish_process(inst); + if (dev->irq >=3D 0) { + irq_subreason =3D + wave5_vdi_read_register(dev, W5_VPU_VINT_REASON); + if (!(irq_subreason & BIT(INT_WAVE5_DEC_PIC))) + wave5_vdi_write_register(dev, + W5_RET_QUEUE_CMD_DONE_INST, + cmd_done); + } + val =3D BIT(INT_WAVE5_DEC_PIC); + kfifo_in(&inst->irq_status, &val, sizeof(int)); } } + } + spin_unlock_irqrestore(&dev->irq_spinlock, flags); + + if (dev->irq < 0) + up(&dev->irq_sem); +} + +static irqreturn_t wave5_vpu_irq(int irq, void *dev_id) +{ + struct vpu_device *dev =3D dev_id; =20 - wave5_vpu_clear_interrupt(inst, irq_reason); + if (wave5_vdi_read_register(dev, W5_VPU_VPU_INT_STS)) { + wave5_vpu_handle_irq(dev); + return IRQ_WAKE_THREAD; } + + return IRQ_HANDLED; } =20 static irqreturn_t wave5_vpu_irq_thread(int irq, void *dev_id) { struct vpu_device *dev =3D dev_id; + struct vpu_instance *inst, *tmp; + int irq_status, ret; =20 - if (wave5_vdi_read_register(dev, W5_VPU_VPU_INT_STS)) - wave5_vpu_handle_irq(dev); + mutex_lock(&dev->irq_lock); + list_for_each_entry_safe(inst, tmp, &dev->instances, list) { + while (kfifo_len(&inst->irq_status)) { + ret =3D kfifo_out(&inst->irq_status, &irq_status, sizeof(int)); + if (!ret) + break; + + inst->ops->finish_process(inst); + } + } + mutex_unlock(&dev->irq_lock); =20 return IRQ_HANDLED; } @@ -121,6 +157,35 @@ static enum hrtimer_restart wave5_vpu_timer_callback(s= truct hrtimer *timer) return HRTIMER_RESTART; } =20 +static int irq_thread(void *data) +{ + struct vpu_device *dev =3D (struct vpu_device *)data; + struct vpu_instance *inst, *tmp; + int irq_status, ret; + + while (!kthread_should_stop()) { + if (down_interruptible(&dev->irq_sem)) + continue; + + if (kthread_should_stop()) + break; + + mutex_lock(&dev->irq_lock); + list_for_each_entry_safe(inst, tmp, &dev->instances, list) { + while (kfifo_len(&inst->irq_status)) { + ret =3D kfifo_out(&inst->irq_status, &irq_status, sizeof(int)); + if (!ret) + break; + + inst->ops->finish_process(inst); + } + } + mutex_unlock(&dev->irq_lock); + } + + return 0; +} + static int wave5_vpu_load_firmware(struct device *dev, const char *fw_name, u32 *revision) { @@ -224,6 +289,8 @@ static int wave5_vpu_probe(struct platform_device *pdev) =20 mutex_init(&dev->dev_lock); mutex_init(&dev->hw_lock); + mutex_init(&dev->irq_lock); + spin_lock_init(&dev->irq_spinlock); dev_set_drvdata(&pdev->dev, dev); dev->dev =3D &pdev->dev; =20 @@ -266,9 +333,13 @@ static int wave5_vpu_probe(struct platform_device *pde= v) } dev->product =3D wave5_vpu_get_product_id(dev); =20 + INIT_LIST_HEAD(&dev->instances); + dev->irq =3D platform_get_irq(pdev, 0); if (dev->irq < 0) { dev_err(&pdev->dev, "failed to get irq resource, falling back to polling= \n"); + sema_init(&dev->irq_sem, 1); + dev->irq_thread =3D kthread_run(irq_thread, dev, "irq thread"); hrtimer_setup(&dev->hrtimer, &wave5_vpu_timer_callback, CLOCK_MONOTONIC, HRTIMER_MODE_REL_PINNED); dev->worker =3D kthread_run_worker(0, "vpu_irq_thread"); @@ -280,7 +351,7 @@ static int wave5_vpu_probe(struct platform_device *pdev) dev->vpu_poll_interval =3D vpu_poll_interval; kthread_init_work(&dev->work, wave5_vpu_irq_work_fn); } else { - ret =3D devm_request_threaded_irq(&pdev->dev, dev->irq, NULL, + ret =3D devm_request_threaded_irq(&pdev->dev, dev->irq, wave5_vpu_irq, wave5_vpu_irq_thread, IRQF_ONESHOT, "vpu_irq", dev); if (ret) { dev_err(&pdev->dev, "Register interrupt handler, fail: %d\n", ret); @@ -288,7 +359,6 @@ static int wave5_vpu_probe(struct platform_device *pdev) } } =20 - INIT_LIST_HEAD(&dev->instances); ret =3D v4l2_device_register(&pdev->dev, &dev->v4l2_dev); if (ret) { dev_err(&pdev->dev, "v4l2_device_register, fail: %d\n", ret); @@ -352,6 +422,11 @@ static void wave5_vpu_remove(struct platform_device *p= dev) struct vpu_device *dev =3D dev_get_drvdata(&pdev->dev); =20 if (dev->irq < 0) { + if (dev->irq_thread) { + kthread_stop(dev->irq_thread); + up(&dev->irq_sem); + dev->irq_thread =3D NULL; + } kthread_destroy_worker(dev->worker); hrtimer_cancel(&dev->hrtimer); } @@ -361,6 +436,7 @@ static void wave5_vpu_remove(struct platform_device *pd= ev) =20 mutex_destroy(&dev->dev_lock); mutex_destroy(&dev->hw_lock); + mutex_destroy(&dev->irq_lock); reset_control_assert(dev->resets); clk_bulk_disable_unprepare(dev->num_clks, dev->clks); wave5_vpu_enc_unregister_device(dev); diff --git a/drivers/media/platform/chips-media/wave5/wave5-vpuapi.h b/driv= ers/media/platform/chips-media/wave5/wave5-vpuapi.h index 45615c15beca..bc101397204d 100644 --- a/drivers/media/platform/chips-media/wave5/wave5-vpuapi.h +++ b/drivers/media/platform/chips-media/wave5/wave5-vpuapi.h @@ -8,6 +8,7 @@ #ifndef VPUAPI_H_INCLUDED #define VPUAPI_H_INCLUDED =20 +#include #include #include #include @@ -747,6 +748,7 @@ struct vpu_device { struct video_device *video_dev_enc; struct mutex dev_lock; /* lock for the src, dst v4l2 queues */ struct mutex hw_lock; /* lock hw configurations */ + struct mutex irq_lock; int irq; enum product_id product; struct vpu_attr attr; @@ -764,7 +766,10 @@ struct vpu_device { struct kthread_worker *worker; int vpu_poll_interval; int num_clks; + struct task_struct *irq_thread; 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charset="utf-8" From: Jackson Lee The dec_output_info should not be a null pointer, WARN_ON around it to indicates a driver issue. Signed-off-by: Jackson Lee Signed-off-by: Nas Chung --- drivers/media/platform/chips-media/wave5/wave5-vpuapi.c | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/drivers/media/platform/chips-media/wave5/wave5-vpuapi.c b/driv= ers/media/platform/chips-media/wave5/wave5-vpuapi.c index e94d6ebc9f81..5b10f9f49b9f 100644 --- a/drivers/media/platform/chips-media/wave5/wave5-vpuapi.c +++ b/drivers/media/platform/chips-media/wave5/wave5-vpuapi.c @@ -485,7 +485,7 @@ int wave5_vpu_dec_get_output_info(struct vpu_instance *= inst, struct dec_output_i struct vpu_device *vpu_dev =3D inst->dev; struct dec_output_info *disp_info; =20 - if (!info) + if (WARN_ON(!info)) return -EINVAL; =20 p_dec_info =3D &inst->codec_info->dec_info; --=20 2.43.0 From nobody Thu Oct 2 05:08:09 2025 Received: from SEVP216CU002.outbound.protection.outlook.com (mail-koreacentralazon11022089.outbound.protection.outlook.com [40.107.43.89]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id 3BAD02ED872; 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charset="utf-8" From: Jackson Lee The current decoding method was to wait until each frame was decoded after feeding a bitstream. As a result, performance was low and Wave5 could not achieve max pixel processing rate. Update driver to use an asynchronous approach for decoding and feeding a bitstream in order to achieve full capabilities of the device. WAVE5 supports command-queueing to maximize performance by pipelining internal commands and by hiding wait cycle taken to receive a command from Host processor. Instead of waiting for each command to be executed before sending the next command, Host processor just places all the commands in the command-queue and goes on doing other things while the commands in the queue are processed by VPU. While Host processor handles its own tasks, it can receive VPU interrupt request (IRQ). In this case, host processor can simply exit interrupt service routine (ISR) without accessing to host interface to read the result of the command reported by VPU. After host processor completed its tasks, host processor can read the command result when host processor needs the reports and does response processing. To achieve this goal, the device_run() calls v4l2_m2m_job_finish so that next command can be sent to VPU continuously, if there is any result, then irq is triggered and gets decoded frames and returns them to upper layer. Theses processes work independently each other without waiting a decoded frame. Signed-off-by: Jackson Lee Signed-off-by: Nas Chung --- .../platform/chips-media/wave5/wave5-hw.c | 2 +- .../chips-media/wave5/wave5-vpu-dec.c | 166 ++++++++++++------ .../platform/chips-media/wave5/wave5-vpu.h | 2 +- .../platform/chips-media/wave5/wave5-vpuapi.c | 46 +++-- .../platform/chips-media/wave5/wave5-vpuapi.h | 6 + .../chips-media/wave5/wave5-vpuconfig.h | 1 + 6 files changed, 154 insertions(+), 69 deletions(-) diff --git a/drivers/media/platform/chips-media/wave5/wave5-hw.c b/drivers/= media/platform/chips-media/wave5/wave5-hw.c index d94cf84c3ee5..687ce6ccf3ae 100644 --- a/drivers/media/platform/chips-media/wave5/wave5-hw.c +++ b/drivers/media/platform/chips-media/wave5/wave5-hw.c @@ -102,7 +102,7 @@ static void _wave5_print_reg_err(struct vpu_device *vpu= _dev, u32 reg_fail_reason dev_dbg(dev, "%s: queueing failure: 0x%x\n", func, reg_val); break; case WAVE5_SYSERR_RESULT_NOT_READY: - dev_err(dev, "%s: result not ready: 0x%x\n", func, reg_fail_reason); + dev_dbg(dev, "%s: result not ready: 0x%x\n", func, reg_fail_reason); break; case WAVE5_SYSERR_ACCESS_VIOLATION_HW: dev_err(dev, "%s: access violation: 0x%x\n", func, reg_fail_reason); diff --git a/drivers/media/platform/chips-media/wave5/wave5-vpu-dec.c b/dri= vers/media/platform/chips-media/wave5/wave5-vpu-dec.c index a3a135946078..e9cc6fedfea8 100644 --- a/drivers/media/platform/chips-media/wave5/wave5-vpu-dec.c +++ b/drivers/media/platform/chips-media/wave5/wave5-vpu-dec.c @@ -268,6 +268,7 @@ static void send_eos_event(struct vpu_instance *inst) =20 v4l2_event_queue_fh(&inst->v4l2_fh, &vpu_event_eos); inst->eos =3D false; + inst->sent_eos =3D true; } =20 static int handle_dynamic_resolution_change(struct vpu_instance *inst) @@ -347,13 +348,12 @@ static void wave5_vpu_dec_finish_decode(struct vpu_in= stance *inst) struct vb2_v4l2_buffer *dec_buf =3D NULL; struct vb2_v4l2_buffer *disp_buf =3D NULL; struct vb2_queue *dst_vq =3D v4l2_m2m_get_dst_vq(m2m_ctx); - struct queue_status_info q_status; =20 dev_dbg(inst->dev->dev, "%s: Fetch output info from firmware.", __func__); =20 ret =3D wave5_vpu_dec_get_output_info(inst, &dec_info); if (ret) { - dev_warn(inst->dev->dev, "%s: could not get output info.", __func__); + dev_dbg(inst->dev->dev, "%s: could not get output info.", __func__); v4l2_m2m_job_finish(inst->v4l2_m2m_dev, m2m_ctx); return; } @@ -442,18 +442,14 @@ static void wave5_vpu_dec_finish_decode(struct vpu_in= stance *inst) spin_unlock_irqrestore(&inst->state_spinlock, flags); } =20 - /* - * During a resolution change and while draining, the firmware may flush - * the reorder queue regardless of having a matching decoding operation - * pending. Only terminate the job if there are no more IRQ coming. - */ - wave5_vpu_dec_give_command(inst, DEC_GET_QUEUE_STATUS, &q_status); - if (q_status.report_queue_count =3D=3D 0 && - (q_status.instance_queue_count =3D=3D 0 || dec_info.sequence_changed)= ) { - dev_dbg(inst->dev->dev, "%s: finishing job.\n", __func__); - pm_runtime_mark_last_busy(inst->dev->dev); - pm_runtime_put_autosuspend(inst->dev->dev); - v4l2_m2m_job_finish(inst->v4l2_m2m_dev, m2m_ctx); + if (inst->sent_eos && + v4l2_m2m_get_curr_priv(inst->v4l2_m2m_dev)) { + struct queue_status_info q_status; + + wave5_vpu_dec_give_command(inst, DEC_GET_QUEUE_STATUS, &q_status); + if (q_status.report_queue_count =3D=3D 0 && + q_status.instance_queue_count =3D=3D 0) + v4l2_m2m_job_finish(inst->v4l2_m2m_dev, m2m_ctx); } } =20 @@ -1143,11 +1139,31 @@ static int write_to_ringbuffer(struct vpu_instance = *inst, void *buffer, size_t b return 0; } =20 +static struct vpu_src_buffer *inst_src_buf_remove(struct vpu_instance *ins= t) +{ + struct vpu_src_buffer *b; + + if (list_empty(&inst->avail_src_bufs)) + return NULL; + inst->queued_count--; + b =3D list_first_entry(&inst->avail_src_bufs, struct vpu_src_buffer, list= ); + list_del(&b->list); + b->list.prev =3D NULL; + b->list.next =3D NULL; + INIT_LIST_HEAD(&b->list); + if (inst->queued_count =3D=3D 0) { + inst->avail_src_bufs.prev =3D NULL; + inst->avail_src_bufs.next =3D NULL; + INIT_LIST_HEAD(&inst->avail_src_bufs); + } + return b; +} + static int fill_ringbuffer(struct vpu_instance *inst) { struct v4l2_m2m_ctx *m2m_ctx =3D inst->v4l2_fh.m2m_ctx; - struct v4l2_m2m_buffer *buf, *n; - int ret; + struct vpu_src_buffer *vpu_buf; + int ret =3D 0; =20 if (m2m_ctx->last_src_buf) { struct vpu_src_buffer *vpu_buf =3D wave5_to_vpu_src_buf(m2m_ctx->last_sr= c_buf); @@ -1158,9 +1174,8 @@ static int fill_ringbuffer(struct vpu_instance *inst) } } =20 - v4l2_m2m_for_each_src_buf_safe(m2m_ctx, buf, n) { - struct vb2_v4l2_buffer *vbuf =3D &buf->vb; - struct vpu_src_buffer *vpu_buf =3D wave5_to_vpu_src_buf(vbuf); + while ((vpu_buf =3D inst_src_buf_remove(inst)) !=3D NULL) { + struct vb2_v4l2_buffer *vbuf =3D &vpu_buf->v4l2_m2m_buf.vb; struct vpu_buf *ring_buffer =3D &inst->bitstream_vbuf; size_t src_size =3D vb2_get_plane_payload(&vbuf->vb2_buf, 0); void *src_buf =3D vb2_plane_vaddr(&vbuf->vb2_buf, 0); @@ -1220,9 +1235,12 @@ static int fill_ringbuffer(struct vpu_instance *inst) dev_dbg(inst->dev->dev, "last src buffer written to the ring buffer\n"); break; } + + inst->queuing_num++; + break; } =20 - return 0; + return ret; } =20 static void wave5_vpu_dec_buf_queue_src(struct vb2_buffer *vb) @@ -1234,7 +1252,8 @@ static void wave5_vpu_dec_buf_queue_src(struct vb2_bu= ffer *vb) =20 vpu_buf->consumed =3D false; vbuf->sequence =3D inst->queued_src_buf_num++; - + list_add_tail(&vpu_buf->list, &inst->avail_src_bufs); + inst->queued_count++; v4l2_m2m_buf_queue(m2m_ctx, vbuf); } =20 @@ -1287,10 +1306,16 @@ static void wave5_vpu_dec_buf_queue(struct vb2_buff= er *vb) __func__, vb->type, vb->index, vb2_plane_size(&vbuf->vb2_buf, 0), vb2_plane_size(&vbuf->vb2_buf, 1), vb2_plane_size(&vbuf->vb2_buf, 2)); =20 - if (vb->type =3D=3D V4L2_BUF_TYPE_VIDEO_OUTPUT_MPLANE) + if (vb->type =3D=3D V4L2_BUF_TYPE_VIDEO_OUTPUT_MPLANE) { + mutex_lock(&inst->feed_lock); wave5_vpu_dec_buf_queue_src(vb); - else if (vb->type =3D=3D V4L2_BUF_TYPE_VIDEO_CAPTURE_MPLANE) + + if (inst->empty_queue) + inst->empty_queue =3D false; + mutex_unlock(&inst->feed_lock); + } else if (vb->type =3D=3D V4L2_BUF_TYPE_VIDEO_CAPTURE_MPLANE) { wave5_vpu_dec_buf_queue_dst(vb); + } } =20 static int wave5_vpu_dec_allocate_ring_buffer(struct vpu_instance *inst) @@ -1385,6 +1410,17 @@ static int streamoff_output(struct vb2_queue *q) dma_addr_t new_rd_ptr; struct dec_output_info dec_info; unsigned int i; + struct vpu_src_buffer *vpu_buf, *tmp; + + inst->retry =3D false; + inst->queuing_num =3D 0; + inst->queued_count =3D 0; + mutex_lock(&inst->feed_lock); + list_for_each_entry_safe(vpu_buf, tmp, &inst->avail_src_bufs, list) { + vpu_buf->consumed =3D false; + list_del(&vpu_buf->list); + } + mutex_unlock(&inst->feed_lock); =20 for (i =3D 0; i < v4l2_m2m_num_dst_bufs_ready(m2m_ctx); i++) { ret =3D wave5_vpu_dec_set_disp_flag(inst, i); @@ -1470,27 +1506,10 @@ static void wave5_vpu_dec_stop_streaming(struct vb2= _queue *q) { struct vpu_instance *inst =3D vb2_get_drv_priv(q); struct v4l2_m2m_ctx *m2m_ctx =3D inst->v4l2_fh.m2m_ctx; - bool check_cmd =3D TRUE; =20 dev_dbg(inst->dev->dev, "%s: type: %u\n", __func__, q->type); pm_runtime_resume_and_get(inst->dev->dev); =20 - while (check_cmd) { - struct queue_status_info q_status; - struct dec_output_info dec_output_info; - - wave5_vpu_dec_give_command(inst, DEC_GET_QUEUE_STATUS, &q_status); - - if (q_status.report_queue_count =3D=3D 0) - break; - - if (wave5_vpu_wait_interrupt(inst, VPU_DEC_TIMEOUT) < 0) - break; - - if (wave5_vpu_dec_get_output_info(inst, &dec_output_info)) - dev_dbg(inst->dev->dev, "there is no output info\n"); - } - v4l2_m2m_update_stop_streaming_state(m2m_ctx, q); =20 if (q->type =3D=3D V4L2_BUF_TYPE_VIDEO_OUTPUT_MPLANE) @@ -1498,6 +1517,8 @@ static void wave5_vpu_dec_stop_streaming(struct vb2_q= ueue *q) else streamoff_capture(q); =20 + inst->empty_queue =3D false; + inst->sent_eos =3D false; pm_runtime_mark_last_busy(inst->dev->dev); pm_runtime_put_autosuspend(inst->dev->dev); } @@ -1577,13 +1598,24 @@ static void wave5_vpu_dec_device_run(void *priv) struct queue_status_info q_status; u32 fail_res =3D 0; int ret =3D 0; + unsigned long flags; =20 dev_dbg(inst->dev->dev, "%s: Fill the ring buffer with new bitstream data= ", __func__); pm_runtime_resume_and_get(inst->dev->dev); - ret =3D fill_ringbuffer(inst); - if (ret) { - dev_warn(inst->dev->dev, "Filling ring buffer failed\n"); - goto finish_job_and_return; + if (!inst->retry) { + mutex_lock(&inst->feed_lock); + ret =3D fill_ringbuffer(inst); + mutex_unlock(&inst->feed_lock); + if (ret < 0) { + dev_warn(inst->dev->dev, "Filling ring buffer failed\n"); + goto finish_job_and_return; + } else if (!inst->eos && + inst->queuing_num =3D=3D 0 && + inst->state =3D=3D VPU_INST_STATE_PIC_RUN) { + dev_dbg(inst->dev->dev, "%s: no bitstream for feeding, so skip ", __fun= c__); + inst->empty_queue =3D true; + goto finish_job_and_return; + } } =20 switch (inst->state) { @@ -1608,7 +1640,9 @@ static void wave5_vpu_dec_device_run(void *priv) } spin_unlock_irqrestore(&inst->state_spinlock, flags); } else { + spin_lock_irqsave(&inst->state_spinlock, flags); switch_state(inst, VPU_INST_STATE_INIT_SEQ); + spin_unlock_irqrestore(&inst->state_spinlock, flags); } =20 break; @@ -1619,8 +1653,9 @@ static void wave5_vpu_dec_device_run(void *priv) * we had a chance to switch, which leads to an invalid state * change. */ + spin_lock_irqsave(&inst->state_spinlock, flags); switch_state(inst, VPU_INST_STATE_PIC_RUN); - + spin_unlock_irqrestore(&inst->state_spinlock, flags); /* * During DRC, the picture decoding remains pending, so just leave the j= ob * active until this decode operation completes. @@ -1634,12 +1669,14 @@ static void wave5_vpu_dec_device_run(void *priv) ret =3D wave5_prepare_fb(inst); if (ret) { dev_warn(inst->dev->dev, "Framebuffer preparation, fail: %d\n", ret); + spin_lock_irqsave(&inst->state_spinlock, flags); switch_state(inst, VPU_INST_STATE_STOP); + spin_unlock_irqrestore(&inst->state_spinlock, flags); break; } =20 if (q_status.instance_queue_count) { - dev_dbg(inst->dev->dev, "%s: leave with active job", __func__); + v4l2_m2m_job_finish(inst->v4l2_m2m_dev, m2m_ctx); return; } =20 @@ -1650,26 +1687,42 @@ static void wave5_vpu_dec_device_run(void *priv) dev_err(inst->dev->dev, "Frame decoding on m2m context (%p), fail: %d (result: %d)\n", m2m_ctx, ret, fail_res); - break; + goto finish_job_and_return; + } + + if (fail_res =3D=3D WAVE5_SYSERR_QUEUEING_FAIL) { + inst->retry =3D true; + } else { + inst->retry =3D false; + if (!inst->eos) + inst->queuing_num--; } - /* Return so that we leave this job active */ - dev_dbg(inst->dev->dev, "%s: leave with active job", __func__); - return; - default: - WARN(1, "Execution of a job in state %s illegal.\n", state_to_str(inst->= state)); break; + default: + dev_dbg(inst->dev->dev, "Execution of a job in state %s illegal.\n", + state_to_str(inst->state)); } =20 finish_job_and_return: dev_dbg(inst->dev->dev, "%s: leave and finish job", __func__); pm_runtime_mark_last_busy(inst->dev->dev); pm_runtime_put_autosuspend(inst->dev->dev); - v4l2_m2m_job_finish(inst->v4l2_m2m_dev, m2m_ctx); + /* + * After receiving CMD_STOP, there is no input, but we have to run device= _run + * to send DEC_PIC command until display index =3D=3D -1, so job_finish w= as always + * called in the device_run to archive it, the logic was very wasteful + * in power and CPU time. + * If EOS is passed, device_run will not call job_finish no more, it is c= alled + * only if HW is idle status in order to reduce overhead. + */ + if (!inst->sent_eos) + v4l2_m2m_job_finish(inst->v4l2_m2m_dev, m2m_ctx); } =20 static void wave5_vpu_dec_job_abort(void *priv) { struct vpu_instance *inst =3D priv; + struct v4l2_m2m_ctx *m2m_ctx =3D inst->v4l2_fh.m2m_ctx; int ret; =20 ret =3D switch_state(inst, VPU_INST_STATE_STOP); @@ -1680,6 +1733,8 @@ static void wave5_vpu_dec_job_abort(void *priv) if (ret) dev_warn(inst->dev->dev, "Setting EOS for the bitstream, fail: %d\n", ret); + + v4l2_m2m_job_finish(inst->v4l2_m2m_dev, m2m_ctx); } =20 static int wave5_vpu_dec_job_ready(void *priv) @@ -1715,7 +1770,8 @@ static int wave5_vpu_dec_job_ready(void *priv) "No capture buffer ready to decode!\n"); break; } else if (!wave5_is_draining_or_eos(inst) && - !v4l2_m2m_num_src_bufs_ready(m2m_ctx)) { + (!v4l2_m2m_num_src_bufs_ready(m2m_ctx) || + inst->empty_queue)) { dev_dbg(inst->dev->dev, "No bitstream data to decode!\n"); break; @@ -1755,6 +1811,8 @@ static int wave5_vpu_open_dec(struct file *filp) inst->ops =3D &wave5_vpu_dec_inst_ops; =20 spin_lock_init(&inst->state_spinlock); + mutex_init(&inst->feed_lock); + INIT_LIST_HEAD(&inst->avail_src_bufs); =20 inst->codec_info =3D kzalloc(sizeof(*inst->codec_info), GFP_KERNEL); if (!inst->codec_info) diff --git a/drivers/media/platform/chips-media/wave5/wave5-vpu.h b/drivers= /media/platform/chips-media/wave5/wave5-vpu.h index 5943bdaa9c4c..99c3be882192 100644 --- a/drivers/media/platform/chips-media/wave5/wave5-vpu.h +++ b/drivers/media/platform/chips-media/wave5/wave5-vpu.h @@ -22,8 +22,8 @@ =20 struct vpu_src_buffer { struct v4l2_m2m_buffer v4l2_m2m_buf; - struct list_head list; bool consumed; + struct list_head list; }; =20 struct vpu_dst_buffer { diff --git a/drivers/media/platform/chips-media/wave5/wave5-vpuapi.c b/driv= ers/media/platform/chips-media/wave5/wave5-vpuapi.c index 5b10f9f49b9f..b967f0efea57 100644 --- a/drivers/media/platform/chips-media/wave5/wave5-vpuapi.c +++ b/drivers/media/platform/chips-media/wave5/wave5-vpuapi.c @@ -52,11 +52,12 @@ int wave5_vpu_init_with_bitcode(struct device *dev, u8 = *bitcode, size_t size) int wave5_vpu_flush_instance(struct vpu_instance *inst) { int ret =3D 0; + int mutex_ret =3D 0; int retry =3D 0; =20 - ret =3D mutex_lock_interruptible(&inst->dev->hw_lock); - if (ret) - return ret; + mutex_ret =3D mutex_lock_interruptible(&inst->dev->hw_lock); + if (mutex_ret) + return mutex_ret; do { /* * Repeat the FLUSH command until the firmware reports that the @@ -80,9 +81,9 @@ int wave5_vpu_flush_instance(struct vpu_instance *inst) =20 mutex_unlock(&inst->dev->hw_lock); wave5_vpu_dec_get_output_info(inst, &dec_info); - ret =3D mutex_lock_interruptible(&inst->dev->hw_lock); - if (ret) - return ret; + mutex_ret =3D mutex_lock_interruptible(&inst->dev->hw_lock); + if (mutex_ret) + return mutex_ret; if (dec_info.index_frame_display > 0) wave5_vpu_dec_set_disp_flag(inst, dec_info.index_frame_display); } @@ -207,6 +208,8 @@ int wave5_vpu_dec_close(struct vpu_instance *inst, u32 = *fail_res) int retry =3D 0; struct vpu_device *vpu_dev =3D inst->dev; int i; + struct dec_output_info dec_info; + int ret_mutex; =20 *fail_res =3D 0; if (!inst->codec_info) @@ -214,10 +217,10 @@ int wave5_vpu_dec_close(struct vpu_instance *inst, u3= 2 *fail_res) =20 pm_runtime_resume_and_get(inst->dev->dev); =20 - ret =3D mutex_lock_interruptible(&vpu_dev->hw_lock); - if (ret) { + ret_mutex =3D mutex_lock_interruptible(&vpu_dev->hw_lock); + if (ret_mutex) { pm_runtime_put_sync(inst->dev->dev); - return ret; + return ret_mutex; } =20 do { @@ -227,11 +230,26 @@ int wave5_vpu_dec_close(struct vpu_instance *inst, u3= 2 *fail_res) goto unlock_and_return; } =20 - if (*fail_res =3D=3D WAVE5_SYSERR_VPU_STILL_RUNNING && - retry++ >=3D MAX_FIRMWARE_CALL_RETRY) { + if (ret =3D=3D 0) + break; + + if (*fail_res !=3D WAVE5_SYSERR_VPU_STILL_RUNNING) { + dev_warn(inst->dev->dev, "dec_finish_seq timed out\n"); + goto unlock_and_return; + } + + if (retry++ >=3D MAX_FIRMWARE_CALL_RETRY) { ret =3D -ETIMEDOUT; goto unlock_and_return; } + + mutex_unlock(&vpu_dev->hw_lock); + wave5_vpu_dec_get_output_info(inst, &dec_info); + ret_mutex =3D mutex_lock_interruptible(&vpu_dev->hw_lock); + if (ret_mutex) { + pm_runtime_put_sync(inst->dev->dev); + return ret_mutex; + } } while (ret !=3D 0); =20 dev_dbg(inst->dev->dev, "%s: dec_finish_seq complete\n", __func__); @@ -248,6 +266,8 @@ int wave5_vpu_dec_close(struct vpu_instance *inst, u32 = *fail_res) =20 wave5_vdi_free_dma_memory(vpu_dev, &p_dec_info->vb_task); =20 + mutex_destroy(&inst->feed_lock); + unlock_and_return: mutex_unlock(&vpu_dev->hw_lock); pm_runtime_put_sync(inst->dev->dev); @@ -460,11 +480,11 @@ int wave5_vpu_dec_set_rd_ptr(struct vpu_instance *ins= t, dma_addr_t addr, int upd dma_addr_t wave5_vpu_dec_get_rd_ptr(struct vpu_instance *inst) { int ret; - dma_addr_t rd_ptr; + dma_addr_t rd_ptr =3D 0; =20 ret =3D mutex_lock_interruptible(&inst->dev->hw_lock); if (ret) - return ret; + return rd_ptr; =20 rd_ptr =3D wave5_dec_get_rd_ptr(inst); =20 diff --git a/drivers/media/platform/chips-media/wave5/wave5-vpuapi.h b/driv= ers/media/platform/chips-media/wave5/wave5-vpuapi.h index bc101397204d..3088f3966fcb 100644 --- a/drivers/media/platform/chips-media/wave5/wave5-vpuapi.h +++ b/drivers/media/platform/chips-media/wave5/wave5-vpuapi.h @@ -818,6 +818,12 @@ struct vpu_instance { bool cbcr_interleave; bool nv21; bool eos; + bool sent_eos; /* check if EOS is sent to application */ + bool retry; /* retry to feed bitstream if failure reason is WAVE5_SYSERR_= QUEUEING_FAIL*/ + int queuing_num; /* count of bitstream queued */ + int queued_count; /* the number of bitstream buffers queued from the buf_= queue */ + struct mutex feed_lock; /* lock for feeding bitstream buffers */ + bool empty_queue; struct vpu_buf bitstream_vbuf; dma_addr_t last_rd_ptr; size_t remaining_consumed_bytes; diff --git a/drivers/media/platform/chips-media/wave5/wave5-vpuconfig.h b/d= rivers/media/platform/chips-media/wave5/wave5-vpuconfig.h index 1ea9f5f31499..4ebd48d5550e 100644 --- a/drivers/media/platform/chips-media/wave5/wave5-vpuconfig.h +++ b/drivers/media/platform/chips-media/wave5/wave5-vpuconfig.h @@ -59,6 +59,7 @@ // application specific configuration #define VPU_ENC_TIMEOUT 60000 #define VPU_DEC_TIMEOUT 60000 +#define VPU_DEC_STOP_TIMEOUT 10 =20 // for WAVE encoder #define USE_SRC_PRP_AXI 0 --=20 2.43.0