From nobody Thu Oct 2 06:34:32 2025 Received: from mailout2.samsung.com (mailout2.samsung.com [203.254.224.25]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id C80422C15AE for ; Mon, 22 Sep 2025 04:19:12 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=none smtp.client-ip=203.254.224.25 ARC-Seal: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1758514756; cv=none; b=Z0CHcs7ijHp00FsZuuaONHMUoOP8dqxay6Xufv6XgXwZiPxZ4thzI/UMFi+3hXNQCNcBzJcYEmWXawDNsQ0FJcrJpTK3T6s6ItNaXQIFEmz4xrvaNhuekyOolfBnR5SGFfOBNfDffwI1yy9daeQs0av1wLPUnbF6tnLuGWZ4YXE= ARC-Message-Signature: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1758514756; c=relaxed/simple; bh=J5lLd/vuL6jZtvy0ljv8wT1z6W/jyQFZVqfO7u/SBDE=; h=From:To:Cc:Subject:Date:Message-ID:In-Reply-To:MIME-Version: Content-Type:References; b=N/3IJkyNKg/L8zG5zfwI0mARYqxxM7/SHYR7Loxl398Tazfm6J16cOq6V3AoNEa+qiqKanc0btQiLtMtCRBNYM21ekme5RfVutLRGw7L52RBypM5zl5vqtjsOkB331Oqf8YE0wP5EBNI4EAcm8qvMjLQt3YLgl57nmpfgpZTJtQ= ARC-Authentication-Results: i=1; smtp.subspace.kernel.org; dmarc=pass (p=none dis=none) header.from=samsung.com; spf=pass smtp.mailfrom=samsung.com; dkim=pass (1024-bit key) header.d=samsung.com header.i=@samsung.com header.b=DMbh9izM; arc=none smtp.client-ip=203.254.224.25 Authentication-Results: smtp.subspace.kernel.org; dmarc=pass (p=none dis=none) header.from=samsung.com Authentication-Results: smtp.subspace.kernel.org; spf=pass smtp.mailfrom=samsung.com Authentication-Results: smtp.subspace.kernel.org; dkim=pass (1024-bit key) header.d=samsung.com header.i=@samsung.com header.b="DMbh9izM" Received: from epcas2p2.samsung.com (unknown [182.195.41.54]) by mailout2.samsung.com (KnoxPortal) with ESMTP id 20250922041904epoutp0230c7e055552975353b66ea2e6ddd8bf4~nf9fjQzAu0973209732epoutp02S for ; Mon, 22 Sep 2025 04:19:04 +0000 (GMT) DKIM-Filter: OpenDKIM Filter v2.11.0 mailout2.samsung.com 20250922041904epoutp0230c7e055552975353b66ea2e6ddd8bf4~nf9fjQzAu0973209732epoutp02S DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=samsung.com; s=mail20170921; t=1758514744; bh=tG27NdAYAB5zCAFtjok5lejCXpe+CazBoZAPMuwAwqw=; h=From:To:Cc:Subject:Date:In-Reply-To:References:From; b=DMbh9izM/KFv2lt5g/Ku8ubp6+6EKHefLDqvsawa0UmISZrmyPXZwfWrL53Nsb0aw a90A1/Tooq0p217rl3iqYZNRgJLAAPSb3J5AoScbNKlYJsrJsverwFqARbU90M55IO FAGpyQfv8vUdnpf4vJgRogIjbrx6mM8RcfRA5y+U= Received: from epsnrtp01.localdomain (unknown [182.195.42.153]) by epcas2p3.samsung.com (KnoxPortal) with ESMTPS id 20250922041903epcas2p3293d46954e1f7bcca3c0e88e334b4903~nf9e2xMH81715517155epcas2p3W; Mon, 22 Sep 2025 04:19:03 +0000 (GMT) Received: from epcas2p1.samsung.com (unknown [182.195.36.70]) by epsnrtp01.localdomain (Postfix) with ESMTP id 4cVVHC2nXZz6B9mB; Mon, 22 Sep 2025 04:19:03 +0000 (GMT) Received: from epsmtip2.samsung.com (unknown [182.195.34.31]) by epcas2p2.samsung.com (KnoxPortal) with ESMTPA id 20250922041902epcas2p226d426e4805801a09ae078387893d1df~nf9dL7o3j2487324873epcas2p2L; Mon, 22 Sep 2025 04:19:02 +0000 (GMT) Received: from asswp60 (unknown [10.229.9.60]) by epsmtip2.samsung.com (KnoxPortal) with ESMTPA id 20250922041902epsmtip2351083f0d9fb4f01e3360c87f43a8329~nf9dF-q180819908199epsmtip24; Mon, 22 Sep 2025 04:19:02 +0000 (GMT) From: Shin Son To: Bartlomiej Zolnierkiewicz , Krzysztof Kozlowski , "Rafael J . Wysocki" , Daniel Lezcano , Zhang Rui , Lukasz Luba , Rob Herring , Conor Dooley , Alim Akhtar , Henrik Grimler Cc: Shin Son , linux-pm@vger.kernel.org, linux-samsung-soc@vger.kernel.org, devicetree@vger.kernel.org, linux-arm-kernel@lists.infradead.org, linux-kernel@vger.kernel.org Subject: [PATCH v4 3/3] arm64: dts: exynosautov920: Add multiple sensors Date: Mon, 22 Sep 2025 13:18:57 +0900 Message-ID: <20250922041857.1107445-4-shin.son@samsung.com> X-Mailer: git-send-email 2.50.1 In-Reply-To: <20250922041857.1107445-1-shin.son@samsung.com> Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable X-CMS-MailID: 20250922041902epcas2p226d426e4805801a09ae078387893d1df X-Msg-Generator: CA Content-Type: text/plain; charset="utf-8" X-Sendblock-Type: AUTO_CONFIDENTIAL CMS-TYPE: 102P cpgsPolicy: CPGSC10-234,Y X-CFilter-Loop: Reflected X-CMS-RootMailID: 20250922041902epcas2p226d426e4805801a09ae078387893d1df References: <20250922041857.1107445-1-shin.son@samsung.com> Create a new exynosautov920-tmu.dtsi describing new TMU hardware and include it from exynosautov920.dtsi. The exynosautov920-tmu node uses the misc clock as its source. This TMU binding defines multiple thermal zones with a critical trip point at 125 degrees: tmu_top : cpus0-0, cpus0-1, cpus0-2, cpus0-3, cpus1-0, cpus1-1, cpus1-2, cpus1-3, cpus1-4, cpus1-5, cpus1-6, cpus1-7 tmu_sub0: cpus0-4, cpus0-5, cpus0-6, cpus0-7, cpus2-0, cpus2-1, cpus2-2, cpus2-3 tmu_sub1: gpu0, gpu1, gpu2, gpu3, npu0, npu1 Signed-off-by: Shin Son --- .../boot/dts/exynos/exynosautov920-tmu.dtsi | 377 ++++++++++++++++++ .../arm64/boot/dts/exynos/exynosautov920.dtsi | 31 ++ 2 files changed, 408 insertions(+) create mode 100644 arch/arm64/boot/dts/exynos/exynosautov920-tmu.dtsi diff --git a/arch/arm64/boot/dts/exynos/exynosautov920-tmu.dtsi b/arch/arm6= 4/boot/dts/exynos/exynosautov920-tmu.dtsi new file mode 100644 index 000000000000..641d142e0eeb --- /dev/null +++ b/arch/arm64/boot/dts/exynos/exynosautov920-tmu.dtsi @@ -0,0 +1,377 @@ +// SPDX-License-Identifier: GPL-2.0 +/* + * Samsung's ExynosAuto920 TMU configurations device tree source + * + * Copyright (c) 2020 Samsung Electronics Co., Ltd. + * + * Samsung's ExynosAuto920 SoC TMU(Thermal Managemenut Unit) are listed as + * device tree nodes in this file. + */ + +/ { + thermal-zones { + cpus0-0-thermal { + polling-delay-passive =3D <0>; + polling-delay =3D <0>; + thermal-sensors =3D <&tmu_top 9>; + + trips { + cpus0_0_critical: cpus0-0-critical { + temperature =3D <125000>; /* millicelsius */ + hysteresis =3D <0>; /* millicelsius */ + type =3D "critical"; + }; + }; + }; + + cpus0-1-thermal { + polling-delay-passive =3D <0>; + polling-delay =3D <0>; + thermal-sensors =3D <&tmu_top 10>; + + trips { + cpus0_1_critical: cpus0-1-critical { + temperature =3D <125000>; /* millicelsius */ + hysteresis =3D <0>; /* millicelsius */ + type =3D "critical"; + }; + }; + }; + + cpus0-2-thermal { + polling-delay-passive =3D <0>; + polling-delay =3D <0>; + thermal-sensors =3D <&tmu_top 11>; + + trips { + cpus0_2_critical: cpus0-2-critical { + temperature =3D <125000>; /* millicelsius */ + hysteresis =3D <0>; /* millicelsius */ + type =3D "critical"; + }; + }; + }; + + cpus0-3-thermal { + polling-delay-passive =3D <0>; + polling-delay =3D <0>; + thermal-sensors =3D <&tmu_top 12>; + + trips { + cpus0_3_critical: cpus0-3-critical { + temperature =3D <125000>; /* millicelsius */ + hysteresis =3D <0>; /* millicelsius */ + type =3D "critical"; + }; + }; + }; + + cpus0-4-thermal { + polling-delay-passive =3D <0>; + polling-delay =3D <0>; + thermal-sensors =3D <&tmu_sub0 7>; + + trips { + cpus0_4_critical: cpus0-4-critical { + temperature =3D <125000>; /* millicelsius */ + hysteresis =3D <0>; /* millicelsius */ + type =3D "critical"; + }; + }; + }; + + cpus0-5-thermal { + polling-delay-passive =3D <0>; + polling-delay =3D <0>; + thermal-sensors =3D <&tmu_sub0 8>; + + trips { + cpus0_5_critical: cpus0-5-critical { + temperature =3D <125000>; /* millicelsius */ + hysteresis =3D <0>; /* millicelsius */ + type =3D "critical"; + }; + }; + }; + + cpus0-6-thermal { + polling-delay-passive =3D <0>; + polling-delay =3D <0>; + thermal-sensors =3D <&tmu_sub0 9>; + + trips { + cpus0_6_critical: cpus0-6-critical { + temperature =3D <125000>; /* millicelsius */ + hysteresis =3D <0>; /* millicelsius */ + type =3D "critical"; + }; + }; + }; + + cpus0-7-thermal { + polling-delay-passive =3D <0>; + polling-delay =3D <0>; + thermal-sensors =3D <&tmu_sub0 10>; + + trips { + cpus0_7_critical: cpus0-7-critical { + temperature =3D <125000>; /* millicelsius */ + hysteresis =3D <0>; /* millicelsius */ + type =3D "critical"; + }; + }; + }; + + cpus1-0-thermal { + polling-delay-passive =3D <0>; + polling-delay =3D <0>; + thermal-sensors =3D <&tmu_top 1>; + + trips { + cpus1_0_critical: cpus1-0-critical { + temperature =3D <125000>; /* millicelsius */ + hysteresis =3D <0>; /* millicelsius */ + type =3D "critical"; + }; + }; + }; + + cpus1-1-thermal { + polling-delay-passive =3D <0>; + polling-delay =3D <0>; + thermal-sensors =3D <&tmu_top 2>; + + trips { + cpus1_1_critical: cpus1-1-critical { + temperature =3D <125000>; /* millicelsius */ + hysteresis =3D <0>; /* millicelsius */ + type =3D "critical"; + }; + }; + }; + + cpus1-2-thermal { + polling-delay-passive =3D <0>; + polling-delay =3D <0>; + thermal-sensors =3D <&tmu_top 3>; + + trips { + cpus1_2_critical: cpus1-2-critical { + temperature =3D <125000>; /* millicelsius */ + hysteresis =3D <0>; /* millicelsius */ + type =3D "critical"; + }; + }; + }; + + cpus1-3-thermal { + polling-delay-passive =3D <0>; + polling-delay =3D <0>; + thermal-sensors =3D <&tmu_top 4>; + + trips { + cpus1_3_critical: cpus1-3-critical { + temperature =3D <125000>; /* millicelsius */ + hysteresis =3D <0>; /* millicelsius */ + type =3D "critical"; + }; + }; + }; + + cpus1-4-thermal { + polling-delay-passive =3D <0>; + polling-delay =3D <0>; + thermal-sensors =3D <&tmu_top 5>; + + trips { + cpus1_4_critical: cpus1-4-critical { + temperature =3D <125000>; /* millicelsius */ + hysteresis =3D <0>; /* millicelsius */ + type =3D "critical"; + }; + }; + }; + + cpus1-5-thermal { + polling-delay-passive =3D <0>; + polling-delay =3D <0>; + thermal-sensors =3D <&tmu_top 6>; + + trips { + cpus1_5_critical: cpus1-5-critical { + temperature =3D <125000>; /* millicelsius */ + hysteresis =3D <0>; /* millicelsius */ + type =3D "critical"; + }; + }; + }; + + cpus1-6-thermal { + polling-delay-passive =3D <0>; + polling-delay =3D <0>; + thermal-sensors =3D <&tmu_top 7>; + + trips { + cpus1_6_critical: cpus1-6-critical { + temperature =3D <125000>; /* millicelsius */ + hysteresis =3D <0>; /* millicelsius */ + type =3D "critical"; + }; + }; + }; + + cpus1-7-thermal { + polling-delay-passive =3D <0>; + polling-delay =3D <0>; + thermal-sensors =3D <&tmu_top 8>; + + trips { + cpus1_7_critical: cpus1-7-critical { + temperature =3D <125000>; /* millicelsius */ + hysteresis =3D <0>; /* millicelsius */ + type =3D "critical"; + }; + }; + }; + + cpus2-0-thermal { + polling-delay-passive =3D <0>; + polling-delay =3D <0>; + thermal-sensors =3D <&tmu_sub0 3>; + + trips { + cpus2_0_critical: cpus2-0-critical { + temperature =3D <125000>; /* millicelsius */ + hysteresis =3D <0>; /* millicelsius */ + type =3D "critical"; + }; + }; + }; + + cpus2-1-thermal { + polling-delay-passive =3D <0>; + polling-delay =3D <0>; + thermal-sensors =3D <&tmu_sub0 4>; + + trips { + cpus2_1_critical: cpus2-1-critical { + temperature =3D <125000>; /* millicelsius */ + hysteresis =3D <0>; /* millicelsius */ + type =3D "critical"; + }; + }; + }; + + cpus2-2-thermal { + polling-delay-passive =3D <0>; + polling-delay =3D <0>; + thermal-sensors =3D <&tmu_sub0 5>; + + trips { + cpus2_2_critical: cpus2-2-critical { + temperature =3D <125000>; /* millicelsius */ + hysteresis =3D <0>; /* millicelsius */ + type =3D "critical"; + }; + }; + }; + + cpus2-3-thermal { + polling-delay-passive =3D <0>; + polling-delay =3D <0>; + thermal-sensors =3D <&tmu_sub0 6>; + + trips { + cpus2_3_critical: cpus2-3-critical { + temperature =3D <125000>; /* millicelsius */ + hysteresis =3D <0>; /* millicelsius */ + type =3D "critical"; + }; + }; + }; + + gpu0-thermal { + polling-delay-passive =3D <0>; + polling-delay =3D <0>; + thermal-sensors =3D <&tmu_sub1 1>; + + trips { + gpu0_critical: gpu0-critical { + temperature =3D <125000>; /* millicelsius */ + hysteresis =3D <0>; /* millicelsius */ + type =3D "critical"; + }; + }; + }; + + gpu1-thermal { + polling-delay-passive =3D <0>; + polling-delay =3D <0>; + thermal-sensors =3D <&tmu_sub1 2>; + + trips { + gpu1_critical: gpu1-critical { + temperature =3D <125000>; /* millicelsius */ + hysteresis =3D <0>; /* millicelsius */ + type =3D "critical"; + }; + }; + }; + + gpu2-thermal { + polling-delay-passive =3D <0>; + polling-delay =3D <0>; + thermal-sensors =3D <&tmu_sub1 3>; + + trips { + gpu2_critical: gpu2-critical { + temperature =3D <125000>; /* millicelsius */ + hysteresis =3D <0>; /* millicelsius */ + type =3D "critical"; + }; + }; + }; + + gpu3-thermal { + polling-delay-passive =3D <0>; + polling-delay =3D <0>; + thermal-sensors =3D <&tmu_sub1 4>; + + trips { + gpu3_critical: gpu3-critical { + temperature =3D <125000>; /* millicelsius */ + hysteresis =3D <0>; /* millicelsius */ + type =3D "critical"; + }; + }; + }; + + npu0-thermal { + polling-delay-passive =3D <0>; + polling-delay =3D <0>; + thermal-sensors =3D <&tmu_sub1 6>; + + trips { + npu0_critical: npu0-critical { + temperature =3D <125000>; /* millicelsius */ + hysteresis =3D <0>; /* millicelsius */ + type =3D "critical"; + }; + }; + }; + + npu1-thermal { + polling-delay-passive =3D <0>; + polling-delay =3D <0>; + thermal-sensors =3D <&tmu_sub1 7>; + + trips { + npu1_critical: npu1-critical { + temperature =3D <125000>; /* millicelsius */ + hysteresis =3D <0>; /* millicelsius */ + type =3D "critical"; + }; + }; + }; + }; +}; diff --git a/arch/arm64/boot/dts/exynos/exynosautov920.dtsi b/arch/arm64/bo= ot/dts/exynos/exynosautov920.dtsi index 0fdf2062930a..fba403e48aed 100644 --- a/arch/arm64/boot/dts/exynos/exynosautov920.dtsi +++ b/arch/arm64/boot/dts/exynos/exynosautov920.dtsi @@ -330,6 +330,36 @@ watchdog_cl1: watchdog@10070000 { samsung,cluster-index =3D <1>; }; =20 + tmu_top: tmu@100a0000 { + compatible =3D "samsung,exynosautov920-tmu"; + reg =3D <0x100A0000 0x1000>; + interrupts =3D ; + #thermal-sensor-cells =3D <1>; + clocks =3D <&cmu_misc CLK_DOUT_MISC_NOCP>; + clock-names =3D "tmu_apbif"; + samsung,sensors =3D <12>; + }; + + tmu_sub0: tmu@100b0000 { + compatible =3D "samsung,exynosautov920-tmu"; + reg =3D <0x100B0000 0x1000>; + interrupts =3D ; + #thermal-sensor-cells =3D <1>; + clocks =3D <&cmu_misc CLK_DOUT_MISC_NOCP>; + clock-names =3D "tmu_apbif"; + samsung,sensors =3D <10>; + }; + + tmu_sub1: tmu@100c0000 { + compatible =3D "samsung,exynosautov920-tmu"; + reg =3D <0x100C0000 0x1000>; + interrupts =3D ; + #thermal-sensor-cells =3D <1>; + clocks =3D <&cmu_misc CLK_DOUT_MISC_NOCP>; + clock-names =3D "tmu_apbif"; + samsung,sensors =3D <7>; + }; + gic: interrupt-controller@10400000 { compatible =3D "arm,gic-v3"; #interrupt-cells =3D <3>; @@ -1507,3 +1537,4 @@ timer { }; =20 #include "exynosautov920-pinctrl.dtsi" +#include "exynosautov920-tmu.dtsi" --=20 2.50.1