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[199.106.103.254]) by smtp.gmail.com with ESMTPSA id d9443c01a7336-2698019821dsm143706275ad.64.2025.09.22.16.34.04 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Mon, 22 Sep 2025 16:34:05 -0700 (PDT) From: Jessica Zhang Date: Mon, 22 Sep 2025 16:32:39 -0700 Subject: [PATCH] drm/msm/dpu: Don't adjust mode clock if 3d merge is supported Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Content-Transfer-Encoding: quoted-printable Message-Id: <20250922-modeclk-fix-v1-1-a9b8faec74f8@oss.qualcomm.com> X-B4-Tracking: v=1; b=H4sIAJbc0WgC/6tWKk4tykwtVrJSqFYqSi3LLM7MzwNyDHUUlJIzE vPSU3UzU4B8JSMDI1MDSyMj3dz8lNTknGzdtMwK3UQLcwNjc9MUS0szAyWgjoKiVKAw2LTo2Np aADo2laBdAAAA X-Change-ID: 20250922-modeclk-fix-a870375d9960 To: Rob Clark , Dmitry Baryshkov , Abhinav Kumar , Sean Paul , Marijn Suijten , David Airlie , Simona Vetter Cc: linux-arm-msm@vger.kernel.org, dri-devel@lists.freedesktop.org, freedreno@lists.freedesktop.org, linux-kernel@vger.kernel.org, Abel Vesa , Jessica Zhang X-Mailer: b4 0.15-dev-a9b2a X-Developer-Signature: v=1; a=ed25519-sha256; t=1758584044; l=1310; i=jessica.zhang@oss.qualcomm.com; s=20230329; h=from:subject:message-id; bh=NO6OCdz9v3Tc/Ktiqg3Wh+gypiA56gt1Z/XEzJOevmM=; b=FqqpcegGZLXcfSidwXQSnQCKvesciEyokTB8ipKxsrgPjY51xArxNhIg82ImuTocCxHkuuPGw VJFOYqL/PstDdIHfGPlZ+Z8RwhNoeEAsIRRkKI74iPOGYZqxpsIOTuW X-Developer-Key: i=jessica.zhang@oss.qualcomm.com; a=ed25519; pk=gAUCgHZ6wTJOzQa3U0GfeCDH7iZLlqIEPo4rrjfDpWE= X-Proofpoint-ORIG-GUID: wsY4gbRpHeLi-mbd62bIVL4e0ZeQWaqw X-Proofpoint-GUID: wsY4gbRpHeLi-mbd62bIVL4e0ZeQWaqw X-Authority-Analysis: v=2.4 cv=No/Rc9dJ c=1 sm=1 tr=0 ts=68d1dcee cx=c_pps a=MTSHoo12Qbhz2p7MsH1ifg==:117 a=JYp8KDb2vCoCEuGobkYCKw==:17 a=IkcTkHD0fZMA:10 a=yJojWOMRYYMA:10 a=KKAkSRfTAAAA:8 a=EUspDBNiAAAA:8 a=NBkOncM4Jvnk2V6n248A:9 a=QEXdDO2ut3YA:10 a=GvdueXVYPmCkWapjIL-Q:22 a=cvBusfyB2V15izCimMoJ:22 X-Proofpoint-Spam-Details-Enc: AW1haW4tMjUwOTIwMDAzNyBTYWx0ZWRfX/dPPCcprrDfY CqeberRTVnV1984r7gxjrJI+XfjczX2BGYt7nwmpJRpJCWC1LDZzK/fSawDW6MhMmMMx+WduY0H kXvbBTz8MOWk1i6Wiu8PVvH3BFYjwmg1jvoT8r57Qv5U052kxrPhR6msLp1aT2aiaso86WVG/M4 XXABFmz1IQj04FueJvogAYwniXcEM+BWOpShhvMdK4gUC8T0dbqIuxJs2L6qNZU5zYrwK1OTHbN N310yMSysILgGApO1oEJU+Lmjg0qO56A2s7KlGJ0sb9U/cxf3+DU8THF/9X0Rwa1mQHeW3asNag EDMmp9/4Fw9Z+adcNnwqZiPhiHC/HKwAd5OaI/iWJpe6EDXKZeLtVZS7GBX16FPNUbgiEoDtxDv HkhVpmIF X-Proofpoint-Virus-Version: vendor=baseguard engine=ICAP:2.0.293,Aquarius:18.0.1117,Hydra:6.1.9,FMLib:17.12.80.40 definitions=2025-09-22_05,2025-09-22_05,2025-03-28_01 X-Proofpoint-Spam-Details: rule=outbound_notspam policy=outbound score=0 clxscore=1015 spamscore=0 suspectscore=0 adultscore=0 malwarescore=0 phishscore=0 bulkscore=0 priorityscore=1501 impostorscore=0 classifier=typeunknown authscore=0 authtc= authcc= route=outbound adjust=0 reason=mlx scancount=1 engine=8.19.0-2507300000 definitions=main-2509200037 Since 3D merge allows for higher mode clocks to be supported across multiple layer mixers, filter modes based on adjusted mode clocks only if 3D merge isn't supported. Reported-by: Abel Vesa Fixes: 62b7d6835288 ("drm/msm/dpu: Filter modes based on adjusted mode cloc= k") Signed-off-by: Jessica Zhang --- drivers/gpu/drm/msm/disp/dpu1/dpu_crtc.c | 3 ++- 1 file changed, 2 insertions(+), 1 deletion(-) diff --git a/drivers/gpu/drm/msm/disp/dpu1/dpu_crtc.c b/drivers/gpu/drm/msm= /disp/dpu1/dpu_crtc.c index 4b970a59deaf..5ac51863a189 100644 --- a/drivers/gpu/drm/msm/disp/dpu1/dpu_crtc.c +++ b/drivers/gpu/drm/msm/disp/dpu1/dpu_crtc.c @@ -1549,7 +1549,8 @@ static enum drm_mode_status dpu_crtc_mode_valid(struc= t drm_crtc *crtc, * The given mode, adjusted for the perf clock factor, should not exceed * the max core clock rate */ - if (dpu_kms->perf.max_core_clk_rate < adjusted_mode_clk * 1000) + if (!dpu_kms->catalog->caps->has_3d_merge && + dpu_kms->perf.max_core_clk_rate < adjusted_mode_clk * 1000) return MODE_CLOCK_HIGH; =20 /* --- base-commit: b5bad77e1e3c7249e4c0c88f98477e1ee7669b63 change-id: 20250922-modeclk-fix-a870375d9960 Best regards, -- =20 Jessica Zhang