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[83.233.6.197]) by smtp.gmail.com with ESMTPSA id 38308e7fff4ca-361a99e99e6sm26982661fa.56.2025.09.21.23.21.39 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Sun, 21 Sep 2025 23:21:40 -0700 (PDT) From: Marcus Folkesson Date: Mon, 22 Sep 2025 08:20:56 +0200 Subject: [PATCH RFC 1/7] i2c: core: add callback to change bus frequency Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Content-Transfer-Encoding: quoted-printable Message-Id: <20250922-i2c-mux-v1-1-28c94a610930@gmail.com> References: <20250922-i2c-mux-v1-0-28c94a610930@gmail.com> In-Reply-To: <20250922-i2c-mux-v1-0-28c94a610930@gmail.com> To: Wolfram Sang , Peter Rosin , Michael Hennerich , Bartosz Golaszewski , Andi Shyti Cc: linux-i2c@vger.kernel.org, linux-kernel@vger.kernel.org, linux-arm-kernel@lists.infradead.org, Marcus Folkesson X-Mailer: b4 0.14.2 X-Developer-Signature: v=1; a=openpgp-sha256; l=1672; i=marcus.folkesson@gmail.com; h=from:subject:message-id; bh=5vuOIHtLq7CFaEidcZicx94qxk7qZlaIZNjnBzwUQCQ=; b=owEBbQKS/ZANAwAKAYiATm9ZXVIyAcsmYgBo0OrOt6PCwljxald5m7gc8+WsI9kpekTN+Q/Rq gbzc/+JJ1KJAjMEAAEKAB0WIQQFUaLotmy1TWTBLGWIgE5vWV1SMgUCaNDqzgAKCRCIgE5vWV1S Ml33D/4jURdHc7ZD+yGYnP7a/o5h0NzCtJOSCoXVcslKAcrezYI1mKiKUpA7cH0pqaP402/dB1o 4UqBwRSE6phGhHOLyI1Da23/uF3tKaOR1xTOH15XJi9KJwhLIOWyPrLAf7L01ROvcSAK+aUPmTC w6jQzpzKirmLZWunBp8RtkLsIXZ+69LIn/Iaj01IjtE5bhWdLGAmVAGlmn5ZH1LZVOXFWmqqi5s jbx31cFHESNh1aNmbszEF6RZaoK3keyxl6xG/EEWOxV2TsFg0FJ08XeP5pbg6zhlKR9+sftC0hK B47jZaSIONjU0wzB7QjmvD9GtZh64vmHCab865FhR8udfElK5I/dz9I+gH/9dMadpLQMtBoPJb7 Lw2aZRQjwo0bOYIYqehCVOrxYWMLFfF7pZHbavriuINk1yyeKy8BJW/feCL4KH1tqMOsv7SRMbC txk2z0uXcqfCw3wBakgNARonovBe7eVzK09pKVy3EVnz57+4hTge2Jmj8rjbhZ4V/MvJZ9CvW3W nI4Z2a0UmxngD4AJzi/+kbi2V6eaFJqXJNdkc29kt/KReJNdUmHHh/cuIHC39p5xHq6NofMWqry zGMg1B9qVbYTHbRMbyStwVZ2Dyxwgph1y1l+zuNJFViwkbJH8yzM9YUOsuqwGt9wcwcJiw/8rib hGMwGk6CRvJw7wA== X-Developer-Key: i=marcus.folkesson@gmail.com; a=openpgp; fpr=AB91D46C7E0F6E6FB2AB640EC0FE25D598F6C127 All devices on the same I2C bus share the same clock line and the bus frequency has therefor be chosen so that all attached devices are able to tolarate that clock rate. IOW, the bus speed must be set for the slowest attached device. With I2C multiplexers/switches on the other hand, it would be possible to have different "domains" that runs with different speeds. Prepare for such a feature by provide an optional callback function to change bus frequency. Signed-off-by: Marcus Folkesson --- include/linux/i2c.h | 13 +++++++++++++ 1 file changed, 13 insertions(+) diff --git a/include/linux/i2c.h b/include/linux/i2c.h index 20fd41b51d5c85ee1665395c07345faafd8e2fca..d147e388dbab27966beb4dfbf86= 9928b429e082c 100644 --- a/include/linux/i2c.h +++ b/include/linux/i2c.h @@ -742,6 +742,8 @@ struct i2c_adapter { struct rt_mutex mux_lock; =20 int timeout; /* in jiffies */ + int clock_hz; + int (*set_clk_freq)(struct i2c_adapter *adap, u32 clock_hz); /* Optional = */ int retries; struct device dev; /* the adapter device */ unsigned long locked_flags; /* owned by the I2C core */ @@ -835,6 +837,17 @@ i2c_unlock_bus(struct i2c_adapter *adapter, unsigned i= nt flags) adapter->lock_ops->unlock_bus(adapter, flags); } =20 +static inline int +i2c_adapter_set_clk_freq(struct i2c_adapter *adapter, u32 clock_hz) +{ + int ret =3D -EOPNOTSUPP; + + if (adapter->set_clk_freq) + ret =3D adapter->set_clk_freq(adapter, clock_hz); + + return ret; +} + /** * i2c_mark_adapter_suspended - Report suspended state of the adapter to t= he core * @adap: Adapter to mark as suspended --=20 2.50.1 From nobody Thu Oct 2 04:44:14 2025 Received: from mail-lj1-f178.google.com (mail-lj1-f178.google.com [209.85.208.178]) (using TLSv1.2 with cipher ECDHE-RSA-AES128-GCM-SHA256 (128/128 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id 51A8827467D for ; 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[83.233.6.197]) by smtp.gmail.com with ESMTPSA id 38308e7fff4ca-361a99e99e6sm26982661fa.56.2025.09.21.23.21.42 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Sun, 21 Sep 2025 23:21:42 -0700 (PDT) From: Marcus Folkesson Date: Mon, 22 Sep 2025 08:20:57 +0200 Subject: [PATCH RFC 2/7] i2c: mux: add idle_state property to i2c_mux_core Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Content-Transfer-Encoding: quoted-printable Message-Id: <20250922-i2c-mux-v1-2-28c94a610930@gmail.com> References: <20250922-i2c-mux-v1-0-28c94a610930@gmail.com> In-Reply-To: <20250922-i2c-mux-v1-0-28c94a610930@gmail.com> To: Wolfram Sang , Peter Rosin , Michael Hennerich , Bartosz Golaszewski , Andi Shyti Cc: linux-i2c@vger.kernel.org, linux-kernel@vger.kernel.org, linux-arm-kernel@lists.infradead.org, Marcus Folkesson X-Mailer: b4 0.14.2 X-Developer-Signature: v=1; a=openpgp-sha256; l=2406; i=marcus.folkesson@gmail.com; h=from:subject:message-id; bh=9bgM+F7I6nEBFXYeWO7UL9pGB4ld3ARupPlzJMnONCI=; b=owEBbQKS/ZANAwAKAYiATm9ZXVIyAcsmYgBo0OrTfjsniWp6URWZI3ApnyPsD8hApZoRIAM7A qI2Xt32A0+JAjMEAAEKAB0WIQQFUaLotmy1TWTBLGWIgE5vWV1SMgUCaNDq0wAKCRCIgE5vWV1S MhRgEAC24JGh3ARAKo2IuHAVAizurwI0LVGbgPTLOp+OuMCKJH2ti7is6Ni7R1PdOuI2QkMPf0F 3V1Llz0v8ml/2axaF0X020StWV1zlx7ZXqrCHIepvG0DP2S1jVUXQ2LRRfZoAfOhzkB1v6yNBU+ kluu4zCd6lPhMpQOzx/1fbsT9cRScclGTSnL+jGdDIQdP6bPhciANQnlQVgSLOkK7H5vc5uObrM 21rWaoj24i+moR5Ty+YMoPX+8fTdelLGqf+JPQl44trRyXPo9t23pbFDdAxrA49Pxhetq5UsvJw lEb0Gc20/sG+m2C4ua+scQVO/fa/aeTiXPN/INQdKjsSRU0qH+1i0zOAL0QVgB9GkrCWkqWwKUt 8HmQt5rTv1V+dls5Q0+igckCg0rcCQOzN/eL7Wwx5gEalLOUBLYcm04DGOQSTqIfRA5ePlzIfbv SY+/69JT9msuRKl3So16O0vrjKazP1P0u+ZaUY3Hy93RymzI+qutLHJuCByu7CFvr0rKvz8BtFH RXEBFv0cLojjXWhV/TPSSSSk5cQ02Cnpx9aaV8rkHGcQUNUHOh+n4CuTXygWFJzyYlxKaJNCURZ J4ZBGP5FgMQIFXAQ41qfy1crDEoZxg9ssaInr6eivS36tjhFIWaiAHYmxkrhHZOjD6Bob3j5CdP yvK0IZpMDl6Lpkg== X-Developer-Key: i=marcus.folkesson@gmail.com; a=openpgp; fpr=AB91D46C7E0F6E6FB2AB640EC0FE25D598F6C127 Muxes treat their channels differently when idle. Let the mux core have this information to make it available for internal use. Reuse the same state values used by CONFIG_MULTIPLEXER. Possible idle states are: - MUX_IDLE_AS_IS: Leave channels as is when idle - MUX_IDLE_DISCONNECT: Disconnect channel (set HiZ when idle) - : Enable channel n when idle Default value is set to MUX_IDLE_AS_IS. Signed-off-by: Marcus Folkesson --- drivers/i2c/i2c-mux.c | 1 + include/linux/i2c-mux.h | 21 +++++++++++++++++++++ 2 files changed, 22 insertions(+) diff --git a/drivers/i2c/i2c-mux.c b/drivers/i2c/i2c-mux.c index 4d8690981a55dc0e1b35454971923791e6ed9f7f..5caa927c0caae512af029f0d1ae= 9b7f845ba3f6f 100644 --- a/drivers/i2c/i2c-mux.c +++ b/drivers/i2c/i2c-mux.c @@ -250,6 +250,7 @@ struct i2c_mux_core *i2c_mux_alloc(struct i2c_adapter *= parent, muxc->select =3D select; muxc->deselect =3D deselect; muxc->max_adapters =3D max_adapters; + muxc->idle_state =3D MUX_IDLE_AS_IS; =20 return muxc; } diff --git a/include/linux/i2c-mux.h b/include/linux/i2c-mux.h index 1784ac7afb116ce64e9e9fca1ee127c2bbbd2fb9..9e230ad69377b74f9ec809c40cc= ffd95538c4595 100644 --- a/include/linux/i2c-mux.h +++ b/include/linux/i2c-mux.h @@ -13,6 +13,7 @@ =20 #ifdef __KERNEL__ =20 +#include #include =20 struct i2c_mux_core { @@ -22,6 +23,12 @@ struct i2c_mux_core { unsigned int arbitrator:1; unsigned int gate:1; =20 + /* + * The mux controller state to use when inactive, or one + * of MUX_IDLE_AS_IS and MUX_IDLE_DISCONNECT. + */ + int idle_state; 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[83.233.6.197]) by smtp.gmail.com with ESMTPSA id 38308e7fff4ca-361a99e99e6sm26982661fa.56.2025.09.21.23.21.43 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Sun, 21 Sep 2025 23:21:43 -0700 (PDT) From: Marcus Folkesson Date: Mon, 22 Sep 2025 08:20:58 +0200 Subject: [PATCH RFC 3/7] i2c: mux: add support for per channel bus frequency Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Content-Transfer-Encoding: quoted-printable Message-Id: <20250922-i2c-mux-v1-3-28c94a610930@gmail.com> References: <20250922-i2c-mux-v1-0-28c94a610930@gmail.com> In-Reply-To: <20250922-i2c-mux-v1-0-28c94a610930@gmail.com> To: Wolfram Sang , Peter Rosin , Michael Hennerich , Bartosz Golaszewski , Andi Shyti Cc: linux-i2c@vger.kernel.org, linux-kernel@vger.kernel.org, linux-arm-kernel@lists.infradead.org, Marcus Folkesson X-Mailer: b4 0.14.2 X-Developer-Signature: v=1; a=openpgp-sha256; l=7882; i=marcus.folkesson@gmail.com; h=from:subject:message-id; bh=UBc7AM0gSO9uZhPLncPbz9SMwH2LrhqeMCqUzN/cGpE=; b=owEBbQKS/ZANAwAKAYiATm9ZXVIyAcsmYgBo0OrY/VgoJ03b/XE53W/Fnnp6hsxPEZWuFyY6f vBnSPuSdf6JAjMEAAEKAB0WIQQFUaLotmy1TWTBLGWIgE5vWV1SMgUCaNDq2AAKCRCIgE5vWV1S MrkmD/9WfPS3fCHXOXE4yGJNyYvFXKN9UpVrhDhni7B6ty7jOOKH85wVttq4AMIyfLo6qIU2NOo jaq7UDZRrjT5KdEb5rECLnqXWVhRgv81m5zXHJFlIoz4+HMeMlZ9SuAaOXI+OVT4kckpZ6Ma1Ee cfRKdMuhEY94TOROSzvRWXrI+bwbVLPpBjeI3ue1wrOEPGbbfBwnduUdA+/xsrOJlcNSrxeCdal 9IXeUHKW6eyIQX2j8qA2So3LIF6/GzPNMxdifLaIu4x8j7lStkuRvzhIR1BuKdPJ8WMMgevEmkZ cHX0oEx30f4GqPHyxwqbhFRDgYtQSjfP4bygPkNRKGT29Ar/1wVpHFDl+daCTC59sorkguQ3RdY npO6dYo2POofexUJyMkLRFYI9VWTQQJOWxJgsFt0XSaaBRYE+/mkAWqfbE3AxmKqSXqGwf9SjnW W0Ygrfc07saUkVWZYRkJIgKMbs82ROnB9UcBOXc8MGjXZe9vnunvlnzfk3jwHSQM9ymwNmJqrDL kvXmTZDFjZ+i3xQQn8gFTWO1HcfBnrIRn1T+gQ48LNlAsbiiaJ1V+mcLsM0iKZQ6pSKB5yecx/N 1rdHH8xi/HtxRIMXJr4wWowsF9S8KKCFDPWXCapkyxXsfLsrqdUhk9eJtvx4ApVHaNE6h6hu1Ao 7DlYHhMUf6Dil4g== X-Developer-Key: i=marcus.folkesson@gmail.com; a=openpgp; fpr=AB91D46C7E0F6E6FB2AB640EC0FE25D598F6C127 There could be several reasons why you may need to use a certain speed on an I2C bus. E.g. - When several devices are attached to the bus, the speed must be selected according to the slowest device. - Electrical conditions may limit the usuable speed on the bus for different reasons. With an I2C multiplexer, it is possible to group the attached devices after their preferred speed by e.g. put all "slow" devices on a separate channel on the multiplexer. Consider the following topology: .----------. 100kHz .--------. .--------. 400kHz | |--------| dev D1 | | root |--+-----| I2C MUX | '--------' '--------' | | |--. 400kHz .--------. | '----------' '-------| dev D2 | | .--------. '--------' '--| dev D3 | '--------' One requirement with this design is that a multiplexer may only use the same or lower bus speed as its parent. Otherwise, if the multiplexer would have to increase the bus frequency, then all siblings (D3 in this case) would run into a clock speed it may not support. The bus frequency for each channel is set in the devicetree. As the i2c-mux bindings import the i2c-controller schema, the clock-frequency property is already allowed. If no clock-frequency property is set, the channel inherit their parent bus speed. The following example uses dt bindings to illustrate the topology above: i2c { clock-frequency =3D <400000>; i2c-mux { i2c@0 { clock-frequency =3D <100000>; D1 { ... }; }; i2c@1 { D2 { ... }; }; }; D3 { ... } }; Signed-off-by: Marcus Folkesson --- drivers/i2c/i2c-mux.c | 126 +++++++++++++++++++++++++++++++++++++++++++++-= ---- 1 file changed, 114 insertions(+), 12 deletions(-) diff --git a/drivers/i2c/i2c-mux.c b/drivers/i2c/i2c-mux.c index 5caa927c0caae512af029f0d1ae9b7f845ba3f6f..22b404597ff91eddb965c48112f= dc63250d71e43 100644 --- a/drivers/i2c/i2c-mux.c +++ b/drivers/i2c/i2c-mux.c @@ -36,6 +36,72 @@ struct i2c_mux_priv { u32 chan_id; }; =20 +static int i2c_mux_select_chan(struct i2c_adapter *adap, u32 chan_id) +{ + struct i2c_mux_priv *priv =3D adap->algo_data; + struct i2c_mux_core *muxc =3D priv->muxc; + struct i2c_adapter *parent =3D muxc->parent; + struct i2c_adapter *root; + int ret; + + if (priv->adap.clock_hz && priv->adap.clock_hz !=3D parent->clock_hz) { + root =3D i2c_root_adapter(&adap->dev); + + /* if we are parent-locked and the root adapter is our parent, + * we already have the lock we need. Otherwise take the bus lock for the= root + * adaper before changing bus clock. + */ + if ((root !=3D parent && !muxc->mux_locked) || muxc->mux_locked) + i2c_lock_bus(parent, I2C_LOCK_ROOT_ADAPTER); + + ret =3D i2c_adapter_set_clk_freq(root, priv->adap.clock_hz); + + if ((root !=3D parent && !muxc->mux_locked) || muxc->mux_locked) + i2c_unlock_bus(parent, I2C_LOCK_ROOT_ADAPTER); + + if (ret < 0) { + dev_err(&adap->dev, + "Failed to set clock frequency %dHz on root adapter %s: %d\n", + priv->adap.clock_hz, root->name, ret); + + return ret; + } + } + + return muxc->select(muxc, priv->chan_id); +} + +static void i2c_mux_deselect_chan(struct i2c_adapter *adap, u32 chan_id) +{ + struct i2c_mux_priv *priv =3D adap->algo_data; + struct i2c_mux_core *muxc =3D priv->muxc; + struct i2c_adapter *parent =3D muxc->parent; + struct i2c_adapter *root; + int ret; + + if (parent->clock_hz && parent->clock_hz !=3D priv->adap.clock_hz) { + root =3D i2c_root_adapter(&parent->dev); + + /* if we are parent-locked and the root adapter is our parent, + * we already have the lock we need. Otherwise take the bus lock for the= root + * adaper before changing bus clock. + */ + if ((root !=3D parent && !muxc->mux_locked) || muxc->mux_locked) + i2c_lock_bus(parent, I2C_LOCK_ROOT_ADAPTER); + + ret =3D i2c_adapter_set_clk_freq(root, parent->clock_hz); + + if ((root !=3D parent && !muxc->mux_locked) || muxc->mux_locked) + i2c_unlock_bus(parent, I2C_LOCK_ROOT_ADAPTER); + + if (ret < 0) + return; + } + + if (muxc->deselect) + muxc->deselect(muxc, priv->chan_id); +} + static int __i2c_mux_master_xfer(struct i2c_adapter *adap, struct i2c_msg msgs[], int num) { @@ -46,11 +112,11 @@ static int __i2c_mux_master_xfer(struct i2c_adapter *a= dap, =20 /* Switch to the right mux port and perform the transfer. */ =20 - ret =3D muxc->select(muxc, priv->chan_id); + ret =3D i2c_mux_select_chan(adap, priv->chan_id); if (ret >=3D 0) ret =3D __i2c_transfer(parent, msgs, num); - if (muxc->deselect) - muxc->deselect(muxc, priv->chan_id); + + i2c_mux_deselect_chan(adap, priv->chan_id); =20 return ret; } @@ -65,11 +131,11 @@ static int i2c_mux_master_xfer(struct i2c_adapter *ada= p, =20 /* Switch to the right mux port and perform the transfer. */ =20 - ret =3D muxc->select(muxc, priv->chan_id); + ret =3D i2c_mux_select_chan(adap, priv->chan_id); if (ret >=3D 0) ret =3D i2c_transfer(parent, msgs, num); - if (muxc->deselect) - muxc->deselect(muxc, priv->chan_id); + + i2c_mux_deselect_chan(adap, priv->chan_id); =20 return ret; } @@ -86,12 +152,12 @@ static int __i2c_mux_smbus_xfer(struct i2c_adapter *ad= ap, =20 /* Select the right mux port and perform the transfer. */ =20 - ret =3D muxc->select(muxc, priv->chan_id); + ret =3D i2c_mux_select_chan(adap, priv->chan_id); if (ret >=3D 0) ret =3D __i2c_smbus_xfer(parent, addr, flags, read_write, command, size, data); - if (muxc->deselect) - muxc->deselect(muxc, priv->chan_id); + + i2c_mux_deselect_chan(adap, priv->chan_id); =20 return ret; } @@ -108,12 +174,12 @@ static int i2c_mux_smbus_xfer(struct i2c_adapter *ada= p, =20 /* Select the right mux port and perform the transfer. */ =20 - ret =3D muxc->select(muxc, priv->chan_id); + ret =3D i2c_mux_select_chan(adap, priv->chan_id); if (ret >=3D 0) ret =3D i2c_smbus_xfer(parent, addr, flags, read_write, command, size, data); - if (muxc->deselect) - muxc->deselect(muxc, priv->chan_id); + + i2c_mux_deselect_chan(adap, priv->chan_id); =20 return ret; } @@ -366,6 +432,42 @@ int i2c_mux_add_adapter(struct i2c_mux_core *muxc, } } =20 + of_property_read_u32(child, "clock-frequency", &priv->adap.clock_hz); + + /* + * Warn if the mux adapter does not disconnect channels or + * if a low-speed channel is seleced during idle. + */ + if (priv->adap.clock_hz < parent->clock_hz) + if (muxc->idle_state !=3D MUX_IDLE_DISCONNECT || + muxc->idle_state =3D=3D chan_id) + dev_warn(muxc->dev, + "channel %u has improper idle state for this configuration\n", + chan_id); + + /* + * Warn if the mux adapter is not parent-locked as + * this may cause issues for some hardware topologies. + */ + if ((priv->adap.clock_hz < parent->clock_hz) && muxc->mux_locked) + dev_warn(muxc->dev, + "channel %u is slower than parent on a non parent-locked mux\n", + chan_id); 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[83.233.6.197]) by smtp.gmail.com with ESMTPSA id 38308e7fff4ca-361a99e99e6sm26982661fa.56.2025.09.21.23.21.44 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Sun, 21 Sep 2025 23:21:45 -0700 (PDT) From: Marcus Folkesson Date: Mon, 22 Sep 2025 08:20:59 +0200 Subject: [PATCH RFC 4/7] i2c: mux: ltc4306: set correct idle_state in i2c_mux_core Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Content-Transfer-Encoding: quoted-printable Message-Id: <20250922-i2c-mux-v1-4-28c94a610930@gmail.com> References: <20250922-i2c-mux-v1-0-28c94a610930@gmail.com> In-Reply-To: <20250922-i2c-mux-v1-0-28c94a610930@gmail.com> To: Wolfram Sang , Peter Rosin , Michael Hennerich , Bartosz Golaszewski , Andi Shyti Cc: linux-i2c@vger.kernel.org, linux-kernel@vger.kernel.org, linux-arm-kernel@lists.infradead.org, Marcus Folkesson X-Mailer: b4 0.14.2 X-Developer-Signature: v=1; a=openpgp-sha256; l=819; i=marcus.folkesson@gmail.com; h=from:subject:message-id; bh=vT3u8z9JcPm3Zs8qxToNt2XUMMG8ua9os0KJiBxmsh8=; b=owEBbQKS/ZANAwAKAYiATm9ZXVIyAcsmYgBo0Ordh5iitf7lhHDQuSZr1/thsDJsbdWjg0XOg w5s41jghYeJAjMEAAEKAB0WIQQFUaLotmy1TWTBLGWIgE5vWV1SMgUCaNDq3QAKCRCIgE5vWV1S Mr4lD/9vC0aI7ksGmf/RIn+tZapTkPe+1EzpkMWshsqYVRseYTMjwPNSWhNoadhZpl4uv1XkhRK jfx90FCx+DXpNmTq3H7JLiKXnfeND1ZXP6cv95bzahIeY8ROtyD4KeM0nv3Eg4NHuqTum6qa2op G1pI0RXDimCosrtTHf9DQfbCNzh+V8UHjwqOuA5Gm2Sp0GomcF81p1g7QVz+NGxrK7xcXzU6GL6 x6xw0KL7K21jspYgtQQh8G+ux7qNoOTNDXpfcMP31ELwrzGufFJ9+dZ5efLA2Ounoi9FgXZriRH UpqS5twxNLEsgDXH6u8of49OpszwtePa+eeyt07v2iSNXcGniBFH2G3gWNVMVKfm5wUxyFAcSxG I+0tS/pDv/4Fi7inJjodbf+LhaTNDeE4SgB6Cj2PnsHoe/we0sNDXlAOVATU3dQTR/9qvMFn4Tz LWoTwEAhLhk/TU5dFL4Jwq2K7fotTPfk4luf/kdVbM508nUhhNk8Jd5nHYIonroOf8+7KyCKGiu puAoOpKJ2I5lp96pzH1oaYo6I4ZjzYFRMrYMy2DBEnhCibitR3H+WNFy0e/aqUTn5HWY2MCneOP //RzjrAVI7AfGJ6X5aYGzA2nh2hyAbFoYOXsa880k5YPzvJUjskNlHR9/oVNNS9UfLnpMhKw03V ybfzSp8q1qX5Zwg== X-Developer-Key: i=marcus.folkesson@gmail.com; a=openpgp; fpr=AB91D46C7E0F6E6FB2AB640EC0FE25D598F6C127 Inform the core if we intend to disconnect channels during idle. Signed-off-by: Marcus Folkesson --- drivers/i2c/muxes/i2c-mux-ltc4306.c | 3 +++ 1 file changed, 3 insertions(+) diff --git a/drivers/i2c/muxes/i2c-mux-ltc4306.c b/drivers/i2c/muxes/i2c-mu= x-ltc4306.c index 50fbc0d06e62b2743dd7f20c9863d56009dcf0e9..4e81002e2e4d6c63f13cf44e165= 81aff836f7d4f 100644 --- a/drivers/i2c/muxes/i2c-mux-ltc4306.c +++ b/drivers/i2c/muxes/i2c-mux-ltc4306.c @@ -232,6 +232,9 @@ static int ltc4306_probe(struct i2c_client *client) data =3D i2c_mux_priv(muxc); data->chip =3D chip; =20 + if (idle_disc) + i2c_mux_set_idle_state(muxc, MUX_IDLE_DISCONNECT); + i2c_set_clientdata(client, muxc); =20 data->regmap =3D devm_regmap_init_i2c(client, <c4306_regmap_config); --=20 2.50.1 From nobody Thu Oct 2 04:44:14 2025 Received: from mail-lj1-f179.google.com (mail-lj1-f179.google.com [209.85.208.179]) (using TLSv1.2 with cipher ECDHE-RSA-AES128-GCM-SHA256 (128/128 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id B2CBA2F0690 for ; Mon, 22 Sep 2025 06:21:49 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=none smtp.client-ip=209.85.208.179 ARC-Seal: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1758522111; cv=none; b=Hdf3sYQN1Wk0dtX9xD0IgNzkdBlkK0OaXNtXXKwRvdB7Uu6SkIgIIXD9dBXN1so5KRuW3glUxqW8mkogqsWg2d9LsgOhx+RSDBCeH9/WSkyyTQ21WLvr7A1/mffNqu+PvRcD1FDODwTOqWNr/SQchteZju/vDVOsQqNrfUyO+uk= ARC-Message-Signature: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1758522111; c=relaxed/simple; bh=MjUg8WhC2ePO7Wob4lthvdC2KmnV9Son3CvTOIR4tgM=; h=From:Date:Subject:MIME-Version:Content-Type:Message-Id:References: In-Reply-To:To:Cc; b=B3zAV6iY+1Rg+8aNeS+d39NNl60g1pUVZnFXQKMOZYADt5lcYKRIxR7fKrxHzbsYfRWTWOrEZV8e9tSp0GTUiJp2NyQUyEaIienmAjb/NO6MWVDhcr+REDhOdXLRIkS+NuA5grJ3pKzPgjr8YGOita3eI9SvYW82/A2KVs2gWhM= ARC-Authentication-Results: i=1; smtp.subspace.kernel.org; dmarc=pass (p=none dis=none) header.from=gmail.com; spf=pass smtp.mailfrom=gmail.com; dkim=pass (2048-bit key) header.d=gmail.com header.i=@gmail.com header.b=L/yOXj5n; arc=none smtp.client-ip=209.85.208.179 Authentication-Results: smtp.subspace.kernel.org; dmarc=pass (p=none dis=none) header.from=gmail.com Authentication-Results: smtp.subspace.kernel.org; spf=pass smtp.mailfrom=gmail.com Authentication-Results: smtp.subspace.kernel.org; dkim=pass (2048-bit key) header.d=gmail.com header.i=@gmail.com header.b="L/yOXj5n" Received: by mail-lj1-f179.google.com with SMTP id 38308e7fff4ca-3515a0bca13so50144371fa.1 for ; Sun, 21 Sep 2025 23:21:49 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=gmail.com; s=20230601; t=1758522108; x=1759126908; darn=vger.kernel.org; h=cc:to:in-reply-to:references:message-id:content-transfer-encoding :mime-version:subject:date:from:from:to:cc:subject:date:message-id :reply-to; bh=HMp6cqsu59t8PToCUbyQtsreHZbwaZi5QAyb9viAGjk=; b=L/yOXj5nQOVjyRVrIUWRbHkuVph6+HTn3TyieHte6AXZxtM+J+ugxxWL4SowKl5QC3 2U9A0WnDAJWr+/3rahUm+vh9r0RBJ3VCmeDEvA8SVe+SZfraqo/cqZ2t3V38IRZkru/V qlFYfmwUTMq8kJIrnTO4dUCA+USJfNAvFLz1u94FdFBVfWj1acmR7ckBKFXxXH8Dguru 0YUYQZ9+Az7K87RlsfTv6S9yy5mVnRpyYtnQ50+vCZmtDxjBgTUoaB8TsPjqWSSbtCNo OwE0OCnojlFwiQiCnMfUkhCaZsvCP13n586z9U8sZkPDeGNKhsd2OcTevs0NFyrfouQr ZMpw== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20230601; t=1758522108; x=1759126908; h=cc:to:in-reply-to:references:message-id:content-transfer-encoding :mime-version:subject:date:from:x-gm-message-state:from:to:cc :subject:date:message-id:reply-to; bh=HMp6cqsu59t8PToCUbyQtsreHZbwaZi5QAyb9viAGjk=; b=fMvV88GXxtNSpSIssVi9/9JMirRRMkvZkuvT6LVyWE2QcZUHWKc9LhMHyQGPbwNbfX Nv/wsewYmIP+DrWVZnrkLznXsfUG7C7MIOZMDtB91TofRGoC/OagA7lmFwNipJhCNHYM QFg92T2p5REZiM5hQp92YdJYWsd9XwwUqXVxuI/zI53iyWX7RBOzd3G1MIJZ3RqQH5qr 21pc5CAtI9smSc2nvyK+qKcm9iCypHmsH6NXUrPepUUlJDuy2b0COvK11AK5dHLX1bw8 D6wdLW7B6/QJSXo4b2cGKUTKFyWJSioTM2b7fhyIsEzBRpsWSi1I3DFubjDGYok6Jec/ Nzxg== X-Forwarded-Encrypted: i=1; AJvYcCXpn1M+SWpiZP9SNjJi+G+SmVW4CX5Vyq4Zm4+1KvaYfqnAANT0vcpY/gALAclDA9nMei41/zuRzMAV7pg=@vger.kernel.org X-Gm-Message-State: AOJu0YziYh2i2G05pKvTLejJKH16y5bDgGEzSIqR/MkGHLsitaibsn8G CD2bhTcTvdGA4CsdvdZJijWF5F5PL/c2w70EBphSf+NgfFPAcRbkBDrZ X-Gm-Gg: ASbGncvwccDnAGNWkUpE2MCFziPbBpi8q5WgaluYBX2hwr6OoMPelcM4vyr1yDh89Zz 0/ZfTvYBkFfKZhPVerIM63+2m71bhMtV+Z/vm1llV6A4boInTeEa1RVvpIOSN4pOx9yex9A+tUG 1ODRgwyIDbbkKP9bjRFLHyrGpqFeIwiPd1GjNT2z8bAy6d4URCluPe6O5lCHgus4IesHknbFLLf E1+5V41DpfAv787syFDyt9IkKZYuraEv5cqY44nlohjoJC9m9i/Wm1SKggF+3eC65xx/R89GLzV E5NYOEmwBV22NPWPr2LCaY5LfUtORyrfcYSjPNZG0EjzgvDAT4vVk+hoYB2LG7GrtweBm9ihtml rLsalKCzeuVh8JJh0xjPrTnEmZCB28hgPW7FawSStWz/bvdBoyqfY+UQ4rRsr+bOaywA= X-Google-Smtp-Source: AGHT+IF0vsidL+U2+O4cbI2W93e2V78iTNBrbec39/ev2fwTbSY9pJ2C+RDb5OzOvmi4WTyIjP7dAA== X-Received: by 2002:a05:651c:4014:b0:336:cf86:d405 with SMTP id 38308e7fff4ca-3640b95714fmr22173211fa.18.1758522107716; Sun, 21 Sep 2025 23:21:47 -0700 (PDT) Received: from [192.168.1.166] (83-233-6-197.cust.bredband2.com. [83.233.6.197]) by smtp.gmail.com with ESMTPSA id 38308e7fff4ca-361a99e99e6sm26982661fa.56.2025.09.21.23.21.46 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Sun, 21 Sep 2025 23:21:47 -0700 (PDT) From: Marcus Folkesson Date: Mon, 22 Sep 2025 08:21:00 +0200 Subject: [PATCH RFC 5/7] i2c: davinci: calculate bus freq from Hz instead of kHz Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Content-Transfer-Encoding: quoted-printable Message-Id: <20250922-i2c-mux-v1-5-28c94a610930@gmail.com> References: <20250922-i2c-mux-v1-0-28c94a610930@gmail.com> In-Reply-To: <20250922-i2c-mux-v1-0-28c94a610930@gmail.com> To: Wolfram Sang , Peter Rosin , Michael Hennerich , Bartosz Golaszewski , Andi Shyti Cc: linux-i2c@vger.kernel.org, linux-kernel@vger.kernel.org, linux-arm-kernel@lists.infradead.org, Marcus Folkesson X-Mailer: b4 0.14.2 X-Developer-Signature: v=1; a=openpgp-sha256; l=2503; i=marcus.folkesson@gmail.com; h=from:subject:message-id; bh=MjUg8WhC2ePO7Wob4lthvdC2KmnV9Son3CvTOIR4tgM=; b=owEBbQKS/ZANAwAKAYiATm9ZXVIyAcsmYgBo0OricZTm/oAQ1+OD0EJGMjU7LFDFZX9qnJlff VHGUBLiknSJAjMEAAEKAB0WIQQFUaLotmy1TWTBLGWIgE5vWV1SMgUCaNDq4gAKCRCIgE5vWV1S MqW5EACBIOGR2Psx5ihNOOXVUpFaHO0xoSUdfph8wVOTYoK4bHA6EJ+dajDjeB81BQiKnzqdROJ q5KO8MrXyBQOclZ6ZLUo9ShVbfDBLkmEsMMmgQ1OwCAItwKVGIbWEoMaL2JkaqE1MN3aM9JJMwF XiocyRzYo7MfQYcQ9fF2MFW9/s3JjQWxNcOxFtRTQL/uiAvShs7xo1qSd9o1MwuYADaOCf5nxtG ok8vGe3ppH1WqTEH2BXlo65q16WaJWibq0cYf2lBoS6pdaXk8AMRZR/S8HqU8riZXZI9Cl6MC3u DaAX4ErhFEgocKTATdFujAYb0uEC8yB1C+Flti/MUX1Hq+qCESRlvj3/FxcFZvsHer7BpT8gZ/N 6ajT1mb+IGjja3U+5vI38z7m+dwvub5O9998V9YxIelT80lQIMQJ84zVAHsJMAm92OBioY/vjyJ glvT0P2t+4BzSMhVVYqYfjFA6dMxqO6vJxLOdX5Z/EMO7HvfYMx8YbZCIkC+iH0PBNhXRPBJtng RqSEu2UMfmAtM33aYuTmM5iDA3QXxOTzF/YFaS2kiMQQGD1+22KcXDYTAJ8105ixvvyuGiUtWfI HyovMLr+YwvPkRfBuTpaCCqEdDM94RAoOo+2BPLHvYOt6Tl3i8r+9UaNtVGyYD2K48gOi4XORrO NT1P0BrqB2o4r6Q== X-Developer-Key: i=marcus.folkesson@gmail.com; a=openpgp; fpr=AB91D46C7E0F6E6FB2AB640EC0FE25D598F6C127 The bus frequency is unnecessarily converted between Hz and kHz in several places. This is probably an old legacy from the old times (pre-devicetrees) when the davinci_i2c_platform_data took the bus_freq in kHz. Stick to Hz. Signed-off-by: Marcus Folkesson --- drivers/i2c/busses/i2c-davinci.c | 14 ++++++-------- 1 file changed, 6 insertions(+), 8 deletions(-) diff --git a/drivers/i2c/busses/i2c-davinci.c b/drivers/i2c/busses/i2c-davi= nci.c index 6a3d4e9e07f45ecc228943e877cde1fd9d72e8cb..6b18938457d0c5cabc323c364d9= 330c2890df107 100644 --- a/drivers/i2c/busses/i2c-davinci.c +++ b/drivers/i2c/busses/i2c-davinci.c @@ -117,8 +117,6 @@ /* timeout for pm runtime autosuspend */ #define DAVINCI_I2C_PM_TIMEOUT 1000 /* ms */ =20 -#define DAVINCI_I2C_DEFAULT_BUS_FREQ 100 - struct davinci_i2c_dev { struct device *dev; void __iomem *base; @@ -209,16 +207,16 @@ static void i2c_davinci_calc_clk_dividers(struct davi= nci_i2c_dev *dev) if (device_is_compatible(dev->dev, "ti,keystone-i2c")) d =3D 6; =20 - clk =3D ((input_clock / (psc + 1)) / (dev->bus_freq * 1000)); + clk =3D ((input_clock / (psc + 1)) / (dev->bus_freq)); /* Avoid driving the bus too fast because of rounding errors above */ - if (input_clock / (psc + 1) / clk > dev->bus_freq * 1000) + if (input_clock / (psc + 1) / clk > dev->bus_freq) clk++; /* * According to I2C-BUS Spec 2.1, in FAST-MODE LOW period should be at * least 1.3uS, which is not the case with 50% duty cycle. Driving HIGH * to LOW ratio as 1 to 2 is more safe. */ - if (dev->bus_freq > 100) + if (dev->bus_freq > 100000) clkl =3D (clk << 1) / 3; else clkl =3D (clk >> 1); @@ -269,7 +267,7 @@ static int i2c_davinci_init(struct davinci_i2c_dev *dev) davinci_i2c_read_reg(dev, DAVINCI_I2C_CLKL_REG)); dev_dbg(dev->dev, "CLKH =3D %d\n", davinci_i2c_read_reg(dev, DAVINCI_I2C_CLKH_REG)); - dev_dbg(dev->dev, "bus_freq =3D %dkHz\n", dev->bus_freq); + dev_dbg(dev->dev, "bus_freq =3D %dHz\n", dev->bus_freq); =20 =20 /* Take the I2C module out of reset: */ @@ -761,9 +759,9 @@ static int davinci_i2c_probe(struct platform_device *pd= ev) =20 r =3D device_property_read_u32(&pdev->dev, "clock-frequency", &prop); if (r) - prop =3D DAVINCI_I2C_DEFAULT_BUS_FREQ; + prop =3D I2C_MAX_STANDARD_MODE_FREQ; =20 - dev->bus_freq =3D prop / 1000; + dev->bus_freq =3D prop; =20 dev->has_pfunc =3D device_property_present(&pdev->dev, "ti,has-pfunc"); =20 --=20 2.50.1 From nobody Thu Oct 2 04:44:14 2025 Received: from mail-lj1-f181.google.com (mail-lj1-f181.google.com [209.85.208.181]) (using TLSv1.2 with cipher ECDHE-RSA-AES128-GCM-SHA256 (128/128 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id 3D0592F1FC3 for ; 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Signed-off-by: Marcus Folkesson Acked-by: Bartosz Golaszewski --- drivers/i2c/busses/i2c-davinci.c | 23 +++++++++++++++++++++++ 1 file changed, 23 insertions(+) diff --git a/drivers/i2c/busses/i2c-davinci.c b/drivers/i2c/busses/i2c-davi= nci.c index 6b18938457d0c5cabc323c364d9330c2890df107..d3e47738f8ee7e8f69fee49509d= cda396c9b7fb6 100644 --- a/drivers/i2c/busses/i2c-davinci.c +++ b/drivers/i2c/busses/i2c-davinci.c @@ -279,6 +279,27 @@ static int i2c_davinci_init(struct davinci_i2c_dev *de= v) return 0; } =20 +static int davinci_i2c_set_clk(struct i2c_adapter *adap, u32 clock_hz) +{ + struct davinci_i2c_dev *dev =3D i2c_get_adapdata(adap); + + if (dev->bus_freq =3D=3D clock_hz) + return 0; + + dev->bus_freq =3D clock_hz; + + /* put I2C into reset */ + davinci_i2c_reset_ctrl(dev, 0); + + /* compute clock dividers */ + i2c_davinci_calc_clk_dividers(dev); + + /* Take the I2C module out of reset: */ + davinci_i2c_reset_ctrl(dev, 1); + + return 0; +} + /* * This routine does i2c bus recovery by using i2c_generic_scl_recovery * which is provided by I2C Bus recovery infrastructure. @@ -810,6 +831,8 @@ static int davinci_i2c_probe(struct platform_device *pd= ev) adap->dev.parent =3D &pdev->dev; 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[83.233.6.197]) by smtp.gmail.com with ESMTPSA id 38308e7fff4ca-361a99e99e6sm26982661fa.56.2025.09.21.23.21.49 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Sun, 21 Sep 2025 23:21:50 -0700 (PDT) From: Marcus Folkesson Date: Mon, 22 Sep 2025 08:21:02 +0200 Subject: [PATCH RFC 7/7] docs: i2c: i2c-topology: add section about bus speed Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Content-Transfer-Encoding: quoted-printable Message-Id: <20250922-i2c-mux-v1-7-28c94a610930@gmail.com> References: <20250922-i2c-mux-v1-0-28c94a610930@gmail.com> In-Reply-To: <20250922-i2c-mux-v1-0-28c94a610930@gmail.com> To: Wolfram Sang , Peter Rosin , Michael Hennerich , Bartosz Golaszewski , Andi Shyti Cc: linux-i2c@vger.kernel.org, linux-kernel@vger.kernel.org, linux-arm-kernel@lists.infradead.org, Marcus Folkesson X-Mailer: b4 0.14.2 X-Developer-Signature: v=1; a=openpgp-sha256; l=8207; i=marcus.folkesson@gmail.com; h=from:subject:message-id; bh=S7HyOptvlFZG+2Q7UACyCuq7yJ1BzDh+UGhw42y2UVE=; b=owEBbQKS/ZANAwAKAYiATm9ZXVIyAcsmYgBo0OrsQeH/4jt8AADCJJyWsja9PeShuzxIPhK2N ReEuabziq6JAjMEAAEKAB0WIQQFUaLotmy1TWTBLGWIgE5vWV1SMgUCaNDq7AAKCRCIgE5vWV1S MrL8EAC71SR0gv0PMX2fkCz6yQlh2q10PmcUOvMym57YsKUaU6uYOnPodRtxThthpqvd0SLlPe5 9JuEl0zRpP1S+J2Hx3Tc3KAEz/aki4zF+S4kEUlWn6cAsq73U5qHxhcbIGe2/d6wRR/0F6i9KWP x6a54MHoJeMWa9a+1xP2kPqqcTWyZMhfe7LYeci5eLqjplD99203lcCzbZYm2gtVXwyfikEHpin 9RJrrJr8xv/a6LA/1soMj1u3mXbEnPP7hrDCQy3b3PjO2oX17LNulfi+Wh9AY62tITR9R9rOFQU P3hMEUnFPRJWU2UgQZ0c1P6Q1SqwsSRxncNf9edn+1gi9bnMMKTqUn5t6avCQyJhR9y7/W1oPq1 jA4aewAG/TITkhKn0xBpfdA3MBiaPWR17McEEYGt1oZa7yKYWpmmVhbJWi+rRm4+Lfm605hPd2Q 6CvIF3ejobCKXMagRW8SUO+hXaipbHKbjwi1E8iFFESRDH7Cx0ewM4N2YEi51w6EaWAd6LQZFLM 87dLaMjehPMdEN9hLzAo78NRJiliy8AiQ1ze/bzehww5cozuRYgOpl9Xg885z5KKDX514HI+Os+ cB40NlNalpBbn/hGVBX08Et23lJEUccmCpXvNbrYEhdGLghYEouK/fWtj64pxNmT6iukF1EX9iN 1AlG9a3DvERIcIg== X-Developer-Key: i=marcus.folkesson@gmail.com; a=openpgp; fpr=AB91D46C7E0F6E6FB2AB640EC0FE25D598F6C127 Describe what needs to be consideraed and taken into account when using different bus speeds for different mux channels. Signed-off-by: Marcus Folkesson --- Documentation/i2c/i2c-topology.rst | 176 +++++++++++++++++++++++++++++++++= ++++ 1 file changed, 176 insertions(+) diff --git a/Documentation/i2c/i2c-topology.rst b/Documentation/i2c/i2c-top= ology.rst index 48fce0f7491bf1bcd4a851f685b010386c9ce0d2..362859b5de224272941576a9c82= a04843e56f0d0 100644 --- a/Documentation/i2c/i2c-topology.rst +++ b/Documentation/i2c/i2c-topology.rst @@ -367,6 +367,182 @@ When D1 or D2 are accessed, accesses to D3 and D4 are= locked out while accesses to D5 may interleave. When D3 or D4 are accessed, accesses to all other devices are locked out. =20 +Bus Speed and I2C Multiplexers +=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D= =3D=3D=3D=3D=3D=3D=3D=3D + +I2C bus multiplexers allows multiple downstream channels to be exposed +as separate I2C adapters which also could set their own bus speed. + +The multiplexer itself cannot change the bus speed as it use the upstream +clock and data lines to communicate with the downstream devices. The speed +is therfor changed in the root adapter resulting in that the whole bus is +affected. + +This increases the complexity of the topology and some considerations must +be taken into. + +Bus speed +---------- + +Downstream channels of an I2C multiplexer can only operate at the same or +lower bus speed as the upstream bus. This is because the upstream bus may +have devices that cannot operate at higher speeds and those will be affect= ed +by the speed change. + +The example below illustrates the problem. +The root adapter is operating at 100kHz. D2 can only operate with 100kHz, +but D2 can operate at 400kHz. When D1 is selected, the bus speed of the +root adapter would have to be is set to 400kHz, a speed that D2 cannot sup= port. + +This topology is therefor not allowed: :: + + .----------. 400kHz .--------. + .--------. 100kHz | mux- |--------| dev D1 | + | root |--+-----| locked | '--------' + '--------' | | mux M1 | + | '----------' + | .--------. + '--| dev D2 | + '--------' + + +This topology is allowed: :: + + .----------. 100kHz .--------. + .--------. 400kHz | mux- |--------| dev D2 | + | root |--+-----| locked | '--------' + '--------' | mux M1 |--. 400kHz .--------. + '----------' '--------| dev D1 | + '--------' + +Preferred topology +------------------- + +The preferred topology when using different bus speeds is to have the mult= iplexer +connected directly to the root adapter without any devices as siblings. +By this arrangement, the bus speed can be changed without affecting any ot= her devices +and many of the caveats are avoided. + +Other multiplexers in parallell is still okay as those are locked out duri= ng transfers. + +This is the preferred topology: :: + + .----------. 100kHz .--------. + .--------. 400kHz | mux- |--------| dev D2 | + | root |--+-----| locked | '--------' + '--------' | mux M1 |--. 400kHz .--------. + '----------' '--------| dev D1 | + '--------' +Locking +-------- + +If the multiplexer is mux-locked, transfers to D3 may interleave between t= he +select-transfer-deselect to D1 or D2. +This results in a situation where the bus speed to D3 may be lower than it +can handle. This is usually not a problem. + +This topology is allowed but some transfers to D3 may be at 100kHz: :: + + .----------. 100kHz .--------. + .--------. 400kHz | mux- |--------| dev D1 | + | root |--+-----| locked | '--------' + '--------' | | mux M1 |--. 400kHz .--------. + | '----------' '--------| dev D2 | + | .--------. '--------' + '--| dev D3 | + '--------' + +Multiple muxes in series +-------------------------- + +When multiple muxes are used in series the same rules applies. + +Transfers to D3 may interleave between select-transfer-deselect to D1, whi= ch +results that the bus speed to D2 or D3 will be at 100KHz. + +Transfers to D2 may interleave between select-transfer-deselect to D1, whi= ch +results in that the bus speed to D1 may be at 400kHz as the transfer to D2 +will set the bus speed to before the transfer to D1 starts. + +This is probably a bad topology :: + + .----------. 400kHz .----------. 100kHz .--------. + .--------.400kHz | mux- |--------| mux- |--------| dev D1 | + | root |--+----| locked | 400kHz | locked | '--------' + '--------' | | mux M1 |--. | mux M2 | + | '----------' | '----------' + | .--------. | .--------. + '--| dev D3 | '--| dev D2 | + '--------' '--------' + +Multiple muxes in parallell +---------------------------- + +When multiple muxes are used in parallell all access to other muxes are lo= cked out +so this is not a problem. + +If the muxes are mux-locked, access to D3 may still interleave though. + +In the example below, D3 may not interleave between select-transfer-desele= ct for D1 +or D2 as both muxes are parent-locked: :: + + + .----------. 100kHz .--------. + | parent- |----------| dev D1 | + .--| locked | '--------' + | | mux M1 | + | '----------' + | .----------. 400KHz .--------. + .--------. 400kHz | parent- |---------| dev D2 | + | root |--+------| locked | '--------' + '--------' | | mux M2 | + | '----------' + | .--------. + '--| dev D3 | + '--------' + +Idle state +----------- + +Muxes have an idle state, which is the state the channels is put into when= no channel +is active. The state is typically one of the following: + +- All channels are disconnected +- The last selected channel is left as-is +- A predefined channel is selected + +Muxes that support an idle state where all channels are disconnected are p= referred when using +different bus speeds. Otherwise high bus speeds may "leak" through to devi= ces that +may not support that higher speed. + +Consider the following example: :: + + .----------. 100kHz .--------. + .--------. 400kHz | mux- |--------| dev D1 | + | root |--+-----| locked | '--------' + '--------' | | mux M1 |--. 400kHz .--------. + | '----------' '--------| dev D2 | + | .--------. '--------' + '--| dev D3 | + '--------' + +If the idle state of M1 is: +- All channels disconnected: No problem, D1 and D2 are not affected by com= munication + to D3. +- Last selected channel: Problem if D1 was the last selected channel. High= speed + communication to D3 will be "leaked" to D1. +- Predefined channel: Problem, if the predefined channel D1. Set predefine= d channel + to D2 as D2 may handle 400kHz. + +Supported controllers +----------------------- + +Not all I2C controllers support setting the bus speed dynamically. +At the time of writint, the following controllers has support: + +=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D= =3D=3D=3D=3D =3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D= =3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D +i2c-davinci Supports dynamic bus speed +=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D= =3D=3D=3D=3D =3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D= =3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D =20 Mux type of existing device drivers =3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D= =3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D --=20 2.50.1