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[103.229.16.4]) by smtp.gmail.com with ESMTPSA id d9443c01a7336-269800529cdsm123806865ad.22.2025.09.22.00.32.03 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Mon, 22 Sep 2025 00:32:05 -0700 (PDT) From: Jie Gan Date: Mon, 22 Sep 2025 15:31:39 +0800 Subject: [PATCH RFC 1/3] coresight: tmc: add the handle of the event to the path Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Content-Transfer-Encoding: quoted-printable Message-Id: <20250922-fix_helper_data-v1-1-905e8115a24e@oss.qualcomm.com> References: <20250922-fix_helper_data-v1-0-905e8115a24e@oss.qualcomm.com> In-Reply-To: <20250922-fix_helper_data-v1-0-905e8115a24e@oss.qualcomm.com> To: Carl Worth , Suzuki K Poulose , Mike Leach , James Clark , Alexander Shishkin , Jie Gan , Tingwei Zhang Cc: coresight@lists.linaro.org, linux-arm-kernel@lists.infradead.org, linux-kernel@vger.kernel.org X-Mailer: b4 0.14.0 X-Developer-Signature: v=1; a=ed25519-sha256; t=1758526319; l=2707; i=jie.gan@oss.qualcomm.com; s=20250909; h=from:subject:message-id; bh=tPjMdil7gxCwjC8YbC6YODeceMt/ZeL5Vyiw0lVmYeE=; b=4mpDNdSNuz9Jpo6MxISK9MiwQupv+EU8xwmuzB++YqlMXtb4VKLAWUNs3Jrz6rmmZ+PG0/aJl VZ9AJQs36h+CreAjWtqFq9ahKJi1iB85MmZ4ayZSfNNrTu4q7s2j3St X-Developer-Key: i=jie.gan@oss.qualcomm.com; a=ed25519; pk=3LxxUZRPCNkvPDlWOvXfJNqNO4SfGdy3eghMb8puHuk= X-Proofpoint-Spam-Details-Enc: AW1haW4tMjUwOTIwMDAzMiBTYWx0ZWRfX35bs1dGc2d/h To8cLGlWiG540g07RzIoR/ZTBv9CEikTQRIFE4s0Dwgb+EZIdvGD/Y5d/eriJN3xEggVE6SrJ8+ Uf3iXRw8w+6ckdElN8rEasAlEuDYOQ4QukJuDsNaxASQ9AHzj+ovBNeQ/ApqMXsBXt2Oi24U5LI 4R7a1gszhO0yujblr87sy9eQ8l7Keid5Umjh/CdKsjcKjDc/RP505cLZnW8luiIaOpQakjIcljd 1e3FDyOl2ZRK/4ouOuZeEBYe/6nbmmbxwlRIYKtQpUCir5ZwDSgJ02Gn67dWmLEG0wEiQUP6nfF biHCzttwa60lD2k56SRwCRYTa3HvcGGB+W0tksT+dUqLg48o6odTWlowAW9ixcHECuzWf731J22 fowAGh4j X-Proofpoint-GUID: q3iAQqjt_5erpI_MCGST0ezUvizQiFjH X-Authority-Analysis: v=2.4 cv=UvtjN/wB c=1 sm=1 tr=0 ts=68d0fb77 cx=c_pps a=JL+w9abYAAE89/QcEU+0QA==:117 a=nuhDOHQX5FNHPW3J6Bj6AA==:17 a=ck2vDrGU2QCsmqff:21 a=IkcTkHD0fZMA:10 a=yJojWOMRYYMA:10 a=vzhER2c_AAAA:8 a=EUspDBNiAAAA:8 a=ml0eKJYL87Gv2QZM9wAA:9 a=QEXdDO2ut3YA:10 a=324X-CrmTo6CU4MGRt3R:22 a=0YTRHmU2iG2pZC6F1fw2:22 X-Proofpoint-ORIG-GUID: q3iAQqjt_5erpI_MCGST0ezUvizQiFjH X-Proofpoint-Virus-Version: vendor=baseguard engine=ICAP:2.0.293,Aquarius:18.0.1117,Hydra:6.1.9,FMLib:17.12.80.40 definitions=2025-09-22_01,2025-09-19_01,2025-03-28_01 X-Proofpoint-Spam-Details: rule=outbound_notspam policy=outbound score=0 spamscore=0 phishscore=0 adultscore=0 impostorscore=0 bulkscore=0 malwarescore=0 suspectscore=0 clxscore=1015 priorityscore=1501 classifier=typeunknown authscore=0 authtc= authcc= route=outbound adjust=0 reason=mlx scancount=1 engine=8.19.0-2507300000 definitions=main-2509200032 From: Carl Worth The handle is essential for retrieving the AUX_EVENT of each CPU and is required in perf mode. It has been added to the coresight_path so that dependent devices can access it from the path when needed. Fixes: 080ee83cc361 ("Coresight: Change functions to accept the coresight_p= ath") Signed-off-by: Carl Worth Co-developed-by: Jie Gan Signed-off-by: Jie Gan Reviewed-by: Leo Yan --- drivers/hwtracing/coresight/coresight-etm-perf.c | 1 + drivers/hwtracing/coresight/coresight-tmc-etr.c | 3 ++- include/linux/coresight.h | 10 ++++++---- 3 files changed, 9 insertions(+), 5 deletions(-) diff --git a/drivers/hwtracing/coresight/coresight-etm-perf.c b/drivers/hwt= racing/coresight/coresight-etm-perf.c index f677c08233ba..5c256af6e54a 100644 --- a/drivers/hwtracing/coresight/coresight-etm-perf.c +++ b/drivers/hwtracing/coresight/coresight-etm-perf.c @@ -520,6 +520,7 @@ static void etm_event_start(struct perf_event *event, i= nt flags) goto out; =20 path =3D etm_event_cpu_path(event_data, cpu); + path->handle =3D handle; /* We need a sink, no need to continue without one */ sink =3D coresight_get_sink(path); if (WARN_ON_ONCE(!sink)) diff --git a/drivers/hwtracing/coresight/coresight-tmc-etr.c b/drivers/hwtr= acing/coresight/coresight-tmc-etr.c index b07fcdb3fe1a..1040f73f0537 100644 --- a/drivers/hwtracing/coresight/coresight-tmc-etr.c +++ b/drivers/hwtracing/coresight/coresight-tmc-etr.c @@ -1327,7 +1327,8 @@ static int tmc_enable_etr_sink_sysfs(struct coresight= _device *csdev) struct etr_buf *tmc_etr_get_buffer(struct coresight_device *csdev, enum cs_mode mode, void *data) { - struct perf_output_handle *handle =3D data; + struct coresight_path *path =3D data; + struct perf_output_handle *handle =3D path->handle; struct etr_perf_buffer *etr_perf; =20 switch (mode) { diff --git a/include/linux/coresight.h b/include/linux/coresight.h index 6de59ce8ef8c..4591121ae1d4 100644 --- a/include/linux/coresight.h +++ b/include/linux/coresight.h @@ -332,12 +332,14 @@ static struct coresight_dev_list (var) =3D { \ =20 /** * struct coresight_path - data needed by enable/disable path - * @path_list: path from source to sink. - * @trace_id: trace_id of the whole path. + * @path_list: path from source to sink. + * @trace_id: trace_id of the whole path. + * struct perf_output_handle: handle of the aux_event. */ struct coresight_path { - struct list_head path_list; - u8 trace_id; + struct list_head path_list; + u8 trace_id; + struct perf_output_handle *handle; }; =20 enum cs_mode { --=20 2.34.1