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[103.229.16.4]) by smtp.gmail.com with ESMTPSA id d9443c01a7336-269800529cdsm123806865ad.22.2025.09.22.00.32.03 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Mon, 22 Sep 2025 00:32:05 -0700 (PDT) From: Jie Gan Date: Mon, 22 Sep 2025 15:31:39 +0800 Subject: [PATCH RFC 1/3] coresight: tmc: add the handle of the event to the path Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Content-Transfer-Encoding: quoted-printable Message-Id: <20250922-fix_helper_data-v1-1-905e8115a24e@oss.qualcomm.com> References: <20250922-fix_helper_data-v1-0-905e8115a24e@oss.qualcomm.com> In-Reply-To: <20250922-fix_helper_data-v1-0-905e8115a24e@oss.qualcomm.com> To: Carl Worth , Suzuki K Poulose , Mike Leach , James Clark , Alexander Shishkin , Jie Gan , Tingwei Zhang Cc: coresight@lists.linaro.org, linux-arm-kernel@lists.infradead.org, linux-kernel@vger.kernel.org X-Mailer: b4 0.14.0 X-Developer-Signature: v=1; a=ed25519-sha256; t=1758526319; l=2707; i=jie.gan@oss.qualcomm.com; s=20250909; h=from:subject:message-id; bh=tPjMdil7gxCwjC8YbC6YODeceMt/ZeL5Vyiw0lVmYeE=; b=4mpDNdSNuz9Jpo6MxISK9MiwQupv+EU8xwmuzB++YqlMXtb4VKLAWUNs3Jrz6rmmZ+PG0/aJl VZ9AJQs36h+CreAjWtqFq9ahKJi1iB85MmZ4ayZSfNNrTu4q7s2j3St X-Developer-Key: i=jie.gan@oss.qualcomm.com; a=ed25519; pk=3LxxUZRPCNkvPDlWOvXfJNqNO4SfGdy3eghMb8puHuk= X-Proofpoint-Spam-Details-Enc: AW1haW4tMjUwOTIwMDAzMiBTYWx0ZWRfX35bs1dGc2d/h To8cLGlWiG540g07RzIoR/ZTBv9CEikTQRIFE4s0Dwgb+EZIdvGD/Y5d/eriJN3xEggVE6SrJ8+ Uf3iXRw8w+6ckdElN8rEasAlEuDYOQ4QukJuDsNaxASQ9AHzj+ovBNeQ/ApqMXsBXt2Oi24U5LI 4R7a1gszhO0yujblr87sy9eQ8l7Keid5Umjh/CdKsjcKjDc/RP505cLZnW8luiIaOpQakjIcljd 1e3FDyOl2ZRK/4ouOuZeEBYe/6nbmmbxwlRIYKtQpUCir5ZwDSgJ02Gn67dWmLEG0wEiQUP6nfF biHCzttwa60lD2k56SRwCRYTa3HvcGGB+W0tksT+dUqLg48o6odTWlowAW9ixcHECuzWf731J22 fowAGh4j X-Proofpoint-GUID: q3iAQqjt_5erpI_MCGST0ezUvizQiFjH X-Authority-Analysis: v=2.4 cv=UvtjN/wB c=1 sm=1 tr=0 ts=68d0fb77 cx=c_pps a=JL+w9abYAAE89/QcEU+0QA==:117 a=nuhDOHQX5FNHPW3J6Bj6AA==:17 a=ck2vDrGU2QCsmqff:21 a=IkcTkHD0fZMA:10 a=yJojWOMRYYMA:10 a=vzhER2c_AAAA:8 a=EUspDBNiAAAA:8 a=ml0eKJYL87Gv2QZM9wAA:9 a=QEXdDO2ut3YA:10 a=324X-CrmTo6CU4MGRt3R:22 a=0YTRHmU2iG2pZC6F1fw2:22 X-Proofpoint-ORIG-GUID: q3iAQqjt_5erpI_MCGST0ezUvizQiFjH X-Proofpoint-Virus-Version: vendor=baseguard engine=ICAP:2.0.293,Aquarius:18.0.1117,Hydra:6.1.9,FMLib:17.12.80.40 definitions=2025-09-22_01,2025-09-19_01,2025-03-28_01 X-Proofpoint-Spam-Details: rule=outbound_notspam policy=outbound score=0 spamscore=0 phishscore=0 adultscore=0 impostorscore=0 bulkscore=0 malwarescore=0 suspectscore=0 clxscore=1015 priorityscore=1501 classifier=typeunknown authscore=0 authtc= authcc= route=outbound adjust=0 reason=mlx scancount=1 engine=8.19.0-2507300000 definitions=main-2509200032 From: Carl Worth The handle is essential for retrieving the AUX_EVENT of each CPU and is required in perf mode. It has been added to the coresight_path so that dependent devices can access it from the path when needed. Fixes: 080ee83cc361 ("Coresight: Change functions to accept the coresight_p= ath") Signed-off-by: Carl Worth Co-developed-by: Jie Gan Signed-off-by: Jie Gan Reviewed-by: Leo Yan --- drivers/hwtracing/coresight/coresight-etm-perf.c | 1 + drivers/hwtracing/coresight/coresight-tmc-etr.c | 3 ++- include/linux/coresight.h | 10 ++++++---- 3 files changed, 9 insertions(+), 5 deletions(-) diff --git a/drivers/hwtracing/coresight/coresight-etm-perf.c b/drivers/hwt= racing/coresight/coresight-etm-perf.c index f677c08233ba..5c256af6e54a 100644 --- a/drivers/hwtracing/coresight/coresight-etm-perf.c +++ b/drivers/hwtracing/coresight/coresight-etm-perf.c @@ -520,6 +520,7 @@ static void etm_event_start(struct perf_event *event, i= nt flags) goto out; =20 path =3D etm_event_cpu_path(event_data, cpu); + path->handle =3D handle; /* We need a sink, no need to continue without one */ sink =3D coresight_get_sink(path); if (WARN_ON_ONCE(!sink)) diff --git a/drivers/hwtracing/coresight/coresight-tmc-etr.c b/drivers/hwtr= acing/coresight/coresight-tmc-etr.c index b07fcdb3fe1a..1040f73f0537 100644 --- a/drivers/hwtracing/coresight/coresight-tmc-etr.c +++ b/drivers/hwtracing/coresight/coresight-tmc-etr.c @@ -1327,7 +1327,8 @@ static int tmc_enable_etr_sink_sysfs(struct coresight= _device *csdev) struct etr_buf *tmc_etr_get_buffer(struct coresight_device *csdev, enum cs_mode mode, void *data) { - struct perf_output_handle *handle =3D data; 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[103.229.16.4]) by smtp.gmail.com with ESMTPSA id d9443c01a7336-269800529cdsm123806865ad.22.2025.09.22.00.32.06 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Mon, 22 Sep 2025 00:32:09 -0700 (PDT) From: Jie Gan Date: Mon, 22 Sep 2025 15:31:40 +0800 Subject: [PATCH RFC 2/3] coresight: change helper_ops to accept coresight_path Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Content-Transfer-Encoding: quoted-printable Message-Id: <20250922-fix_helper_data-v1-2-905e8115a24e@oss.qualcomm.com> References: <20250922-fix_helper_data-v1-0-905e8115a24e@oss.qualcomm.com> In-Reply-To: <20250922-fix_helper_data-v1-0-905e8115a24e@oss.qualcomm.com> To: Carl Worth , Suzuki K Poulose , Mike Leach , James Clark , Alexander Shishkin , Jie Gan , Tingwei Zhang Cc: coresight@lists.linaro.org, linux-arm-kernel@lists.infradead.org, linux-kernel@vger.kernel.org X-Mailer: b4 0.14.0 X-Developer-Signature: v=1; a=ed25519-sha256; t=1758526319; l=9918; i=jie.gan@oss.qualcomm.com; s=20250909; h=from:subject:message-id; bh=QEBlXI+s6Pg9S40qJyLflLft2wUwobd5Tsvp12e09dc=; b=9NtI1pfDUEbYlQdKKADnRMqgOTdWi9zQ4N7QotfDx+WNujMbQNXirNSlwc3H1Mp0+vyG7Wy3v vgZg2zNM47kCzuIl/l8+qeCXInuxQ+ksbRFx6UE3t+X8YxzA3XfmwkE X-Developer-Key: i=jie.gan@oss.qualcomm.com; a=ed25519; pk=3LxxUZRPCNkvPDlWOvXfJNqNO4SfGdy3eghMb8puHuk= X-Proofpoint-Spam-Details-Enc: AW1haW4tMjUwOTIwMDAzMiBTYWx0ZWRfX70jYdzJOu+iT gEPGoqmvrumBPtst6u0IJbuRsnqGbI08J6w43AoafDgkOPavg+kfAqL4qDwG2kKmI7myjAD3cFa h/GmrHkJHbgp++6IHok7KCkGQEVC0MKtrJH7Hw3Qti0f23lX3yzBdbBm3dQo/sn2nreO25Qr1qs SVyuX9h13oqU7ubH9p7sFZSzEwaF59z9bGte2ZiofFh8FpD66nJOU54qsI5vAreqwCtPVtFRjF0 LFYJnttFGNedI3smE1Zr3PM2F9z1x0E6HAerUvGPN+KQsTqDbtnSrtFxF+JqFMm+6FqBiApC8oI 2dtZWBuQ534a8xUTBuhiDtbMyW7SV5UlfqS0P0DZnZzb8JEtYsiI8nu/62LumS4O0LQl+QVr5Yl v9fin141 X-Proofpoint-GUID: DVQ-mMl7V3n7YtsQNXhpeqLWq2Jruh1K X-Authority-Analysis: v=2.4 cv=UvtjN/wB c=1 sm=1 tr=0 ts=68d0fb7a cx=c_pps a=MTSHoo12Qbhz2p7MsH1ifg==:117 a=nuhDOHQX5FNHPW3J6Bj6AA==:17 a=IkcTkHD0fZMA:10 a=yJojWOMRYYMA:10 a=EUspDBNiAAAA:8 a=Gv9EIBWDmE4dLvOUe8gA:9 a=QEXdDO2ut3YA:10 a=GvdueXVYPmCkWapjIL-Q:22 X-Proofpoint-ORIG-GUID: DVQ-mMl7V3n7YtsQNXhpeqLWq2Jruh1K X-Proofpoint-Virus-Version: vendor=baseguard engine=ICAP:2.0.293,Aquarius:18.0.1117,Hydra:6.1.9,FMLib:17.12.80.40 definitions=2025-09-22_01,2025-09-19_01,2025-03-28_01 X-Proofpoint-Spam-Details: rule=outbound_notspam policy=outbound score=0 spamscore=0 phishscore=0 adultscore=0 impostorscore=0 bulkscore=0 malwarescore=0 suspectscore=0 clxscore=1015 priorityscore=1501 classifier=typeunknown authscore=0 authtc= authcc= route=outbound adjust=0 reason=mlx scancount=1 engine=8.19.0-2507300000 definitions=main-2509200032 Update the helper_enable and helper_disable functions to accept coresight_path instead of a generic void *data, as coresight_path encapsulates all the necessary data required by devices along the path. Signed-off-by: Jie Gan Reviewed-by: Carl Worth Reviewed-by: Leo Yan Tested-by: Carl Worth --- drivers/hwtracing/coresight/coresight-catu.c | 10 +++++----- drivers/hwtracing/coresight/coresight-core.c | 20 ++++++++++++-------- drivers/hwtracing/coresight/coresight-ctcu-core.c | 9 +++------ drivers/hwtracing/coresight/coresight-cti-core.c | 5 +++-- drivers/hwtracing/coresight/coresight-cti.h | 5 +++-- drivers/hwtracing/coresight/coresight-tmc-etr.c | 4 ++-- drivers/hwtracing/coresight/coresight-tmc.h | 3 ++- include/linux/coresight.h | 5 +++-- 8 files changed, 33 insertions(+), 28 deletions(-) diff --git a/drivers/hwtracing/coresight/coresight-catu.c b/drivers/hwtraci= ng/coresight/coresight-catu.c index a3ccb7034ae1..69b36bae97ab 100644 --- a/drivers/hwtracing/coresight/coresight-catu.c +++ b/drivers/hwtracing/coresight/coresight-catu.c @@ -397,7 +397,7 @@ static int catu_wait_for_ready(struct catu_drvdata *drv= data) } =20 static int catu_enable_hw(struct catu_drvdata *drvdata, enum cs_mode cs_mo= de, - void *data) + struct coresight_path *path) { int rc; u32 control, mode; @@ -425,7 +425,7 @@ static int catu_enable_hw(struct catu_drvdata *drvdata,= enum cs_mode cs_mode, etrdev =3D coresight_find_input_type( csdev->pdata, CORESIGHT_DEV_TYPE_SINK, etr_subtype); if (etrdev) { - etr_buf =3D tmc_etr_get_buffer(etrdev, cs_mode, data); + etr_buf =3D tmc_etr_get_buffer(etrdev, cs_mode, path); if (IS_ERR(etr_buf)) return PTR_ERR(etr_buf); } @@ -455,7 +455,7 @@ static int catu_enable_hw(struct catu_drvdata *drvdata,= enum cs_mode cs_mode, } =20 static int catu_enable(struct coresight_device *csdev, enum cs_mode mode, - void *data) + struct coresight_path *path) { int rc =3D 0; struct catu_drvdata *catu_drvdata =3D csdev_to_catu_drvdata(csdev); @@ -463,7 +463,7 @@ static int catu_enable(struct coresight_device *csdev, = enum cs_mode mode, guard(raw_spinlock_irqsave)(&catu_drvdata->spinlock); if (csdev->refcnt =3D=3D 0) { CS_UNLOCK(catu_drvdata->base); - rc =3D catu_enable_hw(catu_drvdata, mode, data); + rc =3D catu_enable_hw(catu_drvdata, mode, path); CS_LOCK(catu_drvdata->base); } if (!rc) @@ -488,7 +488,7 @@ static int catu_disable_hw(struct catu_drvdata *drvdata) return rc; } =20 -static int catu_disable(struct coresight_device *csdev, void *__unused) +static int catu_disable(struct coresight_device *csdev, struct coresight_p= ath *path) { int rc =3D 0; struct catu_drvdata *catu_drvdata =3D csdev_to_catu_drvdata(csdev); diff --git a/drivers/hwtracing/coresight/coresight-core.c b/drivers/hwtraci= ng/coresight/coresight-core.c index 3267192f0c1c..f44ec9e5b692 100644 --- a/drivers/hwtracing/coresight/coresight-core.c +++ b/drivers/hwtracing/coresight/coresight-core.c @@ -355,17 +355,20 @@ static bool coresight_is_helper(struct coresight_devi= ce *csdev) } =20 static int coresight_enable_helper(struct coresight_device *csdev, - enum cs_mode mode, void *data) + enum cs_mode mode, + struct coresight_path *path) { - return helper_ops(csdev)->enable(csdev, mode, data); + return helper_ops(csdev)->enable(csdev, mode, path); } =20 -static void coresight_disable_helper(struct coresight_device *csdev, void = *data) +static void coresight_disable_helper(struct coresight_device *csdev, + struct coresight_path *path) { - helper_ops(csdev)->disable(csdev, data); + helper_ops(csdev)->disable(csdev, path); } =20 -static void coresight_disable_helpers(struct coresight_device *csdev, void= *data) +static void coresight_disable_helpers(struct coresight_device *csdev, + struct coresight_path *path) { int i; struct coresight_device *helper; @@ -373,7 +376,7 @@ static void coresight_disable_helpers(struct coresight_= device *csdev, void *data for (i =3D 0; i < csdev->pdata->nr_outconns; ++i) { helper =3D csdev->pdata->out_conns[i]->dest_dev; if (helper && coresight_is_helper(helper)) - coresight_disable_helper(helper, data); + coresight_disable_helper(helper, path); } } =20 @@ -479,7 +482,8 @@ void coresight_disable_path(struct coresight_path *path) EXPORT_SYMBOL_GPL(coresight_disable_path); =20 static int coresight_enable_helpers(struct coresight_device *csdev, - enum cs_mode mode, void *data) + enum cs_mode mode, + struct coresight_path *path) { int i, ret =3D 0; struct coresight_device *helper; @@ -489,7 +493,7 @@ static int coresight_enable_helpers(struct coresight_de= vice *csdev, if (!helper || !coresight_is_helper(helper)) continue; =20 - ret =3D coresight_enable_helper(helper, mode, data); + ret =3D coresight_enable_helper(helper, mode, path); if (ret) return ret; } diff --git a/drivers/hwtracing/coresight/coresight-ctcu-core.c b/drivers/hw= tracing/coresight/coresight-ctcu-core.c index c586495e9a08..abed15eb72b4 100644 --- a/drivers/hwtracing/coresight/coresight-ctcu-core.c +++ b/drivers/hwtracing/coresight/coresight-ctcu-core.c @@ -156,17 +156,14 @@ static int ctcu_set_etr_traceid(struct coresight_devi= ce *csdev, struct coresight return __ctcu_set_etr_traceid(csdev, traceid, port_num, enable); } =20 -static int ctcu_enable(struct coresight_device *csdev, enum cs_mode mode, = void *data) +static int ctcu_enable(struct coresight_device *csdev, enum cs_mode mode, + struct coresight_path *path) { - struct coresight_path *path =3D (struct coresight_path *)data; - return ctcu_set_etr_traceid(csdev, path, true); } =20 -static int ctcu_disable(struct coresight_device *csdev, void *data) +static int ctcu_disable(struct coresight_device *csdev, struct coresight_p= ath *path) { - struct coresight_path *path =3D (struct coresight_path *)data; - return ctcu_set_etr_traceid(csdev, path, false); } =20 diff --git a/drivers/hwtracing/coresight/coresight-cti-core.c b/drivers/hwt= racing/coresight/coresight-cti-core.c index 8fb30dd73fd2..bfbc365bb2ef 100644 --- a/drivers/hwtracing/coresight/coresight-cti-core.c +++ b/drivers/hwtracing/coresight/coresight-cti-core.c @@ -799,14 +799,15 @@ static void cti_pm_release(struct cti_drvdata *drvdat= a) } =20 /** cti ect operations **/ -int cti_enable(struct coresight_device *csdev, enum cs_mode mode, void *da= ta) +int cti_enable(struct coresight_device *csdev, enum cs_mode mode, + struct coresight_path *path) { struct cti_drvdata *drvdata =3D csdev_to_cti_drvdata(csdev); =20 return cti_enable_hw(drvdata); } =20 -int cti_disable(struct coresight_device *csdev, void *data) +int cti_disable(struct coresight_device *csdev, struct coresight_path *pat= h) { struct cti_drvdata *drvdata =3D csdev_to_cti_drvdata(csdev); =20 diff --git a/drivers/hwtracing/coresight/coresight-cti.h b/drivers/hwtracin= g/coresight/coresight-cti.h index 8362a47c939c..4f89091ee93f 100644 --- a/drivers/hwtracing/coresight/coresight-cti.h +++ b/drivers/hwtracing/coresight/coresight-cti.h @@ -216,8 +216,9 @@ int cti_add_connection_entry(struct device *dev, struct= cti_drvdata *drvdata, const char *assoc_dev_name); struct cti_trig_con *cti_allocate_trig_con(struct device *dev, int in_sigs, int out_sigs); -int cti_enable(struct coresight_device *csdev, enum cs_mode mode, void *da= ta); -int cti_disable(struct coresight_device *csdev, void *data); +int cti_enable(struct coresight_device *csdev, enum cs_mode mode, + struct coresight_path *path); +int cti_disable(struct coresight_device *csdev, struct coresight_path *pat= h); void cti_write_all_hw_regs(struct cti_drvdata *drvdata); void cti_write_intack(struct device *dev, u32 ackval); void cti_write_single_reg(struct cti_drvdata *drvdata, int offset, u32 val= ue); diff --git a/drivers/hwtracing/coresight/coresight-tmc-etr.c b/drivers/hwtr= acing/coresight/coresight-tmc-etr.c index 1040f73f0537..b9bdbc745433 100644 --- a/drivers/hwtracing/coresight/coresight-tmc-etr.c +++ b/drivers/hwtracing/coresight/coresight-tmc-etr.c @@ -1325,9 +1325,9 @@ static int tmc_enable_etr_sink_sysfs(struct coresight= _device *csdev) } =20 struct etr_buf *tmc_etr_get_buffer(struct coresight_device *csdev, - enum cs_mode mode, void *data) + enum cs_mode mode, + struct coresight_path *path) { - struct coresight_path *path =3D data; struct perf_output_handle *handle =3D path->handle; struct etr_perf_buffer *etr_perf; =20 diff --git a/drivers/hwtracing/coresight/coresight-tmc.h b/drivers/hwtracin= g/coresight/coresight-tmc.h index cbb4ba439158..95473d131032 100644 --- a/drivers/hwtracing/coresight/coresight-tmc.h +++ b/drivers/hwtracing/coresight/coresight-tmc.h @@ -442,7 +442,8 @@ struct coresight_device *tmc_etr_get_catu_device(struct= tmc_drvdata *drvdata); void tmc_etr_set_catu_ops(const struct etr_buf_operations *catu); void tmc_etr_remove_catu_ops(void); struct etr_buf *tmc_etr_get_buffer(struct coresight_device *csdev, - enum cs_mode mode, void *data); + enum cs_mode mode, + struct coresight_path *path); extern const struct attribute_group coresight_etr_group; =20 #endif diff --git a/include/linux/coresight.h b/include/linux/coresight.h index 4591121ae1d4..a54241ae9aa1 100644 --- a/include/linux/coresight.h +++ b/include/linux/coresight.h @@ -424,8 +424,9 @@ struct coresight_ops_source { */ struct coresight_ops_helper { int (*enable)(struct coresight_device *csdev, enum cs_mode mode, - void *data); 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[103.229.16.4]) by smtp.gmail.com with ESMTPSA id d9443c01a7336-269800529cdsm123806865ad.22.2025.09.22.00.32.09 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Mon, 22 Sep 2025 00:32:12 -0700 (PDT) From: Jie Gan Date: Mon, 22 Sep 2025 15:31:41 +0800 Subject: [PATCH RFC 3/3] coresight: change the sink_ops to accept coresight_path Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Content-Transfer-Encoding: quoted-printable Message-Id: <20250922-fix_helper_data-v1-3-905e8115a24e@oss.qualcomm.com> References: <20250922-fix_helper_data-v1-0-905e8115a24e@oss.qualcomm.com> In-Reply-To: <20250922-fix_helper_data-v1-0-905e8115a24e@oss.qualcomm.com> To: Carl Worth , Suzuki K Poulose , Mike Leach , James Clark , Alexander Shishkin , Jie Gan , Tingwei Zhang Cc: coresight@lists.linaro.org, linux-arm-kernel@lists.infradead.org, linux-kernel@vger.kernel.org X-Mailer: b4 0.14.0 X-Developer-Signature: v=1; a=ed25519-sha256; t=1758526319; l=12603; i=jie.gan@oss.qualcomm.com; s=20250909; h=from:subject:message-id; bh=/OVN9onjWXrmzDeRCV9TCbuim8Q2z/iTEnPS+UpvrJg=; b=yjdgpXl8vW4xTp2hslzPYuXiQmOE6NEJnVtvWgcpwFYiyjbJn4J48GaabGorqnsnOx2zEOY2T FvnmObwuuw5DBPKP5yZirqWf9NjTomMu399enIdFXqE5RV0QrtMnutQ X-Developer-Key: i=jie.gan@oss.qualcomm.com; a=ed25519; pk=3LxxUZRPCNkvPDlWOvXfJNqNO4SfGdy3eghMb8puHuk= X-Authority-Analysis: v=2.4 cv=YPqfyQGx c=1 sm=1 tr=0 ts=68d0fb7e cx=c_pps a=JL+w9abYAAE89/QcEU+0QA==:117 a=nuhDOHQX5FNHPW3J6Bj6AA==:17 a=IkcTkHD0fZMA:10 a=yJojWOMRYYMA:10 a=EUspDBNiAAAA:8 a=t4OZSbUdKNgAmLiGTPYA:9 a=QEXdDO2ut3YA:10 a=324X-CrmTo6CU4MGRt3R:22 X-Proofpoint-ORIG-GUID: QRBVPRoPm6dZbdAaWj4FCfj1wPFYSgSz X-Proofpoint-Spam-Details-Enc: AW1haW4tMjUwOTIwMDAwMCBTYWx0ZWRfX91cF8lUQzQEb QAXR/WK0oVlGjXZl/CXkzAIVkekk6ziN5LSh2qllSLtoKkBqeSnrW2zL1yvjqi5tzwW3/6ix8+n /5IeYjPGJtvUNo54BkAedHf32mzhCwBf9kUEJ+OBtdJklk+8nrHgIc0x83FlxsFpXZUloSo0Xj+ sX4CGk4zEWyBkcfrzGQyi4CGludAlQhFVRXyrS0ppItmFFm2ziSqNycO/34+krzFWep2ovKYGC2 LyW7/Q2BQf0EfSRXxVkTkBRPefgFQSnD7cW0KAQUFAiF57TzIf3IH/yXx3cqvOTRRgpIrZZBj5s k8EJB6859A3dmyORxgWTyVYZE7nnb+2fa5I0JR9ELtuLiGXMvIz8KvgPzk6JpBXipEJ9niqkMfA P/1IL0bf X-Proofpoint-GUID: QRBVPRoPm6dZbdAaWj4FCfj1wPFYSgSz X-Proofpoint-Virus-Version: vendor=baseguard engine=ICAP:2.0.293,Aquarius:18.0.1117,Hydra:6.1.9,FMLib:17.12.80.40 definitions=2025-09-22_01,2025-09-19_01,2025-03-28_01 X-Proofpoint-Spam-Details: rule=outbound_notspam policy=outbound score=0 suspectscore=0 bulkscore=0 priorityscore=1501 phishscore=0 adultscore=0 clxscore=1015 impostorscore=0 spamscore=0 malwarescore=0 classifier=typeunknown authscore=0 authtc= authcc= route=outbound adjust=0 reason=mlx scancount=1 engine=8.19.0-2507300000 definitions=main-2509200000 Update the sink_enable functions to accept coresight_path instead of a generic void *data, as coresight_path encapsulates all the necessary data required by devices along the path. Signed-off-by: Jie Gan Reviewed-by: Carl Worth Reviewed-by: Leo Yan Tested-by: Carl Worth --- drivers/hwtracing/coresight/coresight-core.c | 10 +++++----- drivers/hwtracing/coresight/coresight-dummy.c | 2 +- drivers/hwtracing/coresight/coresight-etb10.c | 8 ++++---- drivers/hwtracing/coresight/coresight-etm-perf.c | 2 +- drivers/hwtracing/coresight/coresight-priv.h | 3 +-- drivers/hwtracing/coresight/coresight-sysfs.c | 2 +- drivers/hwtracing/coresight/coresight-tmc-etf.c | 10 ++++++---- drivers/hwtracing/coresight/coresight-tmc-etr.c | 10 ++++++---- drivers/hwtracing/coresight/coresight-tpiu.c | 2 +- drivers/hwtracing/coresight/coresight-trbe.c | 4 ++-- drivers/hwtracing/coresight/ultrasoc-smb.c | 9 +++++---- include/linux/coresight.h | 2 +- 12 files changed, 34 insertions(+), 30 deletions(-) diff --git a/drivers/hwtracing/coresight/coresight-core.c b/drivers/hwtraci= ng/coresight/coresight-core.c index f44ec9e5b692..c660cf8adb1c 100644 --- a/drivers/hwtracing/coresight/coresight-core.c +++ b/drivers/hwtracing/coresight/coresight-core.c @@ -300,9 +300,10 @@ void coresight_add_helper(struct coresight_device *csd= ev, EXPORT_SYMBOL_GPL(coresight_add_helper); =20 static int coresight_enable_sink(struct coresight_device *csdev, - enum cs_mode mode, void *data) + enum cs_mode mode, + struct coresight_path *path) { - return sink_ops(csdev)->enable(csdev, mode, data); + return sink_ops(csdev)->enable(csdev, mode, path); } =20 static void coresight_disable_sink(struct coresight_device *csdev) @@ -501,8 +502,7 @@ static int coresight_enable_helpers(struct coresight_de= vice *csdev, return 0; } =20 -int coresight_enable_path(struct coresight_path *path, enum cs_mode mode, - void *sink_data) +int coresight_enable_path(struct coresight_path *path, enum cs_mode mode) { int ret =3D 0; u32 type; @@ -532,7 +532,7 @@ int coresight_enable_path(struct coresight_path *path, = enum cs_mode mode, =20 switch (type) { case CORESIGHT_DEV_TYPE_SINK: - ret =3D coresight_enable_sink(csdev, mode, sink_data); + ret =3D coresight_enable_sink(csdev, mode, path); /* * Sink is the first component turned on. If we * failed to enable the sink, there are no components diff --git a/drivers/hwtracing/coresight/coresight-dummy.c b/drivers/hwtrac= ing/coresight/coresight-dummy.c index aaa92b5081e3..14322c99e29d 100644 --- a/drivers/hwtracing/coresight/coresight-dummy.c +++ b/drivers/hwtracing/coresight/coresight-dummy.c @@ -52,7 +52,7 @@ static int dummy_source_trace_id(struct coresight_device = *csdev, __maybe_unused } =20 static int dummy_sink_enable(struct coresight_device *csdev, enum cs_mode = mode, - void *data) + struct coresight_path *path) { dev_dbg(csdev->dev.parent, "Dummy sink enabled\n"); =20 diff --git a/drivers/hwtracing/coresight/coresight-etb10.c b/drivers/hwtrac= ing/coresight/coresight-etb10.c index 35db1b6093d1..6657602d8f2e 100644 --- a/drivers/hwtracing/coresight/coresight-etb10.c +++ b/drivers/hwtracing/coresight/coresight-etb10.c @@ -167,13 +167,13 @@ static int etb_enable_sysfs(struct coresight_device *= csdev) return ret; } =20 -static int etb_enable_perf(struct coresight_device *csdev, void *data) +static int etb_enable_perf(struct coresight_device *csdev, struct coresigh= t_path *path) { int ret =3D 0; pid_t pid; unsigned long flags; struct etb_drvdata *drvdata =3D dev_get_drvdata(csdev->dev.parent); - struct perf_output_handle *handle =3D data; + struct perf_output_handle *handle =3D path->handle; struct cs_buffers *buf =3D etm_perf_sink_config(handle); =20 raw_spin_lock_irqsave(&drvdata->spinlock, flags); @@ -224,7 +224,7 @@ static int etb_enable_perf(struct coresight_device *csd= ev, void *data) } =20 static int etb_enable(struct coresight_device *csdev, enum cs_mode mode, - void *data) + struct coresight_path *path) { int ret; =20 @@ -233,7 +233,7 @@ static int etb_enable(struct coresight_device *csdev, e= num cs_mode mode, ret =3D etb_enable_sysfs(csdev); break; case CS_MODE_PERF: - ret =3D etb_enable_perf(csdev, data); + ret =3D etb_enable_perf(csdev, path); break; default: ret =3D -EINVAL; diff --git a/drivers/hwtracing/coresight/coresight-etm-perf.c b/drivers/hwt= racing/coresight/coresight-etm-perf.c index 5c256af6e54a..17afa0f4cdee 100644 --- a/drivers/hwtracing/coresight/coresight-etm-perf.c +++ b/drivers/hwtracing/coresight/coresight-etm-perf.c @@ -527,7 +527,7 @@ static void etm_event_start(struct perf_event *event, i= nt flags) goto fail_end_stop; =20 /* Nothing will happen without a path */ - if (coresight_enable_path(path, CS_MODE_PERF, handle)) + if (coresight_enable_path(path, CS_MODE_PERF)) goto fail_end_stop; =20 /* Finally enable the tracer */ diff --git a/drivers/hwtracing/coresight/coresight-priv.h b/drivers/hwtraci= ng/coresight/coresight-priv.h index 33e22b1ba043..fd896ac07942 100644 --- a/drivers/hwtracing/coresight/coresight-priv.h +++ b/drivers/hwtracing/coresight/coresight-priv.h @@ -135,8 +135,7 @@ static inline void CS_UNLOCK(void __iomem *addr) } =20 void coresight_disable_path(struct coresight_path *path); -int coresight_enable_path(struct coresight_path *path, enum cs_mode mode, - void *sink_data); +int coresight_enable_path(struct coresight_path *path, enum cs_mode mode); struct coresight_device *coresight_get_sink(struct coresight_path *path); struct coresight_device *coresight_get_sink_by_id(u32 id); struct coresight_device * diff --git a/drivers/hwtracing/coresight/coresight-sysfs.c b/drivers/hwtrac= ing/coresight/coresight-sysfs.c index 5e52324aa9ac..d2a6ed8bcc74 100644 --- a/drivers/hwtracing/coresight/coresight-sysfs.c +++ b/drivers/hwtracing/coresight/coresight-sysfs.c @@ -215,7 +215,7 @@ int coresight_enable_sysfs(struct coresight_device *csd= ev) if (!IS_VALID_CS_TRACE_ID(path->trace_id)) goto err_path; =20 - ret =3D coresight_enable_path(path, CS_MODE_SYSFS, NULL); + ret =3D coresight_enable_path(path, CS_MODE_SYSFS); if (ret) goto err_path; =20 diff --git a/drivers/hwtracing/coresight/coresight-tmc-etf.c b/drivers/hwtr= acing/coresight/coresight-tmc-etf.c index 0f45ab5e5249..8882b1c4cdc0 100644 --- a/drivers/hwtracing/coresight/coresight-tmc-etf.c +++ b/drivers/hwtracing/coresight/coresight-tmc-etf.c @@ -246,13 +246,14 @@ static int tmc_enable_etf_sink_sysfs(struct coresight= _device *csdev) return ret; } =20 -static int tmc_enable_etf_sink_perf(struct coresight_device *csdev, void *= data) +static int tmc_enable_etf_sink_perf(struct coresight_device *csdev, + struct coresight_path *path) { int ret =3D 0; pid_t pid; unsigned long flags; struct tmc_drvdata *drvdata =3D dev_get_drvdata(csdev->dev.parent); - struct perf_output_handle *handle =3D data; + struct perf_output_handle *handle =3D path->handle; struct cs_buffers *buf =3D etm_perf_sink_config(handle); =20 raw_spin_lock_irqsave(&drvdata->spinlock, flags); @@ -304,7 +305,8 @@ static int tmc_enable_etf_sink_perf(struct coresight_de= vice *csdev, void *data) } =20 static int tmc_enable_etf_sink(struct coresight_device *csdev, - enum cs_mode mode, void *data) + enum cs_mode mode, + struct coresight_path *path) { int ret; =20 @@ -313,7 +315,7 @@ static int tmc_enable_etf_sink(struct coresight_device = *csdev, ret =3D tmc_enable_etf_sink_sysfs(csdev); break; case CS_MODE_PERF: - ret =3D tmc_enable_etf_sink_perf(csdev, data); + ret =3D tmc_enable_etf_sink_perf(csdev, path); break; /* We shouldn't be here */ default: diff --git a/drivers/hwtracing/coresight/coresight-tmc-etr.c b/drivers/hwtr= acing/coresight/coresight-tmc-etr.c index b9bdbc745433..bf08f6117a7f 100644 --- a/drivers/hwtracing/coresight/coresight-tmc-etr.c +++ b/drivers/hwtracing/coresight/coresight-tmc-etr.c @@ -1726,13 +1726,14 @@ tmc_update_etr_buffer(struct coresight_device *csde= v, return size; } =20 -static int tmc_enable_etr_sink_perf(struct coresight_device *csdev, void *= data) +static int tmc_enable_etr_sink_perf(struct coresight_device *csdev, + struct coresight_path *path) { int rc =3D 0; pid_t pid; unsigned long flags; struct tmc_drvdata *drvdata =3D dev_get_drvdata(csdev->dev.parent); - struct perf_output_handle *handle =3D data; + struct perf_output_handle *handle =3D path->handle; struct etr_perf_buffer *etr_perf =3D etm_perf_sink_config(handle); =20 raw_spin_lock_irqsave(&drvdata->spinlock, flags); @@ -1780,13 +1781,14 @@ static int tmc_enable_etr_sink_perf(struct coresigh= t_device *csdev, void *data) } =20 static int tmc_enable_etr_sink(struct coresight_device *csdev, - enum cs_mode mode, void *data) + enum cs_mode mode, + struct coresight_path *path) { switch (mode) { case CS_MODE_SYSFS: return tmc_enable_etr_sink_sysfs(csdev); case CS_MODE_PERF: - return tmc_enable_etr_sink_perf(csdev, data); + return tmc_enable_etr_sink_perf(csdev, path); default: return -EINVAL; } diff --git a/drivers/hwtracing/coresight/coresight-tpiu.c b/drivers/hwtraci= ng/coresight/coresight-tpiu.c index 9463afdbda8a..aaa44bc521c3 100644 --- a/drivers/hwtracing/coresight/coresight-tpiu.c +++ b/drivers/hwtracing/coresight/coresight-tpiu.c @@ -75,7 +75,7 @@ static void tpiu_enable_hw(struct csdev_access *csa) } =20 static int tpiu_enable(struct coresight_device *csdev, enum cs_mode mode, - void *__unused) + struct coresight_path *path) { struct tpiu_drvdata *drvdata =3D dev_get_drvdata(csdev->dev.parent); =20 diff --git a/drivers/hwtracing/coresight/coresight-trbe.c b/drivers/hwtraci= ng/coresight/coresight-trbe.c index 43643d2c5bdd..293715b4ff0e 100644 --- a/drivers/hwtracing/coresight/coresight-trbe.c +++ b/drivers/hwtracing/coresight/coresight-trbe.c @@ -1013,11 +1013,11 @@ static int __arm_trbe_enable(struct trbe_buf *buf, } =20 static int arm_trbe_enable(struct coresight_device *csdev, enum cs_mode mo= de, - void *data) + struct coresight_path *path) { struct trbe_drvdata *drvdata =3D dev_get_drvdata(csdev->dev.parent); struct trbe_cpudata *cpudata =3D dev_get_drvdata(&csdev->dev); - struct perf_output_handle *handle =3D data; + struct perf_output_handle *handle =3D path->handle; struct trbe_buf *buf =3D etm_perf_sink_config(handle); =20 WARN_ON(cpudata->cpu !=3D smp_processor_id()); diff --git a/drivers/hwtracing/coresight/ultrasoc-smb.c b/drivers/hwtracing= /coresight/ultrasoc-smb.c index 26cfc939e5bd..8f7922a5e534 100644 --- a/drivers/hwtracing/coresight/ultrasoc-smb.c +++ b/drivers/hwtracing/coresight/ultrasoc-smb.c @@ -213,10 +213,11 @@ static void smb_enable_sysfs(struct coresight_device = *csdev) coresight_set_mode(csdev, CS_MODE_SYSFS); } =20 -static int smb_enable_perf(struct coresight_device *csdev, void *data) +static int smb_enable_perf(struct coresight_device *csdev, + struct coresight_path *path) { struct smb_drv_data *drvdata =3D dev_get_drvdata(csdev->dev.parent); - struct perf_output_handle *handle =3D data; + struct perf_output_handle *handle =3D path->handle; struct cs_buffers *buf =3D etm_perf_sink_config(handle); pid_t pid; =20 @@ -240,7 +241,7 @@ static int smb_enable_perf(struct coresight_device *csd= ev, void *data) } =20 static int smb_enable(struct coresight_device *csdev, enum cs_mode mode, - void *data) + struct coresight_path *path) { struct smb_drv_data *drvdata =3D dev_get_drvdata(csdev->dev.parent); int ret =3D 0; @@ -261,7 +262,7 @@ static int smb_enable(struct coresight_device *csdev, e= num cs_mode mode, smb_enable_sysfs(csdev); break; case CS_MODE_PERF: - ret =3D smb_enable_perf(csdev, data); + ret =3D smb_enable_perf(csdev, path); break; default: ret =3D -EINVAL; diff --git a/include/linux/coresight.h b/include/linux/coresight.h index a54241ae9aa1..fc7004081caa 100644 --- a/include/linux/coresight.h +++ b/include/linux/coresight.h @@ -367,7 +367,7 @@ enum cs_mode { */ struct coresight_ops_sink { int (*enable)(struct coresight_device *csdev, enum cs_mode mode, - void *data); + struct coresight_path *path); int (*disable)(struct coresight_device *csdev); void *(*alloc_buffer)(struct coresight_device *csdev, struct perf_event *event, void **pages, --=20 2.34.1