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These are required for describing the Milianke MLKPAI-FS01 board with DR1V90 SoC from Anlogic, which uses a processor core designed by Nuclei. Acked-by: Krzysztof Kozlowski Signed-off-by: Junhui Liu --- Documentation/devicetree/bindings/vendor-prefixes.yaml | 6 ++++++ 1 file changed, 6 insertions(+) diff --git a/Documentation/devicetree/bindings/vendor-prefixes.yaml b/Docum= entation/devicetree/bindings/vendor-prefixes.yaml index 9ec8947dfcad2fa53b2dca2ca06a63710771a600..d5071dcc3b97b9030087992e872= afc7b6d36160e 100644 --- a/Documentation/devicetree/bindings/vendor-prefixes.yaml +++ b/Documentation/devicetree/bindings/vendor-prefixes.yaml @@ -128,6 +128,8 @@ patternProperties: description: Anbernic "^andestech,.*": description: Andes Technology Corporation + "^anlogic,.*": + description: Shanghai Anlogic Infotech Co., Ltd. "^anvo,.*": description: Anvo-Systems Dresden GmbH "^aoly,.*": @@ -985,6 +987,8 @@ patternProperties: description: MikroElektronika d.o.o. "^mikrotik,.*": description: MikroTik + "^milianke,.*": + description: Changzhou Milianke Electronic Technology Co., Ltd "^milkv,.*": description: MilkV Technology Co., Ltd "^miniand,.*": @@ -1100,6 +1104,8 @@ patternProperties: description: Novatek "^novtech,.*": description: NovTech, Inc. + "^nuclei,.*": + description: Nuclei System Technology "^numonyx,.*": description: Numonyx (deprecated, use micron) deprecated: true --=20 2.51.0 From nobody Thu Oct 2 05:05:15 2025 Received: from sender4-op-o12.zoho.com (sender4-op-o12.zoho.com [136.143.188.12]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id BE90D302773; Mon, 22 Sep 2025 12:48:36 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=pass smtp.client-ip=136.143.188.12 ARC-Seal: i=2; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1758545318; cv=pass; b=eYxRaFjpKeYwjQer7cqYSlI6ePvxqK8Nvzp/X8U7ygxHVYw2TeadlHfMoKZdPr/Q8A4ZV9sW7qpCO4dczhKX7o6VjWUXA1sUmb69XEwRnNKEX9pVT0rtafWoFau+Wc/m96pYGthhxh17iBT681s5wmnGRFtdlrD8YbCySlXrG4o= ARC-Message-Signature: i=2; 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a=ed25519-sha256; t=1758545232; l=946; i=junhui.liu@pigmoral.tech; s=20250910; h=from:subject:message-id; bh=tuo3nrLTJo1bILOOpnJ9HgGZGKW1FMMYee3cJTCpPG4=; b=sE9FcF4gPZyZr2epKp7IRMNEnQqmxCRpsCf826Q0bGwlGwOTjN9mWNabl2adU0HdQSJsIkHo1 Ansfz6o+fYLDVEugRK3oxipsgPunQmA7N78bpTf8n7t6u6fQxWYWvqr X-Developer-Key: i=junhui.liu@pigmoral.tech; a=ed25519; pk=cgATWSU1KfGWmdwNmkPyHGnWgofhqqhE8Vts58wyxe4= X-ZohoMailClient: External The UX900 is a RISC-V core from Nuclei, used in the Anlogic DR1V90 SoC. It features a 64-bit architecture and dual-issue, 9-stage pipeline, with lots of optional extensions including V, K, Zc, and more. Signed-off-by: Junhui Liu Acked-by: Conor Dooley --- Documentation/devicetree/bindings/riscv/cpus.yaml | 1 + 1 file changed, 1 insertion(+) diff --git a/Documentation/devicetree/bindings/riscv/cpus.yaml b/Documentat= ion/devicetree/bindings/riscv/cpus.yaml index 1a0cf0702a45d2df38c48f50d66b3d2ac3715da5..cd3299490380696fff54a41355c= 6ecbc75316047 100644 --- a/Documentation/devicetree/bindings/riscv/cpus.yaml +++ b/Documentation/devicetree/bindings/riscv/cpus.yaml @@ -48,6 +48,7 @@ properties: - amd,mbv64 - andestech,ax45mp - canaan,k210 + - nuclei,ux900 - sifive,bullet0 - sifive,e5 - sifive,e7 --=20 2.51.0 From nobody Thu Oct 2 05:05:15 2025 Received: from sender4-op-o12.zoho.com (sender4-op-o12.zoho.com [136.143.188.12]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id D30D1309EF4; Mon, 22 Sep 2025 12:49:45 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=pass smtp.client-ip=136.143.188.12 ARC-Seal: i=2; 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a=ed25519; pk=cgATWSU1KfGWmdwNmkPyHGnWgofhqqhE8Vts58wyxe4= X-ZohoMailClient: External Add Anlogic DR1V90 FPSoC, featuring a UX900 RISC-V core as the processing system (PS) and 94,464 LUTs programmable logic (PL). It is used by the Milianke MLKPAI-FS01 board, a SBC equipped with 512MB DDR3 memory, USB-C UART, 1GbE RJ45 Ethernet, USB-A 2.0 port, TF card slot, and 256Mbit Quad-SPI flash. Reviewed-by: Krzysztof Kozlowski Signed-off-by: Junhui Liu --- .../devicetree/bindings/riscv/anlogic.yaml | 27 ++++++++++++++++++= ++++ 1 file changed, 27 insertions(+) diff --git a/Documentation/devicetree/bindings/riscv/anlogic.yaml b/Documen= tation/devicetree/bindings/riscv/anlogic.yaml new file mode 100644 index 0000000000000000000000000000000000000000..91b1526c99aa3ca9cc7b0e79788= 61408bd017049 --- /dev/null +++ b/Documentation/devicetree/bindings/riscv/anlogic.yaml @@ -0,0 +1,27 @@ +# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause) +%YAML 1.2 +--- +$id: http://devicetree.org/schemas/riscv/anlogic.yaml# +$schema: http://devicetree.org/meta-schemas/core.yaml# + +title: Anlogic SoC-based boards + +maintainers: + - Junhui Liu + +description: + Anlogic SoC-based boards + +properties: + $nodename: + const: '/' + compatible: + oneOf: + - items: + - enum: + - milianke,mlkpai-fs01 + - const: anlogic,dr1v90 + +additionalProperties: true + +... --=20 2.51.0 From nobody Thu Oct 2 05:05:15 2025 Received: from sender4-op-o12.zoho.com (sender4-op-o12.zoho.com [136.143.188.12]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id A8393262A6; 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Acked-by: Rob Herring (Arm) Signed-off-by: Junhui Liu --- Documentation/devicetree/bindings/timer/sifive,clint.yaml | 1 + 1 file changed, 1 insertion(+) diff --git a/Documentation/devicetree/bindings/timer/sifive,clint.yaml b/Do= cumentation/devicetree/bindings/timer/sifive,clint.yaml index d85a1a088b35dabc0aa202475b926302705c4cf1..16b8c0bdce82a55765046cfdc8d= 1f85a8dfb3912 100644 --- a/Documentation/devicetree/bindings/timer/sifive,clint.yaml +++ b/Documentation/devicetree/bindings/timer/sifive,clint.yaml @@ -29,6 +29,7 @@ properties: oneOf: - items: - enum: + - anlogic,dr1v90-clint # Anlogic DR1V90 - canaan,k210-clint # Canaan Kendryte K210 - eswin,eic7700-clint # ESWIN EIC7700 - sifive,fu540-c000-clint # SiFive FU540 --=20 2.51.0 From nobody Thu Oct 2 05:05:15 2025 Received: from sender4-op-o12.zoho.com (sender4-op-o12.zoho.com [136.143.188.12]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id BB30230AAA9; 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Signed-off-by: Junhui Liu Acked-by: Conor Dooley --- .../devicetree/bindings/interrupt-controller/sifive,plic-1.0.0.yaml |= 1 + 1 file changed, 1 insertion(+) diff --git a/Documentation/devicetree/bindings/interrupt-controller/sifive,= plic-1.0.0.yaml b/Documentation/devicetree/bindings/interrupt-controller/si= five,plic-1.0.0.yaml index 5b827bc243011cda1fd45d739d34eca95c6e1ee2..960d45432a1d7b1042af5674105= 3549f6a8df2cc 100644 --- a/Documentation/devicetree/bindings/interrupt-controller/sifive,plic-1.= 0.0.yaml +++ b/Documentation/devicetree/bindings/interrupt-controller/sifive,plic-1.= 0.0.yaml @@ -58,6 +58,7 @@ properties: - const: andestech,nceplic100 - items: - enum: + - anlogic,dr1v90-plic - canaan,k210-plic - sifive,fu540-c000-plic - spacemit,k1-plic --=20 2.51.0 From nobody Thu Oct 2 05:05:15 2025 Received: from sender4-op-o12.zoho.com (sender4-op-o12.zoho.com [136.143.188.12]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id 2BD4C309EF6; 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a=ed25519; pk=cgATWSU1KfGWmdwNmkPyHGnWgofhqqhE8Vts58wyxe4= X-ZohoMailClient: External The Anlogic DR1V90 SoC integrates a UART controller compatible with snps,dw-apb-uart, operating at a 50 MHz clock. Acked-by: Rob Herring (Arm) Signed-off-by: Junhui Liu --- Documentation/devicetree/bindings/serial/snps-dw-apb-uart.yaml | 1 + 1 file changed, 1 insertion(+) diff --git a/Documentation/devicetree/bindings/serial/snps-dw-apb-uart.yaml= b/Documentation/devicetree/bindings/serial/snps-dw-apb-uart.yaml index cb9da6c97afcfd27a315414959b2b17beb4454cf..691bd0bac6be449516e213b5504= 15acd37badad6 100644 --- a/Documentation/devicetree/bindings/serial/snps-dw-apb-uart.yaml +++ b/Documentation/devicetree/bindings/serial/snps-dw-apb-uart.yaml @@ -51,6 +51,7 @@ properties: - const: renesas,rzn1-uart - items: - enum: + - anlogic,dr1v90-uart - brcm,bcm11351-dw-apb-uart - brcm,bcm21664-dw-apb-uart - rockchip,px30-uart --=20 2.51.0 From nobody Thu Oct 2 05:05:15 2025 Received: from sender4-op-o12.zoho.com (sender4-op-o12.zoho.com [136.143.188.12]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id CE9F72ED164; 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a=ed25519; pk=cgATWSU1KfGWmdwNmkPyHGnWgofhqqhE8Vts58wyxe4= X-ZohoMailClient: External The first SoC in the Anlogic series is DR1V90, which contains a RISC-V core from Nuclei. Signed-off-by: Junhui Liu Acked-by: Conor Dooley --- arch/riscv/Kconfig.socs | 5 +++++ 1 file changed, 5 insertions(+) diff --git a/arch/riscv/Kconfig.socs b/arch/riscv/Kconfig.socs index 61ceae0aa27a6fa3a91da6a46becfd96da99fd09..c1c0681f4364647477c50518725= d9323922ff270 100644 --- a/arch/riscv/Kconfig.socs +++ b/arch/riscv/Kconfig.socs @@ -7,6 +7,11 @@ config ARCH_ANDES help This enables support for Andes SoC platform hardware. =20 +config ARCH_ANLOGIC + bool "Anlogic SoCs" + help + This enables support for Anlogic SoC platform hardware. + config ARCH_MICROCHIP_POLARFIRE def_bool ARCH_MICROCHIP =20 --=20 2.51.0 From nobody Thu Oct 2 05:05:15 2025 Received: from sender4-op-o12.zoho.com (sender4-op-o12.zoho.com [136.143.188.12]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id 534E614A62B; Mon, 22 Sep 2025 12:58:10 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=pass smtp.client-ip=136.143.188.12 ARC-Seal: i=2; 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a=ed25519; pk=cgATWSU1KfGWmdwNmkPyHGnWgofhqqhE8Vts58wyxe4= X-ZohoMailClient: External DR1V90 is a FPSoC from Anlogic, which features a RISC-V core as the PS part and 94,464 LUTs for the PL part. The PS part integrates a Nuclei UX900 RISC-V core with 32KB L1 icache and 32KB L1 dcache. It also provides two "snps,dw-apb-uart" compatible UART controllers. Some basic information of the processor can be obtained by running a simple application from nuclei-sdk [1]: Acked-by: Conor Dooley -----Nuclei RISC-V CPU Configuration Information----- MARCHID: 0xc900 MIMPID: 0x20300 ISA: RV64 A B C D F I M P S U MCFG: TEE ECC ECLIC PLIC PPI ILM DLM ICACHE DCACHE IREGION No-S= afety-Mechanism DLEN=3DVLEN/2 ILM: 256 KB has-ecc DLM: 256 KB has-ecc ICACHE: 32 KB(set=3D256,way=3D2,lsize=3D64,ecc=3D1) DCACHE: 32 KB(set=3D256,way=3D2,lsize=3D64,ecc=3D1) TLB: MainTLB(set=3D32,way=3D2,entry=3D1,ecc=3D1) ITLB(entry=3D= 8) DTLB(entry=3D8) IREGION: 0x68000000 128 MB Unit Size Address INFO 64KB 0x68000000 DEBUG 64KB 0x68010000 ECLIC 64KB 0x68020000 TIMER 64KB 0x68030000 PLIC 64MB 0x6c000000 INFO-Detail: mpasize : 0 PPI: 0xf8000000 128 MB -----End of Nuclei CPU INFO----- Link: https://github.com/Nuclei-Software/nuclei-sdk/blob/master/application= /baremetal/cpuinfo/main.c [1] Signed-off-by: Junhui Liu --- arch/riscv/boot/dts/anlogic/dr1v90.dtsi | 85 +++++++++++++++++++++++++++++= ++++ 1 file changed, 85 insertions(+) diff --git a/arch/riscv/boot/dts/anlogic/dr1v90.dtsi b/arch/riscv/boot/dts/= anlogic/dr1v90.dtsi new file mode 100644 index 0000000000000000000000000000000000000000..f9f8754ceb5247d3ca25e6a65b3= f915916ba6173 --- /dev/null +++ b/arch/riscv/boot/dts/anlogic/dr1v90.dtsi @@ -0,0 +1,85 @@ +// SPDX-License-Identifier: GPL-2.0 OR MIT +/* + * Copyright (C) 2025 Junhui Liu + */ + +/dts-v1/; +/ { + #address-cells =3D <2>; + #size-cells =3D <2>; + model =3D "Anlogic DR1V90"; + compatible =3D "anlogic,dr1v90"; + + cpus { + #address-cells =3D <1>; + #size-cells =3D <0>; + timebase-frequency =3D <800000000>; + + cpu@0 { + compatible =3D "nuclei,ux900", "riscv"; + d-cache-block-size =3D <64>; + d-cache-sets =3D <256>; + d-cache-size =3D <32768>; + device_type =3D "cpu"; + i-cache-block-size =3D <64>; + i-cache-sets =3D <256>; + i-cache-size =3D <32768>; + mmu-type =3D "riscv,sv39"; + reg =3D <0>; + riscv,isa-base =3D "rv64i"; + riscv,isa-extensions =3D "i", "m", "a", "f", "d", "c", "zba", "zbb", "z= bc", + "zbkc", "zbs", "zicntr", "zicsr", "zifencei", + "zihintpause", "zihpm"; + + cpu0_intc: interrupt-controller { + compatible =3D "riscv,cpu-intc"; + #interrupt-cells =3D <1>; + interrupt-controller; + }; + }; + }; + + soc { + compatible =3D "simple-bus"; + interrupt-parent =3D <&plic>; + #address-cells =3D <2>; + #size-cells =3D <2>; + ranges; + + clint: timer@68031000 { + compatible =3D "anlogic,dr1v90-clint", "sifive,clint0"; + reg =3D <0x0 0x68031000 0x0 0xc000>; + interrupts-extended =3D <&cpu0_intc 3>, <&cpu0_intc 7>; + }; + + plic: interrupt-controller@6c000000 { + compatible =3D "anlogic,dr1v90-plic", "sifive,plic-1.0.0"; + reg =3D <0x0 0x6c000000 0x0 0x4000000>; + #address-cells =3D <0>; + #interrupt-cells =3D <1>; + interrupt-controller; + interrupts-extended =3D <&cpu0_intc 11>, <&cpu0_intc 9>; + riscv,ndev =3D <150>; + }; + + uart0: serial@f8400000 { + compatible =3D "anlogic,dr1v90-uart", "snps,dw-apb-uart"; + reg =3D <0x0 0xf8400000 0x0 0x1000>; + clock-frequency =3D <50000000>; + interrupts =3D <71>; + reg-io-width =3D <4>; + reg-shift =3D <2>; + status =3D "disabled"; + }; + + uart1: serial@f8401000 { + compatible =3D "anlogic,dr1v90-uart", "snps,dw-apb-uart"; + reg =3D <0x0 0xf8401000 0x0 0x1000>; + clock-frequency =3D <50000000>; + interrupts =3D <72>; + reg-io-width =3D <4>; + reg-shift =3D <2>; + status =3D "disabled"; + }; + }; +}; --=20 2.51.0 From nobody Thu Oct 2 05:05:15 2025 Received: from sender4-op-o12.zoho.com (sender4-op-o12.zoho.com [136.143.188.12]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id F2D7C3064A0; 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a=ed25519; pk=cgATWSU1KfGWmdwNmkPyHGnWgofhqqhE8Vts58wyxe4= X-ZohoMailClient: External Add support for the Milianke MLKPAI FS01 board based on the Anlogic DR1V90 SoC. The board features 512MB of onboard memory, USB-C UART, 1GbE RJ45 Ethernet, USB-A 2.0 port, TF card slot, and 256Mbit Quad-SPI flash. Currently, the board can boot to a console via UART1, which is connected to the onboard serial chip and routed to the Type-C interface. Signed-off-by: Junhui Liu Acked-by: Conor Dooley --- arch/riscv/boot/dts/Makefile | 1 + arch/riscv/boot/dts/anlogic/Makefile | 2 ++ arch/riscv/boot/dts/anlogic/dr1v90-mlkpai-fs01.dts | 28 ++++++++++++++++++= ++++ 3 files changed, 31 insertions(+) diff --git a/arch/riscv/boot/dts/Makefile b/arch/riscv/boot/dts/Makefile index 3b99e91efa25be2d6ca5bc173342c24a72f87187..3c0005ee037406ac3285ec46621= 02c68592387a3 100644 --- a/arch/riscv/boot/dts/Makefile +++ b/arch/riscv/boot/dts/Makefile @@ -1,6 +1,7 @@ # SPDX-License-Identifier: GPL-2.0 subdir-y +=3D allwinner subdir-y +=3D andes +subdir-y +=3D anlogic subdir-y +=3D canaan subdir-y +=3D microchip subdir-y +=3D renesas diff --git a/arch/riscv/boot/dts/anlogic/Makefile b/arch/riscv/boot/dts/anl= ogic/Makefile new file mode 100644 index 0000000000000000000000000000000000000000..87f3b2f418cfa32012df5ae82d1= 7262a9610f90c --- /dev/null +++ b/arch/riscv/boot/dts/anlogic/Makefile @@ -0,0 +1,2 @@ +# SPDX-License-Identifier: GPL-2.0 +dtb-$(CONFIG_ARCH_ANLOGIC) +=3D dr1v90-mlkpai-fs01.dtb diff --git a/arch/riscv/boot/dts/anlogic/dr1v90-mlkpai-fs01.dts b/arch/risc= v/boot/dts/anlogic/dr1v90-mlkpai-fs01.dts new file mode 100644 index 0000000000000000000000000000000000000000..597407655efd2e74608dabb4559= ab1239662cf41 --- /dev/null +++ b/arch/riscv/boot/dts/anlogic/dr1v90-mlkpai-fs01.dts @@ -0,0 +1,28 @@ +// SPDX-License-Identifier: GPL-2.0 OR MIT +/* + * Copyright (C) 2025 Junhui Liu + */ + +#include "dr1v90.dtsi" + +/ { + model =3D "Milianke MLKPAI-FS01"; + compatible =3D "milianke,mlkpai-fs01", "anlogic,dr1v90"; + + aliases { + serial0 =3D &uart1; + }; + + chosen { + stdout-path =3D "serial0:115200n8"; + }; + + memory@0 { + device_type =3D "memory"; + reg =3D <0x0 0x0 0x0 0x20000000>; + }; +}; + +&uart1 { + status =3D "okay"; +}; --=20 2.51.0 From nobody Thu Oct 2 05:05:15 2025 Received: from sender4-op-o12.zoho.com (sender4-op-o12.zoho.com [136.143.188.12]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id D2B8F30648D; Mon, 22 Sep 2025 13:01:07 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=pass smtp.client-ip=136.143.188.12 ARC-Seal: i=2; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1758546070; cv=pass; b=ConWViZ7Awsl2881hpKOtySg6QlNWXfSLcg2Cp/2kPQKxKKds9j85y+u1XsnAmSBClhplp5vIyInbIkkCm01IPr2/RWFsNlmuEQaAxQBCGmuev8f6FfRglv2VVNOE7If7XQpoHB2En3UZwyl3cNaejQFtzt+/T0s9SudjgD0oOQ= ARC-Message-Signature: i=2; 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Signed-off-by: Junhui Liu Acked-by: Conor Dooley --- arch/riscv/configs/defconfig | 1 + 1 file changed, 1 insertion(+) diff --git a/arch/riscv/configs/defconfig b/arch/riscv/configs/defconfig index 7b5eed17611ad2260a28f9fe9985b88682eb1ebe..889a9f779c94a33b0164626b372= 6e11ac8cf357e 100644 --- a/arch/riscv/configs/defconfig +++ b/arch/riscv/configs/defconfig @@ -23,6 +23,7 @@ CONFIG_CHECKPOINT_RESTORE=3Dy CONFIG_BLK_DEV_INITRD=3Dy CONFIG_PROFILING=3Dy CONFIG_ARCH_ANDES=3Dy +CONFIG_ARCH_ANLOGIC=3Dy CONFIG_ARCH_MICROCHIP=3Dy CONFIG_ARCH_SIFIVE=3Dy CONFIG_ARCH_SOPHGO=3Dy --=20 2.51.0 From nobody Thu Oct 2 05:05:15 2025 Received: from sender4-op-o12.zoho.com (sender4-op-o12.zoho.com [136.143.188.12]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id 16AE913A3ED; Mon, 22 Sep 2025 13:01:37 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=pass smtp.client-ip=136.143.188.12 ARC-Seal: i=2; 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charset="utf-8" Content-Transfer-Encoding: quoted-printable Message-Id: <20250922-dr1v90-basic-dt-v2-11-64d28500cb37@pigmoral.tech> References: <20250922-dr1v90-basic-dt-v2-0-64d28500cb37@pigmoral.tech> In-Reply-To: <20250922-dr1v90-basic-dt-v2-0-64d28500cb37@pigmoral.tech> To: Rob Herring , Krzysztof Kozlowski , Conor Dooley , Paul Walmsley , Palmer Dabbelt , Albert Ou , Alexandre Ghiti , Daniel Lezcano , Thomas Gleixner , Samuel Holland , Anup Patel , Greg Kroah-Hartman , Jiri Slaby , Junhui Liu Cc: devicetree@vger.kernel.org, linux-kernel@vger.kernel.org, Palmer Dabbelt , Conor Dooley , linux-riscv@lists.infradead.org, linux-serial@vger.kernel.org X-Mailer: b4 0.14.2 X-Developer-Signature: v=1; a=ed25519-sha256; t=1758545232; l=1069; i=junhui.liu@pigmoral.tech; s=20250910; h=from:subject:message-id; bh=5FXdFyIr2fRFf+Ae1txoKmwxWECY148pHNFz1j152tE=; b=IKikTb5co2cwNgrDLxDroyXreMVTXAoHZa+CQqra3scT3SaZzrdaZa1Q1MeY0mcQp56V9YJ9N EfVgRbMK/4CBSfh0ZHiW5jirdnKVjs3bog/WzarlnDoxYotD+QM6oEj X-Developer-Key: i=junhui.liu@pigmoral.tech; a=ed25519; pk=cgATWSU1KfGWmdwNmkPyHGnWgofhqqhE8Vts58wyxe4= X-ZohoMailClient: External Add myself as the maintainer of the Anlogic DR1V90 SoC tree, including the corresponding DTS and DT bindings paths for Anlogic RISC-V-based SoCs. Signed-off-by: Junhui Liu Acked-by: Conor Dooley --- MAINTAINERS | 9 +++++++++ 1 file changed, 9 insertions(+) diff --git a/MAINTAINERS b/MAINTAINERS index 520fb4e379a3954ff9b163bfdfda857e5c5b99d4..44b4b4f7e53c5904f6b9076f954= 2866292d33fce 100644 --- a/MAINTAINERS +++ b/MAINTAINERS @@ -21681,6 +21681,15 @@ T: git git://git.kernel.org/pub/scm/linux/kernel/g= it/iommu/linux.git F: Documentation/devicetree/bindings/iommu/riscv,iommu.yaml F: drivers/iommu/riscv/ =20 +RISC-V ANLOGIC DR1V90 SoC SUPPORT +M: Junhui Liu +L: linux-riscv@lists.infradead.org +S: Maintained +T: git https://github.com/pigmoral/linux-dr1v90 +F: Documentation/devicetree/bindings/riscv/anlogic.yaml +F: arch/riscv/boot/dts/anlogic/ +N: dr1v90 + RISC-V MICROCHIP FPGA SUPPORT M: Conor Dooley M: Daire McNamara --=20 2.51.0