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[2a02:8440:750d:3377:171e:75f8:f2d4:2af8]) by smtp.gmail.com with ESMTPSA id ffacd0b85a97d-3ee073f3d8csm17958416f8f.9.2025.09.22.01.12.31 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Mon, 22 Sep 2025 01:12:32 -0700 (PDT) From: =?utf-8?q?Cl=C3=A9ment_Le_Goffic?= Date: Mon, 22 Sep 2025 10:12:19 +0200 Subject: [PATCH v7 2/3] clk: stm32mp25: add firewall grant_access ops Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Content-Transfer-Encoding: quoted-printable Message-Id: <20250922-b4-rcc-upstream-v7-2-2dfc4e018f40@gmail.com> References: <20250922-b4-rcc-upstream-v7-0-2dfc4e018f40@gmail.com> In-Reply-To: <20250922-b4-rcc-upstream-v7-0-2dfc4e018f40@gmail.com> To: Michael Turquette , Stephen Boyd , Rob Herring , Krzysztof Kozlowski , Conor Dooley , Maxime Coquelin , Alexandre Torgue , Gabriel Fernandez Cc: linux-clk@vger.kernel.org, devicetree@vger.kernel.org, linux-stm32@st-md-mailman.stormreply.com, linux-arm-kernel@lists.infradead.org, linux-kernel@vger.kernel.org, =?utf-8?q?Cl=C3=A9ment_Le_Goffic?= , =?utf-8?q?Cl=C3=A9ment_Le_Goffic?= X-Mailer: b4 0.15-dev-0dae4 From: Cl=C3=A9ment Le Goffic On STM32MP25, the RCC peripheral manages the secure level of resources that are used by other devices such as clocks. Declare this peripheral as a firewall controller. Signed-off-by: Cl=C3=A9ment Le Goffic Signed-off-by: Cl=C3=A9ment Le Goffic --- drivers/clk/stm32/clk-stm32mp25.c | 40 +++++++++++++++++++++++++++++++++++= +++- 1 file changed, 39 insertions(+), 1 deletion(-) diff --git a/drivers/clk/stm32/clk-stm32mp25.c b/drivers/clk/stm32/clk-stm3= 2mp25.c index 52f0e8a12926..af4bc06d703a 100644 --- a/drivers/clk/stm32/clk-stm32mp25.c +++ b/drivers/clk/stm32/clk-stm32mp25.c @@ -4,8 +4,10 @@ * Author: Gabriel Fernandez for STMicroel= ectronics. */ =20 +#include #include #include +#include #include #include =20 @@ -1602,6 +1604,11 @@ static int stm32_rcc_get_access(void __iomem *base, = u32 index) return 0; } =20 +static int stm32mp25_rcc_grant_access(struct stm32_firewall_controller *ct= rl, u32 firewall_id) +{ + return stm32_rcc_get_access(ctrl->mmio, firewall_id); +} + static int stm32mp25_check_security(struct device_node *np, void __iomem *= base, const struct clock_config *cfg) { @@ -1970,6 +1977,7 @@ MODULE_DEVICE_TABLE(of, stm32mp25_match_data); =20 static int stm32mp25_rcc_clocks_probe(struct platform_device *pdev) { + struct stm32_firewall_controller *rcc_controller; struct device *dev =3D &pdev->dev; void __iomem *base; int ret; @@ -1982,7 +1990,36 @@ static int stm32mp25_rcc_clocks_probe(struct platfor= m_device *pdev) if (ret) return ret; =20 - return stm32_rcc_init(dev, stm32mp25_match_data, base); + ret =3D stm32_rcc_init(dev, stm32mp25_match_data, base); + if (ret) + return ret; + + rcc_controller =3D devm_kzalloc(&pdev->dev, sizeof(*rcc_controller), GFP_= KERNEL); + if (!rcc_controller) + return -ENOMEM; + + rcc_controller->dev =3D dev; + rcc_controller->mmio =3D base; + rcc_controller->name =3D dev_driver_string(dev); + rcc_controller->type =3D STM32_PERIPHERAL_FIREWALL; + rcc_controller->grant_access =3D stm32mp25_rcc_grant_access; + + platform_set_drvdata(pdev, rcc_controller); + + ret =3D stm32_firewall_controller_register(rcc_controller); + if (ret) { + dev_err(dev, "Couldn't register as a firewall controller: %d\n", ret); + return ret; + } + + return 0; +} + +static void stm32mp25_rcc_clocks_remove(struct platform_device *pdev) +{ + struct stm32_firewall_controller *rcc_controller =3D platform_get_drvdata= (pdev); + + stm32_firewall_controller_unregister(rcc_controller); } =20 static struct platform_driver stm32mp25_rcc_clocks_driver =3D { @@ -1991,6 +2028,7 @@ static struct platform_driver stm32mp25_rcc_clocks_dr= iver =3D { .of_match_table =3D stm32mp25_match_data, }, .probe =3D stm32mp25_rcc_clocks_probe, + .remove =3D stm32mp25_rcc_clocks_remove, }; =20 static int __init stm32mp25_clocks_init(void) --=20 2.43.0