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[2a02:8440:750d:3377:171e:75f8:f2d4:2af8]) by smtp.gmail.com with ESMTPSA id ffacd0b85a97d-3f3c118cd47sm10016624f8f.29.2025.09.22.03.06.23 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Mon, 22 Sep 2025 03:06:23 -0700 (PDT) From: =?utf-8?q?Cl=C3=A9ment_Le_Goffic?= Date: Mon, 22 Sep 2025 12:06:16 +0200 Subject: [PATCH v7 3/7] dt-bindings: memory: factorise LPDDR channel binding into SDRAM channel Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Content-Transfer-Encoding: quoted-printable Message-Id: <20250922-b4-ddr-bindings-v7-3-b3dd20e54db6@gmail.com> References: <20250922-b4-ddr-bindings-v7-0-b3dd20e54db6@gmail.com> In-Reply-To: <20250922-b4-ddr-bindings-v7-0-b3dd20e54db6@gmail.com> To: Krzysztof Kozlowski , Rob Herring , Conor Dooley , Julius Werner , Krzysztof Kozlowski , Maxime Coquelin , Alexandre Torgue Cc: linux-kernel@vger.kernel.org, devicetree@vger.kernel.org, linux-stm32@st-md-mailman.stormreply.com, linux-arm-kernel@lists.infradead.org, =?utf-8?q?Cl=C3=A9ment_Le_Goffic?= , =?utf-8?q?Cl=C3=A9ment_Le_Goffic?= X-Mailer: b4 0.15-dev-0dae4 From: Cl=C3=A9ment Le Goffic LPDDR, DDR and so SDRAM channels exist and share the same properties, they have a compatible, ranks, and an io-width. Signed-off-by: Cl=C3=A9ment Le Goffic Reviewed-by: Rob Herring (Arm) Signed-off-by: Cl=C3=A9ment Le Goffic --- ...lpddr-channel.yaml =3D> jedec,sdram-channel.yaml} | 23 +++++++++++-----= ------ 1 file changed, 12 insertions(+), 11 deletions(-) diff --git a/Documentation/devicetree/bindings/memory-controllers/ddr/jedec= ,lpddr-channel.yaml b/Documentation/devicetree/bindings/memory-controllers/= ddr/jedec,sdram-channel.yaml similarity index 83% rename from Documentation/devicetree/bindings/memory-controllers/ddr/jedec,= lpddr-channel.yaml rename to Documentation/devicetree/bindings/memory-controllers/ddr/jedec,sd= ram-channel.yaml index 34b5bd153f63..9892da520fe4 100644 --- a/Documentation/devicetree/bindings/memory-controllers/ddr/jedec,lpddr-= channel.yaml +++ b/Documentation/devicetree/bindings/memory-controllers/ddr/jedec,sdram-= channel.yaml @@ -1,16 +1,17 @@ # SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause) %YAML 1.2 --- -$id: http://devicetree.org/schemas/memory-controllers/ddr/jedec,lpddr-chan= nel.yaml# +$id: http://devicetree.org/schemas/memory-controllers/ddr/jedec,sdram-chan= nel.yaml# $schema: http://devicetree.org/meta-schemas/core.yaml# =20 -title: LPDDR channel with chip/rank topology description +title: SDRAM channel with chip/rank topology description =20 description: - An LPDDR channel is a completely independent set of LPDDR pins (DQ, CA, = CS, - CK, etc.) that connect one or more LPDDR chips to a host system. The main - purpose of this node is to overall LPDDR topology of the system, includi= ng the - amount of individual LPDDR chips and the ranks per chip. + A memory channel of SDRAM memory like DDR SDRAM or LPDDR SDRAM is a comp= letely + independent set of pins (DQ, CA, CS, CK, etc.) that connect one or more = memory + chips to a host system. The main purpose of this node is to overall memo= ry + topology of the system, including the amount of individual memory chips = and + the ranks per chip. =20 maintainers: - Julius Werner @@ -26,14 +27,14 @@ properties: io-width: description: The number of DQ pins in the channel. If this number is different - from (a multiple of) the io-width of the LPDDR chip, that means that + from (a multiple of) the io-width of the SDRAM chip, that means that multiple instances of that type of chip are wired in parallel on this channel (with the channel's DQ pins split up between the different chips, and the CA, CS, etc. pins of the different chips all shorted together). This means that the total physical memory controlled by a channel is equal to the sum of the densities of each rank on the - connected LPDDR chip, times the io-width of the channel divided by - the io-width of the LPDDR chip. + connected SDRAM chip, times the io-width of the channel divided by + the io-width of the SDRAM chip. enum: - 8 - 16 @@ -51,8 +52,8 @@ patternProperties: "^rank@[0-9]+$": type: object description: - Each physical LPDDR chip may have one or more ranks. Ranks are - internal but fully independent sub-units of the chip. Each LPDDR bus + Each physical SDRAM chip may have one or more ranks. Ranks are + internal but fully independent sub-units of the chip. Each SDRAM bus transaction on the channel targets exactly one rank, based on the state of the CS pins. Different ranks may have different densities a= nd timing requirements. --=20 2.43.0