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[2a02:8440:750d:3377:171e:75f8:f2d4:2af8]) by smtp.gmail.com with ESMTPSA id 5b1f17b1804b1-464f527d6cdsm221291945e9.12.2025.09.22.03.06.20 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Mon, 22 Sep 2025 03:06:20 -0700 (PDT) From: =?utf-8?q?Cl=C3=A9ment_Le_Goffic?= Date: Mon, 22 Sep 2025 12:06:14 +0200 Subject: [PATCH v7 1/7] dt-bindings: memory: factorise LPDDR props into SDRAM props Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Content-Transfer-Encoding: quoted-printable Message-Id: <20250922-b4-ddr-bindings-v7-1-b3dd20e54db6@gmail.com> References: <20250922-b4-ddr-bindings-v7-0-b3dd20e54db6@gmail.com> In-Reply-To: <20250922-b4-ddr-bindings-v7-0-b3dd20e54db6@gmail.com> To: Krzysztof Kozlowski , Rob Herring , Conor Dooley , Julius Werner , Krzysztof Kozlowski , Maxime Coquelin , Alexandre Torgue Cc: linux-kernel@vger.kernel.org, devicetree@vger.kernel.org, linux-stm32@st-md-mailman.stormreply.com, linux-arm-kernel@lists.infradead.org, =?utf-8?q?Cl=C3=A9ment_Le_Goffic?= , =?utf-8?q?Cl=C3=A9ment_Le_Goffic?= X-Mailer: b4 0.15-dev-0dae4 From: Cl=C3=A9ment Le Goffic LPDDR and DDR bindings are SDRAM types and are likely to share the same properties (at least for density, io-width and reg). To avoid bindings duplication, factorise the properties. The compatible description has been updated because the MR (Mode registers) used to get manufacturer ID and revision ID are not present in case of DDR. Those information should be in a SPD (Serial Presence Detect) EEPROM in case of DIMM module or are known in case of soldered memory chips as they are in the datasheet of the memory chips. Signed-off-by: Cl=C3=A9ment Le Goffic Signed-off-by: Cl=C3=A9ment Le Goffic --- .../memory-controllers/ddr/jedec,lpddr-props.yaml | 74 ----------------- .../memory-controllers/ddr/jedec,lpddr2.yaml | 2 +- .../memory-controllers/ddr/jedec,lpddr3.yaml | 2 +- .../memory-controllers/ddr/jedec,lpddr4.yaml | 2 +- .../memory-controllers/ddr/jedec,lpddr5.yaml | 2 +- .../memory-controllers/ddr/jedec,sdram-props.yaml | 94 ++++++++++++++++++= ++++ 6 files changed, 98 insertions(+), 78 deletions(-) diff --git a/Documentation/devicetree/bindings/memory-controllers/ddr/jedec= ,lpddr-props.yaml b/Documentation/devicetree/bindings/memory-controllers/dd= r/jedec,lpddr-props.yaml deleted file mode 100644 index 30267ce70124..000000000000 --- a/Documentation/devicetree/bindings/memory-controllers/ddr/jedec,lpddr-= props.yaml +++ /dev/null @@ -1,74 +0,0 @@ -# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause) -%YAML 1.2 ---- -$id: http://devicetree.org/schemas/memory-controllers/ddr/jedec,lpddr-prop= s.yaml# -$schema: http://devicetree.org/meta-schemas/core.yaml# - -title: Common properties for LPDDR types - -description: - Different LPDDR types generally use the same properties and only differ = in the - range of legal values for each. This file defines the common parts that = can be - reused for each type. Nodes using this schema should generally be nested= under - an LPDDR channel node. - -maintainers: - - Krzysztof Kozlowski - -properties: - compatible: - description: - Compatible strings can be either explicit vendor names and part numb= ers - (e.g. elpida,ECB240ABACN), or generated strings of the form - lpddrX-YY,ZZZZ where X is the LPDDR version, YY is the manufacturer = ID - (from MR5) and ZZZZ is the revision ID (from MR6 and MR7). Both IDs = are - formatted in lower case hexadecimal representation with leading zero= es. - The latter form can be useful when LPDDR nodes are created at runtim= e by - boot firmware that doesn't have access to static part number informa= tion. - - reg: - description: - The rank number of this LPDDR rank when used as a subnode to an LPDDR - channel. - minimum: 0 - maximum: 3 - - revision-id: - $ref: /schemas/types.yaml#/definitions/uint32-array - description: - Revision IDs read from Mode Register 6 and 7. One byte per uint32 ce= ll (i.e. ). - maxItems: 2 - items: - minimum: 0 - maximum: 255 - - density: - $ref: /schemas/types.yaml#/definitions/uint32 - description: - Density in megabits of SDRAM chip. Decoded from Mode Register 8. - enum: - - 64 - - 128 - - 256 - - 512 - - 1024 - - 2048 - - 3072 - - 4096 - - 6144 - - 8192 - - 12288 - - 16384 - - 24576 - - 32768 - - io-width: - $ref: /schemas/types.yaml#/definitions/uint32 - description: - IO bus width in bits of SDRAM chip. Decoded from Mode Register 8. - enum: - - 8 - - 16 - - 32 - -additionalProperties: true diff --git a/Documentation/devicetree/bindings/memory-controllers/ddr/jedec= ,lpddr2.yaml b/Documentation/devicetree/bindings/memory-controllers/ddr/jed= ec,lpddr2.yaml index a237bc259273..704bbc562528 100644 --- a/Documentation/devicetree/bindings/memory-controllers/ddr/jedec,lpddr2= .yaml +++ b/Documentation/devicetree/bindings/memory-controllers/ddr/jedec,lpddr2= .yaml @@ -10,7 +10,7 @@ maintainers: - Krzysztof Kozlowski =20 allOf: - - $ref: jedec,lpddr-props.yaml# + - $ref: jedec,sdram-props.yaml# =20 properties: compatible: diff --git a/Documentation/devicetree/bindings/memory-controllers/ddr/jedec= ,lpddr3.yaml b/Documentation/devicetree/bindings/memory-controllers/ddr/jed= ec,lpddr3.yaml index e328a1195ba6..0d28df3d2bfa 100644 --- a/Documentation/devicetree/bindings/memory-controllers/ddr/jedec,lpddr3= .yaml +++ b/Documentation/devicetree/bindings/memory-controllers/ddr/jedec,lpddr3= .yaml @@ -10,7 +10,7 @@ maintainers: - Krzysztof Kozlowski =20 allOf: - - $ref: jedec,lpddr-props.yaml# + - $ref: jedec,sdram-props.yaml# =20 properties: compatible: diff --git a/Documentation/devicetree/bindings/memory-controllers/ddr/jedec= ,lpddr4.yaml b/Documentation/devicetree/bindings/memory-controllers/ddr/jed= ec,lpddr4.yaml index a078892fecee..65aa07861453 100644 --- a/Documentation/devicetree/bindings/memory-controllers/ddr/jedec,lpddr4= .yaml +++ b/Documentation/devicetree/bindings/memory-controllers/ddr/jedec,lpddr4= .yaml @@ -10,7 +10,7 @@ maintainers: - Krzysztof Kozlowski =20 allOf: - - $ref: jedec,lpddr-props.yaml# + - $ref: jedec,sdram-props.yaml# =20 properties: compatible: diff --git a/Documentation/devicetree/bindings/memory-controllers/ddr/jedec= ,lpddr5.yaml b/Documentation/devicetree/bindings/memory-controllers/ddr/jed= ec,lpddr5.yaml index e441dac5f154..cf5d5a8e94b3 100644 --- a/Documentation/devicetree/bindings/memory-controllers/ddr/jedec,lpddr5= .yaml +++ b/Documentation/devicetree/bindings/memory-controllers/ddr/jedec,lpddr5= .yaml @@ -10,7 +10,7 @@ maintainers: - Krzysztof Kozlowski =20 allOf: - - $ref: jedec,lpddr-props.yaml# + - $ref: jedec,sdram-props.yaml# =20 properties: compatible: diff --git a/Documentation/devicetree/bindings/memory-controllers/ddr/jedec= ,sdram-props.yaml b/Documentation/devicetree/bindings/memory-controllers/dd= r/jedec,sdram-props.yaml new file mode 100644 index 000000000000..38472a3febc5 --- /dev/null +++ b/Documentation/devicetree/bindings/memory-controllers/ddr/jedec,sdram-= props.yaml @@ -0,0 +1,94 @@ +# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause) +%YAML 1.2 +--- +$id: http://devicetree.org/schemas/memory-controllers/ddr/jedec,sdram-prop= s.yaml# +$schema: http://devicetree.org/meta-schemas/core.yaml# + +title: Common properties for SDRAM types + +description: + Different SDRAM types generally use the same properties and only differ = in the + range of legal values for each. This file defines the common parts that = can be + reused for each type. Nodes using this schema should generally be nested= under + a SDRAM channel node. + +maintainers: + - Krzysztof Kozlowski + +properties: + compatible: + description: | + Compatible strings can be either explicit vendor names and part numb= ers + (e.g. elpida,ECB240ABACN), or generated strings of the form + lpddrX,YY,ZZZZ or ddrX-YYYY,AAAA...,ZZ where X, Y, and Z are in lower + case hexadecimal with leading zeroes and A is in lowercase ASCII. + For LPDDR and DDR SDRAM, X is the SDRAM version (2, 3, 4, etc.). + For LPDDR SDRAM: + - YY is the manufacturer ID (from MR5), 1 byte + - ZZZZ is the revision ID (from MR6 and MR7), 2 bytes + For DDR4 SDRAM with SPD, according to JEDEC SPD4.1.2.L-6 : + - YYYY is the manufacturer ID, 2 bytes, from bytes 320 and 321 + - AAAA... is the part number, 20 bytes (10 chars) from bytes 329 t= o 348 + without trailing spaces. + - ZZ is the revision ID, 1 byte, from byte 349 + The former form is useful when the SDRAM vendor and part number are + known, such as when the SDRAM is soldered on the board. + The latter form can be useful when SDRAM nodes are created at runtim= e by + boot firmware that doesn't have access to statis part number informa= tion. + + reg: + description: + The rank number of this memory rank when used as a subnode to an mem= ory + channel. + minimum: 0 + maximum: 3 + + revision-id: + $ref: /schemas/types.yaml#/definitions/uint32-array + description: | + SDRAM revision ID: + - LPDDR SDRAM, decoded from Mode Register 6 and 7, always 2 bytes. + - DDR4 SDRAM, decoded from the SPD from byte 349 according to + JEDEC SPD4.1.2.L-6, always 1 byte. + One byte per uint32 cell (i.e. ). + maxItems: 2 + items: + minimum: 0 + maximum: 255 + + density: + $ref: /schemas/types.yaml#/definitions/uint32 + description: | + Density of SDRAM chip in megabits: + - LPDDR SDRAM, decoded from Mode Register 8. + - DDR4 SDRAM, decoded from the SPD from bits 3~0 of byte 4 accordi= ng to + JEDEC SPD4.1.2.L-6. + enum: + - 64 + - 128 + - 256 + - 512 + - 1024 + - 2048 + - 3072 + - 4096 + - 6144 + - 8192 + - 12288 + - 16384 + - 24576 + - 32768 + + io-width: + $ref: /schemas/types.yaml#/definitions/uint32 + description: | + IO bus width in bits of SDRAM chip: + - LPDDR SDRAM, decoded from Mode Register 8. + - DDR4 SDRAM, decoded from the SPD from bits 2~0 of byte 12 accord= ing to + JEDEC SPD4.1.2.L-6. + enum: + - 8 + - 16 + - 32 + +additionalProperties: true --=20 2.43.0 From nobody Thu Oct 2 04:44:14 2025 Received: from mail-wm1-f42.google.com (mail-wm1-f42.google.com [209.85.128.42]) (using TLSv1.2 with cipher ECDHE-RSA-AES128-GCM-SHA256 (128/128 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id 3CAF42F659C for ; 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Signed-off-by: Cl=C3=A9ment Le Goffic Signed-off-by: Cl=C3=A9ment Le Goffic --- .../memory-controllers/ddr/jedec,ddr4.yaml | 34 ++++++++++++++++++= ++++ 1 file changed, 34 insertions(+) diff --git a/Documentation/devicetree/bindings/memory-controllers/ddr/jedec= ,ddr4.yaml b/Documentation/devicetree/bindings/memory-controllers/ddr/jedec= ,ddr4.yaml new file mode 100644 index 000000000000..bf1dae15b65b --- /dev/null +++ b/Documentation/devicetree/bindings/memory-controllers/ddr/jedec,ddr4.y= aml @@ -0,0 +1,34 @@ +# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause) +%YAML 1.2 +--- +$id: http://devicetree.org/schemas/memory-controllers/ddr/jedec,ddr4.yaml# +$schema: http://devicetree.org/meta-schemas/core.yaml# + +title: DDR4 SDRAM compliant to JEDEC JESD79-4D + +maintainers: + - Krzysztof Kozlowski + +allOf: + - $ref: jedec,sdram-props.yaml# + +properties: + compatible: + items: + - pattern: "^ddr4-[0-9a-f]{4},[a-z]{1,10},[0-9a-f]{2}$" + - const: jedec,ddr4 + +required: + - compatible + - density + - io-width + +unevaluatedProperties: false + +examples: + - | + ddr { + compatible =3D "ddr4-00ff,azaz,ff", "jedec,ddr4"; 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[2a02:8440:750d:3377:171e:75f8:f2d4:2af8]) by smtp.gmail.com with ESMTPSA id ffacd0b85a97d-3f3c118cd47sm10016624f8f.29.2025.09.22.03.06.23 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Mon, 22 Sep 2025 03:06:23 -0700 (PDT) From: =?utf-8?q?Cl=C3=A9ment_Le_Goffic?= Date: Mon, 22 Sep 2025 12:06:16 +0200 Subject: [PATCH v7 3/7] dt-bindings: memory: factorise LPDDR channel binding into SDRAM channel Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Content-Transfer-Encoding: quoted-printable Message-Id: <20250922-b4-ddr-bindings-v7-3-b3dd20e54db6@gmail.com> References: <20250922-b4-ddr-bindings-v7-0-b3dd20e54db6@gmail.com> In-Reply-To: <20250922-b4-ddr-bindings-v7-0-b3dd20e54db6@gmail.com> To: Krzysztof Kozlowski , Rob Herring , Conor Dooley , Julius Werner , Krzysztof Kozlowski , Maxime Coquelin , Alexandre Torgue Cc: linux-kernel@vger.kernel.org, devicetree@vger.kernel.org, linux-stm32@st-md-mailman.stormreply.com, linux-arm-kernel@lists.infradead.org, =?utf-8?q?Cl=C3=A9ment_Le_Goffic?= , =?utf-8?q?Cl=C3=A9ment_Le_Goffic?= X-Mailer: b4 0.15-dev-0dae4 From: Cl=C3=A9ment Le Goffic LPDDR, DDR and so SDRAM channels exist and share the same properties, they have a compatible, ranks, and an io-width. Signed-off-by: Cl=C3=A9ment Le Goffic Reviewed-by: Rob Herring (Arm) Signed-off-by: Cl=C3=A9ment Le Goffic --- ...lpddr-channel.yaml =3D> jedec,sdram-channel.yaml} | 23 +++++++++++-----= ------ 1 file changed, 12 insertions(+), 11 deletions(-) diff --git a/Documentation/devicetree/bindings/memory-controllers/ddr/jedec= ,lpddr-channel.yaml b/Documentation/devicetree/bindings/memory-controllers/= ddr/jedec,sdram-channel.yaml similarity index 83% rename from Documentation/devicetree/bindings/memory-controllers/ddr/jedec,= lpddr-channel.yaml rename to Documentation/devicetree/bindings/memory-controllers/ddr/jedec,sd= ram-channel.yaml index 34b5bd153f63..9892da520fe4 100644 --- a/Documentation/devicetree/bindings/memory-controllers/ddr/jedec,lpddr-= channel.yaml +++ b/Documentation/devicetree/bindings/memory-controllers/ddr/jedec,sdram-= channel.yaml @@ -1,16 +1,17 @@ # SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause) %YAML 1.2 --- -$id: http://devicetree.org/schemas/memory-controllers/ddr/jedec,lpddr-chan= nel.yaml# +$id: http://devicetree.org/schemas/memory-controllers/ddr/jedec,sdram-chan= nel.yaml# $schema: http://devicetree.org/meta-schemas/core.yaml# =20 -title: LPDDR channel with chip/rank topology description +title: SDRAM channel with chip/rank topology description =20 description: - An LPDDR channel is a completely independent set of LPDDR pins (DQ, CA, = CS, - CK, etc.) that connect one or more LPDDR chips to a host system. The main - purpose of this node is to overall LPDDR topology of the system, includi= ng the - amount of individual LPDDR chips and the ranks per chip. + A memory channel of SDRAM memory like DDR SDRAM or LPDDR SDRAM is a comp= letely + independent set of pins (DQ, CA, CS, CK, etc.) that connect one or more = memory + chips to a host system. The main purpose of this node is to overall memo= ry + topology of the system, including the amount of individual memory chips = and + the ranks per chip. =20 maintainers: - Julius Werner @@ -26,14 +27,14 @@ properties: io-width: description: The number of DQ pins in the channel. If this number is different - from (a multiple of) the io-width of the LPDDR chip, that means that + from (a multiple of) the io-width of the SDRAM chip, that means that multiple instances of that type of chip are wired in parallel on this channel (with the channel's DQ pins split up between the different chips, and the CA, CS, etc. pins of the different chips all shorted together). This means that the total physical memory controlled by a channel is equal to the sum of the densities of each rank on the - connected LPDDR chip, times the io-width of the channel divided by - the io-width of the LPDDR chip. + connected SDRAM chip, times the io-width of the channel divided by + the io-width of the SDRAM chip. enum: - 8 - 16 @@ -51,8 +52,8 @@ patternProperties: "^rank@[0-9]+$": type: object description: - Each physical LPDDR chip may have one or more ranks. Ranks are - internal but fully independent sub-units of the chip. Each LPDDR bus + Each physical SDRAM chip may have one or more ranks. Ranks are + internal but fully independent sub-units of the chip. Each SDRAM bus transaction on the channel targets exactly one rank, based on the state of the CS pins. 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Signed-off-by: Cl=C3=A9ment Le Goffic Reviewed-by: Rob Herring (Arm) Signed-off-by: Cl=C3=A9ment Le Goffic --- .../bindings/memory-controllers/ddr/jedec,sdram-channel.yaml | 10 ++++++= ++++ 1 file changed, 10 insertions(+) diff --git a/Documentation/devicetree/bindings/memory-controllers/ddr/jedec= ,sdram-channel.yaml b/Documentation/devicetree/bindings/memory-controllers/= ddr/jedec,sdram-channel.yaml index 9892da520fe4..866af40b654d 100644 --- a/Documentation/devicetree/bindings/memory-controllers/ddr/jedec,sdram-= channel.yaml +++ b/Documentation/devicetree/bindings/memory-controllers/ddr/jedec,sdram-= channel.yaml @@ -19,6 +19,7 @@ maintainers: properties: compatible: enum: + - jedec,ddr4-channel - jedec,lpddr2-channel - jedec,lpddr3-channel - jedec,lpddr4-channel @@ -61,6 +62,15 @@ patternProperties: - reg =20 allOf: + - if: + properties: + compatible: + contains: + const: jedec,ddr4-channel + then: + patternProperties: + "^rank@[0-9]+$": + $ref: /schemas/memory-controllers/ddr/jedec,ddr4.yaml# - if: properties: compatible: --=20 2.43.0 From nobody Thu Oct 2 04:44:14 2025 Received: from mail-wr1-f45.google.com (mail-wr1-f45.google.com [209.85.221.45]) (using TLSv1.2 with cipher ECDHE-RSA-AES128-GCM-SHA256 (128/128 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id 418A02FF175 for ; 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Signed-off-by: Cl=C3=A9ment Le Goffic Reviewed-by: Rob Herring (Arm) Signed-off-by: Cl=C3=A9ment Le Goffic --- .../bindings/memory-controllers/ddr/jedec,sdram-channel.yaml | 7 +++= ++-- 1 file changed, 5 insertions(+), 2 deletions(-) diff --git a/Documentation/devicetree/bindings/memory-controllers/ddr/jedec= ,sdram-channel.yaml b/Documentation/devicetree/bindings/memory-controllers/= ddr/jedec,sdram-channel.yaml index 866af40b654d..5cdd8ef45100 100644 --- a/Documentation/devicetree/bindings/memory-controllers/ddr/jedec,sdram-= channel.yaml +++ b/Documentation/devicetree/bindings/memory-controllers/ddr/jedec,sdram-= channel.yaml @@ -17,6 +17,9 @@ maintainers: - Julius Werner =20 properties: + $nodename: + pattern: "sdram-channel-[0-9]+$" + compatible: enum: - jedec,ddr4-channel @@ -118,7 +121,7 @@ additionalProperties: false =20 examples: - | - lpddr-channel0 { + sdram-channel-0 { #address-cells =3D <1>; #size-cells =3D <0>; compatible =3D "jedec,lpddr3-channel"; @@ -133,7 +136,7 @@ examples: }; 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[2a02:8440:750d:3377:171e:75f8:f2d4:2af8]) by smtp.gmail.com with ESMTPSA id ffacd0b85a97d-3ee0fbc7188sm19867335f8f.37.2025.09.22.03.06.28 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Mon, 22 Sep 2025 03:06:29 -0700 (PDT) From: =?utf-8?q?Cl=C3=A9ment_Le_Goffic?= Date: Mon, 22 Sep 2025 12:06:20 +0200 Subject: [PATCH v7 7/7] arm64: dts: st: add DDR channel to stm32mp257f-ev1 board Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Content-Transfer-Encoding: quoted-printable Message-Id: <20250922-b4-ddr-bindings-v7-7-b3dd20e54db6@gmail.com> References: <20250922-b4-ddr-bindings-v7-0-b3dd20e54db6@gmail.com> In-Reply-To: <20250922-b4-ddr-bindings-v7-0-b3dd20e54db6@gmail.com> To: Krzysztof Kozlowski , Rob Herring , Conor Dooley , Julius Werner , Krzysztof Kozlowski , Maxime Coquelin , Alexandre Torgue Cc: linux-kernel@vger.kernel.org, devicetree@vger.kernel.org, linux-stm32@st-md-mailman.stormreply.com, linux-arm-kernel@lists.infradead.org, =?utf-8?q?Cl=C3=A9ment_Le_Goffic?= , =?utf-8?q?Cl=C3=A9ment_Le_Goffic?= X-Mailer: b4 0.15-dev-0dae4 From: Cl=C3=A9ment Le Goffic Add 32bits DDR4 channel to the stm32mp257f-dk board. Signed-off-by: Cl=C3=A9ment Le Goffic Signed-off-by: Cl=C3=A9ment Le Goffic --- arch/arm64/boot/dts/st/stm32mp257f-ev1.dts | 7 +++++++ 1 file changed, 7 insertions(+) diff --git a/arch/arm64/boot/dts/st/stm32mp257f-ev1.dts b/arch/arm64/boot/d= ts/st/stm32mp257f-ev1.dts index 836b1958ce65..c4223f06396a 100644 --- a/arch/arm64/boot/dts/st/stm32mp257f-ev1.dts +++ b/arch/arm64/boot/dts/st/stm32mp257f-ev1.dts @@ -41,6 +41,13 @@ pad_clk: pad-clk { }; }; =20 + ddr_channel: sdram-channel-0 { + #address-cells =3D <1>; + #size-cells =3D <0>; + compatible =3D "jedec,ddr4-channel"; + io-width =3D <32>; + }; + imx335_2v9: regulator-2v9 { compatible =3D "regulator-fixed"; regulator-name =3D "imx335-avdd"; --=20 2.43.0