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Bae" To: linux-kernel@vger.kernel.org Cc: x86@kernel.org, tglx@linutronix.de, mingo@redhat.com, bp@alien8.de, dave.hansen@linux.intel.com, chao.gao@intel.com, abusse@amazon.de, tony.luck@intel.com, chang.seok.bae@intel.com Subject: [PATCH v6 3/7] x86/microcode/intel: Establish staging control logic Date: Sun, 21 Sep 2025 15:48:37 -0700 Message-ID: <20250921224841.3545-4-chang.seok.bae@intel.com> X-Mailer: git-send-email 2.48.1 In-Reply-To: <20250921224841.3545-1-chang.seok.bae@intel.com> References: <20250921224841.3545-1-chang.seok.bae@intel.com> Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Content-Type: text/plain; charset="utf-8" When microcode staging is initiated, operations are carried out through an MMIO interface. Each package has a unique interface specified by the IA32_MCU_STAGING_MBOX_ADDR MSR, which maps to a set of 32-bit registers. Prepare staging with the following steps: 1. Ensure the microcode image is 32-bit aligned to match the MMIO register size. 2. Identify each MMIO interface based on its per-package scope. 3. Invoke the staging function for each identified interface, which will be implemented separately. Suggested-by: Thomas Gleixner Signed-off-by: Chang S. Bae Tested-by: Anselm Busse Reviewed-by: Tony Luck Link: https://lore.kernel.org/all/871pznq229.ffs@tglx --- V5 -> V6: * Remove stale text in changelog (Boris) * Place MSR definition in the right spot in msr-index.h (Boris) * Dump error code instead of vague message (Boris) * Collect Tony's review tag V4 -> V5: * Rebase on the primary thread cpumask fix (Dave) * Clean up the revision print code (Dave) * rdmsrl_on_cpu() -> rdmsrq_on_cpu (Chao) V2 -> V3: * Remove a global variable and adjust stage_microcode() (Dave). * Simplify for_each_cpu() loop control code * Handle rdmsrl_on_cpu() return code explicitly (Chao) V1 -> V2: * Adjust to reference the staging_state struct. * Add lockdep_assert_cpus_held() (Boris) --- arch/x86/include/asm/msr-index.h | 2 ++ arch/x86/kernel/cpu/microcode/intel.c | 48 +++++++++++++++++++++++++++ 2 files changed, 50 insertions(+) diff --git a/arch/x86/include/asm/msr-index.h b/arch/x86/include/asm/msr-in= dex.h index 718a55d82fe4..0736e44f7c69 100644 --- a/arch/x86/include/asm/msr-index.h +++ b/arch/x86/include/asm/msr-index.h @@ -1222,6 +1222,8 @@ #define MSR_IA32_VMX_VMFUNC 0x00000491 #define MSR_IA32_VMX_PROCBASED_CTLS3 0x00000492 =20 +#define MSR_IA32_MCU_STAGING_MBOX_ADDR 0x000007a5 + /* Resctrl MSRs: */ /* - Intel: */ #define MSR_IA32_L3_QOS_CFG 0xc81 diff --git a/arch/x86/kernel/cpu/microcode/intel.c b/arch/x86/kernel/cpu/mi= crocode/intel.c index 371ca6eac00e..daae74858347 100644 --- a/arch/x86/kernel/cpu/microcode/intel.c +++ b/arch/x86/kernel/cpu/microcode/intel.c @@ -299,6 +299,53 @@ static __init struct microcode_intel *scan_microcode(v= oid *data, size_t size, return size ? NULL : patch; } =20 +/* + * Handle the staging process using the mailbox MMIO interface. + * Return 0 on success or an error code on failure. + */ +static int do_stage(u64 mmio_pa) +{ + pr_debug_once("Staging implementation is pending.\n"); + return -EPROTONOSUPPORT; +} + +static void stage_microcode(void) +{ + unsigned int pkg_id =3D UINT_MAX; + int cpu, err; + u64 mmio_pa; + + if (!IS_ALIGNED(get_totalsize(&ucode_patch_late->hdr), sizeof(u32))) + return; + + lockdep_assert_cpus_held(); + + /* + * The MMIO address is unique per package, and all the SMT + * primary threads are online here. Find each MMIO space by + * their package ids to avoid duplicate staging. + */ + for_each_cpu(cpu, cpu_primary_thread_mask) { + if (topology_logical_package_id(cpu) =3D=3D pkg_id) + continue; + + pkg_id =3D topology_logical_package_id(cpu); + + err =3D rdmsrq_on_cpu(cpu, MSR_IA32_MCU_STAGING_MBOX_ADDR, &mmio_pa); + if (WARN_ON_ONCE(err)) + return; + + err =3D do_stage(mmio_pa); + if (err) { + pr_err("Error: staging failed (code =3D %d) for CPU%d at package %u.\n", + err, cpu, pkg_id); + return; + } + } + + pr_info("Staging of patch revision 0x%x succeeded.\n", ucode_patch_late->= hdr.rev); +} + static enum ucode_state __apply_microcode(struct ucode_cpu_info *uci, struct microcode_intel *mc, u32 *cur_rev) @@ -627,6 +674,7 @@ static struct microcode_ops microcode_intel_ops =3D { .collect_cpu_info =3D collect_cpu_info, .apply_microcode =3D apply_microcode_late, .finalize_late_load =3D finalize_late_load, + .stage_microcode =3D stage_microcode, .use_nmi =3D IS_ENABLED(CONFIG_X86_64), }; =20 --=20 2.48.1