From nobody Thu Oct 2 06:19:41 2025 Received: from sender4-op-o15.zoho.com (sender4-op-o15.zoho.com [136.143.188.15]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id 5835C221287; Sun, 21 Sep 2025 08:36:01 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=pass smtp.client-ip=136.143.188.15 ARC-Seal: i=2; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1758443762; cv=pass; b=Uv0ITRevrulpOboVzhVKPGcZXYfB+tSHK4+En1ga9jm86h46M/c1luWIWPGyImutWGy7bebg/v/Nv+QjAi9hR90j8CI+OByGXvrmbsGEi7dhVCF2r/HtlhgUznfk8Tg6fsBnPabDNEBXvEdrmWx/POk1AXruk+j0KLHezituNm4= ARC-Message-Signature: i=2; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1758443762; c=relaxed/simple; bh=LxbRM1vIIcAZKRXych6yKl9bLISYb+iu7HaZR6CpFvg=; h=From:To:Cc:Subject:Date:Message-ID:In-Reply-To:References: MIME-Version; b=J+Z328ZBdPDC4Ko6JH9JzEh5NPNxYtLFtNpIHc1EtEYGjWuPhOxLdDkuW2BAHe2yguJs/X5mNKRxkourdNHIZ9vkTLqfKAX6HfXBKom6vkIfgDnrtDJHz4pZ2+nEHeArotknXkxwKJJHoGfYXTD3l6ueTNH0OdeB2RYd9NN3S24= ARC-Authentication-Results: i=2; smtp.subspace.kernel.org; dmarc=pass (p=none dis=none) header.from=icenowy.me; spf=pass smtp.mailfrom=icenowy.me; dkim=pass (2048-bit key) header.d=icenowy.me header.i=uwu@icenowy.me header.b=oYhd4n59; arc=pass smtp.client-ip=136.143.188.15 Authentication-Results: smtp.subspace.kernel.org; dmarc=pass (p=none dis=none) header.from=icenowy.me Authentication-Results: smtp.subspace.kernel.org; spf=pass smtp.mailfrom=icenowy.me Authentication-Results: smtp.subspace.kernel.org; dkim=pass (2048-bit key) header.d=icenowy.me header.i=uwu@icenowy.me header.b="oYhd4n59" ARC-Seal: i=1; a=rsa-sha256; t=1758443726; cv=none; d=zohomail.com; s=zohoarc; b=gsMA6quhUM1kWSDHXIaOjv2msYYcL73neNuoI0yUGWd3pgSG5k1Nr3xw6/iGmhE8or6WTSU+h02o6J00Q4G1C+WD/PD+k2L/VwpJghuhigvkDjrnEzBN63GcSoSp6Rb93CxgmCx5qyJ/GsNRdaJ68+jcl7bt3X3n8ITDcl3EMug= ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=zohomail.com; s=zohoarc; t=1758443726; h=Content-Transfer-Encoding:Cc:Cc:Date:Date:From:From:In-Reply-To:MIME-Version:Message-ID:References:Subject:Subject:To:To:Message-Id:Reply-To; bh=efmETRccs8kLEdcb77jPapZRIKSB0g2ptOw7m7XUf8o=; b=WdwDiKpYm/wKw4bQhJGHMnrN12dA8NOAOUjExt9h8TL7Iy5ptVcweo9Xp+Tqglmy2FYhbQpqoiyHZSSh50ocvSUex/l1YWXWlWphMoKraw9QAiv902vWpgTOSv/CFJHuZf8n/InvZYzGoFPS43ful4Pnsfnt148XqfyHeqyUQoc= ARC-Authentication-Results: i=1; mx.zohomail.com; dkim=pass header.i=icenowy.me; spf=pass smtp.mailfrom=uwu@icenowy.me; dmarc=pass header.from= DKIM-Signature: v=1; a=rsa-sha256; q=dns/txt; c=relaxed/relaxed; t=1758443726; s=zmail2; d=icenowy.me; i=uwu@icenowy.me; h=From:From:To:To:Cc:Cc:Subject:Subject:Date:Date:Message-ID:In-Reply-To:References:MIME-Version:Content-Transfer-Encoding:Message-Id:Reply-To; bh=efmETRccs8kLEdcb77jPapZRIKSB0g2ptOw7m7XUf8o=; b=oYhd4n59U9zx2jaqND+0Vfz9I9c442p7Q4nnhK4NOZkLBr8dIvFb4yn1uPv645M9 2sYPqBY1FJk0XC6bol77PYKZ9tEIUB6ETO3755/n24t/GFR1VHAxCFtxekFo4VRFx76 r3lCFrRUYDOeNdKm6R0f6JqayBW4lvHEAmraA8BN86y/uhgk9IP+wID6uG0ZMUBnVOi Xi6lqK8keXavlInpSJyEYXNBdV5MzEDYWJjueoGSbUZcJRPC7kjGTttKQ9HiAnl/SDO rR7OmnTRXfdIYrjWafohEzaNRFZuXw8LEhgXVisza83K5zjb1MbO+PBBsYmC45M74YR XGsYU8GADA== Received: by mx.zohomail.com with SMTPS id 1758443723225109.34629747101064; Sun, 21 Sep 2025 01:35:23 -0700 (PDT) From: Icenowy Zheng To: Maarten Lankhorst , Maxime Ripard , Thomas Zimmermann , David Airlie , Simona Vetter , Rob Herring , Krzysztof Kozlowski , Conor Dooley , Drew Fustini , Guo Ren , Fu Wei , Philipp Zabel , Heiko Stuebner , Andrzej Hajda , Neil Armstrong , Robert Foss , Laurent Pinchart , Jonas Karlman , Jernej Skrabec , Michal Wilczynski Cc: Han Gao , Yao Zi , dri-devel@lists.freedesktop.org, devicetree@vger.kernel.org, linux-kernel@vger.kernel.org, linux-riscv@lists.infradead.org, Icenowy Zheng Subject: [PATCH v2 1/8] dt-bindings: vendor-prefixes: add verisilicon Date: Sun, 21 Sep 2025 16:34:39 +0800 Message-ID: <20250921083446.790374-2-uwu@icenowy.me> X-Mailer: git-send-email 2.51.0 In-Reply-To: <20250921083446.790374-1-uwu@icenowy.me> References: <20250921083446.790374-1-uwu@icenowy.me> Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable X-ZohoMailClient: External Content-Type: text/plain; charset="utf-8" VeriSilicon is a Silicon IP vendor, which is the current owner of Vivante series video-related IPs and Hantro series video codec IPs. Add a vendor prefix for this company. Signed-off-by: Icenowy Zheng Acked-by: Rob Herring (Arm) --- No changes in v2. Documentation/devicetree/bindings/vendor-prefixes.yaml | 2 ++ 1 file changed, 2 insertions(+) diff --git a/Documentation/devicetree/bindings/vendor-prefixes.yaml b/Docum= entation/devicetree/bindings/vendor-prefixes.yaml index 9ec8947dfcad2..b24ab511251b6 100644 --- a/Documentation/devicetree/bindings/vendor-prefixes.yaml +++ b/Documentation/devicetree/bindings/vendor-prefixes.yaml @@ -1656,6 +1656,8 @@ patternProperties: description: Variscite Ltd. "^vdl,.*": description: Van der Laan b.v. + "^verisilicon,.*": + description: VeriSilicon Microelectronics (Shanghai) Co., Ltd. "^vertexcom,.*": description: Vertexcom Technologies, Inc. "^via,.*": --=20 2.51.0 From nobody Thu Oct 2 06:19:41 2025 Received: from sender4-op-o15.zoho.com (sender4-op-o15.zoho.com [136.143.188.15]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id 5FF61173; Sun, 21 Sep 2025 08:36:22 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=pass smtp.client-ip=136.143.188.15 ARC-Seal: i=2; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1758443784; cv=pass; b=iCyK2spYGlKXD+EQCMDBDBWrewXrNhoKA3l4Wc9AIAD9vi1aEukrwx7F5aSUB3czG/vbKTSLHjK1AgsIpLvb2848A0jQZVTPsVEaAbOYvCmAPbDcHDUsZRMzZ8QKQjEOwTKRgQD9qWgU+WMhiFaldyoA6VcDSSoRAt7LPrrM0+8= ARC-Message-Signature: i=2; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1758443784; c=relaxed/simple; bh=RqLC0OHabIK2Usoy8P7sOPRsURrsxd+yc0qi1R0srpg=; h=From:To:Cc:Subject:Date:Message-ID:In-Reply-To:References: MIME-Version; b=Ih5HiLT2e+QyRv4qa3RjX55Yl4legwfJtypw5reFzGR2d8yWn97ZXfKn60MKZuRLwqsimcoVA4PfI5UVPywSDxqKoRRGAioQkkrnzScN8qQAlpTHF4gj/eY2efhuxCCOMzUKUCK6Jy+9F9FFpRfQ+gE2idxiDRpvoV7txh2pJRo= ARC-Authentication-Results: i=2; smtp.subspace.kernel.org; dmarc=pass (p=none dis=none) header.from=icenowy.me; spf=pass smtp.mailfrom=icenowy.me; dkim=pass (2048-bit key) header.d=icenowy.me header.i=uwu@icenowy.me header.b=GYrqDiGw; arc=pass smtp.client-ip=136.143.188.15 Authentication-Results: smtp.subspace.kernel.org; dmarc=pass (p=none dis=none) header.from=icenowy.me Authentication-Results: smtp.subspace.kernel.org; spf=pass smtp.mailfrom=icenowy.me Authentication-Results: smtp.subspace.kernel.org; dkim=pass (2048-bit key) header.d=icenowy.me header.i=uwu@icenowy.me header.b="GYrqDiGw" ARC-Seal: i=1; a=rsa-sha256; t=1758443737; cv=none; d=zohomail.com; s=zohoarc; b=ADDWRgmqXZCDzYwZeoMknYPylFGLq46uTQl+FwNqHYQyQZNi5wYyZ6BcyVegw3O64orDZ+SCrvHFXXRXm3lxn89DA5ytp1GZ+MkhtQ6Bm800gpFGUS4NgqVqRyWa4ybTC5uasmDu3QmKZ4jeDiAfjbiWg/6iNFio4B1CYVGV8pk= ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=zohomail.com; s=zohoarc; t=1758443737; h=Content-Transfer-Encoding:Cc:Cc:Date:Date:From:From:In-Reply-To:MIME-Version:Message-ID:References:Subject:Subject:To:To:Message-Id:Reply-To; bh=BzVuxTb2Ec94oHmJJK3j5PrFE2OXgoL9kzrNkPO5Lq4=; b=I1wm7nFsukKdC+rFRfNxzcu09Bj1ShESyD3RpmouPvRGAez1huwG/UUWjYomtd51hgWuFDBgFq9Yo22/fnH0UmCGPZ649Oje5XlkahaDFcaJlFDvy6k6BoyzF1dlfLoh4eSDBnSyuIZYAFsh9jS77LVZnf/sW2D5262uBpT2HUI= ARC-Authentication-Results: i=1; mx.zohomail.com; dkim=pass header.i=icenowy.me; spf=pass smtp.mailfrom=uwu@icenowy.me; dmarc=pass header.from= DKIM-Signature: v=1; a=rsa-sha256; q=dns/txt; c=relaxed/relaxed; t=1758443737; s=zmail2; d=icenowy.me; i=uwu@icenowy.me; h=From:From:To:To:Cc:Cc:Subject:Subject:Date:Date:Message-ID:In-Reply-To:References:MIME-Version:Content-Transfer-Encoding:Message-Id:Reply-To; bh=BzVuxTb2Ec94oHmJJK3j5PrFE2OXgoL9kzrNkPO5Lq4=; b=GYrqDiGw+IIN8iBsvyBbPrdKF25NVSGGBFtNd11Nz2HJXFscbq31w9FZpNOl6lid TaGlj/mGWT51S+pJhYy3jfOsuQ5PjxRihhCcAQBM7t6wFsGgUbiPVU15FKkmTqb5ILS y6vLPb3cUfp3Ofug9F+Q8lqt2HnLWkNh8N1kD3gWCMhb1CKARP1nXM0jEeGkkig+Htr oPKkKQB1mxWAX88CtoZWX7s8/oFuPqx6J9UeUii0aGpRkVztfxFsc2NfsEdQNMTmusc bry5PcBoT4VbbigpjCeokaxjXoaW8PKlMP1l8kcggFlOADfN6ld3tWfS8HovBzZINxr 5COB8hm/Nw== Received: by mx.zohomail.com with SMTPS id 1758443735773654.766181253001; Sun, 21 Sep 2025 01:35:35 -0700 (PDT) From: Icenowy Zheng To: Maarten Lankhorst , Maxime Ripard , Thomas Zimmermann , David Airlie , Simona Vetter , Rob Herring , Krzysztof Kozlowski , Conor Dooley , Drew Fustini , Guo Ren , Fu Wei , Philipp Zabel , Heiko Stuebner , Andrzej Hajda , Neil Armstrong , Robert Foss , Laurent Pinchart , Jonas Karlman , Jernej Skrabec , Michal Wilczynski Cc: Han Gao , Yao Zi , dri-devel@lists.freedesktop.org, devicetree@vger.kernel.org, linux-kernel@vger.kernel.org, linux-riscv@lists.infradead.org, Icenowy Zheng Subject: [PATCH v2 2/8] dt-bindings: display: add verisilicon,dc Date: Sun, 21 Sep 2025 16:34:40 +0800 Message-ID: <20250921083446.790374-3-uwu@icenowy.me> X-Mailer: git-send-email 2.51.0 In-Reply-To: <20250921083446.790374-1-uwu@icenowy.me> References: <20250921083446.790374-1-uwu@icenowy.me> Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable X-ZohoMailClient: External Content-Type: text/plain; charset="utf-8" Verisilicon has a series of display controllers prefixed with DC and with self-identification facility like their GC series GPUs. Add a device tree binding for it. Depends on the specific DC model, it can have either one or two display outputs, and each display output could be set to DPI signal or "DP" signal (which seems to be some plain parallel bus to HDMI controllers). Signed-off-by: Icenowy Zheng --- Changes in v2: - Fixed misspelt "versilicon" in title. - Moved minItems in clock properties to be earlier than items. - Re-aligned multi-line clocks and resets in example. .../bindings/display/verisilicon,dc.yaml | 127 ++++++++++++++++++ 1 file changed, 127 insertions(+) create mode 100644 Documentation/devicetree/bindings/display/verisilicon,d= c.yaml diff --git a/Documentation/devicetree/bindings/display/verisilicon,dc.yaml = b/Documentation/devicetree/bindings/display/verisilicon,dc.yaml new file mode 100644 index 0000000000000..07fedc4c7cc13 --- /dev/null +++ b/Documentation/devicetree/bindings/display/verisilicon,dc.yaml @@ -0,0 +1,127 @@ +# SPDX-License-Identifier: (GPL-2.0 OR BSD-2-Clause) +%YAML 1.2 +--- +$id: http://devicetree.org/schemas/display/verisilicon,dc.yaml# +$schema: http://devicetree.org/meta-schemas/core.yaml# + +title: Verisilicon DC-series display controllers + +maintainers: + - Icenowy Zheng + +properties: + $nodename: + pattern: "^display@[0-9a-f]+$" + + compatible: + const: verisilicon,dc + + reg: + maxItems: 1 + + interrupts: + maxItems: 1 + + clocks: + minItems: 4 + items: + - description: DC Core clock + - description: DMA AXI bus clock + - description: Configuration AHB bus clock + - description: Pixel clock of output 0 + - description: Pixel clock of output 1 + + clock-names: + minItems: 4 + items: + - const: core + - const: axi + - const: ahb + - const: pix0 + - const: pix1 + + resets: + items: + - description: DC Core reset + - description: DMA AXI bus reset + - description: Configuration AHB bus reset + + reset-names: + items: + - const: core + - const: axi + - const: ahb + + ports: + $ref: /schemas/graph.yaml#/properties/ports + + properties: + port@0: + $ref: /schemas/graph.yaml#/properties/port + description: The first output channel, endpoint 0 should be + used for DPI format output and endpoint 1 should be used + for DP format output. + + port@1: + $ref: /schemas/graph.yaml#/properties/port + description: The second output channel if the DC variant + supports and used. Follow the same endpoint addressing + rule with the first port. + + required: + - port@0 + +required: + - compatible + - reg + - interrupts + - clocks + - clock-names + - ports + +additionalProperties: false + +examples: + - | + #include + #include + #include + soc { + #address-cells =3D <2>; + #size-cells =3D <2>; + + display@ffef600000 { + compatible =3D "verisilicon,dc"; + reg =3D <0xff 0xef600000 0x0 0x100000>; + interrupts =3D <93 IRQ_TYPE_LEVEL_HIGH>; + clocks =3D <&clk_vo CLK_DPU_CCLK>, + <&clk_vo CLK_DPU_ACLK>, + <&clk_vo CLK_DPU_HCLK>, + <&clk_vo CLK_DPU_PIXELCLK0>, + <&clk_vo CLK_DPU_PIXELCLK1>; + clock-names =3D "core", "axi", "ahb", "pix0", "pix1"; + resets =3D <&rst TH1520_RESET_ID_DPU_CORE>, + <&rst TH1520_RESET_ID_DPU_AXI>, + <&rst TH1520_RESET_ID_DPU_AHB>; + reset-names =3D "core", "axi", "ahb"; + + ports { + #address-cells =3D <1>; + #size-cells =3D <0>; + port@0 { + reg =3D <0>; + }; + + port@1 { + reg =3D <1>; + #address-cells =3D <1>; + #size-cells =3D <0>; + + dpu_out_dp1: endpoint@1 { + reg =3D <1>; + remote-endpoint =3D <&hdmi_in>; + }; + }; + }; + }; + }; --=20 2.51.0 From nobody Thu Oct 2 06:19:41 2025 Received: from sender4-op-o15.zoho.com (sender4-op-o15.zoho.com [136.143.188.15]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id 81C2523E35F; Sun, 21 Sep 2025 08:36:32 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=pass smtp.client-ip=136.143.188.15 ARC-Seal: i=2; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1758443796; cv=pass; b=cXYUxvqURME0OfjJJNlaZY8Hhcmg9twL+HsoLA5pMsE76qARLItENI165QMt/FKxue9UpB3k7AdbpHXFx1wyYu6L9nrS6BhXwUY3CYIVU2V4umVUoivVoCfmD3WbsVn+lm/MYi6AmIwQpZhlLnj0VK2GhMCSqlac1lE6vQcf4jg= ARC-Message-Signature: i=2; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1758443796; c=relaxed/simple; bh=Uzy096oBg2JBCJ5dtwCM4xvYqiS5xoG1j7dTyuxvKF8=; h=From:To:Cc:Subject:Date:Message-ID:In-Reply-To:References: MIME-Version; b=BsL36WBQZewgUUgBCYwsUmKIrr3sFsUDXr7Fk7kb1Uwm+sx1S+nK+kNTBfIENlfcFU2UztHJ1c72lPcFnf5nfWGNgPzHWCZSkB3GMsz9VtXhfyCqayQUQ5GrlDIcLk/EPhODw61Z956bgfSrJi0AJdnTkwkP5dx64rQbDTve7fs= ARC-Authentication-Results: i=2; smtp.subspace.kernel.org; dmarc=pass (p=none dis=none) header.from=icenowy.me; spf=pass smtp.mailfrom=icenowy.me; dkim=pass (2048-bit key) header.d=icenowy.me header.i=uwu@icenowy.me header.b=bJsuA6Mp; arc=pass smtp.client-ip=136.143.188.15 Authentication-Results: smtp.subspace.kernel.org; dmarc=pass (p=none dis=none) header.from=icenowy.me Authentication-Results: smtp.subspace.kernel.org; spf=pass smtp.mailfrom=icenowy.me Authentication-Results: smtp.subspace.kernel.org; dkim=pass (2048-bit key) header.d=icenowy.me header.i=uwu@icenowy.me header.b="bJsuA6Mp" ARC-Seal: i=1; a=rsa-sha256; t=1758443749; cv=none; d=zohomail.com; s=zohoarc; b=kZzxXIqCUjH7/iwMEFCMr8ulqFqapCbhRM5CtQ6M4K10QvXxWmFthHEkzqL43vWxEj42L9yBoj7LNg17AL+Sj2u7HojhoVA7dj72OEqce3asIV1WubYno5yfz5RXQow4kDNuFsFAukrXxKijGVBIE5HLY5SLuXjdPosH9zUYGLk= ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=zohomail.com; s=zohoarc; t=1758443749; h=Content-Transfer-Encoding:Cc:Cc:Date:Date:From:From:In-Reply-To:MIME-Version:Message-ID:References:Subject:Subject:To:To:Message-Id:Reply-To; bh=ZQMW3pDG5WDodQGYeG70/5D1wcY//Br6I7ApUTIn31c=; b=jKLg4iplQhStR5g5crc+Tb6XOVTwifl+fpFaQ3dMreWh3TJG4E7t61OCpOFjopMeov1sDlv+H9W/Jn8a/7senawdO0LUWlwRk7Ia8v//6XPhGvqCgmBGHfRTK73RcHWvZKO4FxB2EUFOhBxVlxe5YuQjNrqLKfnehHrGRAhwGZY= ARC-Authentication-Results: i=1; mx.zohomail.com; dkim=pass header.i=icenowy.me; spf=pass smtp.mailfrom=uwu@icenowy.me; dmarc=pass header.from= DKIM-Signature: v=1; a=rsa-sha256; q=dns/txt; c=relaxed/relaxed; t=1758443748; s=zmail2; d=icenowy.me; i=uwu@icenowy.me; h=From:From:To:To:Cc:Cc:Subject:Subject:Date:Date:Message-ID:In-Reply-To:References:MIME-Version:Content-Transfer-Encoding:Message-Id:Reply-To; bh=ZQMW3pDG5WDodQGYeG70/5D1wcY//Br6I7ApUTIn31c=; b=bJsuA6MpOHlhryLBeKEsg3O6ffmN+xL1wF6EeJ/FJbjDvtAXLejOkQXNX8wNT7tT x+BGuB7S9szntmsTLnDU1hXuioX55QmV7gvb2TuOlINYOo29udvXpZbvl5acDs9pk7K QMrXiACk2+xag9ix+XQfucc5BJDVdt5difTzAIej3Wyd8oJGJ/NfC5Wk7KHPHzYMoWn oD+tQZuwAb6vEXSuzXgudQW+i+ZNUgISWj6s4lTnQ3ZYIXVPBDlR4RPZ2gwWC4LK5rE 0fymylMpetf1vmqGFTSJdIJ1LnCxeR2wFeBNwa6u8Ga2FIDDK1KwW4J6mOTBa3AOHX3 +yi7m1dFaQ== Received: by mx.zohomail.com with SMTPS id 1758443747174375.15260920239746; Sun, 21 Sep 2025 01:35:47 -0700 (PDT) From: Icenowy Zheng To: Maarten Lankhorst , Maxime Ripard , Thomas Zimmermann , David Airlie , Simona Vetter , Rob Herring , Krzysztof Kozlowski , Conor Dooley , Drew Fustini , Guo Ren , Fu Wei , Philipp Zabel , Heiko Stuebner , Andrzej Hajda , Neil Armstrong , Robert Foss , Laurent Pinchart , Jonas Karlman , Jernej Skrabec , Michal Wilczynski Cc: Han Gao , Yao Zi , dri-devel@lists.freedesktop.org, devicetree@vger.kernel.org, linux-kernel@vger.kernel.org, linux-riscv@lists.infradead.org, Icenowy Zheng Subject: [PATCH v2 3/8] drm: verisilicon: add a driver for Verisilicon display controllers Date: Sun, 21 Sep 2025 16:34:41 +0800 Message-ID: <20250921083446.790374-4-uwu@icenowy.me> X-Mailer: git-send-email 2.51.0 In-Reply-To: <20250921083446.790374-1-uwu@icenowy.me> References: <20250921083446.790374-1-uwu@icenowy.me> Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable X-ZohoMailClient: External Content-Type: text/plain; charset="utf-8" This is a from-scratch driver targeting Verisilicon DC-series display controllers, which feature self-identification functionality like their GC-series GPUs. Only DC8200 is being supported now, and only the main framebuffer is set up (as the DRM primary plane). Support for more DC models and more features is my further targets. As the display controller is delivered to SoC vendors as a whole part, this driver does not use component framework and extra bridges inside a SoC is expected to be implemented as dedicated bridges (this driver properly supports bridge chaining). Signed-off-by: Icenowy Zheng --- Changes in v2: - Changed some Control flows according to previous reviews. - Added missing of_node_put when checking of endpoints for output type. - Switched all userspace-visible modeset objects to be managed by drmm instead of devm. - Utilize devm_drm_bridge_alloc() in internal bridge. - Prevented the usage of simple encoder helpers by passing a NULL funcs poi= nter. - Let devm enable clocks when getting them. - Removed explicit `.cache_type =3D REGCACHE_NONE` in regmap config. - Fixed a debug print using a variable before initialization. - Fixed a wrong index when using bulk to handle resets. - Added missing configuration for DPI format (currently fixed RGB888). drivers/gpu/drm/Kconfig | 2 + drivers/gpu/drm/Makefile | 1 + drivers/gpu/drm/verisilicon/Kconfig | 15 + drivers/gpu/drm/verisilicon/Makefile | 5 + drivers/gpu/drm/verisilicon/vs_bridge.c | 330 ++++++++++++++++++ drivers/gpu/drm/verisilicon/vs_bridge.h | 40 +++ drivers/gpu/drm/verisilicon/vs_bridge_regs.h | 54 +++ drivers/gpu/drm/verisilicon/vs_crtc.c | 217 ++++++++++++ drivers/gpu/drm/verisilicon/vs_crtc.h | 29 ++ drivers/gpu/drm/verisilicon/vs_crtc_regs.h | 60 ++++ drivers/gpu/drm/verisilicon/vs_dc.c | 205 +++++++++++ drivers/gpu/drm/verisilicon/vs_dc.h | 39 +++ drivers/gpu/drm/verisilicon/vs_dc_top_regs.h | 27 ++ drivers/gpu/drm/verisilicon/vs_drm.c | 177 ++++++++++ drivers/gpu/drm/verisilicon/vs_drm.h | 29 ++ drivers/gpu/drm/verisilicon/vs_hwdb.c | 150 ++++++++ drivers/gpu/drm/verisilicon/vs_hwdb.h | 29 ++ drivers/gpu/drm/verisilicon/vs_plane.c | 102 ++++++ drivers/gpu/drm/verisilicon/vs_plane.h | 68 ++++ .../gpu/drm/verisilicon/vs_primary_plane.c | 157 +++++++++ .../drm/verisilicon/vs_primary_plane_regs.h | 53 +++ 21 files changed, 1789 insertions(+) create mode 100644 drivers/gpu/drm/verisilicon/Kconfig create mode 100644 drivers/gpu/drm/verisilicon/Makefile create mode 100644 drivers/gpu/drm/verisilicon/vs_bridge.c create mode 100644 drivers/gpu/drm/verisilicon/vs_bridge.h create mode 100644 drivers/gpu/drm/verisilicon/vs_bridge_regs.h create mode 100644 drivers/gpu/drm/verisilicon/vs_crtc.c create mode 100644 drivers/gpu/drm/verisilicon/vs_crtc.h create mode 100644 drivers/gpu/drm/verisilicon/vs_crtc_regs.h create mode 100644 drivers/gpu/drm/verisilicon/vs_dc.c create mode 100644 drivers/gpu/drm/verisilicon/vs_dc.h create mode 100644 drivers/gpu/drm/verisilicon/vs_dc_top_regs.h create mode 100644 drivers/gpu/drm/verisilicon/vs_drm.c create mode 100644 drivers/gpu/drm/verisilicon/vs_drm.h create mode 100644 drivers/gpu/drm/verisilicon/vs_hwdb.c create mode 100644 drivers/gpu/drm/verisilicon/vs_hwdb.h create mode 100644 drivers/gpu/drm/verisilicon/vs_plane.c create mode 100644 drivers/gpu/drm/verisilicon/vs_plane.h create mode 100644 drivers/gpu/drm/verisilicon/vs_primary_plane.c create mode 100644 drivers/gpu/drm/verisilicon/vs_primary_plane_regs.h diff --git a/drivers/gpu/drm/Kconfig b/drivers/gpu/drm/Kconfig index f7ea8e895c0c0..33601485ecdba 100644 --- a/drivers/gpu/drm/Kconfig +++ b/drivers/gpu/drm/Kconfig @@ -396,6 +396,8 @@ source "drivers/gpu/drm/sprd/Kconfig" =20 source "drivers/gpu/drm/imagination/Kconfig" =20 +source "drivers/gpu/drm/verisilicon/Kconfig" + config DRM_HYPERV tristate "DRM Support for Hyper-V synthetic video device" depends on DRM && PCI && HYPERV diff --git a/drivers/gpu/drm/Makefile b/drivers/gpu/drm/Makefile index 4dafbdc8f86ac..32ed4cf9df1bd 100644 --- a/drivers/gpu/drm/Makefile +++ b/drivers/gpu/drm/Makefile @@ -231,6 +231,7 @@ obj-y +=3D solomon/ obj-$(CONFIG_DRM_SPRD) +=3D sprd/ obj-$(CONFIG_DRM_LOONGSON) +=3D loongson/ obj-$(CONFIG_DRM_POWERVR) +=3D imagination/ +obj-$(CONFIG_DRM_VERISILICON_DC) +=3D verisilicon/ =20 # Ensure drm headers are self-contained and pass kernel-doc hdrtest-files :=3D \ diff --git a/drivers/gpu/drm/verisilicon/Kconfig b/drivers/gpu/drm/verisili= con/Kconfig new file mode 100644 index 0000000000000..0235577c72824 --- /dev/null +++ b/drivers/gpu/drm/verisilicon/Kconfig @@ -0,0 +1,15 @@ +# SPDX-License-Identifier: GPL-2.0-only +config DRM_VERISILICON_DC + tristate "DRM Support for Verisilicon DC-series display controllers" + depends on DRM && COMMON_CLK + depends on RISCV || COMPILER_TEST + select DRM_CLIENT_SELECTION + select DRM_GEM_DMA_HELPER + select DRM_KMS_HELPER + select DRM_BRIDGE_CONNECTOR + select REGMAP_MMIO + select VIDEOMODE_HELPERS + help + Choose this option if you have a SoC with Verisilicon DC-series + display controllers. If M is selected, the module will be called + verisilicon-dc. diff --git a/drivers/gpu/drm/verisilicon/Makefile b/drivers/gpu/drm/verisil= icon/Makefile new file mode 100644 index 0000000000000..fd8d805fbcde1 --- /dev/null +++ b/drivers/gpu/drm/verisilicon/Makefile @@ -0,0 +1,5 @@ +# SPDX-License-Identifier: GPL-2.0-only + +verisilicon-dc-objs :=3D vs_bridge.o vs_crtc.o vs_dc.o vs_drm.o vs_hwdb.o = vs_plane.o vs_primary_plane.o + +obj-$(CONFIG_DRM_VERISILICON_DC) +=3D verisilicon-dc.o diff --git a/drivers/gpu/drm/verisilicon/vs_bridge.c b/drivers/gpu/drm/veri= silicon/vs_bridge.c new file mode 100644 index 0000000000000..9696e574bcc7c --- /dev/null +++ b/drivers/gpu/drm/verisilicon/vs_bridge.c @@ -0,0 +1,330 @@ +// SPDX-License-Identifier: GPL-2.0-only +/* + * Copyright (C) 2025 Icenowy Zheng + */ + +#include +#include + +#include + +#include +#include +#include +#include +#include +#include +#include +#include +#include + +#include "vs_bridge.h" +#include "vs_bridge_regs.h" +#include "vs_crtc.h" +#include "vs_dc.h" + +static int vs_bridge_attach(struct drm_bridge *bridge, + struct drm_encoder *encoder, + enum drm_bridge_attach_flags flags) +{ + struct vs_bridge *vbridge =3D drm_bridge_to_vs_bridge(bridge); + + return drm_bridge_attach(encoder, vbridge->next, + bridge, flags); +} + +struct vsdc_dp_format { + u32 linux_fmt; + bool is_yuv; + u32 vsdc_fmt; +}; + +static struct vsdc_dp_format vsdc_dp_supported_fmts[] =3D { + /* default to RGB888 */ + { MEDIA_BUS_FMT_FIXED, false, VSDC_DISP_DP_CONFIG_FMT_RGB888 }, + { MEDIA_BUS_FMT_RGB888_1X24, false, VSDC_DISP_DP_CONFIG_FMT_RGB888 }, + { MEDIA_BUS_FMT_RGB565_1X16, false, VSDC_DISP_DP_CONFIG_FMT_RGB565 }, + { MEDIA_BUS_FMT_RGB666_1X18, false, VSDC_DISP_DP_CONFIG_FMT_RGB666 }, + { MEDIA_BUS_FMT_RGB101010_1X30, + false, VSDC_DISP_DP_CONFIG_FMT_RGB101010 }, + { MEDIA_BUS_FMT_UYVY8_1X16, true, VSDC_DISP_DP_CONFIG_YUV_FMT_UYVY8 }, + { MEDIA_BUS_FMT_UYVY10_1X20, true, VSDC_DISP_DP_CONFIG_YUV_FMT_UYVY10 }, + { MEDIA_BUS_FMT_YUV8_1X24, true, VSDC_DISP_DP_CONFIG_YUV_FMT_YUV8 }, + { MEDIA_BUS_FMT_YUV10_1X30, true, VSDC_DISP_DP_CONFIG_YUV_FMT_YUV10 }, + { MEDIA_BUS_FMT_UYYVYY8_0_5X24, + true, VSDC_DISP_DP_CONFIG_YUV_FMT_UYYVYY8 }, + { MEDIA_BUS_FMT_UYYVYY10_0_5X30, + true, VSDC_DISP_DP_CONFIG_YUV_FMT_UYYVYY10 }, +}; + +static u32 *vs_bridge_atomic_get_output_bus_fmts(struct drm_bridge *bridge, + struct drm_bridge_state *bridge_state, + struct drm_crtc_state *crtc_state, + struct drm_connector_state *conn_state, + unsigned int *num_output_fmts) +{ + struct vs_bridge *vbridge =3D drm_bridge_to_vs_bridge(bridge); + u32 *output_fmts; + unsigned int i; + + if (vbridge->intf =3D=3D VSDC_OUTPUT_INTERFACE_DPI) + *num_output_fmts =3D 2; + else + *num_output_fmts =3D ARRAY_SIZE(vsdc_dp_supported_fmts); + + output_fmts =3D kcalloc(*num_output_fmts, sizeof(*output_fmts), + GFP_KERNEL); + if (!output_fmts) + return NULL; + + if (vbridge->intf =3D=3D VSDC_OUTPUT_INTERFACE_DPI) { + /* TODO: support more DPI output formats */ + output_fmts[0] =3D MEDIA_BUS_FMT_RGB888_1X24; + output_fmts[1] =3D MEDIA_BUS_FMT_FIXED; + } else { + for (i =3D 0; i < *num_output_fmts; i++) + output_fmts[i] =3D vsdc_dp_supported_fmts[i].linux_fmt; + } + + return output_fmts; +} + +static bool vs_bridge_out_dp_fmt_supported(u32 out_fmt) +{ + unsigned int i; + + for (i =3D 0; i < ARRAY_SIZE(vsdc_dp_supported_fmts); i++) + if (vsdc_dp_supported_fmts[i].linux_fmt =3D=3D out_fmt) + return true; + + return false; +} + +static u32 *vs_bridge_atomic_get_input_bus_fmts(struct drm_bridge *bridge, + struct drm_bridge_state *bridge_state, + struct drm_crtc_state *crtc_state, + struct drm_connector_state *conn_state, + u32 output_fmt, + unsigned int *num_input_fmts) +{ + struct vs_bridge *vbridge =3D drm_bridge_to_vs_bridge(bridge); + + if (vbridge->intf =3D=3D VSDC_OUTPUT_INTERFACE_DP && + !vs_bridge_out_dp_fmt_supported(output_fmt)) { + *num_input_fmts =3D 0; + return NULL; + } + + return drm_atomic_helper_bridge_propagate_bus_fmt(bridge, bridge_state, + crtc_state, + conn_state, + output_fmt, + num_input_fmts); +} + +static int vs_bridge_atomic_check(struct drm_bridge *bridge, + struct drm_bridge_state *bridge_state, + struct drm_crtc_state *crtc_state, + struct drm_connector_state *conn_state) +{ + struct vs_bridge *vbridge =3D drm_bridge_to_vs_bridge(bridge); + + if (vbridge->intf =3D=3D VSDC_OUTPUT_INTERFACE_DP && + !vs_bridge_out_dp_fmt_supported(bridge_state->output_bus_cfg.format)) + return -EINVAL; + + vbridge->output_bus_fmt =3D bridge_state->output_bus_cfg.format; + + return 0; +} + +static void vs_bridge_atomic_enable(struct drm_bridge *bridge, + struct drm_atomic_state *state) +{ + struct vs_bridge *vbridge =3D drm_bridge_to_vs_bridge(bridge); + struct drm_bridge_state *br_state =3D drm_atomic_get_bridge_state(state, + bridge); + struct vs_crtc *crtc =3D vbridge->crtc; + struct vs_dc *dc =3D crtc->dc; + unsigned int output =3D crtc->id; + u32 dp_fmt; + unsigned int i; + + DRM_DEBUG_DRIVER("Enabling output %u\n", output); + + switch (vbridge->intf) { + case VSDC_OUTPUT_INTERFACE_DPI: + regmap_clear_bits(dc->regs, VSDC_DISP_DP_CONFIG(output), + VSDC_DISP_DP_CONFIG_DP_EN); + regmap_write(dc->regs, VSDC_DISP_DPI_CONFIG(output), + VSDC_DISP_DPI_CONFIG_FMT_RGB888); + break; + case VSDC_OUTPUT_INTERFACE_DP: + for (i =3D 0; i < ARRAY_SIZE(vsdc_dp_supported_fmts); i++) { + if (vsdc_dp_supported_fmts[i].linux_fmt =3D=3D + vbridge->output_bus_fmt) + break; + } + if (WARN_ON_ONCE(i =3D=3D ARRAY_SIZE(vsdc_dp_supported_fmts))) + return; + dp_fmt =3D vsdc_dp_supported_fmts[i].vsdc_fmt; + dp_fmt |=3D VSDC_DISP_DP_CONFIG_DP_EN; + regmap_write(dc->regs, VSDC_DISP_DP_CONFIG(output), dp_fmt); + regmap_assign_bits(dc->regs, + VSDC_DISP_PANEL_CONFIG(output), + VSDC_DISP_PANEL_CONFIG_YUV, + vsdc_dp_supported_fmts[i].is_yuv); + break; + } + + regmap_clear_bits(dc->regs, VSDC_DISP_PANEL_CONFIG(output), + VSDC_DISP_PANEL_CONFIG_DAT_POL); + regmap_assign_bits(dc->regs, VSDC_DISP_PANEL_CONFIG(output), + VSDC_DISP_PANEL_CONFIG_DE_POL, + br_state->output_bus_cfg.flags & + DRM_BUS_FLAG_DE_LOW); + regmap_assign_bits(dc->regs, VSDC_DISP_PANEL_CONFIG(output), + VSDC_DISP_PANEL_CONFIG_CLK_POL, + br_state->output_bus_cfg.flags & + DRM_BUS_FLAG_PIXDATA_DRIVE_NEGEDGE); + regmap_set_bits(dc->regs, VSDC_DISP_PANEL_CONFIG(output), + VSDC_DISP_PANEL_CONFIG_DE_EN | + VSDC_DISP_PANEL_CONFIG_DAT_EN | + VSDC_DISP_PANEL_CONFIG_CLK_EN); + regmap_set_bits(dc->regs, VSDC_DISP_PANEL_CONFIG(output), + VSDC_DISP_PANEL_CONFIG_RUNNING); + regmap_clear_bits(dc->regs, VSDC_DISP_PANEL_START, + VSDC_DISP_PANEL_START_MULTI_DISP_SYNC); + regmap_set_bits(dc->regs, VSDC_DISP_PANEL_START, + VSDC_DISP_PANEL_START_RUNNING(output)); + + regmap_set_bits(dc->regs, VSDC_DISP_PANEL_CONFIG_EX(crtc->id), + VSDC_DISP_PANEL_CONFIG_EX_COMMIT); +} + +static void vs_bridge_atomic_disable(struct drm_bridge *bridge, + struct drm_atomic_state *state) +{ + struct vs_bridge *vbridge =3D drm_bridge_to_vs_bridge(bridge); + struct vs_crtc *crtc =3D vbridge->crtc; + struct vs_dc *dc =3D crtc->dc; + unsigned int output =3D crtc->id; + + DRM_DEBUG_DRIVER("Disabling output %u\n", output); + + regmap_clear_bits(dc->regs, VSDC_DISP_PANEL_START, + VSDC_DISP_PANEL_START_MULTI_DISP_SYNC | + VSDC_DISP_PANEL_START_RUNNING(output)); + regmap_clear_bits(dc->regs, VSDC_DISP_PANEL_CONFIG(output), + VSDC_DISP_PANEL_CONFIG_RUNNING); + + regmap_set_bits(dc->regs, VSDC_DISP_PANEL_CONFIG_EX(crtc->id), + VSDC_DISP_PANEL_CONFIG_EX_COMMIT); +} + +static const struct drm_bridge_funcs vs_bridge_funcs =3D { + .attach =3D vs_bridge_attach, + .atomic_enable =3D vs_bridge_atomic_enable, + .atomic_disable =3D vs_bridge_atomic_disable, + .atomic_check =3D vs_bridge_atomic_check, + .atomic_get_input_bus_fmts =3D vs_bridge_atomic_get_input_bus_fmts, + .atomic_get_output_bus_fmts =3D vs_bridge_atomic_get_output_bus_fmts, + .atomic_duplicate_state =3D drm_atomic_helper_bridge_duplicate_state, + .atomic_destroy_state =3D drm_atomic_helper_bridge_destroy_state, + .atomic_reset =3D drm_atomic_helper_bridge_reset, +}; + +static int vs_bridge_detect_output_interface(struct device_node *of_node, + unsigned int output) +{ + int ret; + struct device_node *remote; + + remote =3D of_graph_get_remote_node(of_node, output, + VSDC_OUTPUT_INTERFACE_DPI); + if (remote) { + ret =3D VSDC_OUTPUT_INTERFACE_DPI; + } else { + remote =3D of_graph_get_remote_node(of_node, output, + VSDC_OUTPUT_INTERFACE_DP); + if (remote) + ret =3D VSDC_OUTPUT_INTERFACE_DP; + else + ret =3D -ENODEV; + } + + if (remote) + of_node_put(remote); + + return ret; +} + +struct vs_bridge *vs_bridge_init(struct drm_device *drm_dev, + struct vs_crtc *crtc) +{ + unsigned int output =3D crtc->id; + struct vs_bridge *bridge; + struct drm_bridge *next; + enum vs_bridge_output_interface intf; + int ret, enctype; + + intf =3D vs_bridge_detect_output_interface(drm_dev->dev->of_node, + output); + if (intf =3D=3D -ENODEV) { + dev_info(drm_dev->dev, "Skipping output %u\n", output); + return NULL; + } + + next =3D devm_drm_of_get_bridge(drm_dev->dev, drm_dev->dev->of_node, + output, intf); + if (IS_ERR(next)) { + ret =3D PTR_ERR(next); + dev_err_probe(drm_dev->dev, ret, + "Cannot get downstream bridge of output %u\n", + output); + return ERR_PTR(ret); + } + + bridge =3D devm_drm_bridge_alloc(drm_dev->dev, struct vs_bridge, base, + &vs_bridge_funcs); + if (!bridge) + return ERR_PTR(-ENOMEM); + + bridge->crtc =3D crtc; + bridge->intf =3D intf; + bridge->next =3D next; + + if (intf =3D=3D VSDC_OUTPUT_INTERFACE_DPI) + enctype =3D DRM_MODE_ENCODER_DPI; + else + enctype =3D DRM_MODE_ENCODER_NONE; + + bridge->enc =3D drmm_plain_encoder_alloc(drm_dev, NULL, enctype, NULL); + if (IS_ERR(bridge->enc)) { + dev_err(drm_dev->dev, + "Cannot initialize encoder for output %u\n", output); + ret =3D PTR_ERR(bridge->enc); + return ERR_PTR(ret); + } + + bridge->enc->possible_crtcs =3D drm_crtc_mask(&crtc->base); + + ret =3D drm_bridge_attach(bridge->enc, &bridge->base, NULL, + DRM_BRIDGE_ATTACH_NO_CONNECTOR); + if (ret) { + dev_err(drm_dev->dev, + "Cannot attach bridge for output %u\n", output); + return ERR_PTR(ret); + } + + bridge->conn =3D drm_bridge_connector_init(drm_dev, bridge->enc); + if (IS_ERR(bridge->conn)) { + dev_err(drm_dev->dev, + "Cannot create connector for output %u\n", output); + ret =3D PTR_ERR(bridge->conn); + return ERR_PTR(ret); + } + drm_connector_attach_encoder(bridge->conn, bridge->enc); + + return bridge; +} diff --git a/drivers/gpu/drm/verisilicon/vs_bridge.h b/drivers/gpu/drm/veri= silicon/vs_bridge.h new file mode 100644 index 0000000000000..4120abafdaed6 --- /dev/null +++ b/drivers/gpu/drm/verisilicon/vs_bridge.h @@ -0,0 +1,40 @@ +/* SPDX-License-Identifier: GPL-2.0-only */ +/* + * Copyright (C) 2025 Icenowy Zheng + */ + +#ifndef _VS_BRIDGE_H_ +#define _VS_BRIDGE_H_ + +#include + +#include +#include +#include + +struct vs_crtc; + +enum vs_bridge_output_interface { + VSDC_OUTPUT_INTERFACE_DPI =3D 0, + VSDC_OUTPUT_INTERFACE_DP =3D 1 +}; + +struct vs_bridge { + struct drm_bridge base; + struct drm_encoder *enc; + struct drm_connector *conn; + + struct vs_crtc *crtc; + struct drm_bridge *next; + enum vs_bridge_output_interface intf; + u32 output_bus_fmt; +}; + +static inline struct vs_bridge *drm_bridge_to_vs_bridge(struct drm_bridge = *bridge) +{ + return container_of(bridge, struct vs_bridge, base); +} + +struct vs_bridge *vs_bridge_init(struct drm_device *drm_dev, + struct vs_crtc *crtc); +#endif /* _VS_BRIDGE_H_ */ diff --git a/drivers/gpu/drm/verisilicon/vs_bridge_regs.h b/drivers/gpu/drm= /verisilicon/vs_bridge_regs.h new file mode 100644 index 0000000000000..9eb30e4564beb --- /dev/null +++ b/drivers/gpu/drm/verisilicon/vs_bridge_regs.h @@ -0,0 +1,54 @@ +/* SPDX-License-Identifier: GPL-2.0-only */ +/* + * Copyright (C) 2025 Icenowy Zheng + * + * Based on vs_dc_hw.h, which is: + * Copyright (C) 2023 VeriSilicon Holdings Co., Ltd. + */ + +#ifndef _VS_BRIDGE_REGS_H_ +#define _VS_BRIDGE_REGS_H_ + +#include + +#define VSDC_DISP_PANEL_CONFIG(n) (0x1418 + 0x4 * (n)) +#define VSDC_DISP_PANEL_CONFIG_DE_EN BIT(0) +#define VSDC_DISP_PANEL_CONFIG_DE_POL BIT(1) +#define VSDC_DISP_PANEL_CONFIG_DAT_EN BIT(4) +#define VSDC_DISP_PANEL_CONFIG_DAT_POL BIT(5) +#define VSDC_DISP_PANEL_CONFIG_CLK_EN BIT(8) +#define VSDC_DISP_PANEL_CONFIG_CLK_POL BIT(9) +#define VSDC_DISP_PANEL_CONFIG_RUNNING BIT(12) +#define VSDC_DISP_PANEL_CONFIG_GAMMA BIT(13) +#define VSDC_DISP_PANEL_CONFIG_YUV BIT(16) + +#define VSDC_DISP_DPI_CONFIG(n) (0x14B8 + 0x4 * (n)) +#define VSDC_DISP_DPI_CONFIG_FMT_MASK GENMASK(2, 0) +#define VSDC_DISP_DPI_CONFIG_FMT_RGB565 (0) +#define VSDC_DISP_DPI_CONFIG_FMT_RGB666 (3) +#define VSDC_DISP_DPI_CONFIG_FMT_RGB888 (5) +#define VSDC_DISP_DPI_CONFIG_FMT_RGB101010 (6) + +#define VSDC_DISP_PANEL_START 0x1CCC +#define VSDC_DISP_PANEL_START_RUNNING(n) BIT(n) +#define VSDC_DISP_PANEL_START_MULTI_DISP_SYNC BIT(3) + +#define VSDC_DISP_DP_CONFIG(n) (0x1CD0 + 0x4 * (n)) +#define VSDC_DISP_DP_CONFIG_DP_EN BIT(3) +#define VSDC_DISP_DP_CONFIG_FMT_MASK GENMASK(2, 0) +#define VSDC_DISP_DP_CONFIG_FMT_RGB565 (0) +#define VSDC_DISP_DP_CONFIG_FMT_RGB666 (1) +#define VSDC_DISP_DP_CONFIG_FMT_RGB888 (2) +#define VSDC_DISP_DP_CONFIG_FMT_RGB101010 (3) +#define VSDC_DISP_DP_CONFIG_YUV_FMT_MASK GENMASK(7, 4) +#define VSDC_DISP_DP_CONFIG_YUV_FMT_UYVY8 (2 << 4) +#define VSDC_DISP_DP_CONFIG_YUV_FMT_YUV8 (4 << 4) +#define VSDC_DISP_DP_CONFIG_YUV_FMT_UYVY10 (8 << 4) +#define VSDC_DISP_DP_CONFIG_YUV_FMT_YUV10 (10 << 4) +#define VSDC_DISP_DP_CONFIG_YUV_FMT_UYYVYY8 (12 << 4) +#define VSDC_DISP_DP_CONFIG_YUV_FMT_UYYVYY10 (13 << 4) + +#define VSDC_DISP_PANEL_CONFIG_EX(n) (0x2518 + 0x4 * (n)) +#define VSDC_DISP_PANEL_CONFIG_EX_COMMIT BIT(0) + +#endif /* _VS_BRIDGE_REGS_H_ */ diff --git a/drivers/gpu/drm/verisilicon/vs_crtc.c b/drivers/gpu/drm/verisi= licon/vs_crtc.c new file mode 100644 index 0000000000000..8825b77ed3ca0 --- /dev/null +++ b/drivers/gpu/drm/verisilicon/vs_crtc.c @@ -0,0 +1,217 @@ +// SPDX-License-Identifier: GPL-2.0-only +/* + * Copyright (C) 2025 Icenowy Zheng + */ + +#include +#include + +#include +#include +#include +#include + +#include "vs_crtc_regs.h" +#include "vs_crtc.h" +#include "vs_dc.h" +#include "vs_dc_top_regs.h" +#include "vs_plane.h" + +static void vs_crtc_atomic_flush(struct drm_crtc *crtc, + struct drm_atomic_state *state) +{ + struct vs_crtc *vcrtc =3D drm_crtc_to_vs_crtc(crtc); + struct drm_crtc_state *crtc_state =3D drm_atomic_get_new_crtc_state(state, + crtc); + struct drm_pending_vblank_event *event =3D crtc_state->event; + + DRM_DEBUG_DRIVER("Flushing CRTC %u vblank events\n", vcrtc->id); + + if (event) { + crtc_state->event =3D NULL; + + spin_lock_irq(&crtc->dev->event_lock); + if (drm_crtc_vblank_get(crtc) =3D=3D 0) + drm_crtc_arm_vblank_event(crtc, event); + else + drm_crtc_send_vblank_event(crtc, event); + spin_unlock_irq(&crtc->dev->event_lock); + } +} + +static void vs_crtc_atomic_disable(struct drm_crtc *crtc, + struct drm_atomic_state *state) +{ + struct vs_crtc *vcrtc =3D drm_crtc_to_vs_crtc(crtc); + struct vs_dc *dc =3D vcrtc->dc; + unsigned int output =3D vcrtc->id; + + DRM_DEBUG_DRIVER("Disabling CRTC %u\n", output); + + drm_crtc_vblank_off(crtc); + + clk_disable_unprepare(dc->pix_clk[output]); +} + +static void vs_crtc_atomic_enable(struct drm_crtc *crtc, + struct drm_atomic_state *state) +{ + struct vs_crtc *vcrtc =3D drm_crtc_to_vs_crtc(crtc); + struct vs_dc *dc =3D vcrtc->dc; + unsigned int output =3D vcrtc->id; + + DRM_DEBUG_DRIVER("Enabling CRTC %u\n", output); + + WARN_ON(clk_prepare_enable(dc->pix_clk[output])); + + drm_crtc_vblank_on(crtc); +} + +static void vs_crtc_mode_set_nofb(struct drm_crtc *crtc) +{ + struct drm_display_mode *mode =3D &crtc->state->adjusted_mode; + struct vs_crtc *vcrtc =3D drm_crtc_to_vs_crtc(crtc); + struct vs_dc *dc =3D vcrtc->dc; + unsigned int output =3D vcrtc->id; + + DRM_DEBUG_DRIVER("Setting mode on CRTC %u\n", output); + + regmap_write(dc->regs, VSDC_DISP_HSIZE(output), + VSDC_DISP_HSIZE_DISP(mode->hdisplay) | + VSDC_DISP_HSIZE_TOTAL(mode->htotal)); + regmap_write(dc->regs, VSDC_DISP_VSIZE(output), + VSDC_DISP_VSIZE_DISP(mode->vdisplay) | + VSDC_DISP_VSIZE_TOTAL(mode->vtotal)); + regmap_write(dc->regs, VSDC_DISP_HSYNC(output), + VSDC_DISP_HSYNC_START(mode->hsync_start) | + VSDC_DISP_HSYNC_END(mode->hsync_end) | + VSDC_DISP_HSYNC_EN); + if (!(mode->flags & DRM_MODE_FLAG_PHSYNC)) + regmap_set_bits(dc->regs, VSDC_DISP_HSYNC(output), + VSDC_DISP_HSYNC_POL); + regmap_write(dc->regs, VSDC_DISP_VSYNC(output), + VSDC_DISP_VSYNC_START(mode->vsync_start) | + VSDC_DISP_VSYNC_END(mode->vsync_end) | + VSDC_DISP_VSYNC_EN); + if (!(mode->flags & DRM_MODE_FLAG_PVSYNC)) + regmap_set_bits(dc->regs, VSDC_DISP_VSYNC(output), + VSDC_DISP_VSYNC_POL); + + WARN_ON(clk_set_rate(dc->pix_clk[output], mode->crtc_clock * 1000)); +} + +static enum drm_mode_status +vs_crtc_mode_valid(struct drm_crtc *crtc, const struct drm_display_mode *m= ode) +{ + struct vs_crtc *vcrtc =3D drm_crtc_to_vs_crtc(crtc); + struct vs_dc *dc =3D vcrtc->dc; + unsigned int output =3D vcrtc->id; + long rate; + + if (mode->htotal > 0x7FFF) + return MODE_BAD_HVALUE; + if (mode->vtotal > 0x7FFF) + return MODE_BAD_VVALUE; + + rate =3D clk_round_rate(dc->pix_clk[output], mode->clock * 1000); + if (rate <=3D 0) + return MODE_CLOCK_RANGE; + + return MODE_OK; +} + +static bool vs_crtc_mode_fixup(struct drm_crtc *crtc, + const struct drm_display_mode *m, + struct drm_display_mode *adjusted_mode) +{ + struct vs_crtc *vcrtc =3D drm_crtc_to_vs_crtc(crtc); + struct vs_dc *dc =3D vcrtc->dc; + unsigned int output =3D vcrtc->id; + long clk_rate; + + drm_mode_set_crtcinfo(adjusted_mode, 0); + + /* Feedback the pixel clock to crtc_clock */ + clk_rate =3D adjusted_mode->crtc_clock * 1000; + clk_rate =3D clk_round_rate(dc->pix_clk[output], clk_rate); + if (clk_rate <=3D 0) + return false; + + adjusted_mode->crtc_clock =3D clk_rate / 1000; + + return true; +} + +static const struct drm_crtc_helper_funcs vs_crtc_helper_funcs =3D { + .atomic_flush =3D vs_crtc_atomic_flush, + .atomic_enable =3D vs_crtc_atomic_enable, + .atomic_disable =3D vs_crtc_atomic_disable, + .mode_set_nofb =3D vs_crtc_mode_set_nofb, + .mode_valid =3D vs_crtc_mode_valid, + .mode_fixup =3D vs_crtc_mode_fixup, +}; + +static int vs_crtc_enable_vblank(struct drm_crtc *crtc) +{ + struct vs_crtc *vcrtc =3D drm_crtc_to_vs_crtc(crtc); + struct vs_dc *dc =3D vcrtc->dc; + + DRM_DEBUG_DRIVER("Enabling VBLANK on CRTC %u\n", vcrtc->id); + regmap_set_bits(dc->regs, VSDC_TOP_IRQ_EN, VSDC_TOP_IRQ_VSYNC(vcrtc->id)); + + return 0; +} + +static void vs_crtc_disable_vblank(struct drm_crtc *crtc) +{ + struct vs_crtc *vcrtc =3D drm_crtc_to_vs_crtc(crtc); + struct vs_dc *dc =3D vcrtc->dc; + + DRM_DEBUG_DRIVER("Disabling VBLANK on CRTC %u\n", vcrtc->id); + regmap_clear_bits(dc->regs, VSDC_TOP_IRQ_EN, VSDC_TOP_IRQ_VSYNC(vcrtc->id= )); +} + +static const struct drm_crtc_funcs vs_crtc_funcs =3D { + .atomic_destroy_state =3D drm_atomic_helper_crtc_destroy_state, + .atomic_duplicate_state =3D drm_atomic_helper_crtc_duplicate_state, + .page_flip =3D drm_atomic_helper_page_flip, + .reset =3D drm_atomic_helper_crtc_reset, + .set_config =3D drm_atomic_helper_set_config, + .enable_vblank =3D vs_crtc_enable_vblank, + .disable_vblank =3D vs_crtc_disable_vblank, +}; + +struct vs_crtc *vs_crtc_init(struct drm_device *drm_dev, struct vs_dc *dc, + unsigned int output) +{ + struct vs_crtc *vcrtc; + struct drm_plane *primary; + int ret; + + vcrtc =3D drmm_kzalloc(drm_dev, sizeof(*vcrtc), GFP_KERNEL); + if (!vcrtc) + return ERR_PTR(-ENOMEM); + vcrtc->dc =3D dc; + vcrtc->id =3D output; + + /* Create our primary plane */ + primary =3D vs_primary_plane_init(drm_dev, dc); + if (IS_ERR(primary)) { + dev_err(drm_dev->dev, "Couldn't create the primary plane\n"); + return ERR_PTR(PTR_ERR(primary)); + } + + ret =3D drmm_crtc_init_with_planes(drm_dev, &vcrtc->base, + primary, + NULL, + &vs_crtc_funcs, + NULL); + if (ret) { + dev_err(drm_dev->dev, "Couldn't initialize CRTC\n"); + return ERR_PTR(ret); + } + + drm_crtc_helper_add(&vcrtc->base, &vs_crtc_helper_funcs); + + return vcrtc; +} diff --git a/drivers/gpu/drm/verisilicon/vs_crtc.h b/drivers/gpu/drm/verisi= licon/vs_crtc.h new file mode 100644 index 0000000000000..6f862d609b984 --- /dev/null +++ b/drivers/gpu/drm/verisilicon/vs_crtc.h @@ -0,0 +1,29 @@ +/* SPDX-License-Identifier: GPL-2.0-only */ +/* + * Copyright (C) 2025 Icenowy Zheng + */ + +#ifndef _VS_CRTC_H_ +#define _VS_CRTC_H_ + +#include +#include + +struct vs_dc; + +struct vs_crtc { + struct drm_crtc base; + + struct vs_dc *dc; + unsigned int id; +}; + +static inline struct vs_crtc *drm_crtc_to_vs_crtc(struct drm_crtc *crtc) +{ + return container_of(crtc, struct vs_crtc, base); +} + +struct vs_crtc *vs_crtc_init(struct drm_device *drm_dev, struct vs_dc *dc, + unsigned int output); + +#endif /* _VS_CRTC_H_ */ diff --git a/drivers/gpu/drm/verisilicon/vs_crtc_regs.h b/drivers/gpu/drm/v= erisilicon/vs_crtc_regs.h new file mode 100644 index 0000000000000..c7930e817635c --- /dev/null +++ b/drivers/gpu/drm/verisilicon/vs_crtc_regs.h @@ -0,0 +1,60 @@ +/* SPDX-License-Identifier: GPL-2.0-only */ +/* + * Copyright (C) 2025 Icenowy Zheng + * + * Based on vs_dc_hw.h, which is: + * Copyright (C) 2023 VeriSilicon Holdings Co., Ltd. + */ + +#ifndef _VS_CRTC_REGS_H_ +#define _VS_CRTC_REGS_H_ + +#include + +#define VSDC_DISP_DITHER_CONFIG(n) (0x1410 + 0x4 * (n)) + +#define VSDC_DISP_DITHER_TABLE_LOW(n) (0x1420 + 0x4 * (n)) +#define VSDC_DISP_DITHER_TABLE_LOW_DEFAULT 0x7B48F3C0 + +#define VSDC_DISP_DITHER_TABLE_HIGH(n) (0x1428 + 0x4 * (n)) +#define VSDC_DISP_DITHER_TABLE_HIGH_DEFAULT 0x596AD1E2 + +#define VSDC_DISP_HSIZE(n) (0x1430 + 0x4 * (n)) +#define VSDC_DISP_HSIZE_DISP_MASK GENMASK(14, 0) +#define VSDC_DISP_HSIZE_DISP(v) ((v) << 0) +#define VSDC_DISP_HSIZE_TOTAL_MASK GENMASK(30, 16) +#define VSDC_DISP_HSIZE_TOTAL(v) ((v) << 16) + +#define VSDC_DISP_HSYNC(n) (0x1438 + 0x4 * (n)) +#define VSDC_DISP_HSYNC_START_MASK GENMASK(14, 0) +#define VSDC_DISP_HSYNC_START(v) ((v) << 0) +#define VSDC_DISP_HSYNC_END_MASK GENMASK(29, 15) +#define VSDC_DISP_HSYNC_END(v) ((v) << 15) +#define VSDC_DISP_HSYNC_EN BIT(30) +#define VSDC_DISP_HSYNC_POL BIT(31) + +#define VSDC_DISP_VSIZE(n) (0x1440 + 0x4 * (n)) +#define VSDC_DISP_VSIZE_DISP_MASK GENMASK(14, 0) +#define VSDC_DISP_VSIZE_DISP(v) ((v) << 0) +#define VSDC_DISP_VSIZE_TOTAL_MASK GENMASK(30, 16) +#define VSDC_DISP_VSIZE_TOTAL(v) ((v) << 16) + +#define VSDC_DISP_VSYNC(n) (0x1448 + 0x4 * (n)) +#define VSDC_DISP_VSYNC_START_MASK GENMASK(14, 0) +#define VSDC_DISP_VSYNC_START(v) ((v) << 0) +#define VSDC_DISP_VSYNC_END_MASK GENMASK(29, 15) +#define VSDC_DISP_VSYNC_END(v) ((v) << 15) +#define VSDC_DISP_VSYNC_EN BIT(30) +#define VSDC_DISP_VSYNC_POL BIT(31) + +#define VSDC_DISP_CURRENT_LOCATION(n) (0x1450 + 0x4 * (n)) + +#define VSDC_DISP_GAMMA_INDEX(n) (0x1458 + 0x4 * (n)) + +#define VSDC_DISP_GAMMA_DATA(n) (0x1460 + 0x4 * (n)) + +#define VSDC_DISP_IRQ_STA 0x147C + +#define VSDC_DISP_IRQ_EN 0x1480 + +#endif /* _VS_CRTC_REGS_H_ */ diff --git a/drivers/gpu/drm/verisilicon/vs_dc.c b/drivers/gpu/drm/verisili= con/vs_dc.c new file mode 100644 index 0000000000000..a413479c6cfff --- /dev/null +++ b/drivers/gpu/drm/verisilicon/vs_dc.c @@ -0,0 +1,205 @@ +// SPDX-License-Identifier: GPL-2.0-only +/* + * Copyright (C) 2025 Icenowy Zheng + */ + +#include +#include +#include + +#include "vs_crtc.h" +#include "vs_dc.h" +#include "vs_dc_top_regs.h" +#include "vs_drm.h" +#include "vs_hwdb.h" + +static const struct regmap_config vs_dc_regmap_cfg =3D { + .reg_bits =3D 32, + .val_bits =3D 32, + .reg_stride =3D sizeof(u32), + /* VSDC_OVL_CONFIG_EX(1) */ + .max_register =3D 0x2544, +}; + +static const struct of_device_id vs_dc_driver_dt_match[] =3D { + { .compatible =3D "verisilicon,dc" }, + {}, +}; +MODULE_DEVICE_TABLE(of, vs_dc_driver_dt_match); + +static irqreturn_t vs_dc_irq_handler(int irq, void *private) +{ + struct vs_dc *dc =3D private; + u32 irqs; + + regmap_read(dc->regs, VSDC_TOP_IRQ_ACK, &irqs); + + return vs_drm_handle_irq(dc, irqs); +} + +static int vs_dc_probe(struct platform_device *pdev) +{ + struct device *dev =3D &pdev->dev; + struct vs_dc *dc; + void __iomem *regs; + unsigned int outputs, i; + /* pix0/pix1 */ + char pixclk_name[5]; + int irq, ret; + + if (!dev->of_node) { + dev_err(dev, "can't find DC devices\n"); + return -ENODEV; + } + + outputs =3D of_graph_get_port_count(dev->of_node); + if (!outputs) { + dev_err(dev, "can't find DC downstream ports\n"); + return -ENODEV; + } + if (outputs > VSDC_MAX_OUTPUTS) { + dev_err(dev, "too many DC downstream ports than possible\n"); + return -EINVAL; + } + + ret =3D dma_set_mask_and_coherent(&pdev->dev, DMA_BIT_MASK(32)); + if (ret) { + dev_err(dev, "No suitable DMA available\n"); + return ret; + } + + dc =3D devm_kzalloc(dev, sizeof(*dc), GFP_KERNEL); + if (!dc) + return -ENOMEM; + + dc->outputs =3D outputs; + + dc->rsts[0].id =3D "core"; + dc->rsts[1].id =3D "axi"; + dc->rsts[2].id =3D "ahb"; + + ret =3D devm_reset_control_bulk_get_optional_shared(dev, VSDC_RESET_COUNT, + dc->rsts); + if (ret) { + dev_err(dev, "can't get reset lines\n"); + return ret; + } + + dc->core_clk =3D devm_clk_get_enabled(dev, "core"); + if (IS_ERR(dc->core_clk)) { + dev_err(dev, "can't get core clock\n"); + return PTR_ERR(dc->core_clk); + } + + dc->axi_clk =3D devm_clk_get_enabled(dev, "axi"); + if (IS_ERR(dc->axi_clk)) { + dev_err(dev, "can't get axi clock\n"); + return PTR_ERR(dc->axi_clk); + } + + dc->ahb_clk =3D devm_clk_get_enabled(dev, "ahb"); + if (IS_ERR(dc->ahb_clk)) { + dev_err(dev, "can't get ahb clock\n"); + return PTR_ERR(dc->ahb_clk); + } + + for (i =3D 0; i < outputs; i++) { + snprintf(pixclk_name, sizeof(pixclk_name), "pix%u", i); + dc->pix_clk[i] =3D devm_clk_get(dev, pixclk_name); + if (IS_ERR(dc->pix_clk[i])) { + dev_err(dev, "can't get pixel clk %u\n", i); + return PTR_ERR(dc->pix_clk[i]); + } + } + + irq =3D platform_get_irq(pdev, 0); + if (irq < 0) { + dev_err(dev, "can't get irq\n"); + return irq; + } + + ret =3D reset_control_bulk_deassert(VSDC_RESET_COUNT, dc->rsts); + if (ret) { + dev_err(dev, "can't deassert reset lines\n"); + return ret; + } + + regs =3D devm_platform_ioremap_resource(pdev, 0); + if (IS_ERR(regs)) { + dev_err(dev, "can't map registers"); + ret =3D PTR_ERR(regs); + goto err_rst_assert; + } + + dc->regs =3D devm_regmap_init_mmio(dev, regs, &vs_dc_regmap_cfg); + if (IS_ERR(dc->regs)) { + ret =3D PTR_ERR(dc->regs); + goto err_rst_assert; + } + + ret =3D vs_fill_chip_identity(dc->regs, &dc->identity); + if (ret) + goto err_rst_assert; + + dev_info(dev, "DC%x rev %x customer %x\n", dc->identity.model, + dc->identity.revision, dc->identity.customer_id); + + if (outputs > dc->identity.display_count) { + dev_err(dev, "too many downstream ports than HW capability\n"); + ret =3D -EINVAL; + goto err_rst_assert; + } + + ret =3D devm_request_irq(dev, irq, vs_dc_irq_handler, 0, + dev_name(dev), dc); + if (ret) { + dev_err(dev, "can't request irq\n"); + goto err_rst_assert; + } + + dev_set_drvdata(dev, dc); + + ret =3D vs_drm_initialize(dc, pdev); + if (ret) + goto err_rst_assert; + + return 0; + +err_rst_assert: + reset_control_bulk_assert(VSDC_RESET_COUNT, dc->rsts); + return ret; +} + +static void vs_dc_remove(struct platform_device *pdev) +{ + struct vs_dc *dc =3D dev_get_drvdata(&pdev->dev); + + vs_drm_finalize(dc); + + dev_set_drvdata(&pdev->dev, NULL); + + reset_control_bulk_assert(VSDC_RESET_COUNT, dc->rsts); +} + +static void vs_dc_shutdown(struct platform_device *pdev) +{ + struct vs_dc *dc =3D dev_get_drvdata(&pdev->dev); + + vs_drm_shutdown_handler(dc); +} + +struct platform_driver vs_dc_platform_driver =3D { + .probe =3D vs_dc_probe, + .remove =3D vs_dc_remove, + .shutdown =3D vs_dc_shutdown, + .driver =3D { + .name =3D "verisilicon-dc", + .of_match_table =3D vs_dc_driver_dt_match, + }, +}; + +module_platform_driver(vs_dc_platform_driver); + +MODULE_AUTHOR("Icenowy Zheng "); +MODULE_DESCRIPTION("Verisilicon display controller driver"); +MODULE_LICENSE("GPL"); diff --git a/drivers/gpu/drm/verisilicon/vs_dc.h b/drivers/gpu/drm/verisili= con/vs_dc.h new file mode 100644 index 0000000000000..5e071501b1c38 --- /dev/null +++ b/drivers/gpu/drm/verisilicon/vs_dc.h @@ -0,0 +1,39 @@ +/* SPDX-License-Identifier: GPL-2.0-only */ +/* + * Copyright (C) 2025 Icenowy Zheng + * + * Based on vs_dc_hw.h, which is: + * Copyright (C) 2023 VeriSilicon Holdings Co., Ltd. + */ + +#ifndef _VS_DC_H_ +#define _VS_DC_H_ + +#include +#include +#include + +#include + +#include "vs_hwdb.h" + +#define VSDC_MAX_OUTPUTS 2 +#define VSDC_RESET_COUNT 3 + +struct vs_drm_dev; +struct vs_crtc; + +struct vs_dc { + struct regmap *regs; + struct clk *core_clk; + struct clk *axi_clk; + struct clk *ahb_clk; + struct clk *pix_clk[VSDC_MAX_OUTPUTS]; + struct reset_control_bulk_data rsts[VSDC_RESET_COUNT]; + + struct vs_drm_dev *drm_dev; + struct vs_chip_identity identity; + unsigned int outputs; +}; + +#endif /* _VS_DC_H_ */ diff --git a/drivers/gpu/drm/verisilicon/vs_dc_top_regs.h b/drivers/gpu/drm= /verisilicon/vs_dc_top_regs.h new file mode 100644 index 0000000000000..50509bbbff08f --- /dev/null +++ b/drivers/gpu/drm/verisilicon/vs_dc_top_regs.h @@ -0,0 +1,27 @@ +/* SPDX-License-Identifier: GPL-2.0-only */ +/* + * Copyright (C) 2025 Icenowy Zheng + * + * Based on vs_dc_hw.h, which is: + * Copyright (C) 2023 VeriSilicon Holdings Co., Ltd. + */ + +#ifndef _VS_DC_TOP_H_ +#define _VS_DC_TOP_H_ + +#include + +#define VSDC_TOP_RST 0x0000 + +#define VSDC_TOP_IRQ_ACK 0x0010 +#define VSDC_TOP_IRQ_VSYNC(n) BIT(n) + +#define VSDC_TOP_IRQ_EN 0x0014 + +#define VSDC_TOP_CHIP_MODEL 0x0020 + +#define VSDC_TOP_CHIP_REV 0x0024 + +#define VSDC_TOP_CHIP_CUSTOMER_ID 0x0030 + +#endif /* _VS_DC_TOP_H_ */ diff --git a/drivers/gpu/drm/verisilicon/vs_drm.c b/drivers/gpu/drm/verisil= icon/vs_drm.c new file mode 100644 index 0000000000000..f356d7832c449 --- /dev/null +++ b/drivers/gpu/drm/verisilicon/vs_drm.c @@ -0,0 +1,177 @@ +// SPDX-License-Identifier: GPL-2.0-only +/* + * Copyright (C) 2025 Icenowy Zheng + */ + +#include +#include +#include +#include +#include +#include +#include + +#include +#include +#include +#include +#include +#include +#include +#include +#include + +#include "vs_bridge.h" +#include "vs_crtc.h" +#include "vs_dc.h" +#include "vs_dc_top_regs.h" +#include "vs_drm.h" + +#define DRIVER_NAME "verisilicon" +#define DRIVER_DESC "Verisilicon DC-series display controller driver" +#define DRIVER_MAJOR 1 +#define DRIVER_MINOR 0 + +static int vs_gem_dumb_create(struct drm_file *file_priv, + struct drm_device *drm, + struct drm_mode_create_dumb *args) +{ + /* The hardware wants 128B-aligned pitches for linear buffers. */ + args->pitch =3D ALIGN(DIV_ROUND_UP(args->width * args->bpp, 8), 128); + + return drm_gem_dma_dumb_create_internal(file_priv, drm, args); +} + +DEFINE_DRM_GEM_FOPS(vs_drm_driver_fops); + +static const struct drm_driver vs_drm_driver =3D { + .driver_features =3D DRIVER_MODESET | DRIVER_GEM | DRIVER_ATOMIC, + .fops =3D &vs_drm_driver_fops, + .name =3D DRIVER_NAME, + .desc =3D DRIVER_DESC, + .major =3D DRIVER_MAJOR, + .minor =3D DRIVER_MINOR, + + /* GEM Operations */ + DRM_GEM_DMA_DRIVER_OPS_WITH_DUMB_CREATE(vs_gem_dumb_create), + DRM_FBDEV_DMA_DRIVER_OPS, +}; + +static const struct drm_mode_config_funcs vs_mode_config_funcs =3D { + .fb_create =3D drm_gem_fb_create, + .atomic_check =3D drm_atomic_helper_check, + .atomic_commit =3D drm_atomic_helper_commit, +}; + +static struct drm_mode_config_helper_funcs vs_mode_config_helper_funcs =3D= { + .atomic_commit_tail =3D drm_atomic_helper_commit_tail, +}; + +static void vs_mode_config_init(struct drm_device *drm) +{ + drm_mode_config_reset(drm); + + drm->mode_config.min_width =3D 0; + drm->mode_config.min_height =3D 0; + drm->mode_config.max_width =3D 8192; + drm->mode_config.max_height =3D 8192; + drm->mode_config.funcs =3D &vs_mode_config_funcs; + drm->mode_config.helper_private =3D &vs_mode_config_helper_funcs; +} + +int vs_drm_initialize(struct vs_dc *dc, struct platform_device *pdev) +{ + struct device *dev =3D &pdev->dev; + struct vs_drm_dev *vdrm; + struct drm_device *drm; + struct vs_crtc *crtc; + struct vs_bridge *bridge; + unsigned int i; + int ret; + + vdrm =3D devm_drm_dev_alloc(dev, &vs_drm_driver, struct vs_drm_dev, base); + if (IS_ERR(vdrm)) + return PTR_ERR(vdrm); + + drm =3D &vdrm->base; + vdrm->dc =3D dc; + dc->drm_dev =3D vdrm; + + ret =3D drmm_mode_config_init(drm); + if (ret) + return ret; + + for (i =3D 0; i < dc->outputs; i++) { + crtc =3D vs_crtc_init(drm, dc, i); + if (IS_ERR(crtc)) + return PTR_ERR(crtc); + + bridge =3D vs_bridge_init(drm, crtc); + if (IS_ERR(bridge)) + return PTR_ERR(bridge); + + vdrm->crtcs[i] =3D crtc; + } + + ret =3D drm_vblank_init(drm, dc->outputs); + if (ret) + return ret; + + /* Remove early framebuffers (ie. simplefb) */ + ret =3D aperture_remove_all_conflicting_devices(DRIVER_NAME); + if (ret) + return ret; + + vs_mode_config_init(drm); + + /* Enable connectors polling */ + drm_kms_helper_poll_init(drm); + + ret =3D drm_dev_register(drm, 0); + if (ret) + goto err_fini_poll; + + drm_client_setup(drm, NULL); + + return 0; + +err_fini_poll: + drm_kms_helper_poll_fini(drm); + return ret; +} + +void vs_drm_finalize(struct vs_dc *dc) +{ + struct vs_drm_dev *vdrm =3D dc->drm_dev; + struct drm_device *drm =3D &vdrm->base; + + drm_dev_unregister(drm); + drm_kms_helper_poll_fini(drm); + drm_atomic_helper_shutdown(drm); + dc->drm_dev =3D NULL; +} + +void vs_drm_shutdown_handler(struct vs_dc *dc) +{ + struct vs_drm_dev *vdrm =3D dc->drm_dev; + + drm_atomic_helper_shutdown(&vdrm->base); +} + +irqreturn_t vs_drm_handle_irq(struct vs_dc *dc, u32 irqs) +{ + unsigned int i; + + for (i =3D 0; i < dc->outputs; i++) { + if (irqs & VSDC_TOP_IRQ_VSYNC(i)) { + irqs &=3D ~VSDC_TOP_IRQ_VSYNC(i); + if (dc->drm_dev->crtcs[i]) + drm_crtc_handle_vblank(&dc->drm_dev->crtcs[i]->base); + } + } + + if (irqs) + pr_warn("Unknown Verisilicon DC interrupt 0x%x fired!\n", irqs); + + return IRQ_HANDLED; +} diff --git a/drivers/gpu/drm/verisilicon/vs_drm.h b/drivers/gpu/drm/verisil= icon/vs_drm.h new file mode 100644 index 0000000000000..bbcd2e527deb6 --- /dev/null +++ b/drivers/gpu/drm/verisilicon/vs_drm.h @@ -0,0 +1,29 @@ +/* SPDX-License-Identifier: GPL-2.0-only */ +/* + * Copyright (C) 2025 Icenowy Zheng + */ + +#ifndef _VS_DRM_H_ +#define _VS_DRM_H_ + +#include +#include +#include + +#include + +struct vs_dc; + +struct vs_drm_dev { + struct drm_device base; + + struct vs_dc *dc; + struct vs_crtc *crtcs[VSDC_MAX_OUTPUTS]; +}; + +int vs_drm_initialize(struct vs_dc *dc, struct platform_device *pdev); +void vs_drm_finalize(struct vs_dc *dc); +void vs_drm_shutdown_handler(struct vs_dc *dc); +irqreturn_t vs_drm_handle_irq(struct vs_dc *dc, u32 irqs); + +#endif /* _VS_DRM_H_ */ diff --git a/drivers/gpu/drm/verisilicon/vs_hwdb.c b/drivers/gpu/drm/verisi= licon/vs_hwdb.c new file mode 100644 index 0000000000000..4a87e5d4701f3 --- /dev/null +++ b/drivers/gpu/drm/verisilicon/vs_hwdb.c @@ -0,0 +1,150 @@ +// SPDX-License-Identifier: GPL-2.0-only +/* + * Copyright (C) 2025 Icenowy Zheng + */ + +#include + +#include + +#include "vs_dc_top_regs.h" +#include "vs_hwdb.h" + +static const u32 vs_formats_array_no_yuv444[] =3D { + DRM_FORMAT_XRGB4444, + DRM_FORMAT_XBGR4444, + DRM_FORMAT_RGBX4444, + DRM_FORMAT_BGRX4444, + DRM_FORMAT_ARGB4444, + DRM_FORMAT_ABGR4444, + DRM_FORMAT_RGBA4444, + DRM_FORMAT_BGRA4444, + DRM_FORMAT_XRGB1555, + DRM_FORMAT_XBGR1555, + DRM_FORMAT_RGBX5551, + DRM_FORMAT_BGRX5551, + DRM_FORMAT_ARGB1555, + DRM_FORMAT_ABGR1555, + DRM_FORMAT_RGBA5551, + DRM_FORMAT_BGRA5551, + DRM_FORMAT_RGB565, + DRM_FORMAT_BGR565, + DRM_FORMAT_XRGB8888, + DRM_FORMAT_XBGR8888, + DRM_FORMAT_RGBX8888, + DRM_FORMAT_BGRX8888, + DRM_FORMAT_ARGB8888, + DRM_FORMAT_ABGR8888, + DRM_FORMAT_RGBA8888, + DRM_FORMAT_BGRA8888, + DRM_FORMAT_ARGB2101010, + DRM_FORMAT_ABGR2101010, + DRM_FORMAT_RGBA1010102, + DRM_FORMAT_BGRA1010102, + /* TODO: non-RGB formats */ +}; + +static const u32 vs_formats_array_with_yuv444[] =3D { + DRM_FORMAT_XRGB4444, + DRM_FORMAT_XBGR4444, + DRM_FORMAT_RGBX4444, + DRM_FORMAT_BGRX4444, + DRM_FORMAT_ARGB4444, + DRM_FORMAT_ABGR4444, + DRM_FORMAT_RGBA4444, + DRM_FORMAT_BGRA4444, + DRM_FORMAT_XRGB1555, + DRM_FORMAT_XBGR1555, + DRM_FORMAT_RGBX5551, + DRM_FORMAT_BGRX5551, + DRM_FORMAT_ARGB1555, + DRM_FORMAT_ABGR1555, + DRM_FORMAT_RGBA5551, + DRM_FORMAT_BGRA5551, + DRM_FORMAT_RGB565, + DRM_FORMAT_BGR565, + DRM_FORMAT_XRGB8888, + DRM_FORMAT_XBGR8888, + DRM_FORMAT_RGBX8888, + DRM_FORMAT_BGRX8888, + DRM_FORMAT_ARGB8888, + DRM_FORMAT_ABGR8888, + DRM_FORMAT_RGBA8888, + DRM_FORMAT_BGRA8888, + DRM_FORMAT_ARGB2101010, + DRM_FORMAT_ABGR2101010, + DRM_FORMAT_RGBA1010102, + DRM_FORMAT_BGRA1010102, + /* TODO: non-RGB formats */ +}; + +static const struct vs_formats vs_formats_no_yuv444 =3D { + .array =3D vs_formats_array_no_yuv444, + .num =3D ARRAY_SIZE(vs_formats_array_no_yuv444) +}; + +static const struct vs_formats vs_formats_with_yuv444 =3D { + .array =3D vs_formats_array_with_yuv444, + .num =3D ARRAY_SIZE(vs_formats_array_with_yuv444) +}; + +static struct vs_chip_identity vs_chip_identities[] =3D { + { + .model =3D 0x8200, + .revision =3D 0x5720, + .customer_id =3D ~0U, + + .display_count =3D 2, + .formats =3D &vs_formats_no_yuv444, + }, + { + .model =3D 0x8200, + .revision =3D 0x5721, + .customer_id =3D 0x30B, + + .display_count =3D 2, + .formats =3D &vs_formats_no_yuv444, + }, + { + .model =3D 0x8200, + .revision =3D 0x5720, + .customer_id =3D 0x310, + + .display_count =3D 2, + .formats =3D &vs_formats_with_yuv444, + }, + { + .model =3D 0x8200, + .revision =3D 0x5720, + .customer_id =3D 0x311, + + .display_count =3D 2, + .formats =3D &vs_formats_no_yuv444, + }, +}; + +int vs_fill_chip_identity(struct regmap *regs, + struct vs_chip_identity *ident) +{ + u32 model; + u32 revision; + u32 customer_id; + int i; + + regmap_read(regs, VSDC_TOP_CHIP_MODEL, &model); + regmap_read(regs, VSDC_TOP_CHIP_REV, &revision); + regmap_read(regs, VSDC_TOP_CHIP_CUSTOMER_ID, &customer_id); + + for (i =3D 0; i < ARRAY_SIZE(vs_chip_identities); i++) { + if (vs_chip_identities[i].model =3D=3D model && + vs_chip_identities[i].revision =3D=3D revision && + (vs_chip_identities[i].customer_id =3D=3D customer_id || + vs_chip_identities[i].customer_id =3D=3D ~0U)) { + memcpy(ident, &vs_chip_identities[i], sizeof(*ident)); + ident->customer_id =3D customer_id; + return 0; + } + } + + return -EINVAL; +} diff --git a/drivers/gpu/drm/verisilicon/vs_hwdb.h b/drivers/gpu/drm/verisi= licon/vs_hwdb.h new file mode 100644 index 0000000000000..92192e4fa0862 --- /dev/null +++ b/drivers/gpu/drm/verisilicon/vs_hwdb.h @@ -0,0 +1,29 @@ +/* SPDX-License-Identifier: GPL-2.0-only */ +/* + * Copyright (C) 2025 Icenowy Zheng + */ + +#ifndef _VS_HWDB_H_ +#define _VS_HWDB_H_ + +#include +#include + +struct vs_formats { + const u32 *array; + unsigned int num; +}; + +struct vs_chip_identity { + u32 model; + u32 revision; + u32 customer_id; + + u32 display_count; + const struct vs_formats *formats; +}; + +int vs_fill_chip_identity(struct regmap *regs, + struct vs_chip_identity *ident); + +#endif /* _VS_HWDB_H_ */ diff --git a/drivers/gpu/drm/verisilicon/vs_plane.c b/drivers/gpu/drm/veris= ilicon/vs_plane.c new file mode 100644 index 0000000000000..f3c9963b6a4ea --- /dev/null +++ b/drivers/gpu/drm/verisilicon/vs_plane.c @@ -0,0 +1,102 @@ +// SPDX-License-Identifier: GPL-2.0-only +/* + * Copyright (C) 2025 Icenowy Zheng + */ + +#include + +#include +#include + +#include "vs_plane.h" + +void drm_format_to_vs_format(u32 drm_format, struct vs_format *vs_format) +{ + switch (drm_format) { + case DRM_FORMAT_XRGB4444: + case DRM_FORMAT_RGBX4444: + case DRM_FORMAT_XBGR4444: + case DRM_FORMAT_BGRX4444: + vs_format->color =3D VSDC_COLOR_FORMAT_X4R4G4B4; + break; + case DRM_FORMAT_ARGB4444: + case DRM_FORMAT_RGBA4444: + case DRM_FORMAT_ABGR4444: + case DRM_FORMAT_BGRA4444: + vs_format->color =3D VSDC_COLOR_FORMAT_A4R4G4B4; + break; + case DRM_FORMAT_XRGB1555: + case DRM_FORMAT_RGBX5551: + case DRM_FORMAT_XBGR1555: + case DRM_FORMAT_BGRX5551: + vs_format->color =3D VSDC_COLOR_FORMAT_X1R5G5B5; + break; + case DRM_FORMAT_ARGB1555: + case DRM_FORMAT_RGBA5551: + case DRM_FORMAT_ABGR1555: + case DRM_FORMAT_BGRA5551: + vs_format->color =3D VSDC_COLOR_FORMAT_A1R5G5B5; + break; + case DRM_FORMAT_RGB565: + case DRM_FORMAT_BGR565: + vs_format->color =3D VSDC_COLOR_FORMAT_R5G6B5; + break; + case DRM_FORMAT_XRGB8888: + case DRM_FORMAT_RGBX8888: + case DRM_FORMAT_XBGR8888: + case DRM_FORMAT_BGRX8888: + vs_format->color =3D VSDC_COLOR_FORMAT_X8R8G8B8; + break; + case DRM_FORMAT_ARGB8888: + case DRM_FORMAT_RGBA8888: + case DRM_FORMAT_ABGR8888: + case DRM_FORMAT_BGRA8888: + vs_format->color =3D VSDC_COLOR_FORMAT_A8R8G8B8; + break; + case DRM_FORMAT_ARGB2101010: + case DRM_FORMAT_RGBA1010102: + case DRM_FORMAT_ABGR2101010: + case DRM_FORMAT_BGRA1010102: + vs_format->color =3D VSDC_COLOR_FORMAT_A2R10G10B10; + break; + default: + DRM_WARN("Unexpected drm format!\n"); + } + + switch (drm_format) { + case DRM_FORMAT_RGBX4444: + case DRM_FORMAT_RGBA4444: + case DRM_FORMAT_RGBX5551: + case DRM_FORMAT_RGBA5551: + case DRM_FORMAT_RGBX8888: + case DRM_FORMAT_RGBA8888: + case DRM_FORMAT_RGBA1010102: + vs_format->swizzle =3D VSDC_SWIZZLE_RGBA; + break; + case DRM_FORMAT_XBGR4444: + case DRM_FORMAT_ABGR4444: + case DRM_FORMAT_XBGR1555: + case DRM_FORMAT_ABGR1555: + case DRM_FORMAT_BGR565: + case DRM_FORMAT_XBGR8888: + case DRM_FORMAT_ABGR8888: + case DRM_FORMAT_ABGR2101010: + vs_format->swizzle =3D VSDC_SWIZZLE_ABGR; + break; + case DRM_FORMAT_BGRX4444: + case DRM_FORMAT_BGRA4444: + case DRM_FORMAT_BGRX5551: + case DRM_FORMAT_BGRA5551: + case DRM_FORMAT_BGRX8888: + case DRM_FORMAT_BGRA8888: + case DRM_FORMAT_BGRA1010102: + vs_format->swizzle =3D VSDC_SWIZZLE_BGRA; + break; + default: + /* N/A for YUV formats */ + vs_format->swizzle =3D VSDC_SWIZZLE_ARGB; + } + + /* N/A for non-YUV formats */ + vs_format->uv_swizzle =3D false; +} diff --git a/drivers/gpu/drm/verisilicon/vs_plane.h b/drivers/gpu/drm/veris= ilicon/vs_plane.h new file mode 100644 index 0000000000000..3595267c89b53 --- /dev/null +++ b/drivers/gpu/drm/verisilicon/vs_plane.h @@ -0,0 +1,68 @@ +/* SPDX-License-Identifier: GPL-2.0-only */ +/* + * Copyright (C) 2025 Icenowy Zheng + * + * Based on vs_dc_hw.h, which is: + * Copyright (C) 2023 VeriSilicon Holdings Co., Ltd. + */ + +#ifndef _VS_PLANE_H_ +#define _VS_PLANE_H_ + +#include + +#include +#include + +#define VSDC_MAKE_PLANE_SIZE(w, h) (((w) & 0x7fff) | (((h) & 0x7fff) << 15= )) +#define VSDC_MAKE_PLANE_POS(x, y) (((x) & 0x7fff) | (((y) & 0x7fff) << 15)) + +struct vs_dc; + +enum vs_color_format { + VSDC_COLOR_FORMAT_X4R4G4B4, + VSDC_COLOR_FORMAT_A4R4G4B4, + VSDC_COLOR_FORMAT_X1R5G5B5, + VSDC_COLOR_FORMAT_A1R5G5B5, + VSDC_COLOR_FORMAT_R5G6B5, + VSDC_COLOR_FORMAT_X8R8G8B8, + VSDC_COLOR_FORMAT_A8R8G8B8, + VSDC_COLOR_FORMAT_YUY2, + VSDC_COLOR_FORMAT_UYVY, + VSDC_COLOR_FORMAT_INDEX8, + VSDC_COLOR_FORMAT_MONOCHROME, + VSDC_COLOR_FORMAT_YV12 =3D 0xf, + VSDC_COLOR_FORMAT_A8, + VSDC_COLOR_FORMAT_NV12, + VSDC_COLOR_FORMAT_NV16, + VSDC_COLOR_FORMAT_RG16, + VSDC_COLOR_FORMAT_R8, + VSDC_COLOR_FORMAT_NV12_10BIT, + VSDC_COLOR_FORMAT_A2R10G10B10, + VSDC_COLOR_FORMAT_NV16_10BIT, + VSDC_COLOR_FORMAT_INDEX1, + VSDC_COLOR_FORMAT_INDEX2, + VSDC_COLOR_FORMAT_INDEX4, + VSDC_COLOR_FORMAT_P010, + VSDC_COLOR_FORMAT_YUV444, + VSDC_COLOR_FORMAT_YUV444_10BIT +}; + +enum vs_swizzle { + VSDC_SWIZZLE_ARGB, + VSDC_SWIZZLE_RGBA, + VSDC_SWIZZLE_ABGR, + VSDC_SWIZZLE_BGRA, +}; + +struct vs_format { + enum vs_color_format color; + enum vs_swizzle swizzle; + bool uv_swizzle; +}; + +void drm_format_to_vs_format(u32 drm_format, struct vs_format *vs_format); + +struct drm_plane *vs_primary_plane_init(struct drm_device *dev, struct vs_= dc *dc); + +#endif /* _VS_PLANE_H_ */ diff --git a/drivers/gpu/drm/verisilicon/vs_primary_plane.c b/drivers/gpu/d= rm/verisilicon/vs_primary_plane.c new file mode 100644 index 0000000000000..e5dcfc76f0702 --- /dev/null +++ b/drivers/gpu/drm/verisilicon/vs_primary_plane.c @@ -0,0 +1,157 @@ +// SPDX-License-Identifier: GPL-2.0-only +/* + * Copyright (C) 2025 Icenowy Zheng + */ + +#include + +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include + +#include "vs_crtc.h" +#include "vs_plane.h" +#include "vs_dc.h" +#include "vs_primary_plane_regs.h" + +static int vs_primary_plane_atomic_check(struct drm_plane *plane, + struct drm_atomic_state *state) +{ + struct drm_plane_state *new_plane_state =3D drm_atomic_get_new_plane_stat= e(state, + plane); + struct drm_crtc *crtc =3D new_plane_state->crtc; + struct drm_crtc_state *crtc_state; + + if (!crtc) + return 0; + + crtc_state =3D drm_atomic_get_existing_crtc_state(state, crtc); + if (WARN_ON(!crtc_state)) + return -EINVAL; + + return drm_atomic_helper_check_plane_state(new_plane_state, + crtc_state, + DRM_PLANE_NO_SCALING, + DRM_PLANE_NO_SCALING, + false, true); +} + + +static void vs_primary_plane_atomic_update(struct drm_plane *plane, + struct drm_atomic_state *atomic_state) +{ + struct drm_plane_state *state =3D drm_atomic_get_new_plane_state(atomic_s= tate, + plane); + struct drm_framebuffer *fb =3D state->fb; + struct drm_crtc *crtc =3D state->crtc; + struct drm_gem_dma_object *gem; + struct vs_dc *dc; + struct vs_crtc *vcrtc; + struct vs_format fmt; + unsigned int output, bpp; + dma_addr_t dma_addr; + + if (!crtc) + return; + + vcrtc =3D drm_crtc_to_vs_crtc(crtc); + output =3D vcrtc->id; + dc =3D vcrtc->dc; + + DRM_DEBUG_DRIVER("Updating output %d primary plane\n", output); + + regmap_update_bits(dc->regs, VSDC_FB_CONFIG_EX(output), + VSDC_FB_CONFIG_EX_DISPLAY_ID_MASK, + VSDC_FB_CONFIG_EX_DISPLAY_ID(output)); + + if (!state->visible || !fb) { + regmap_write(dc->regs, VSDC_FB_CONFIG(output), 0); + regmap_write(dc->regs, VSDC_FB_CONFIG_EX(output), 0); + goto commit; + } else { + regmap_set_bits(dc->regs, VSDC_FB_CONFIG_EX(output), + VSDC_FB_CONFIG_EX_FB_EN); + } + + drm_format_to_vs_format(state->fb->format->format, &fmt); + + regmap_update_bits(dc->regs, VSDC_FB_CONFIG(output), + VSDC_FB_CONFIG_FMT_MASK, + VSDC_FB_CONFIG_FMT(fmt.color)); + regmap_update_bits(dc->regs, VSDC_FB_CONFIG(output), + VSDC_FB_CONFIG_SWIZZLE_MASK, + VSDC_FB_CONFIG_SWIZZLE(fmt.swizzle)); + regmap_assign_bits(dc->regs, VSDC_FB_CONFIG(output), + VSDC_FB_CONFIG_UV_SWIZZLE_EN, fmt.uv_swizzle); + + /* Get the physical address of the buffer in memory */ + gem =3D drm_fb_dma_get_gem_obj(fb, 0); + + /* Compute the start of the displayed memory */ + bpp =3D fb->format->cpp[0]; + dma_addr =3D gem->dma_addr + fb->offsets[0]; + + /* Fixup framebuffer address for src coordinates */ + dma_addr +=3D (state->src.x1 >> 16) * bpp; + dma_addr +=3D (state->src.y1 >> 16) * fb->pitches[0]; + + regmap_write(dc->regs, VSDC_FB_ADDRESS(output), + lower_32_bits(dma_addr)); + regmap_write(dc->regs, VSDC_FB_STRIDE(output), + fb->pitches[0]); + + regmap_write(dc->regs, VSDC_FB_TOP_LEFT(output), + VSDC_MAKE_PLANE_POS(state->crtc_x, state->crtc_y)); + regmap_write(dc->regs, VSDC_FB_BOTTOM_RIGHT(output), + VSDC_MAKE_PLANE_POS(state->crtc_x + state->crtc_w, + state->crtc_y + state->crtc_h)); + regmap_write(dc->regs, VSDC_FB_SIZE(output), + VSDC_MAKE_PLANE_SIZE(state->crtc_w, state->crtc_h)); + + regmap_write(dc->regs, VSDC_FB_BLEND_CONFIG(output), + VSDC_FB_BLEND_CONFIG_BLEND_DISABLE); +commit: + regmap_set_bits(dc->regs, VSDC_FB_CONFIG_EX(output), + VSDC_FB_CONFIG_EX_COMMIT); +} + +static const struct drm_plane_helper_funcs vs_primary_plane_helper_funcs = =3D { + .atomic_check =3D vs_primary_plane_atomic_check, + .atomic_update =3D vs_primary_plane_atomic_update, +}; + +static const struct drm_plane_funcs vs_primary_plane_funcs =3D { + .atomic_destroy_state =3D drm_atomic_helper_plane_destroy_state, + .atomic_duplicate_state =3D drm_atomic_helper_plane_duplicate_state, + .disable_plane =3D drm_atomic_helper_disable_plane, + .reset =3D drm_atomic_helper_plane_reset, + .update_plane =3D drm_atomic_helper_update_plane, +}; + +struct drm_plane *vs_primary_plane_init(struct drm_device *drm_dev, struct= vs_dc *dc) +{ + struct drm_plane *plane; + + plane =3D drmm_universal_plane_alloc(drm_dev, struct drm_plane, dev, 0, + &vs_primary_plane_funcs, + dc->identity.formats->array, + dc->identity.formats->num, + NULL, + DRM_PLANE_TYPE_PRIMARY, + NULL); + + if (IS_ERR(plane)) + return plane; + + drm_plane_helper_add(plane, &vs_primary_plane_helper_funcs); + + return plane; +} diff --git a/drivers/gpu/drm/verisilicon/vs_primary_plane_regs.h b/drivers/= gpu/drm/verisilicon/vs_primary_plane_regs.h new file mode 100644 index 0000000000000..cbb125c46b390 --- /dev/null +++ b/drivers/gpu/drm/verisilicon/vs_primary_plane_regs.h @@ -0,0 +1,53 @@ +/* SPDX-License-Identifier: GPL-2.0-only */ +/* + * Copyright (C) 2025 Icenowy Zheng + * + * Based on vs_dc_hw.h, which is: + * Copyright (C) 2023 VeriSilicon Holdings Co., Ltd. + */ + +#ifndef _VS_PRIMARY_PLANE_REGS_H_ +#define _VS_PRIMARY_PLANE_REGS_H_ + +#include + +#define VSDC_FB_ADDRESS(n) (0x1400 + 0x4 * (n)) + +#define VSDC_FB_STRIDE(n) (0x1408 + 0x4 * (n)) + +#define VSDC_FB_CONFIG(n) (0x1518 + 0x4 * (n)) +#define VSDC_FB_CONFIG_CLEAR_EN BIT(8) +#define VSDC_FB_CONFIG_ROT_MASK GENMASK(13, 11) +#define VSDC_FB_CONFIG_ROT(v) ((v) << 11) +#define VSDC_FB_CONFIG_YUV_SPACE_MASK GENMASK(16, 14) +#define VSDC_FB_CONFIG_YUV_SPACE(v) ((v) << 14) +#define VSDC_FB_CONFIG_TILE_MODE_MASK GENMASK(21, 17) +#define VSDC_FB_CONFIG_TILE_MODE(v) ((v) << 14) +#define VSDC_FB_CONFIG_SCALE_EN BIT(22) +#define VSDC_FB_CONFIG_SWIZZLE_MASK GENMASK(24, 23) +#define VSDC_FB_CONFIG_SWIZZLE(v) ((v) << 23) +#define VSDC_FB_CONFIG_UV_SWIZZLE_EN BIT(25) +#define VSDC_FB_CONFIG_FMT_MASK GENMASK(31, 26) +#define VSDC_FB_CONFIG_FMT(v) ((v) << 26) + +#define VSDC_FB_SIZE(n) (0x1810 + 0x4 * (n)) +/* Fill with value generated with VSDC_MAKE_PLANE_SIZE(w, h) */ + +#define VSDC_FB_CONFIG_EX(n) (0x1CC0 + 0x4 * (n)) +#define VSDC_FB_CONFIG_EX_COMMIT BIT(12) +#define VSDC_FB_CONFIG_EX_FB_EN BIT(13) +#define VSDC_FB_CONFIG_EX_ZPOS_MASK GENMASK(18, 16) +#define VSDC_FB_CONFIG_EX_ZPOS(v) ((v) << 16) +#define VSDC_FB_CONFIG_EX_DISPLAY_ID_MASK GENMASK(19, 19) +#define VSDC_FB_CONFIG_EX_DISPLAY_ID(v) ((v) << 19) + +#define VSDC_FB_TOP_LEFT(n) (0x24D8 + 0x4 * (n)) +/* Fill with value generated with VSDC_MAKE_PLANE_POS(x, y) */ + +#define VSDC_FB_BOTTOM_RIGHT(n) (0x24E0 + 0x4 * (n)) +/* Fill with value generated with VSDC_MAKE_PLANE_POS(x, y) */ + +#define VSDC_FB_BLEND_CONFIG(n) (0x2510 + 0x4 * (n)) +#define VSDC_FB_BLEND_CONFIG_BLEND_DISABLE BIT(1) + +#endif /* _VS_PRIMARY_PLANE_REGS_H_ */ --=20 2.51.0 From nobody Thu Oct 2 06:19:41 2025 Received: from sender4-op-o15.zoho.com (sender4-op-o15.zoho.com [136.143.188.15]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id 02C5222CBC0; Sun, 21 Sep 2025 08:36:41 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=pass smtp.client-ip=136.143.188.15 ARC-Seal: i=2; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1758443803; cv=pass; b=ulUooZEC3sgtvVdaqHvKBTs4M8Q+/jVN7v1xLAhyg6fUz2gWEkQRXlHJH2EooFMXJpcxu6fLpdHj6wjJ7qUiPBOgWq+7DusTL6ADFbYK07l/XzhI3LRBqHWSHpmrmqKXnfoKOha7yRSE1H4U/bZPpgEWI3hQ08aW5RGOQy8Jx0g= ARC-Message-Signature: i=2; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1758443803; c=relaxed/simple; bh=IZ9F3NS1M2AUOVBZZf7r9qzYydISFqwXt9fG+i59pOI=; h=From:To:Cc:Subject:Date:Message-ID:In-Reply-To:References: MIME-Version; b=HGnmTo+YNJ+mMuF/50t5B494RqoAId/HVPNNCbjIF+JcBtxShIPmZyRWq2syDOlYooV6VG3DjDV+0Y+yAeicLJDRqQh/UAGHUu54ThVat4c9352d3GGmXfWt0ynmtIBm9jrcBcYD2jgbw65X303uwD81be8KqGngocVJgwsytKo= ARC-Authentication-Results: i=2; smtp.subspace.kernel.org; dmarc=pass (p=none dis=none) header.from=icenowy.me; spf=pass smtp.mailfrom=icenowy.me; dkim=pass (2048-bit key) header.d=icenowy.me header.i=uwu@icenowy.me header.b=RFHUWAuy; arc=pass smtp.client-ip=136.143.188.15 Authentication-Results: smtp.subspace.kernel.org; dmarc=pass (p=none dis=none) header.from=icenowy.me Authentication-Results: smtp.subspace.kernel.org; spf=pass smtp.mailfrom=icenowy.me Authentication-Results: smtp.subspace.kernel.org; dkim=pass (2048-bit key) header.d=icenowy.me header.i=uwu@icenowy.me header.b="RFHUWAuy" ARC-Seal: i=1; a=rsa-sha256; t=1758443762; cv=none; d=zohomail.com; s=zohoarc; b=JHYrdiw4cX583wjUQjpVOc+s3YqXLV30Ak7vRvLTTZWxMqrk1by2tIdcV8lHJ8KA5MAIqGpCMZh8/2uRSF/8k7q13jrRutJuPKflknux1YunJJ6U8axNsOxC0GJ0ajghu+3drT8i0cyTjSgkCDJGOMW0gCjXD5AyWGyNcRXM92M= ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=zohomail.com; s=zohoarc; t=1758443762; h=Content-Transfer-Encoding:Cc:Cc:Date:Date:From:From:In-Reply-To:MIME-Version:Message-ID:References:Subject:Subject:To:To:Message-Id:Reply-To; bh=UummsIlLCqmOdqHJZnvTjKcukpG7EfpYHc84mjTRvVE=; b=ClwfO+GrwB6BvQcTC0F29lelVRyWjQO5cJCDTIpGUlEzuZzuIjWuPM+Cmj3yJqXG74w8LHHzdKBh6/Eh/RPSmw9xzFni8k9o1D4Wrqry67PZX7EigXCbhxOE50i6677VwgsbFUxsWTuZodJBD3jCZytFdbpoNXM4bgQvVMQj6Bs= ARC-Authentication-Results: i=1; mx.zohomail.com; dkim=pass header.i=icenowy.me; spf=pass smtp.mailfrom=uwu@icenowy.me; dmarc=pass header.from= DKIM-Signature: v=1; a=rsa-sha256; q=dns/txt; c=relaxed/relaxed; t=1758443762; s=zmail2; d=icenowy.me; i=uwu@icenowy.me; h=From:From:To:To:Cc:Cc:Subject:Subject:Date:Date:Message-ID:In-Reply-To:References:MIME-Version:Content-Transfer-Encoding:Message-Id:Reply-To; bh=UummsIlLCqmOdqHJZnvTjKcukpG7EfpYHc84mjTRvVE=; b=RFHUWAuyB3dm23rD+bHxqcetPXhCoYxpFbqBEN48fh9DtL3ztC8WSgRSOa407PBF VtAFsWJj7u+C2rMmgu5OwzYI8Tah88ooqEhm66+aFubgnAh+fvRkPgKCUnpoEsvj48F kuEaoR/cdHT5TdhkvohpCf2r6tZGmim8++PZeFX4IejJe3GcY1IFZAz/Qm4UX/TblT6 TOZdsjGj52zDDSEqED4kSAsGXDNrIQHTkcrQEsd1Kdy7Rz1g2OxnLdZ16gudm9hfXYF vE/1RwLhIAp7H4JK7aLXoUp5E5+cAKBPVK/Gio8bqllfYAOWOSyHz3wP56IgJepfYiz e2ebVufc6A== Received: by mx.zohomail.com with SMTPS id 175844375941682.81760504450949; Sun, 21 Sep 2025 01:35:59 -0700 (PDT) From: Icenowy Zheng To: Maarten Lankhorst , Maxime Ripard , Thomas Zimmermann , David Airlie , Simona Vetter , Rob Herring , Krzysztof Kozlowski , Conor Dooley , Drew Fustini , Guo Ren , Fu Wei , Philipp Zabel , Heiko Stuebner , Andrzej Hajda , Neil Armstrong , Robert Foss , Laurent Pinchart , Jonas Karlman , Jernej Skrabec , Michal Wilczynski Cc: Han Gao , Yao Zi , dri-devel@lists.freedesktop.org, devicetree@vger.kernel.org, linux-kernel@vger.kernel.org, linux-riscv@lists.infradead.org, Icenowy Zheng , Krzysztof Kozlowski Subject: [PATCH v2 4/8] dt-bindings: display/bridge: add binding for TH1520 HDMI controller Date: Sun, 21 Sep 2025 16:34:42 +0800 Message-ID: <20250921083446.790374-5-uwu@icenowy.me> X-Mailer: git-send-email 2.51.0 In-Reply-To: <20250921083446.790374-1-uwu@icenowy.me> References: <20250921083446.790374-1-uwu@icenowy.me> Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable X-ZohoMailClient: External Content-Type: text/plain; charset="utf-8" T-Head TH1520 SoC contains a Synopsys DesignWare HDMI controller paired with DesignWare HDMI PHY, with an extra clock gate for HDMI pixel clock and two reset controls. Add a device tree binding to it. Signed-off-by: Icenowy Zheng Reviewed-by: Krzysztof Kozlowski --- Changes in v2: - Re-aligned multi-line clocks/resets in example. - Added Krzysztof's R-b. .../display/bridge/thead,th1520-dw-hdmi.yaml | 120 ++++++++++++++++++ 1 file changed, 120 insertions(+) create mode 100644 Documentation/devicetree/bindings/display/bridge/thead,= th1520-dw-hdmi.yaml diff --git a/Documentation/devicetree/bindings/display/bridge/thead,th1520-= dw-hdmi.yaml b/Documentation/devicetree/bindings/display/bridge/thead,th152= 0-dw-hdmi.yaml new file mode 100644 index 0000000000000..68fff885ce15b --- /dev/null +++ b/Documentation/devicetree/bindings/display/bridge/thead,th1520-dw-hdmi= .yaml @@ -0,0 +1,120 @@ +# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause) +%YAML 1.2 +--- +$id: http://devicetree.org/schemas/display/bridge/thead,th1520-dw-hdmi.yam= l# +$schema: http://devicetree.org/meta-schemas/core.yaml# + +title: T-Head TH1520 DesignWare HDMI TX Encoder + +maintainers: + - Icenowy Zheng + +description: + The HDMI transmitter is a Synopsys DesignWare HDMI TX controller + paired with a DesignWare HDMI Gen2 TX PHY. + +allOf: + - $ref: /schemas/display/bridge/synopsys,dw-hdmi.yaml# + +properties: + compatible: + enum: + - thead,th1520-dw-hdmi + + reg-io-width: + const: 4 + + clocks: + maxItems: 4 + + clock-names: + items: + - const: iahb + - const: isfr + - const: cec + - const: pix + + resets: + items: + - description: Main reset + - description: Configuration APB reset + + reset-names: + items: + - const: main + - const: apb + + ports: + $ref: /schemas/graph.yaml#/properties/ports + + properties: + port@0: + $ref: /schemas/graph.yaml#/properties/port + description: Input port connected to DC8200 DPU "DP" output + + port@1: + $ref: /schemas/graph.yaml#/properties/port + description: HDMI output port + + required: + - port@0 + - port@1 + +required: + - compatible + - reg + - reg-io-width + - clocks + - clock-names + - resets + - reset-names + - interrupts + - ports + +unevaluatedProperties: false + +examples: + - | + #include + #include + #include + + soc { + #address-cells =3D <2>; + #size-cells =3D <2>; + + hdmi@ffef540000 { + compatible =3D "thead,th1520-dw-hdmi"; + reg =3D <0xff 0xef540000 0x0 0x40000>; + reg-io-width =3D <4>; + interrupts =3D <111 IRQ_TYPE_LEVEL_HIGH>; + clocks =3D <&clk_vo CLK_HDMI_PCLK>, + <&clk_vo CLK_HDMI_SFR>, + <&clk_vo CLK_HDMI_CEC>, + <&clk_vo CLK_HDMI_PIXCLK>; + clock-names =3D "iahb", "isfr", "cec", "pix"; + resets =3D <&rst_vo TH1520_RESET_ID_HDMI>, + <&rst_vo TH1520_RESET_ID_HDMI_APB>; + reset-names =3D "main", "apb"; + + ports { + #address-cells =3D <1>; + #size-cells =3D <0>; + port@0 { + reg =3D <0>; + + hdmi_in: endpoint { + remote-endpoint =3D <&dpu_out_dp1>; + }; + }; + + port@1 { + reg =3D <1>; + + hdmi_out_conn: endpoint { + remote-endpoint =3D <&hdmi_conn_in>; + }; + }; + }; + }; + }; --=20 2.51.0 From nobody Thu Oct 2 06:19:41 2025 Received: from sender4-op-o15.zoho.com (sender4-op-o15.zoho.com [136.143.188.15]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id 5CB4C23E23C; Sun, 21 Sep 2025 08:37:05 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=pass smtp.client-ip=136.143.188.15 ARC-Seal: i=2; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1758443827; cv=pass; b=gu6vMTE9LV0hgqbE9sNMhlN2DZcnFFjaGZR4QpgnMXUGSi5N7kOTPXw3lG+ohOIi7sxGeQ5EKiuRMHoWsncIK3uUXXEB0vq8Di49RucIHRwdD8cuxyqjSvVBAaXIhZHUAhWBx4V/ZTfihCqq1gRwLFWleKqG38QKem5r3gezdQI= ARC-Message-Signature: i=2; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1758443827; c=relaxed/simple; bh=e8O3AAtIeGRM9Ht4uV18likb8in/5eB4M4BRgt2jvKo=; h=From:To:Cc:Subject:Date:Message-ID:In-Reply-To:References: MIME-Version; b=Ml67SDfr79SgUFjNNgkpFMzkmZfzaC1oICP3NpVp8olv2EKcXv8umbGhF/XZk5YKspLaJPDjJQyb1DpXjR7XtniuhdPYEXxcTnG8o8wcQEsMkJi+RpYwmqHz45pni5pmE7OZ2FLhwwaywTFR6gy7Ol75HuNZsD+D6dUF5YQjhNs= ARC-Authentication-Results: i=2; smtp.subspace.kernel.org; dmarc=pass (p=none dis=none) header.from=icenowy.me; spf=pass smtp.mailfrom=icenowy.me; dkim=pass (2048-bit key) header.d=icenowy.me header.i=uwu@icenowy.me header.b=Iepk3Lnt; arc=pass smtp.client-ip=136.143.188.15 Authentication-Results: smtp.subspace.kernel.org; dmarc=pass (p=none dis=none) header.from=icenowy.me Authentication-Results: smtp.subspace.kernel.org; spf=pass smtp.mailfrom=icenowy.me Authentication-Results: smtp.subspace.kernel.org; dkim=pass (2048-bit key) header.d=icenowy.me header.i=uwu@icenowy.me header.b="Iepk3Lnt" ARC-Seal: i=1; a=rsa-sha256; t=1758443792; cv=none; d=zohomail.com; s=zohoarc; b=cJLjBy93QyDUnEnwVlvyxRH6EyLX57O9pe9TSiMlgdNEbOVzJHQU8+L8nQiVNPMeRRTcI+wq0ClYfJgeV4a1ePI6Z7X4olNQpmq+oMDLt5ZtUs2mSYAJjk1qVS9QYDwyeDlhu0mf+QRqu1sboTYRzwdUA+ZD3qDiMtvDyzdZmgA= ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=zohomail.com; s=zohoarc; t=1758443792; h=Content-Transfer-Encoding:Cc:Cc:Date:Date:From:From:In-Reply-To:MIME-Version:Message-ID:References:Subject:Subject:To:To:Message-Id:Reply-To; bh=+/B8fvIMZPaRWSNHG7t+VuDASYKnqulNzE2HvO5LAfk=; b=EiYhg1a7w1GOuBxKDK9U+ftPBuf/X9kxPFdTLh5Lc+4kl2APWbm8z2MKZhkM1kco8BVT8n90aydwRNLUVMGr8xJmefhog9qhi9lRynxktivbcOTF/cfGKpnjfavAldsv70cQEL/fu5sJWSbS04zTBojj+NPhrjLCCGjC/p2wm+A= ARC-Authentication-Results: i=1; mx.zohomail.com; dkim=pass header.i=icenowy.me; spf=pass smtp.mailfrom=uwu@icenowy.me; dmarc=pass header.from= DKIM-Signature: v=1; a=rsa-sha256; q=dns/txt; c=relaxed/relaxed; t=1758443792; s=zmail2; d=icenowy.me; i=uwu@icenowy.me; h=From:From:To:To:Cc:Cc:Subject:Subject:Date:Date:Message-ID:In-Reply-To:References:MIME-Version:Content-Transfer-Encoding:Message-Id:Reply-To; bh=+/B8fvIMZPaRWSNHG7t+VuDASYKnqulNzE2HvO5LAfk=; b=Iepk3LntI/vBxQNlCgIeaeqF4Gsy4WBxf0qN595owNJx/IAqVJvMamxBOZ4paxuy BiJulO3scdr2fJXeI4u7JHzhhuu+lGkexDN7MXUHm6HMMC9AeOuMg6ky/oFMHd67EkH 1a0Ur/4rHrhYM6g7Px8td2cT8/gMBX2th+kKFPPvvy3cf13cmOmxOx5aNSrp6n+tEMG VtfQHy/qNK8NlgBWVQ8Aa29pm2Xh0KRiv/K3dFHIdoCJIQ3dONwbKiLo3Q/NGU+eobH fQCO7W3U7hX6bF4fjU0dNkIQ68j+SigbdzSSYOgx1thgfbzgyFq61X8hOniuQ08cco3 DvYrtYHgQQ== Received: by mx.zohomail.com with SMTPS id 1758443789244756.2990749927618; Sun, 21 Sep 2025 01:36:29 -0700 (PDT) From: Icenowy Zheng To: Maarten Lankhorst , Maxime Ripard , Thomas Zimmermann , David Airlie , Simona Vetter , Rob Herring , Krzysztof Kozlowski , Conor Dooley , Drew Fustini , Guo Ren , Fu Wei , Philipp Zabel , Heiko Stuebner , Andrzej Hajda , Neil Armstrong , Robert Foss , Laurent Pinchart , Jonas Karlman , Jernej Skrabec , Michal Wilczynski Cc: Han Gao , Yao Zi , dri-devel@lists.freedesktop.org, devicetree@vger.kernel.org, linux-kernel@vger.kernel.org, linux-riscv@lists.infradead.org, Icenowy Zheng Subject: [PATCH v2 5/8] drm/bridge: add a driver for T-Head TH1520 HDMI controller Date: Sun, 21 Sep 2025 16:34:43 +0800 Message-ID: <20250921083446.790374-6-uwu@icenowy.me> X-Mailer: git-send-email 2.51.0 In-Reply-To: <20250921083446.790374-1-uwu@icenowy.me> References: <20250921083446.790374-1-uwu@icenowy.me> Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable X-ZohoMailClient: External Content-Type: text/plain; charset="utf-8" T-Head TH1520 SoC contains a Synopsys DesignWare HDMI controller (paired with DesignWare HDMI TX PHY Gen2) that takes the "DP" output from the display controller. Add a driver for this controller utilizing the common DesignWare HDMI code in the kernel. Signed-off-by: Icenowy Zheng --- Changes in v2: - Created a new function to set PHY parameters and refactored the control flow of the configure_phy callback. MAINTAINERS | 1 + drivers/gpu/drm/bridge/Kconfig | 10 ++ drivers/gpu/drm/bridge/Makefile | 1 + drivers/gpu/drm/bridge/th1520-dw-hdmi.c | 173 ++++++++++++++++++++++++ 4 files changed, 185 insertions(+) create mode 100644 drivers/gpu/drm/bridge/th1520-dw-hdmi.c diff --git a/MAINTAINERS b/MAINTAINERS index f6206963efbf0..98af9dd3664f5 100644 --- a/MAINTAINERS +++ b/MAINTAINERS @@ -21759,6 +21759,7 @@ F: Documentation/devicetree/bindings/reset/thead,th= 1520-reset.yaml F: arch/riscv/boot/dts/thead/ F: drivers/clk/thead/clk-th1520-ap.c F: drivers/firmware/thead,th1520-aon.c +F: drivers/gpu/drm/bridge/th1520-dw-hdmi.c F: drivers/mailbox/mailbox-th1520.c F: drivers/net/ethernet/stmicro/stmmac/dwmac-thead.c F: drivers/pinctrl/pinctrl-th1520.c diff --git a/drivers/gpu/drm/bridge/Kconfig b/drivers/gpu/drm/bridge/Kconfig index b9e0ca85226a6..f75e6ad04179f 100644 --- a/drivers/gpu/drm/bridge/Kconfig +++ b/drivers/gpu/drm/bridge/Kconfig @@ -322,6 +322,16 @@ config DRM_THINE_THC63LVD1024 help Thine THC63LVD1024 LVDS/parallel converter driver. =20 +config DRM_THEAD_TH1520_DW_HDMI + tristate "T-Head TH1520 DesignWare HDMI bridge" + depends on OF + depends on COMMON_CLK + depends on ARCH_THEAD || COMPILE_TEST + select DRM_DW_HDMI + help + Choose this to enable support for the internal HDMI bridge found + on the T-Head TH1520 SoC. + config DRM_TOSHIBA_TC358762 tristate "TC358762 DSI/DPI bridge" depends on OF diff --git a/drivers/gpu/drm/bridge/Makefile b/drivers/gpu/drm/bridge/Makef= ile index 245e8a27e3fc5..421e445ff1cd9 100644 --- a/drivers/gpu/drm/bridge/Makefile +++ b/drivers/gpu/drm/bridge/Makefile @@ -27,6 +27,7 @@ obj-$(CONFIG_DRM_SIL_SII8620) +=3D sil-sii8620.o obj-$(CONFIG_DRM_SII902X) +=3D sii902x.o obj-$(CONFIG_DRM_SII9234) +=3D sii9234.o obj-$(CONFIG_DRM_SIMPLE_BRIDGE) +=3D simple-bridge.o +obj-$(CONFIG_DRM_THEAD_TH1520_DW_HDMI) +=3D th1520-dw-hdmi.o obj-$(CONFIG_DRM_THINE_THC63LVD1024) +=3D thc63lvd1024.o obj-$(CONFIG_DRM_TOSHIBA_TC358762) +=3D tc358762.o obj-$(CONFIG_DRM_TOSHIBA_TC358764) +=3D tc358764.o diff --git a/drivers/gpu/drm/bridge/th1520-dw-hdmi.c b/drivers/gpu/drm/brid= ge/th1520-dw-hdmi.c new file mode 100644 index 0000000000000..efb27d37ff652 --- /dev/null +++ b/drivers/gpu/drm/bridge/th1520-dw-hdmi.c @@ -0,0 +1,173 @@ +// SPDX-License-Identifier: GPL-2.0+ +/* + * Copyright (C) 2025 Icenowy Zheng + * + * Based on rcar_dw_hdmi.c, which is: + * Copyright (C) 2016 Renesas Electronics Corporation + * Based on imx8mp-hdmi-tx.c, which is: + * Copyright (C) 2022 Pengutronix, Lucas Stach + */ + +#include +#include +#include +#include +#include + +#include +#include + +#define TH1520_HDMI_PHY_OPMODE_PLLCFG 0x06 /* Mode of operation and PLL di= viders */ +#define TH1520_HDMI_PHY_CKSYMTXCTRL 0x09 /* Clock Symbol and Transmitter C= ontrol Register */ +#define TH1520_HDMI_PHY_VLEVCTRL 0x0e /* Voltage Level Control Register */ +#define TH1520_HDMI_PHY_PLLCURRGMPCTRL 0x10 /* PLL current and Gmp (conduc= tance) */ +#define TH1520_HDMI_PHY_PLLDIVCTRL 0x11 /* PLL dividers */ +#define TH1520_HDMI_PHY_TXTERM 0x19 /* Transmission Termination Register = */ + +struct th1520_hdmi_phy_params { + unsigned long mpixelclock; + u16 opmode_pllcfg; + u16 pllcurrgmpctrl; + u16 plldivctrl; + u16 cksymtxctrl; + u16 vlevctrl; + u16 txterm; +}; + +static const struct th1520_hdmi_phy_params th1520_hdmi_phy_params[] =3D { + { 35500000, 0x0003, 0x0283, 0x0628, 0x8088, 0x01a0, 0x0007 }, + { 44900000, 0x0003, 0x0285, 0x0228, 0x8088, 0x01a0, 0x0007 }, + { 71000000, 0x0002, 0x1183, 0x0614, 0x8088, 0x01a0, 0x0007 }, + { 90000000, 0x0002, 0x1142, 0x0214, 0x8088, 0x01a0, 0x0007 }, + { 121750000, 0x0001, 0x20c0, 0x060a, 0x8088, 0x01a0, 0x0007 }, + { 165000000, 0x0001, 0x2080, 0x020a, 0x8088, 0x01a0, 0x0007 }, + { 198000000, 0x0000, 0x3040, 0x0605, 0x83c8, 0x0120, 0x0004 }, + { 297000000, 0x0000, 0x3041, 0x0205, 0x81dc, 0x0200, 0x0005 }, + { 371250000, 0x0640, 0x3041, 0x0205, 0x80f6, 0x0140, 0x0000 }, + { 495000000, 0x0640, 0x3080, 0x0005, 0x80f6, 0x0140, 0x0000 }, + { 594000000, 0x0640, 0x3080, 0x0005, 0x80fa, 0x01e0, 0x0004 }, +}; + +struct th1520_hdmi { + struct dw_hdmi_plat_data plat_data; + struct dw_hdmi *dw_hdmi; + struct clk *pixclk; + struct reset_control *mainrst, *prst; +}; + +static enum drm_mode_status +th1520_hdmi_mode_valid(struct dw_hdmi *hdmi, void *data, + const struct drm_display_info *info, + const struct drm_display_mode *mode) +{ + /* + * The maximum supported clock frequency is 594 MHz, as shown in the PHY + * parameters table. + */ + if (mode->clock > 594000) + return MODE_CLOCK_HIGH; + + return MODE_OK; +} + +static void th1520_hdmi_phy_set_params(struct dw_hdmi *hdmi, + const struct th1520_hdmi_phy_params *params) +{ + dw_hdmi_phy_i2c_write(hdmi, params->opmode_pllcfg, + TH1520_HDMI_PHY_OPMODE_PLLCFG); + dw_hdmi_phy_i2c_write(hdmi, params->pllcurrgmpctrl, + TH1520_HDMI_PHY_PLLCURRGMPCTRL); + dw_hdmi_phy_i2c_write(hdmi, params->plldivctrl, + TH1520_HDMI_PHY_PLLDIVCTRL); + dw_hdmi_phy_i2c_write(hdmi, params->vlevctrl, + TH1520_HDMI_PHY_VLEVCTRL); + dw_hdmi_phy_i2c_write(hdmi, params->cksymtxctrl, + TH1520_HDMI_PHY_CKSYMTXCTRL); + dw_hdmi_phy_i2c_write(hdmi, params->txterm, + TH1520_HDMI_PHY_TXTERM); +} + +static int th1520_hdmi_phy_configure(struct dw_hdmi *hdmi, void *data, + unsigned long mpixelclock) +{ + unsigned int i; + + for (i =3D 0; i < ARRAY_SIZE(th1520_hdmi_phy_params); i++) { + if (mpixelclock <=3D th1520_hdmi_phy_params[i].mpixelclock) { + th1520_hdmi_phy_set_params(hdmi, + &th1520_hdmi_phy_params[i]); + return 0; + } + } + + return -EINVAL; +} + +static int th1520_dw_hdmi_probe(struct platform_device *pdev) +{ + struct th1520_hdmi *hdmi; + struct dw_hdmi_plat_data *plat_data; + struct device *dev =3D &pdev->dev; + + hdmi =3D devm_kzalloc(dev, sizeof(*hdmi), GFP_KERNEL); + if (!hdmi) + return -ENOMEM; + + plat_data =3D &hdmi->plat_data; + + hdmi->pixclk =3D devm_clk_get_enabled(dev, "pix"); + if (IS_ERR(hdmi->pixclk)) + return dev_err_probe(dev, PTR_ERR(hdmi->pixclk), + "Unable to get pixel clock\n"); + + hdmi->mainrst =3D devm_reset_control_get_exclusive_deasserted(dev, "main"= ); + if (IS_ERR(hdmi->mainrst)) + return dev_err_probe(dev, PTR_ERR(hdmi->mainrst), + "Unable to get main reset\n"); + + hdmi->prst =3D devm_reset_control_get_exclusive_deasserted(dev, "apb"); + if (IS_ERR(hdmi->prst)) + return dev_err_probe(dev, PTR_ERR(hdmi->prst), + "Unable to get apb reset\n"); + + plat_data->output_port =3D 1; + plat_data->mode_valid =3D th1520_hdmi_mode_valid; + plat_data->configure_phy =3D th1520_hdmi_phy_configure; + plat_data->priv_data =3D hdmi; + + hdmi->dw_hdmi =3D dw_hdmi_probe(pdev, plat_data); + if (IS_ERR(hdmi)) + return PTR_ERR(hdmi); + + platform_set_drvdata(pdev, hdmi); + + return 0; +} + +static void th1520_dw_hdmi_remove(struct platform_device *pdev) +{ + struct dw_hdmi *hdmi =3D platform_get_drvdata(pdev); + + dw_hdmi_remove(hdmi); +} + +static const struct of_device_id th1520_dw_hdmi_of_table[] =3D { + { .compatible =3D "thead,th1520-dw-hdmi" }, + { /* Sentinel */ }, +}; +MODULE_DEVICE_TABLE(of, th1520_dw_hdmi_of_table); + +static struct platform_driver th1520_dw_hdmi_platform_driver =3D { + .probe =3D th1520_dw_hdmi_probe, + .remove =3D th1520_dw_hdmi_remove, + .driver =3D { + .name =3D "th1520-dw-hdmi", + .of_match_table =3D th1520_dw_hdmi_of_table, + }, +}; + +module_platform_driver(th1520_dw_hdmi_platform_driver); + +MODULE_AUTHOR("Icenowy Zheng "); +MODULE_DESCRIPTION("T-Head TH1520 HDMI Encoder Driver"); +MODULE_LICENSE("GPL"); --=20 2.51.0 From nobody Thu Oct 2 06:19:41 2025 Received: from sender4-op-o15.zoho.com (sender4-op-o15.zoho.com [136.143.188.15]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id F2AE31684A4; Sun, 21 Sep 2025 08:37:21 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=pass smtp.client-ip=136.143.188.15 ARC-Seal: i=2; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1758443843; cv=pass; b=JpwZ/ayPmMLuVd1reQRfc6cFcqXv6dmjFqA2/zUbtM9/DtLJlkcSbAuYy0WgKi6ktnwh0cpO1s/00oUxaBF0LYt8iZD8SCCrwmfb8lNCZFkrtjZATi4zTh61X/6aWWj2lvSZnaibIi66vorvS/n+oYrkxA5uX6LVwwCo5+NaRf4= ARC-Message-Signature: i=2; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1758443843; c=relaxed/simple; bh=H8KR0Bz4Tgjbl55X6vagHJ6YH/WuCEg10cSnTBuTg+U=; h=From:To:Cc:Subject:Date:Message-ID:In-Reply-To:References: MIME-Version; b=W4dVBPo3GC3FG20HU7x6iZp+C/T2nZzUBKEhtwFgrHPzwKpgU+q+1lJLQlVbbz3Nq4ProE7/UBJkUvkc60pMaGWpKh0HZLYCNyrEKJ8ZeBZbw3Mh7yEC7EsmNxw3Jdy8TXEPRWPxcuTbejUeE1QVWwoSMeftB8KyLCSWj3c/iIs= ARC-Authentication-Results: i=2; smtp.subspace.kernel.org; dmarc=pass (p=none dis=none) header.from=icenowy.me; spf=pass smtp.mailfrom=icenowy.me; dkim=pass (2048-bit key) header.d=icenowy.me header.i=uwu@icenowy.me header.b=BO+0t6IQ; arc=pass smtp.client-ip=136.143.188.15 Authentication-Results: smtp.subspace.kernel.org; dmarc=pass (p=none dis=none) header.from=icenowy.me Authentication-Results: smtp.subspace.kernel.org; spf=pass smtp.mailfrom=icenowy.me Authentication-Results: smtp.subspace.kernel.org; dkim=pass (2048-bit key) header.d=icenowy.me header.i=uwu@icenowy.me header.b="BO+0t6IQ" ARC-Seal: i=1; a=rsa-sha256; t=1758443802; cv=none; d=zohomail.com; s=zohoarc; b=WPqPnTQbFJxbkqA+h0xKvBLHwraN98u655+A7nF/4zkMZSc1hzcGtdN2t3ZVMAzMb+lYX7wQ8Z89V7TCCmZU6oNMMUh9mhWYAGa6Jgpt0SEykMp63lxM8fqUjPUKqCJHHjwjrvolB3qdLuKR0I4K2W7OmQMP7ccZbJW6DXy2JKw= ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=zohomail.com; s=zohoarc; t=1758443802; h=Content-Transfer-Encoding:Cc:Cc:Date:Date:From:From:In-Reply-To:MIME-Version:Message-ID:References:Subject:Subject:To:To:Message-Id:Reply-To; bh=8F+JwGCuCjf3w8Hhvlrd5/2iHdj26ikVBVJ1VKCtDTc=; b=ez/QpJ2G0NowWpIB0JRmqtiU40TxoScXu+Q0Da2I0y91AQ35W9CQAJ1a2i3iX6QToLeeiySpd8XwskktfaMrIHFp2wlyWC9DoW9sIg8tI8iWA73E4dC8sDQhGfRJqbBwcFTI4uIlFXEjoAuZ8fGTQXBTuPjgcO/YR/IgwEyxnzY= ARC-Authentication-Results: i=1; mx.zohomail.com; dkim=pass header.i=icenowy.me; spf=pass smtp.mailfrom=uwu@icenowy.me; dmarc=pass header.from= DKIM-Signature: v=1; a=rsa-sha256; q=dns/txt; c=relaxed/relaxed; t=1758443802; s=zmail2; d=icenowy.me; i=uwu@icenowy.me; h=From:From:To:To:Cc:Cc:Subject:Subject:Date:Date:Message-ID:In-Reply-To:References:MIME-Version:Content-Transfer-Encoding:Message-Id:Reply-To; bh=8F+JwGCuCjf3w8Hhvlrd5/2iHdj26ikVBVJ1VKCtDTc=; b=BO+0t6IQ8piEQNXez8qXW7GulWVcYba1iCKdswdbNC/hengw8n+Y9clHPk5UmoRB qIhZzFQCjwyof/e7BssMy9Weho+GE26D54+y2MDhzAyV6kpjLUXX6+Uq+WHPGHlLaKa Fr8eJzzZbvslEIXbjieYhLeNcKVTczyk0s2Noq1Zlvf7DkltMwlbP3tVmmmP4VEED0T lMg2skohdM+mknt95nvKRxRdsjrDVmbIWdzOPRpC2/eXPbp/DXX5BMEqGG3rbHqT8IA KnpZngsyD7pba6jbS06LxqVxU+h4p9lZLyYImw9saPjgPTE893SJZkuPG88bq5Fqi1I /Y5UNO5rgg== Received: by mx.zohomail.com with SMTPS id 1758443801039866.307085468272; Sun, 21 Sep 2025 01:36:41 -0700 (PDT) From: Icenowy Zheng To: Maarten Lankhorst , Maxime Ripard , Thomas Zimmermann , David Airlie , Simona Vetter , Rob Herring , Krzysztof Kozlowski , Conor Dooley , Drew Fustini , Guo Ren , Fu Wei , Philipp Zabel , Heiko Stuebner , Andrzej Hajda , Neil Armstrong , Robert Foss , Laurent Pinchart , Jonas Karlman , Jernej Skrabec , Michal Wilczynski Cc: Han Gao , Yao Zi , dri-devel@lists.freedesktop.org, devicetree@vger.kernel.org, linux-kernel@vger.kernel.org, linux-riscv@lists.infradead.org, Icenowy Zheng Subject: [PATCH v2 6/8] riscv: dts: thead: add DPU and HDMI device tree nodes Date: Sun, 21 Sep 2025 16:34:44 +0800 Message-ID: <20250921083446.790374-7-uwu@icenowy.me> X-Mailer: git-send-email 2.51.0 In-Reply-To: <20250921083446.790374-1-uwu@icenowy.me> References: <20250921083446.790374-1-uwu@icenowy.me> Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable X-ZohoMailClient: External Content-Type: text/plain; charset="utf-8" T-Head TH1520 SoC contains a Verisilicon DC8200 display controller (called DPU in manual) and a Synopsys DesignWare HDMI TX controller. Add device tree nodes to them. Signed-off-by: Icenowy Zheng --- No changes in v2. arch/riscv/boot/dts/thead/th1520.dtsi | 70 +++++++++++++++++++++++++++ 1 file changed, 70 insertions(+) diff --git a/arch/riscv/boot/dts/thead/th1520.dtsi b/arch/riscv/boot/dts/th= ead/th1520.dtsi index 03f1d73190499..8cebf4eaee5e3 100644 --- a/arch/riscv/boot/dts/thead/th1520.dtsi +++ b/arch/riscv/boot/dts/thead/th1520.dtsi @@ -515,6 +515,76 @@ clk_vo: clock-controller@ffef528050 { #clock-cells =3D <1>; }; =20 + hdmi: hdmi@ffef540000 { + compatible =3D "thead,th1520-dw-hdmi"; + reg =3D <0xff 0xef540000 0x0 0x40000>; + reg-io-width =3D <4>; + interrupts =3D <111 IRQ_TYPE_LEVEL_HIGH>; + clocks =3D <&clk_vo CLK_HDMI_PCLK>, + <&clk_vo CLK_HDMI_SFR>, + <&clk_vo CLK_HDMI_CEC>, + <&clk_vo CLK_HDMI_PIXCLK>; + clock-names =3D "iahb", "isfr", "cec", "pix"; + resets =3D <&rst TH1520_RESET_ID_HDMI>, + <&rst TH1520_RESET_ID_HDMI_APB>; + reset-names =3D "main", "apb"; + status =3D "disabled"; + + ports { + #address-cells =3D <1>; + #size-cells =3D <0>; + + port@0 { + reg =3D <0>; + + hdmi_in: endpoint { + remote-endpoint =3D <&dpu_out_dp1>; + }; + }; + + hdmi_out_port: port@1 { + reg =3D <1>; + }; + }; + }; + + dpu: display@ffef600000 { + compatible =3D "verisilicon,dc"; + reg =3D <0xff 0xef600000 0x0 0x100000>; + interrupts =3D <93 IRQ_TYPE_LEVEL_HIGH>; + clocks =3D <&clk_vo CLK_DPU_CCLK>, + <&clk_vo CLK_DPU_ACLK>, + <&clk_vo CLK_DPU_HCLK>, + <&clk_vo CLK_DPU_PIXELCLK0>, + <&clk_vo CLK_DPU_PIXELCLK1>; + clock-names =3D "core", "axi", "ahb", "pix0", "pix1"; + resets =3D <&rst TH1520_RESET_ID_DPU_CORE>, + <&rst TH1520_RESET_ID_DPU_AXI>, + <&rst TH1520_RESET_ID_DPU_AHB>; + reset-names =3D "core", "axi", "ahb"; + status =3D "disabled"; + + ports { + #address-cells =3D <1>; + #size-cells =3D <0>; + + dpu_port0: port@0 { + reg =3D <0>; + }; + + dpu_port1: port@1 { + reg =3D <1>; + #address-cells =3D <1>; + #size-cells =3D <0>; + + dpu_out_dp1: endpoint@1 { + reg =3D <1>; + remote-endpoint =3D <&hdmi_in>; + }; + }; + }; + }; + dmac0: dma-controller@ffefc00000 { compatible =3D "snps,axi-dma-1.01a"; reg =3D <0xff 0xefc00000 0x0 0x1000>; --=20 2.51.0 From nobody Thu Oct 2 06:19:41 2025 Received: from sender4-op-o15.zoho.com (sender4-op-o15.zoho.com [136.143.188.15]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id 76717245005; Sun, 21 Sep 2025 08:37:31 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=pass smtp.client-ip=136.143.188.15 ARC-Seal: i=2; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1758443853; cv=pass; b=kFwdhSgnxbA3JUUCq/0Tm65cqKAyv45p91buIIl0S/7UTMXt7LG/tZfnyR484rqqKOWmnoqLvqxWb7znsROI/91kmUr66utJfL3FUpCCvb8MzyuP9vuOCttprZhE3fsB8IE5ruDzHX2S4/ZZgS4gWjR/RzT+4WuBtgFtY0ddHGE= ARC-Message-Signature: i=2; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1758443853; c=relaxed/simple; bh=8fGGb5vMfRTqsz37MGb+srjgn0HOdqThDS/upQGPYKM=; h=From:To:Cc:Subject:Date:Message-ID:In-Reply-To:References: MIME-Version; b=DVAk6YqQIuSccBgLv2Kv04b/1KmRvn5muOaat2Iez/qC2q07AY9wnA59n01zWn68Pr50B/pR01yPurE4xXZaYAyTUOZMtMNjz1/vb61FwxMQtqQf1XWd/2Rm4/YXJadzhdG27pq7XL05M0ksBXsjILyIFsAK79YDDtjuaizm8+Y= ARC-Authentication-Results: i=2; smtp.subspace.kernel.org; dmarc=pass (p=none dis=none) header.from=icenowy.me; spf=pass smtp.mailfrom=icenowy.me; dkim=pass (2048-bit key) header.d=icenowy.me header.i=uwu@icenowy.me header.b=UfF29hF1; arc=pass smtp.client-ip=136.143.188.15 Authentication-Results: smtp.subspace.kernel.org; dmarc=pass (p=none dis=none) header.from=icenowy.me Authentication-Results: smtp.subspace.kernel.org; spf=pass smtp.mailfrom=icenowy.me Authentication-Results: smtp.subspace.kernel.org; dkim=pass (2048-bit key) header.d=icenowy.me header.i=uwu@icenowy.me header.b="UfF29hF1" ARC-Seal: i=1; a=rsa-sha256; t=1758443816; cv=none; d=zohomail.com; s=zohoarc; b=nxXNMqI2qg6zufy0Xd4Y514jhC0IROp7AKcI+Aanga4iNtC53S+f5SZL28kR7zqaLaKqnEOeEdfFgZZaSSjYIl0mPPFMAT0Cfj+G3lVh2nZNyrNxZVjiKR3/GoZHdaVYCpz3JnsLttwE6Cp1y1to0+RcxHJ1/L0hbdOyCc5ma+8= ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=zohomail.com; s=zohoarc; t=1758443816; h=Content-Transfer-Encoding:Cc:Cc:Date:Date:From:From:In-Reply-To:MIME-Version:Message-ID:References:Subject:Subject:To:To:Message-Id:Reply-To; bh=codWgtTq6Zb64pUUOo3Dzr6/p0mx/o9YUriH+67Le3Y=; b=OZWl27m87tvRQ788UMUql8HK10J3MIqNzlvXMwQJ6vcMokzda0xrsNi1mptshA5/cIUt62X0XQwyo2Kwce7HsF9ciMa7SNzzEdzCZ3gWW6yMssgRly90DoLOJlLjfMz8uHa4eOqQI/gTI5BvQ4YI2x/0TvuxOnixhzNoEKr24fc= ARC-Authentication-Results: i=1; mx.zohomail.com; dkim=pass header.i=icenowy.me; spf=pass smtp.mailfrom=uwu@icenowy.me; dmarc=pass header.from= DKIM-Signature: v=1; a=rsa-sha256; q=dns/txt; c=relaxed/relaxed; t=1758443816; s=zmail2; d=icenowy.me; i=uwu@icenowy.me; h=From:From:To:To:Cc:Cc:Subject:Subject:Date:Date:Message-ID:In-Reply-To:References:MIME-Version:Content-Transfer-Encoding:Message-Id:Reply-To; bh=codWgtTq6Zb64pUUOo3Dzr6/p0mx/o9YUriH+67Le3Y=; b=UfF29hF1PQmU2MZ1Ge9X15w6oi2ao/rzoft/tWrDjnjk2+okrjGjfXRQI0xCNBub UVPT3Tu9DJNDAtKt2eW1Ew/fDjDHd3TkCa2aPYSrXtqQTjU56WEdmdLjKlQhqFARjHl 9Kv/R6793q+gkpEcZc/12JSK9MGbqJyzG4soMAFYY7MuMUulyjY2dnOdw1Sb/XuJPnu 0+L3lyKvwsuruJcQQU36oQFC1hRIcKxeOtkaDoWCgrPH5134OWdtyuud08tftrbvXo7 tdUzRqiYaUOkkC9VjOPVYWn3caGMCW2Yy8ltlL9OjUuFbLZJWH4k+QyFquq4NOfjZ00 vQCziCay2g== Received: by mx.zohomail.com with SMTPS id 1758443814250482.2030454290558; Sun, 21 Sep 2025 01:36:54 -0700 (PDT) From: Icenowy Zheng To: Maarten Lankhorst , Maxime Ripard , Thomas Zimmermann , David Airlie , Simona Vetter , Rob Herring , Krzysztof Kozlowski , Conor Dooley , Drew Fustini , Guo Ren , Fu Wei , Philipp Zabel , Heiko Stuebner , Andrzej Hajda , Neil Armstrong , Robert Foss , Laurent Pinchart , Jonas Karlman , Jernej Skrabec , Michal Wilczynski Cc: Han Gao , Yao Zi , dri-devel@lists.freedesktop.org, devicetree@vger.kernel.org, linux-kernel@vger.kernel.org, linux-riscv@lists.infradead.org, Icenowy Zheng Subject: [PATCH v2 7/8] riscv: dts: thead: lichee-pi-4a: enable HDMI Date: Sun, 21 Sep 2025 16:34:45 +0800 Message-ID: <20250921083446.790374-8-uwu@icenowy.me> X-Mailer: git-send-email 2.51.0 In-Reply-To: <20250921083446.790374-1-uwu@icenowy.me> References: <20250921083446.790374-1-uwu@icenowy.me> Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable X-ZohoMailClient: External Content-Type: text/plain; charset="utf-8" Lichee Pi 4A board features a HDMI Type-A connector connected to the HDMI TX controller of TH1520 SoC. Add a device tree node describing the connector, connect it to the HDMI controller, and enable everything on this display pipeline. Signed-off-by: Icenowy Zheng --- No changes in v2. .../boot/dts/thead/th1520-lichee-pi-4a.dts | 25 +++++++++++++++++++ 1 file changed, 25 insertions(+) diff --git a/arch/riscv/boot/dts/thead/th1520-lichee-pi-4a.dts b/arch/riscv= /boot/dts/thead/th1520-lichee-pi-4a.dts index 4020c727f09e8..3e99f905dc316 100644 --- a/arch/riscv/boot/dts/thead/th1520-lichee-pi-4a.dts +++ b/arch/riscv/boot/dts/thead/th1520-lichee-pi-4a.dts @@ -28,6 +28,17 @@ aliases { chosen { stdout-path =3D "serial0:115200n8"; }; + + hdmi-connector { + compatible =3D "hdmi-connector"; + type =3D "a"; + + port { + hdmi_con_in: endpoint { + remote-endpoint =3D <&hdmi_out_con>; + }; + }; + }; }; =20 &padctrl0_apsys { @@ -54,6 +65,20 @@ rx-pins { }; }; =20 +&dpu { + status =3D "okay"; +}; + +&hdmi { + status =3D "okay"; +}; + +&hdmi_out_port { + hdmi_out_con: endpoint { + remote-endpoint =3D <&hdmi_con_in>; + }; +}; + &uart0 { pinctrl-names =3D "default"; pinctrl-0 =3D <&uart0_pins>; --=20 2.51.0 From nobody Thu Oct 2 06:19:41 2025 Received: from sender4-op-o15.zoho.com (sender4-op-o15.zoho.com [136.143.188.15]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id 6DA851684A4; Sun, 21 Sep 2025 08:37:48 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=pass smtp.client-ip=136.143.188.15 ARC-Seal: i=2; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1758443870; cv=pass; b=YJlbt0tz2dsE+ak/v1QuPRoKoXRVGDBw88DD4Ba4denLb6u3fnWsRG6EVLTzKiYphAB9OxrpxARI/3pzdHfHRJ7eTrwf0KtjJsiArFDqBzhaN64t7+77uqcs5YAWfx6E4ArM4ySCsCpZCZP4wYPPBRxsUbB7r5X4xQfV4Tm1fc8= ARC-Message-Signature: i=2; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1758443870; c=relaxed/simple; bh=5Nz/aipbqPUv+GhHEM/dv1l3XjiTL0M4qlO2ONrekqA=; h=From:To:Cc:Subject:Date:Message-ID:In-Reply-To:References: MIME-Version; b=s+6NjbH8xuRHypzBwYUUE74rwXXa8G/YTf5Yh396E0WJEk1hDMJmvWA6+c9BwsFVDG83nO6e5+lYpzXp/A4pb8ff1SZ7TYGP4mkllFmYNBc0YtXBjdiolBkw5iAREg+/quEePUfk30aVe4Mqyp8eO4swYMv9hM1RS54zUn4Ic1I= ARC-Authentication-Results: i=2; smtp.subspace.kernel.org; dmarc=pass (p=none dis=none) header.from=icenowy.me; spf=pass smtp.mailfrom=icenowy.me; dkim=pass (2048-bit key) header.d=icenowy.me header.i=uwu@icenowy.me header.b=NesjRj/g; arc=pass smtp.client-ip=136.143.188.15 Authentication-Results: smtp.subspace.kernel.org; dmarc=pass (p=none dis=none) header.from=icenowy.me Authentication-Results: smtp.subspace.kernel.org; spf=pass smtp.mailfrom=icenowy.me Authentication-Results: smtp.subspace.kernel.org; dkim=pass (2048-bit key) header.d=icenowy.me header.i=uwu@icenowy.me header.b="NesjRj/g" ARC-Seal: i=1; a=rsa-sha256; t=1758443829; cv=none; d=zohomail.com; s=zohoarc; b=WurbZSMAucWJMG9KteVgGhWwjgsyMgg8B/RMRKCiOq4+ILUxejB4ENCxMgKzGGoRwVfoWdftOgYd0VI1RXqLbRMRUv3qJ6NbecpPzFCdusyihpMlysxPY58P5LP+1mPT9vsfGHF7XA29xkIijPeewvnLxVa0D5R7Krt4b7XQVWc= ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=zohomail.com; s=zohoarc; t=1758443829; h=Content-Transfer-Encoding:Cc:Cc:Date:Date:From:From:In-Reply-To:MIME-Version:Message-ID:References:Subject:Subject:To:To:Message-Id:Reply-To; bh=BISvAyyTH0h3AbD1RfOd4M5Y4uTH6JugxkSpXzZ0EJk=; b=Gz9qkt6gLx3oicvXY8PaoTrk1u3+OW5VKy0fwj00pDFDKDSp54BEGZV2Zn3gV0rGMcULDZPkHN79ul9PQ7e6CN7dvn1T+ARbcO7uyYYBtASR4IZ6QR/pF3EcuP34/kgKzJ3tkujcL2xnn+Cxjz20xwnwhs+JtAjmwHpnbrEVA6c= ARC-Authentication-Results: i=1; mx.zohomail.com; dkim=pass header.i=icenowy.me; spf=pass smtp.mailfrom=uwu@icenowy.me; dmarc=pass header.from= DKIM-Signature: v=1; a=rsa-sha256; q=dns/txt; c=relaxed/relaxed; t=1758443829; s=zmail2; d=icenowy.me; i=uwu@icenowy.me; h=From:From:To:To:Cc:Cc:Subject:Subject:Date:Date:Message-ID:In-Reply-To:References:MIME-Version:Content-Transfer-Encoding:Message-Id:Reply-To; bh=BISvAyyTH0h3AbD1RfOd4M5Y4uTH6JugxkSpXzZ0EJk=; b=NesjRj/gNsGIUHJsHrhk9FMhNcV6WFDxKodILy/mkysSawpiQoHD0BcvUZFirAqj W1bkUEvwT6guxuK9RsNZwzlnvJMjS+WUJLqdAHgDgAZ4OSpxlF+/FmRkplGqFbPiQAU F83Qw+GcnLFTIAPvSBFltLi2bbhRm+7uyHlfC3bRv9Ukv00C3Cg+JtIjtKwAWsU+aqu moJUPBSOdhvVUIIKddh114MtxmRWBVgJHNMpoC8POj2xMhdNg8Eeq72ykyxzmC/BXgZ fDZdruXoXrh8qI85XZyRWceMW7KXt5y9LUTcy+/AFOKUBdVWjZ4nXTDQsZX3/IWU6lN VJepNihaqw== Received: by mx.zohomail.com with SMTPS id 1758443826199803.7477831973885; Sun, 21 Sep 2025 01:37:06 -0700 (PDT) From: Icenowy Zheng To: Maarten Lankhorst , Maxime Ripard , Thomas Zimmermann , David Airlie , Simona Vetter , Rob Herring , Krzysztof Kozlowski , Conor Dooley , Drew Fustini , Guo Ren , Fu Wei , Philipp Zabel , Heiko Stuebner , Andrzej Hajda , Neil Armstrong , Robert Foss , Laurent Pinchart , Jonas Karlman , Jernej Skrabec , Michal Wilczynski Cc: Han Gao , Yao Zi , dri-devel@lists.freedesktop.org, devicetree@vger.kernel.org, linux-kernel@vger.kernel.org, linux-riscv@lists.infradead.org, Icenowy Zheng Subject: [PATCH v2 8/8] MAINTAINERS: assign myself as maintainer for verisilicon DC driver Date: Sun, 21 Sep 2025 16:34:46 +0800 Message-ID: <20250921083446.790374-9-uwu@icenowy.me> X-Mailer: git-send-email 2.51.0 In-Reply-To: <20250921083446.790374-1-uwu@icenowy.me> References: <20250921083446.790374-1-uwu@icenowy.me> Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable X-ZohoMailClient: External Content-Type: text/plain; charset="utf-8" As I am the author of this rewritten driver, it makes sense for me to be the maintainer. Confirm this in MAINTAINERS file. Signed-off-by: Icenowy Zheng --- No changes in v2. MAINTAINERS | 7 +++++++ 1 file changed, 7 insertions(+) diff --git a/MAINTAINERS b/MAINTAINERS index 98af9dd3664f5..348caaaa929a5 100644 --- a/MAINTAINERS +++ b/MAINTAINERS @@ -8393,6 +8393,13 @@ F: Documentation/devicetree/bindings/display/brcm,bc= m2835-*.yaml F: drivers/gpu/drm/vc4/ F: include/uapi/drm/vc4_drm.h =20 +DRM DRIVERS FOR VERISILICON DISPLAY CONTROLLER IP +M: Icenowy Zheng +L: dri-devel@lists.freedesktop.org +S: Maintained +F: Documentation/devicetree/bindings/display/verisilicon,dc.yaml +F: drivers/gpu/drm/verisilicon/ + DRM DRIVERS FOR VIVANTE GPU IP M: Lucas Stach R: Russell King --=20 2.51.0