From nobody Thu Oct 2 06:16:43 2025 Received: from mailgw01.mediatek.com (unknown [60.244.123.138]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id 085FE221F26 for ; Sun, 21 Sep 2025 05:55:07 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=none smtp.client-ip=60.244.123.138 ARC-Seal: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1758434110; cv=none; b=ngnSNBate6oNwb8vLPp146cIzan/GcNfg4fbE317djuE5PkYN1RfnC9qkHwYnfLV4RzU57RQEhDZJ9gi3MjhoSa0hYyf7iUymXpFAiz8sKV50C6NjARoPHTGbj8xyWZ0pDGqfrxCsOwUJtikIAThpLvuRMTWKtb4Hq1VX0CZ9Pg= ARC-Message-Signature: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1758434110; c=relaxed/simple; bh=0b7r3I02uePqzH5che42p3vt1NbPMHfs3HQiYSgdSV4=; h=From:To:CC:Subject:Date:Message-ID:In-Reply-To:References: MIME-Version:Content-Type; b=rJD9Js6UPlT/Zn4yug0yPCjBc5Nbv9RMx1+CZK2GZV/T7WpocwVM58qYLcrr8fXwvksKxrurS/dInsxiNVof15NXs9qHBB2KdykQ8+KKV24coBlY6IL0zp5GGCM9tTxFJYY8JVtwXSS2/H0aTg6oIcF2KrXPFI3dLdl61Da6IWI= ARC-Authentication-Results: i=1; smtp.subspace.kernel.org; dmarc=pass (p=quarantine dis=none) header.from=mediatek.com; spf=pass smtp.mailfrom=mediatek.com; dkim=pass (1024-bit key) header.d=mediatek.com header.i=@mediatek.com header.b=LC3s9qsu; arc=none smtp.client-ip=60.244.123.138 Authentication-Results: smtp.subspace.kernel.org; dmarc=pass (p=quarantine dis=none) header.from=mediatek.com Authentication-Results: smtp.subspace.kernel.org; spf=pass smtp.mailfrom=mediatek.com Authentication-Results: smtp.subspace.kernel.org; dkim=pass (1024-bit key) header.d=mediatek.com header.i=@mediatek.com header.b="LC3s9qsu" X-UUID: 8394c33296af11f08d9e1119e76e3a28-20250921 DKIM-Signature: v=1; a=rsa-sha256; q=dns/txt; c=relaxed/relaxed; d=mediatek.com; s=dk; h=Content-Type:Content-Transfer-Encoding:MIME-Version:References:In-Reply-To:Message-ID:Date:Subject:CC:To:From; bh=QX86LULi1lNCUxDv79hdC2i0nPDCwie71771w9KqkA0=; b=LC3s9qsucNtxIkjLiP5W9fujUiDdmEfUaoiQAuSTjcxSGz4ewRj7EZbLQySqDB9Ox1seQRcqsB1E/WMp+IEALJ5UzBB91qzeoBwnCUW9TnqYX7M04kKOzGk+PSdsqHqWkBq6nvvMVv0aMJEhRQymQF1pfll5Wq+t43AaBB4Wu7E=; X-CID-P-RULE: Release_Ham X-CID-O-INFO: VERSION:1.3.4,REQID:0200a29a-2309-4da4-ad39-bfc54faae7de,IP:0,UR L:0,TC:0,Content:0,EDM:-25,RT:0,SF:0,FILE:0,BULK:0,RULE:Release_Ham,ACTION :release,TS:-25 X-CID-META: VersionHash:1ca6b93,CLOUDID:0d612d91-68e1-4022-b848-86f5c49a6751,B ulkID:nil,BulkQuantity:0,Recheck:0,SF:81|82|102|836|888|898,TC:-5,Content: 0|15|50,EDM:1,IP:nil,URL:0,File:nil,RT:nil,Bulk:nil,QS:nil,BEC:nil,COL:0,O SI:0,OSA:0,AV:0,LES:1,SPR:NO,DKR:0,DKP:0,BRR:0,BRE:0,ARC:0 X-CID-BVR: 2,SSN|SDN X-CID-BAS: 2,SSN|SDN,0,_ X-CID-FACTOR: TF_CID_SPAM_SNR X-CID-RHF: D41D8CD98F00B204E9800998ECF8427E X-UUID: 8394c33296af11f08d9e1119e76e3a28-20250921 Received: from mtkmbs10n1.mediatek.inc [(172.21.101.34)] by mailgw01.mediatek.com (envelope-from ) (Generic MTA with TLSv1.2 ECDHE-RSA-AES256-GCM-SHA384 256/256) with ESMTP id 1598463930; Sun, 21 Sep 2025 13:55:01 +0800 Received: from mtkmbs13n2.mediatek.inc (172.21.101.108) by mtkmbs13n1.mediatek.inc (172.21.101.193) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_256_GCM_SHA384) id 15.2.1748.10; Sun, 21 Sep 2025 13:55:00 +0800 Received: from mhfsdcap04.gcn.mediatek.inc (10.17.3.154) by mtkmbs13n2.mediatek.inc (172.21.101.73) with Microsoft SMTP Server id 15.2.1748.10 via Frontend Transport; Sun, 21 Sep 2025 13:55:00 +0800 From: Jay Liu To: Chun-Kuang Hu , Philipp Zabel , David Airlie , Simona Vetter , Matthias Brugger , AngeloGioacchino Del Regno , Yongqiang Niu , CK Hu , Hsin-Yi Wang CC: , , , , Jay Liu Subject: [PATCH v1 1/1] drm/mediatek: fix CCORR mtk_ctm_s31_32_to_s1_n function issue Date: Sun, 21 Sep 2025 13:53:05 +0800 Message-ID: <20250921055416.25588-2-jay.liu@mediatek.com> X-Mailer: git-send-email 2.46.0 In-Reply-To: <20250921055416.25588-1-jay.liu@mediatek.com> References: <20250921055416.25588-1-jay.liu@mediatek.com> Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Content-Type: text/plain; charset="utf-8" if matrixbit is 11, The range of color matrix is from 0 to (BIT(12) - 1). Values from 0 to (BIT(11) - 1) represent positive numbers, values from BIT(11) to (BIT(12) - 1) represent negative numbers. For example, -1 need converted to 8191. so convert S31.32 to HW Q2.11 format by drm_color_ctm_s31_32_to_qm_n, and set int_bits to 2. Fixes: 738ed4156fba ("drm/mediatek: Add matrix_bits private data for ccorr") Change-Id: Icb2aae1dee21d9ea34f263a54850fee26d97d455 Reviewed-by: AngeloGioacchino Del Regno Signed-off-by: Jay Liu --- drivers/gpu/drm/mediatek/mtk_disp_ccorr.c | 26 +++-------------------- 1 file changed, 3 insertions(+), 23 deletions(-) diff --git a/drivers/gpu/drm/mediatek/mtk_disp_ccorr.c b/drivers/gpu/drm/me= diatek/mtk_disp_ccorr.c index 10d60d2c2a56..634b31346921 100644 --- a/drivers/gpu/drm/mediatek/mtk_disp_ccorr.c +++ b/drivers/gpu/drm/mediatek/mtk_disp_ccorr.c @@ -80,28 +80,7 @@ void mtk_ccorr_stop(struct device *dev) writel_relaxed(0x0, ccorr->regs + DISP_CCORR_EN); } =20 -/* Converts a DRM S31.32 value to the HW S1.n format. */ -static u16 mtk_ctm_s31_32_to_s1_n(u64 in, u32 n) -{ - u16 r; - - /* Sign bit. */ - r =3D in & BIT_ULL(63) ? BIT(n + 1) : 0; - - if ((in & GENMASK_ULL(62, 33)) > 0) { - /* identity value 0x100000000 -> 0x400(mt8183), */ - /* identity value 0x100000000 -> 0x800(mt8192), */ - /* if bigger this, set it to max 0x7ff. */ - r |=3D GENMASK(n, 0); - } else { - /* take the n+1 most important bits. */ - r |=3D (in >> (32 - n)) & GENMASK(n, 0); - } - - return r; -} - -void mtk_ccorr_ctm_set(struct device *dev, struct drm_crtc_state *state) +bool mtk_ccorr_ctm_set(struct device *dev, struct drm_crtc_state *state) { struct mtk_disp_ccorr *ccorr =3D dev_get_drvdata(dev); struct drm_property_blob *blob =3D state->ctm; @@ -109,6 +88,7 @@ void mtk_ccorr_ctm_set(struct device *dev, struct drm_cr= tc_state *state) const u64 *input; uint16_t coeffs[9] =3D { 0 }; int i; + int int_bits =3D 2; struct cmdq_pkt *cmdq_pkt =3D NULL; u32 matrix_bits =3D ccorr->data->matrix_bits; =20 @@ -119,7 +99,7 @@ void mtk_ccorr_ctm_set(struct device *dev, struct drm_cr= tc_state *state) input =3D ctm->matrix; =20 for (i =3D 0; i < ARRAY_SIZE(coeffs); i++) - coeffs[i] =3D mtk_ctm_s31_32_to_s1_n(input[i], matrix_bits); + coeffs[i] =3D drm_color_ctm_s31_32_to_qm_n(input[i], int_bits, matrix_bi= ts); =20 mtk_ddp_write(cmdq_pkt, coeffs[0] << 16 | coeffs[1], &ccorr->cmdq_reg, ccorr->regs, DISP_CCORR_COEF_0); --=20 2.46.0