From nobody Thu Oct 2 06:14:37 2025 Received: from smtp.kernel.org (aws-us-west-2-korg-mail-1.web.codeaurora.org [10.30.226.201]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id 69DFB8F5B; Sun, 21 Sep 2025 11:04:09 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=none smtp.client-ip=10.30.226.201 ARC-Seal: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1758452649; cv=none; b=e+2wzWn1k6kowYkHUgAQYZ8X0s4AOCUs+lH59hogVLomi/RlTDeOlAFOAma2jQINiqMmtlofiCoGxAE/h1onH0eJAMwHwcVzlYW+KwQI5tfjG7DXrQtf3VZl4BBqWbZY6l682zK2WYbSOwOLW/E8/Rs7jKTNlqq4GAONNr1MdTg= ARC-Message-Signature: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1758452649; c=relaxed/simple; bh=qZbUvkV3I4SIv7OEUq7HXI4u9eGtm6gZMNg1T88s4O4=; h=From:Date:Subject:MIME-Version:Content-Type:Message-Id:References: In-Reply-To:To:Cc; b=s88ap6NCOL10eODmKuIMqH2Da28JYuqlzPTSifTHk9QxpyScd/iODMEIEsSEYhA4QuoNeGleeHd67FbvrjnV3djVZQCwscNjxYTZWZxBXyxBFtoe2WCW1SEMilfvp+jDZ/fR2PsDzfBeqKVoXV55o38gawr5l+EySEuNUGGEjQw= ARC-Authentication-Results: i=1; smtp.subspace.kernel.org; dkim=pass (2048-bit key) header.d=kernel.org header.i=@kernel.org header.b=mxPSD9yu; arc=none smtp.client-ip=10.30.226.201 Authentication-Results: smtp.subspace.kernel.org; dkim=pass (2048-bit key) header.d=kernel.org header.i=@kernel.org header.b="mxPSD9yu" Received: by smtp.kernel.org (Postfix) with ESMTPS id 11332C113D0; Sun, 21 Sep 2025 11:04:09 +0000 (UTC) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=kernel.org; s=k20201202; t=1758452649; bh=qZbUvkV3I4SIv7OEUq7HXI4u9eGtm6gZMNg1T88s4O4=; h=From:Date:Subject:References:In-Reply-To:To:Cc:Reply-To:From; b=mxPSD9yuN4VkI3XvPm6joul3OHUgxWhxFiAwPiYFVpf73ekd7v76P/MvQcRV4Q6gO v9nj6kYaTHwiQC0kT30tKhEwAQ0Yk2b99NuvwtrOe12EoomB9ww4PUwLzThWAPYUh9 lFg0fIUktkCAERlPUjEHiaFm4X9wg0AioWJ/PyqTJfP5TmjbPnRk1EIXwTJIoBTEn7 QCh2H57CmcXFurQUVC9lFJiVxH98EgkURes4T9AbJS4hAXoKUovPgm9UIld64hKyHV 38Zfm+FD0XCXtY4ACezhPd4BYh32i2l+1/4YrG9v81C0/i948xsZH38ZYsmUngfCt0 +aBCzqBFOliNQ== Received: from aws-us-west-2-korg-lkml-1.web.codeaurora.org (localhost.localdomain [127.0.0.1]) by smtp.lore.kernel.org (Postfix) with ESMTP id 00F66CAC5A7; Sun, 21 Sep 2025 11:04:09 +0000 (UTC) From: Max Shevchenko via B4 Relay Date: Sun, 21 Sep 2025 14:03:40 +0300 Subject: [PATCH 1/3] dt-bindings: dma: mediatek,uart-dma: drop mediatek,dma-33bits property Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Content-Transfer-Encoding: quoted-printable Message-Id: <20250921-uart-apdma-v1-1-107543c7102c@proton.me> References: <20250921-uart-apdma-v1-0-107543c7102c@proton.me> In-Reply-To: <20250921-uart-apdma-v1-0-107543c7102c@proton.me> To: Sean Wang , Vinod Koul , Rob Herring , Krzysztof Kozlowski , Conor Dooley , Matthias Brugger , AngeloGioacchino Del Regno , Long Cheng Cc: dmaengine@vger.kernel.org, linux-arm-kernel@lists.infradead.org, linux-mediatek@lists.infradead.org, devicetree@vger.kernel.org, linux-kernel@vger.kernel.org, Max Shevchenko X-Mailer: b4 0.14.2 X-Developer-Signature: v=1; a=ed25519-sha256; t=1758452646; l=1846; i=wctrl@proton.me; s=20250603; h=from:subject:message-id; bh=TB4BCx1QYYV4SmqIa8ENnGfC/AB4i29OQtOF7WQHovg=; b=I3qa4PxpaBPKoU6fi7fhLxPcD3csXcw7CPfWSXpq7UuMv9OoZ9NtUPgrB3r4Fe5nltPitCZXj UCi2HFiDvpIDS0qTK6ZmeNqloia69Lkev+R2nCbnT8xCU05mNgjYFlI X-Developer-Key: i=wctrl@proton.me; a=ed25519; pk=JXUx3mL/OrnRvbK57HXgugBjEBKq4QgDKJqp7BALm74= X-Endpoint-Received: by B4 Relay for wctrl@proton.me/20250603 with auth_id=421 X-Original-From: Max Shevchenko Reply-To: wctrl@proton.me From: Max Shevchenko Many newer SoCs support more than 33 bits for DMA. Drop the property in order to switch to the platform data. The reference SoCs were taken from the downstream kernel (6.6) for the MT6991 SoC. Signed-off-by: Max Shevchenko --- Documentation/devicetree/bindings/dma/mediatek,uart-dma.yaml | 11 ++++----= --- 1 file changed, 4 insertions(+), 7 deletions(-) diff --git a/Documentation/devicetree/bindings/dma/mediatek,uart-dma.yaml b= /Documentation/devicetree/bindings/dma/mediatek,uart-dma.yaml index dab468a88942d694525aa391f695c44d192f0c42..9dfdfe81af7edbe3540e4b75754= 7a5d5e6ae810c 100644 --- a/Documentation/devicetree/bindings/dma/mediatek,uart-dma.yaml +++ b/Documentation/devicetree/bindings/dma/mediatek,uart-dma.yaml @@ -22,12 +22,14 @@ properties: - items: - enum: - mediatek,mt2712-uart-dma - - mediatek,mt6795-uart-dma - mediatek,mt8365-uart-dma - mediatek,mt8516-uart-dma - const: mediatek,mt6577-uart-dma - enum: - - mediatek,mt6577-uart-dma + - mediatek,mt6577-uart-dma # 32 bits + - mediatek,mt6795-uart-dma # 33 bits + - mediatek,mt6779-uart-dma # 34 bits + - mediatek,mt6985-uart-dma # 35 bits =20 reg: minItems: 1 @@ -56,10 +58,6 @@ properties: Number of virtual channels of the UART APDMA controller maximum: 16 =20 - mediatek,dma-33bits: - type: boolean - description: Enable 33-bits UART APDMA support - required: - compatible - reg @@ -116,7 +114,6 @@ examples: dma-requests =3D <12>; clocks =3D <&pericfg CLK_PERI_AP_DMA>; clock-names =3D "apdma"; - mediatek,dma-33bits; #dma-cells =3D <1>; }; }; --=20 2.51.0 From nobody Thu Oct 2 06:14:37 2025 Received: from smtp.kernel.org (aws-us-west-2-korg-mail-1.web.codeaurora.org [10.30.226.201]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id 8B40D22069E; Sun, 21 Sep 2025 11:04:09 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=none smtp.client-ip=10.30.226.201 ARC-Seal: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1758452649; cv=none; b=RczfmRkwAJIRflynTc3j2gS9kvRoaIJJZe3xALTSniXfBf4y2zbQEvZozsyalkwe/Mjz6lV1zz9eCwFhv/ZsBlfqbRjqx6Q6JaDlf5GT5sZmKOTLr+LD+lAuPMRxUyHrhD13v2AQUidYe2tUE3AFqmQ7ODZrhCxTFyfA3/hF3wM= ARC-Message-Signature: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1758452649; c=relaxed/simple; bh=ZwpRe43I5VpGo3wIi+bC13qk5rK8A78m5VM7bKe4ulc=; h=From:Date:Subject:MIME-Version:Content-Type:Message-Id:References: In-Reply-To:To:Cc; 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Sun, 21 Sep 2025 11:04:09 +0000 (UTC) From: Max Shevchenko via B4 Relay Date: Sun, 21 Sep 2025 14:03:41 +0300 Subject: [PATCH 2/3] dmaengine: mediatek: mtk-uart-apdma: support more than 33 bits for DMA bitmask Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Content-Transfer-Encoding: quoted-printable Message-Id: <20250921-uart-apdma-v1-2-107543c7102c@proton.me> References: <20250921-uart-apdma-v1-0-107543c7102c@proton.me> In-Reply-To: <20250921-uart-apdma-v1-0-107543c7102c@proton.me> To: Sean Wang , Vinod Koul , Rob Herring , Krzysztof Kozlowski , Conor Dooley , Matthias Brugger , AngeloGioacchino Del Regno , Long Cheng Cc: dmaengine@vger.kernel.org, linux-arm-kernel@lists.infradead.org, linux-mediatek@lists.infradead.org, devicetree@vger.kernel.org, linux-kernel@vger.kernel.org, Max Shevchenko X-Mailer: b4 0.14.2 X-Developer-Signature: v=1; a=ed25519-sha256; t=1758452646; l=3836; i=wctrl@proton.me; s=20250603; h=from:subject:message-id; bh=UkczX1bFRaMGp10NOd3W6tGmV9gfRhg9tG4OjCZWL14=; b=yoy3rBto0yqvXKa2q7FupadhIQI8nEqoZjvnx8zEMbQXPCJAOktpJ8D7shhNd0fbp7vjXI4c/ vPHxZcPP8B7A4ETjyPXHjVu6xtFMXg7Je3j5ekWJej3OjSJdyJiXg55 X-Developer-Key: i=wctrl@proton.me; a=ed25519; pk=JXUx3mL/OrnRvbK57HXgugBjEBKq4QgDKJqp7BALm74= X-Endpoint-Received: by B4 Relay for wctrl@proton.me/20250603 with auth_id=421 X-Original-From: Max Shevchenko Reply-To: wctrl@proton.me From: Max Shevchenko Drop mediatek,dma-33bits property and introduce a platform data with field representing DMA bitmask. The reference SoCs were taken from the downstream kernel (6.6) for the MT6991 SoC. Signed-off-by: Max Shevchenko --- drivers/dma/mediatek/mtk-uart-apdma.c | 47 +++++++++++++++++++++++++------= ---- 1 file changed, 34 insertions(+), 13 deletions(-) diff --git a/drivers/dma/mediatek/mtk-uart-apdma.c b/drivers/dma/mediatek/m= tk-uart-apdma.c index 08e15177427b94246951d38a2a1d76875c1e452e..68dd3a4ee0d88fd508870a5de24= ae67505023495 100644 --- a/drivers/dma/mediatek/mtk-uart-apdma.c +++ b/drivers/dma/mediatek/mtk-uart-apdma.c @@ -42,6 +42,7 @@ #define VFF_EN_CLR_B 0 #define VFF_INT_EN_CLR_B 0 #define VFF_4G_SUPPORT_CLR_B 0 +#define VFF_ORI_ADDR_BITS_NUM 32 =20 /* * interrupt trigger level for tx @@ -74,10 +75,14 @@ #define VFF_DEBUG_STATUS 0x50 #define VFF_4G_SUPPORT 0x54 =20 +struct mtk_uart_apdma_data { + unsigned int dma_bits; +}; + struct mtk_uart_apdmadev { struct dma_device ddev; struct clk *clk; - bool support_33bits; + unsigned int support_bits; unsigned int dma_requests; }; =20 @@ -148,7 +153,7 @@ static void mtk_uart_apdma_start_tx(struct mtk_chan *c) mtk_uart_apdma_write(c, VFF_WPT, 0); mtk_uart_apdma_write(c, VFF_INT_FLAG, VFF_TX_INT_CLR_B); =20 - if (mtkd->support_33bits) + if (mtkd->support_bits > VFF_ORI_ADDR_BITS_NUM) mtk_uart_apdma_write(c, VFF_4G_SUPPORT, VFF_4G_EN_B); } =20 @@ -191,7 +196,7 @@ static void mtk_uart_apdma_start_rx(struct mtk_chan *c) mtk_uart_apdma_write(c, VFF_RPT, 0); mtk_uart_apdma_write(c, VFF_INT_FLAG, VFF_RX_INT_CLR_B); =20 - if (mtkd->support_33bits) + if (mtkd->support_bits > VFF_ORI_ADDR_BITS_NUM) mtk_uart_apdma_write(c, VFF_4G_SUPPORT, VFF_4G_EN_B); } =20 @@ -297,7 +302,7 @@ static int mtk_uart_apdma_alloc_chan_resources(struct d= ma_chan *chan) goto err_pm; } =20 - if (mtkd->support_33bits) + if (mtkd->support_bits > VFF_ORI_ADDR_BITS_NUM) mtk_uart_apdma_write(c, VFF_4G_SUPPORT, VFF_4G_SUPPORT_CLR_B); =20 err_pm: @@ -467,8 +472,27 @@ static void mtk_uart_apdma_free(struct mtk_uart_apdmad= ev *mtkd) } } =20 +static const struct mtk_uart_apdma_data mt6577_data =3D { + .dma_bits =3D 32 +}; + +static const struct mtk_uart_apdma_data mt6795_data =3D { + .dma_bits =3D 33 +}; + +static const struct mtk_uart_apdma_data mt6779_data =3D { + .dma_bits =3D 34 +}; + +static const struct mtk_uart_apdma_data mt6985_data =3D { + .dma_bits =3D 35 +}; + static const struct of_device_id mtk_uart_apdma_match[] =3D { - { .compatible =3D "mediatek,mt6577-uart-dma", }, + { .compatible =3D "mediatek,mt6577-uart-dma", .data =3D &mt6577_data }, + { .compatible =3D "mediatek,mt6795-uart-dma", .data =3D &mt6795_data }, + { .compatible =3D "mediatek,mt6779-uart-dma", .data =3D &mt6779_data }, + { .compatible =3D "mediatek,mt6985-uart-dma", .data =3D &mt6985_data }, { /* sentinel */ }, }; MODULE_DEVICE_TABLE(of, mtk_uart_apdma_match); @@ -477,7 +501,8 @@ static int mtk_uart_apdma_probe(struct platform_device = *pdev) { struct device_node *np =3D pdev->dev.of_node; struct mtk_uart_apdmadev *mtkd; - int bit_mask =3D 32, rc; + const struct mtk_uart_apdma_data *data; + int rc; struct mtk_chan *c; unsigned int i; =20 @@ -492,13 +517,9 @@ static int mtk_uart_apdma_probe(struct platform_device= *pdev) return rc; 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b=t56+27g4EaW8nnlv1PZ3Su58UPdFiDAuie2uyPMxsjoXMsAHjpTucLIK9bOBDIqh+ hOPhXrFJXSbC0efVuWfAWR7eXSVgn67VtYEq4GaYEOdqqVSc8c1TlF9PpvtqJjpJMc 49cqXUyZX9RNUC/qsFCCRLZZQJFyzxUPu2DV0EemhUDp8T9fjmCvMfoip0kyF63n1c iGGIXaXAE6vsAA7nrSz2sLhAN48GmTAXyvdWHH6u+VR/UOIK8DxcfxBKpAKeWmPSx8 A+5+VOKGv0ND8GwvuonbgB6E2H4ASAWv/YpmuljOY06Kr/bP7jPZTlQWlUJmHpPF/I y9/Ti4RN2hUVQ== Received: from aws-us-west-2-korg-lkml-1.web.codeaurora.org (localhost.localdomain [127.0.0.1]) by smtp.lore.kernel.org (Postfix) with ESMTP id 1C82ACAC5A8; Sun, 21 Sep 2025 11:04:09 +0000 (UTC) From: Max Shevchenko via B4 Relay Date: Sun, 21 Sep 2025 14:03:42 +0300 Subject: [PATCH 3/3] arm64: dts: mediatek: mt6795: drop mediatek,dma-33bits property Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Content-Transfer-Encoding: quoted-printable Message-Id: <20250921-uart-apdma-v1-3-107543c7102c@proton.me> References: <20250921-uart-apdma-v1-0-107543c7102c@proton.me> In-Reply-To: <20250921-uart-apdma-v1-0-107543c7102c@proton.me> To: Sean Wang , Vinod Koul , Rob Herring , Krzysztof Kozlowski , Conor Dooley , Matthias Brugger , AngeloGioacchino Del Regno , Long Cheng Cc: dmaengine@vger.kernel.org, linux-arm-kernel@lists.infradead.org, linux-mediatek@lists.infradead.org, devicetree@vger.kernel.org, linux-kernel@vger.kernel.org, Max Shevchenko X-Mailer: b4 0.14.2 X-Developer-Signature: v=1; a=ed25519-sha256; t=1758452646; l=1089; i=wctrl@proton.me; s=20250603; h=from:subject:message-id; bh=efNh38U+hbw7SE9tyV1qJBxX+aihILQofpcGc0kC/ts=; b=P2Den4CzqXR4nni1RZlcgJUrU+BdnDEx6nZid1RneZyCMn5h8Mysh1cY8Rig6oOMQpbLsXBdS golrZUGOoSGA2ZCKjBqltNqDh1rkr621J5L7bYeinB8Sw0aZmqZIF3B X-Developer-Key: i=wctrl@proton.me; a=ed25519; pk=JXUx3mL/OrnRvbK57HXgugBjEBKq4QgDKJqp7BALm74= X-Endpoint-Received: by B4 Relay for wctrl@proton.me/20250603 with auth_id=421 X-Original-From: Max Shevchenko Reply-To: wctrl@proton.me From: Max Shevchenko Drop the mediatek,dma-33bits property and use compatible for the platform data instead. Signed-off-by: Max Shevchenko --- arch/arm64/boot/dts/mediatek/mt6795.dtsi | 4 +--- 1 file changed, 1 insertion(+), 3 deletions(-) diff --git a/arch/arm64/boot/dts/mediatek/mt6795.dtsi b/arch/arm64/boot/dts= /mediatek/mt6795.dtsi index e5e269a660b11b0e94da1a1cf362ff0839f0dabf..5123316b21285cf589c0c616c0a= 12420f0b1ef19 100644 --- a/arch/arm64/boot/dts/mediatek/mt6795.dtsi +++ b/arch/arm64/boot/dts/mediatek/mt6795.dtsi @@ -547,8 +547,7 @@ uart1: serial@11003000 { }; =20 apdma: dma-controller@11000380 { - compatible =3D "mediatek,mt6795-uart-dma", - "mediatek,mt6577-uart-dma"; + compatible =3D "mediatek,mt6795-uart-dma"; reg =3D <0 0x11000380 0 0x60>, <0 0x11000400 0 0x60>, <0 0x11000480 0 0x60>, @@ -568,7 +567,6 @@ apdma: dma-controller@11000380 { dma-requests =3D <8>; clocks =3D <&pericfg CLK_PERI_AP_DMA>; clock-names =3D "apdma"; - mediatek,dma-33bits; #dma-cells =3D <1>; }; =20 --=20 2.51.0