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Sun, 21 Sep 2025 03:08:39 +0000 Received: from [172.17.0.2] (unknown [180.253.43.125]) (Authenticated sender: linux@smankusors.com) by smtp.hostinger.com (smtp.hostinger.com) with ESMTPSA id 4cTrlw31XKzHTnH0; Sun, 21 Sep 2025 03:08:12 +0000 (UTC) From: Antony Kurniawan Soemardi Subject: [PATCH v2 4/5] ARM: dts: qcom: msm8960: add I2C nodes for gsbi1 and gsbi8 Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Content-Transfer-Encoding: quoted-printable Message-Id: <20250921-msm8960-reorder-v2-4-26c478366d21@smankusors.com> References: <20250921-msm8960-reorder-v2-0-26c478366d21@smankusors.com> In-Reply-To: <20250921-msm8960-reorder-v2-0-26c478366d21@smankusors.com> To: Bjorn Andersson , Konrad Dybcio , Rob Herring , Krzysztof Kozlowski , Conor Dooley Cc: linux-arm-msm@vger.kernel.org, devicetree@vger.kernel.org, linux-kernel@vger.kernel.org, Antony Kurniawan Soemardi , David Heidelberg , Max Shevchenko , Rudraksha Gupta , Shinjo Park X-Mailer: b4 0.14.2 X-Developer-Signature: v=1; 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The nodes are added disabled by default. Co-developed-by: Shinjo Park Signed-off-by: Shinjo Park Signed-off-by: Antony Kurniawan Soemardi Reviewed-by: Dmitry Baryshkov --- arch/arm/boot/dts/qcom/qcom-msm8960.dtsi | 70 ++++++++++++++++++++++++++++= ++++ 1 file changed, 70 insertions(+) diff --git a/arch/arm/boot/dts/qcom/qcom-msm8960.dtsi b/arch/arm/boot/dts/q= com/qcom-msm8960.dtsi index 890b34bdf8c3376659570218500e28ce5809c26a..0aaf60dcda647dc2f7ce11ae7cd= e05a0bcd35716 100644 --- a/arch/arm/boot/dts/qcom/qcom-msm8960.dtsi +++ b/arch/arm/boot/dts/qcom/qcom-msm8960.dtsi @@ -131,6 +131,24 @@ msmgpio: pinctrl@800000 { interrupt-controller; #interrupt-cells =3D <2>; =20 + i2c1_default_state: i2c1-default-state { + i2c1-pins { + pins =3D "gpio8", "gpio9"; + function =3D "gsbi1"; + drive-strength =3D <8>; + bias-disable; + }; + }; + + i2c1_sleep_state: i2c1-sleep-state { + i2c1-pins { + pins =3D "gpio8", "gpio9"; + function =3D "gpio"; + drive-strength =3D <2>; + bias-bus-hold; + }; + }; + i2c3_default_state: i2c3-default-state { i2c3-pins { pins =3D "gpio16", "gpio17"; @@ -149,6 +167,24 @@ i2c3-pins { }; }; =20 + i2c8_default_state: i2c8-default-state { + i2c8-pins { + pins =3D "gpio36", "gpio37"; + function =3D "gsbi8"; + drive-strength =3D <8>; + bias-disable; + }; + }; + + i2c8_sleep_state: i2c8-sleep-state { + i2c8-pins { + pins =3D "gpio36", "gpio37"; + function =3D "gpio"; + drive-strength =3D <2>; + bias-bus-hold; + }; + }; + i2c10_default_state: i2c10-default-state { i2c10-pins { pins =3D "gpio73", "gpio74"; @@ -474,6 +510,23 @@ gsbi1: gsbi@16000000 { =20 status =3D "disabled"; =20 + gsbi1_i2c: i2c@16080000 { + compatible =3D "qcom,i2c-qup-v1.1.1"; + reg =3D <0x16080000 0x1000>; + pinctrl-0 =3D <&i2c1_default_state>; + pinctrl-1 =3D <&i2c1_sleep_state>; + pinctrl-names =3D "default", "sleep"; + interrupts =3D ; + clocks =3D <&gcc GSBI1_QUP_CLK>, + <&gcc GSBI1_H_CLK>; + clock-names =3D "core", + "iface"; + #address-cells =3D <1>; + #size-cells =3D <0>; + + status =3D "disabled"; + }; + gsbi1_spi: spi@16080000 { compatible =3D "qcom,spi-qup-v1.1.1"; reg =3D <0x16080000 0x1000>; @@ -572,6 +625,23 @@ gsbi8_serial: serial@1a040000 { =20 status =3D "disabled"; }; + + gsbi8_i2c: i2c@1a080000 { + compatible =3D "qcom,i2c-qup-v1.1.1"; + reg =3D <0x1a080000 0x1000>; + pinctrl-0 =3D <&i2c8_default_state>; + pinctrl-1 =3D <&i2c8_sleep_state>; + pinctrl-names =3D "default", "sleep"; + interrupts =3D ; + clocks =3D <&gcc GSBI8_QUP_CLK>, + <&gcc GSBI8_H_CLK>; + clock-names =3D "core", + "iface"; + #address-cells =3D <1>; + #size-cells =3D <0>; + + status =3D "disabled"; + }; }; =20 gsbi10: gsbi@1a200000 { --=20 2.34.1