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Sun, 21 Sep 2025 03:08:10 +0000 Received: from [172.17.0.2] (unknown [180.253.43.125]) (Authenticated sender: linux@smankusors.com) by smtp.hostinger.com (smtp.hostinger.com) with ESMTPSA id 4cTrlk0Xx9zHTq4c; Sun, 21 Sep 2025 03:08:01 +0000 (UTC) From: Antony Kurniawan Soemardi Subject: [PATCH v2 1/5] ARM: dts: qcom: msm8960: reorder nodes and properties Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Content-Transfer-Encoding: quoted-printable Message-Id: <20250921-msm8960-reorder-v2-1-26c478366d21@smankusors.com> References: <20250921-msm8960-reorder-v2-0-26c478366d21@smankusors.com> In-Reply-To: <20250921-msm8960-reorder-v2-0-26c478366d21@smankusors.com> To: Bjorn Andersson , Konrad Dybcio , Rob Herring , Krzysztof Kozlowski , Conor Dooley Cc: linux-arm-msm@vger.kernel.org, devicetree@vger.kernel.org, linux-kernel@vger.kernel.org, Antony Kurniawan Soemardi , David Heidelberg , Max Shevchenko , Rudraksha Gupta , Shinjo Park X-Mailer: b4 0.14.2 X-Developer-Signature: v=1; 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This is a cosmetic change only, with no functional impact. Tested-by: Rudraksha Gupta Tested-by: Shinjo Park Signed-off-by: Antony Kurniawan Soemardi Reviewed-by: Dmitry Baryshkov --- arch/arm/boot/dts/qcom/qcom-msm8960.dtsi | 545 ++++++++++++++++-----------= ---- 1 file changed, 280 insertions(+), 265 deletions(-) diff --git a/arch/arm/boot/dts/qcom/qcom-msm8960.dtsi b/arch/arm/boot/dts/q= com/qcom-msm8960.dtsi index 6e272d5345a85fde706d8666ac0fe6f2d40bcf37..6884f7f5b11889f9b28a2cf6189= 0e50e1b1405dd 100644 --- a/arch/arm/boot/dts/qcom/qcom-msm8960.dtsi +++ b/arch/arm/boot/dts/qcom/qcom-msm8960.dtsi @@ -15,6 +15,35 @@ / { compatible =3D "qcom,msm8960"; interrupt-parent =3D <&intc>; =20 + clocks { + cxo_board: cxo_board { + compatible =3D "fixed-clock"; + #clock-cells =3D <0>; + clock-frequency =3D <19200000>; + clock-output-names =3D "cxo_board"; + }; + + pxo_board: pxo_board { + compatible =3D "fixed-clock"; + #clock-cells =3D <0>; + clock-frequency =3D <27000000>; + clock-output-names =3D "pxo_board"; + }; + + sleep_clk: sleep_clk { + compatible =3D "fixed-clock"; + #clock-cells =3D <0>; + clock-frequency =3D <32768>; + clock-output-names =3D "sleep_clk"; + }; + }; + + cpu-pmu { + compatible =3D "qcom,krait-pmu"; + interrupts =3D ; + qcom,no-pc-write; + }; + cpus { #address-cells =3D <1>; #size-cells =3D <0>; @@ -22,9 +51,9 @@ cpus { =20 cpu@0 { compatible =3D "qcom,krait"; + reg =3D <0>; enable-method =3D "qcom,kpss-acc-v1"; device_type =3D "cpu"; - reg =3D <0>; next-level-cache =3D <&l2>; qcom,acc =3D <&acc0>; qcom,saw =3D <&saw0>; @@ -32,9 +61,9 @@ cpu@0 { =20 cpu@1 { compatible =3D "qcom,krait"; + reg =3D <1>; enable-method =3D "qcom,kpss-acc-v1"; device_type =3D "cpu"; - reg =3D <1>; next-level-cache =3D <&l2>; qcom,acc =3D <&acc1>; qcom,saw =3D <&saw1>; @@ -52,111 +81,29 @@ memory@80000000 { reg =3D <0x80000000 0>; }; =20 - thermal-zones { - cpu0-thermal { - polling-delay-passive =3D <250>; - polling-delay =3D <1000>; - thermal-sensors =3D <&tsens 0>; - - trips { - cpu_alert0: trip0 { - temperature =3D <60000>; - hysteresis =3D <10000>; - type =3D "passive"; - }; - - cpu_crit0: trip1 { - temperature =3D <95000>; - hysteresis =3D <10000>; - type =3D "critical"; - }; - }; - }; - - cpu1-thermal { - polling-delay-passive =3D <250>; - polling-delay =3D <1000>; - thermal-sensors =3D <&tsens 1>; - - trips { - cpu_alert1: trip0 { - temperature =3D <60000>; - hysteresis =3D <10000>; - type =3D "passive"; - }; - - cpu_crit1: trip1 { - temperature =3D <95000>; - hysteresis =3D <10000>; - type =3D "critical"; - }; - }; - }; - }; - - cpu-pmu { - compatible =3D "qcom,krait-pmu"; - interrupts =3D ; - qcom,no-pc-write; - }; - - clocks { - cxo_board: cxo_board { - compatible =3D "fixed-clock"; - #clock-cells =3D <0>; - clock-frequency =3D <19200000>; - clock-output-names =3D "cxo_board"; - }; - - pxo_board: pxo_board { - compatible =3D "fixed-clock"; - #clock-cells =3D <0>; - clock-frequency =3D <27000000>; - clock-output-names =3D "pxo_board"; - }; - - sleep_clk: sleep_clk { - compatible =3D "fixed-clock"; - #clock-cells =3D <0>; - clock-frequency =3D <32768>; - clock-output-names =3D "sleep_clk"; - }; - }; - - /* Temporary fixed regulator */ - vsdcc_fixed: vsdcc-regulator { - compatible =3D "regulator-fixed"; - regulator-name =3D "SDCC Power"; - regulator-min-microvolt =3D <2700000>; - regulator-max-microvolt =3D <2700000>; - regulator-always-on; - }; - soc: soc { + compatible =3D "simple-bus"; + ranges; #address-cells =3D <1>; #size-cells =3D <1>; - ranges; - compatible =3D "simple-bus"; =20 - intc: interrupt-controller@2000000 { - compatible =3D "qcom,msm-qgic2"; - interrupt-controller; - #interrupt-cells =3D <3>; - reg =3D <0x02000000 0x1000>, - <0x02002000 0x1000>; + rpm: rpm@108000 { + compatible =3D "qcom,rpm-msm8960"; + reg =3D <0x108000 0x1000>; + qcom,ipc =3D <&l2cc 0x8 2>; + + interrupts =3D , + , + ; + interrupt-names =3D "ack", + "err", + "wakeup"; }; =20 - timer@200a000 { - compatible =3D "qcom,kpss-wdt-msm8960", "qcom,kpss-timer", - "qcom,msm-timer"; - interrupts =3D , - , - ; - reg =3D <0x0200a000 0x100>; - clock-frequency =3D <27000000>; - clocks =3D <&sleep_clk>; - clock-names =3D "sleep"; - cpu-offset =3D <0x80000>; + ssbi: ssbi@500000 { + compatible =3D "qcom,ssbi"; + reg =3D <0x500000 0x1000>; + qcom,controller-type =3D "pmic-arbiter"; }; =20 qfprom: efuse@700000 { @@ -176,24 +123,26 @@ tsens_backup: backup-calib@414 { =20 msmgpio: pinctrl@800000 { compatible =3D "qcom,msm8960-pinctrl"; + reg =3D <0x800000 0x4000>; gpio-controller; gpio-ranges =3D <&msmgpio 0 0 152>; #gpio-cells =3D <2>; interrupts =3D ; interrupt-controller; #interrupt-cells =3D <2>; - reg =3D <0x800000 0x4000>; }; =20 gcc: clock-controller@900000 { compatible =3D "qcom,gcc-msm8960", "syscon"; + reg =3D <0x900000 0x4000>; #clock-cells =3D <1>; #reset-cells =3D <1>; - reg =3D <0x900000 0x4000>; clocks =3D <&cxo_board>, <&pxo_board>, <&lcc PLL4>; - clock-names =3D "cxo", "pxo", "pll4"; + clock-names =3D "cxo", + "pxo", + "pll4"; =20 tsens: thermal-sensor { compatible =3D "qcom,msm8960-tsens"; @@ -208,49 +157,25 @@ tsens: thermal-sensor { }; }; =20 - lcc: clock-controller@28000000 { - compatible =3D "qcom,lcc-msm8960"; - reg =3D <0x28000000 0x1000>; - #clock-cells =3D <1>; - #reset-cells =3D <1>; - clocks =3D <&pxo_board>, - <&gcc PLL4_VOTE>, - <0>, - <0>, <0>, - <0>, <0>, - <0>; - clock-names =3D "pxo", - "pll4_vote", - "mi2s_codec_clk", - "codec_i2s_mic_codec_clk", - "spare_i2s_mic_codec_clk", - "codec_i2s_spkr_codec_clk", - "spare_i2s_spkr_codec_clk", - "pcm_codec_clk"; + intc: interrupt-controller@2000000 { + compatible =3D "qcom,msm-qgic2"; + reg =3D <0x02000000 0x1000>, + <0x02002000 0x1000>; + interrupt-controller; + #interrupt-cells =3D <3>; }; =20 - clock-controller@4000000 { - compatible =3D "qcom,mmcc-msm8960"; - reg =3D <0x4000000 0x1000>; - #clock-cells =3D <1>; - #power-domain-cells =3D <1>; - #reset-cells =3D <1>; - clocks =3D <&pxo_board>, - <&gcc PLL3>, - <&gcc PLL8_VOTE>, - <0>, - <0>, - <0>, - <0>, - <0>; - clock-names =3D "pxo", - "pll3", - "pll8_vote", - "dsi1pll", - "dsi1pllbyte", - "dsi2pll", - "dsi2pllbyte", - "hdmipll"; + timer@200a000 { + compatible =3D "qcom,kpss-wdt-msm8960", "qcom,kpss-timer", + "qcom,msm-timer"; + reg =3D <0x0200a000 0x100>; + interrupts =3D , + , + ; + clock-frequency =3D <27000000>; + clocks =3D <&sleep_clk>; + clock-names =3D "sleep"; + cpu-offset =3D <0x80000>; }; =20 l2cc: clock-controller@2011000 { @@ -261,17 +186,6 @@ l2cc: clock-controller@2011000 { #clock-cells =3D <0>; }; =20 - rpm: rpm@108000 { - compatible =3D "qcom,rpm-msm8960"; - reg =3D <0x108000 0x1000>; - qcom,ipc =3D <&l2cc 0x8 2>; - - interrupts =3D , - , - ; - interrupt-names =3D "ack", "err", "wakeup"; - }; - acc0: clock-controller@2088000 { compatible =3D "qcom,kpss-acc-v1"; reg =3D <0x02088000 0x1000>, <0x02008000 0x1000>; @@ -281,15 +195,6 @@ acc0: clock-controller@2088000 { #clock-cells =3D <0>; }; =20 - acc1: clock-controller@2098000 { - compatible =3D "qcom,kpss-acc-v1"; - reg =3D <0x02098000 0x1000>, <0x02008000 0x1000>; - clocks =3D <&gcc PLL8_VOTE>, <&pxo_board>; - clock-names =3D "pll8_vote", "pxo"; - clock-output-names =3D "acpu1_aux"; - #clock-cells =3D <0>; - }; - saw0: power-manager@2089000 { compatible =3D "qcom,msm8960-saw2-cpu", "qcom,saw2"; reg =3D <0x02089000 0x1000>, <0x02009000 0x1000>; @@ -300,6 +205,15 @@ saw0_vreg: regulator { }; }; =20 + acc1: clock-controller@2098000 { + compatible =3D "qcom,kpss-acc-v1"; + reg =3D <0x02098000 0x1000>, <0x02008000 0x1000>; + clocks =3D <&gcc PLL8_VOTE>, <&pxo_board>; + clock-names =3D "pll8_vote", "pxo"; + clock-output-names =3D "acpu1_aux"; + #clock-cells =3D <0>; + }; + saw1: power-manager@2099000 { compatible =3D "qcom,msm8960-saw2-cpu", "qcom,saw2"; reg =3D <0x02099000 0x1000>, <0x02009000 0x1000>; @@ -310,77 +224,34 @@ saw1_vreg: regulator { }; }; =20 - gsbi5: gsbi@16400000 { - compatible =3D "qcom,gsbi-v1.0.0"; - cell-index =3D <5>; - reg =3D <0x16400000 0x100>; - clocks =3D <&gcc GSBI5_H_CLK>; - clock-names =3D "iface"; - #address-cells =3D <1>; - #size-cells =3D <1>; - ranges; - - syscon-tcsr =3D <&tcsr>; - - status =3D "disabled"; - - gsbi5_serial: serial@16440000 { - compatible =3D "qcom,msm-uartdm-v1.3", "qcom,msm-uartdm"; - reg =3D <0x16440000 0x1000>, - <0x16400000 0x1000>; - interrupts =3D ; - clocks =3D <&gcc GSBI5_UART_CLK>, <&gcc GSBI5_H_CLK>; - clock-names =3D "core", "iface"; - status =3D "disabled"; - }; - }; - - gsbi8: gsbi@1a000000 { - compatible =3D "qcom,gsbi-v1.0.0"; - cell-index =3D <8>; - reg =3D <0x1a000000 0x100>; - clocks =3D <&gcc GSBI8_H_CLK>; - clock-names =3D "iface"; - #address-cells =3D <1>; - #size-cells =3D <1>; - ranges; - - syscon-tcsr =3D <&tcsr>; - - status =3D "disabled"; - - gsbi8_serial: serial@1a040000 { - compatible =3D "qcom,msm-uartdm-v1.3", "qcom,msm-uartdm"; - reg =3D <0x1a040000 0x1000>, - <0x1a000000 0x1000>; - interrupts =3D ; - clocks =3D <&gcc GSBI8_UART_CLK>, - <&gcc GSBI8_H_CLK>; - clock-names =3D "core", - "iface"; - - status =3D "disabled"; - }; - }; - - ssbi: ssbi@500000 { - compatible =3D "qcom,ssbi"; - reg =3D <0x500000 0x1000>; - qcom,controller-type =3D "pmic-arbiter"; - }; - - rng@1a500000 { - compatible =3D "qcom,prng"; - reg =3D <0x1a500000 0x200>; - clocks =3D <&gcc PRNG_CLK>; - clock-names =3D "core"; + clock-controller@4000000 { + compatible =3D "qcom,mmcc-msm8960"; + reg =3D <0x4000000 0x1000>; + #clock-cells =3D <1>; + #power-domain-cells =3D <1>; + #reset-cells =3D <1>; + clocks =3D <&pxo_board>, + <&gcc PLL3>, + <&gcc PLL8_VOTE>, + <0>, + <0>, + <0>, + <0>, + <0>; + clock-names =3D "pxo", + "pll3", + "pll8_vote", + "dsi1pll", + "dsi1pllbyte", + "dsi2pll", + "dsi2pllbyte", + "hdmipll"; }; =20 sdcc3: mmc@12180000 { compatible =3D "arm,pl18x", "arm,primecell"; - arm,primecell-periphid =3D <0x00051180>; - status =3D "disabled"; reg =3D <0x12180000 0x2000>; + arm,primecell-periphid =3D <0x00051180>; interrupts =3D ; clocks =3D <&gcc SDC3_CLK>, <&gcc SDC3_H_CLK>; clock-names =3D "mclk", "apb_pclk"; @@ -392,6 +263,8 @@ sdcc3: mmc@12180000 { vmmc-supply =3D <&vsdcc_fixed>; dmas =3D <&sdcc3bam 2>, <&sdcc3bam 1>; dma-names =3D "tx", "rx"; + + status =3D "disabled"; }; =20 sdcc3bam: dma-controller@12182000 { @@ -405,10 +278,9 @@ sdcc3bam: dma-controller@12182000 { }; =20 sdcc1: mmc@12400000 { - status =3D "disabled"; compatible =3D "arm,pl18x", "arm,primecell"; - arm,primecell-periphid =3D <0x00051180>; reg =3D <0x12400000 0x2000>; + arm,primecell-periphid =3D <0x00051180>; interrupts =3D ; clocks =3D <&gcc SDC1_CLK>, <&gcc SDC1_H_CLK>; clock-names =3D "mclk", "apb_pclk"; @@ -420,6 +292,8 @@ sdcc1: mmc@12400000 { vmmc-supply =3D <&vsdcc_fixed>; dmas =3D <&sdcc1bam 2>, <&sdcc1bam 1>; dma-names =3D "tx", "rx"; + + status =3D "disabled"; }; =20 sdcc1bam: dma-controller@12402000 { @@ -432,37 +306,6 @@ sdcc1bam: dma-controller@12402000 { qcom,ee =3D <0>; }; =20 - tcsr: syscon@1a400000 { - compatible =3D "qcom,tcsr-msm8960", "syscon"; - reg =3D <0x1a400000 0x100>; - }; - - gsbi1: gsbi@16000000 { - compatible =3D "qcom,gsbi-v1.0.0"; - cell-index =3D <1>; - reg =3D <0x16000000 0x100>; - clocks =3D <&gcc GSBI1_H_CLK>; - clock-names =3D "iface"; - #address-cells =3D <1>; - #size-cells =3D <1>; - ranges; - - status =3D "disabled"; - - gsbi1_spi: spi@16080000 { - compatible =3D "qcom,spi-qup-v1.1.1"; - #address-cells =3D <1>; - #size-cells =3D <0>; - reg =3D <0x16080000 0x1000>; - interrupts =3D ; - cs-gpios =3D <&msmgpio 8 0>; - - clocks =3D <&gcc GSBI1_QUP_CLK>, <&gcc GSBI1_H_CLK>; - clock-names =3D "core", "iface"; - status =3D "disabled"; - }; - }; - usb1: usb@12500000 { compatible =3D "qcom,ci-hdrc"; reg =3D <0x12500000 0x200>, @@ -479,6 +322,7 @@ usb1: usb@12500000 { phys =3D <&usb_hs1_phy>; phy-names =3D "usb-phy"; #reset-cells =3D <1>; + status =3D "disabled"; =20 ulpi { @@ -494,6 +338,34 @@ usb_hs1_phy: phy { }; }; =20 + gsbi1: gsbi@16000000 { + compatible =3D "qcom,gsbi-v1.0.0"; + reg =3D <0x16000000 0x100>; + ranges; + cell-index =3D <1>; + clocks =3D <&gcc GSBI1_H_CLK>; + clock-names =3D "iface"; + #address-cells =3D <1>; + #size-cells =3D <1>; + + status =3D "disabled"; + + gsbi1_spi: spi@16080000 { + compatible =3D "qcom,spi-qup-v1.1.1"; + reg =3D <0x16080000 0x1000>; + #address-cells =3D <1>; + #size-cells =3D <0>; + interrupts =3D ; + cs-gpios =3D <&msmgpio 8 0>; + clocks =3D <&gcc GSBI1_QUP_CLK>, + <&gcc GSBI1_H_CLK>; + clock-names =3D "core", + "iface"; + + status =3D "disabled"; + }; + }; + gsbi3: gsbi@16200000 { compatible =3D "qcom,gsbi-v1.0.0"; reg =3D <0x16200000 0x100>; @@ -503,6 +375,7 @@ gsbi3: gsbi@16200000 { clock-names =3D "iface"; #address-cells =3D <1>; #size-cells =3D <1>; + status =3D "disabled"; =20 gsbi3_i2c: i2c@16280000 { @@ -514,12 +387,154 @@ gsbi3_i2c: i2c@16280000 { interrupts =3D ; clocks =3D <&gcc GSBI3_QUP_CLK>, <&gcc GSBI3_H_CLK>; - clock-names =3D "core", "iface"; + clock-names =3D "core", + "iface"; #address-cells =3D <1>; #size-cells =3D <0>; + + status =3D "disabled"; + }; + }; + + gsbi5: gsbi@16400000 { + compatible =3D "qcom,gsbi-v1.0.0"; + reg =3D <0x16400000 0x100>; + ranges; + cell-index =3D <5>; + clocks =3D <&gcc GSBI5_H_CLK>; + clock-names =3D "iface"; + #address-cells =3D <1>; + #size-cells =3D <1>; + syscon-tcsr =3D <&tcsr>; + + status =3D "disabled"; + + gsbi5_serial: serial@16440000 { + compatible =3D "qcom,msm-uartdm-v1.3", "qcom,msm-uartdm"; + reg =3D <0x16440000 0x1000>, + <0x16400000 0x1000>; + interrupts =3D ; + clocks =3D <&gcc GSBI5_UART_CLK>, + <&gcc GSBI5_H_CLK>; + clock-names =3D "core", + "iface"; + status =3D "disabled"; }; }; + + gsbi8: gsbi@1a000000 { + compatible =3D "qcom,gsbi-v1.0.0"; + reg =3D <0x1a000000 0x100>; + ranges; + cell-index =3D <8>; + clocks =3D <&gcc GSBI8_H_CLK>; + clock-names =3D "iface"; + #address-cells =3D <1>; + #size-cells =3D <1>; + syscon-tcsr =3D <&tcsr>; + + status =3D "disabled"; + + gsbi8_serial: serial@1a040000 { + compatible =3D "qcom,msm-uartdm-v1.3", "qcom,msm-uartdm"; + reg =3D <0x1a040000 0x1000>, + <0x1a000000 0x1000>; + interrupts =3D ; + clocks =3D <&gcc GSBI8_UART_CLK>, + <&gcc GSBI8_H_CLK>; + clock-names =3D "core", + "iface"; + + status =3D "disabled"; + }; + }; + + tcsr: syscon@1a400000 { + compatible =3D "qcom,tcsr-msm8960", "syscon"; + reg =3D <0x1a400000 0x100>; + }; + + rng@1a500000 { + compatible =3D "qcom,prng"; + reg =3D <0x1a500000 0x200>; + clocks =3D <&gcc PRNG_CLK>; + clock-names =3D "core"; + }; + + lcc: clock-controller@28000000 { + compatible =3D "qcom,lcc-msm8960"; + reg =3D <0x28000000 0x1000>; + #clock-cells =3D <1>; + #reset-cells =3D <1>; + clocks =3D <&pxo_board>, + <&gcc PLL4_VOTE>, + <0>, + <0>, + <0>, + <0>, + <0>, + <0>; + clock-names =3D "pxo", + "pll4_vote", + "mi2s_codec_clk", + "codec_i2s_mic_codec_clk", + "spare_i2s_mic_codec_clk", + "codec_i2s_spkr_codec_clk", + "spare_i2s_spkr_codec_clk", + "pcm_codec_clk"; + }; + }; + + thermal-zones { + cpu0-thermal { + polling-delay-passive =3D <250>; + polling-delay =3D <1000>; + thermal-sensors =3D <&tsens 0>; + + trips { + cpu_alert0: trip0 { + temperature =3D <60000>; + hysteresis =3D <10000>; + type =3D "passive"; + }; + + cpu_crit0: trip1 { + temperature =3D <95000>; + hysteresis =3D <10000>; + type =3D "critical"; + }; + }; + }; + + cpu1-thermal { + polling-delay-passive =3D <250>; + polling-delay =3D <1000>; + thermal-sensors =3D <&tsens 1>; + + trips { + cpu_alert1: trip0 { + temperature =3D <60000>; + hysteresis =3D <10000>; + type =3D "passive"; + }; + + cpu_crit1: trip1 { + temperature =3D <95000>; + hysteresis =3D <10000>; + type =3D "critical"; + }; + }; + }; + }; + + /* Temporary fixed regulator */ + vsdcc_fixed: vsdcc-regulator { + compatible =3D "regulator-fixed"; + regulator-name =3D "SDCC Power"; + regulator-min-microvolt =3D <2700000>; + regulator-max-microvolt =3D <2700000>; + regulator-always-on; }; }; #include "qcom-msm8960-pins.dtsi" --=20 2.34.1