From nobody Thu Oct 2 07:43:52 2025 Received: from mail-pg1-f202.google.com (mail-pg1-f202.google.com [209.85.215.202]) (using TLSv1.2 with cipher ECDHE-RSA-AES128-GCM-SHA256 (128/128 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id D929610957 for ; Fri, 19 Sep 2025 21:59:38 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=none smtp.client-ip=209.85.215.202 ARC-Seal: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1758319180; cv=none; b=rrWBe483mxfHeEzIqrwwXYtjo0uegUUTpgJFEasH76mr2OStD12ddsGbi5PYi2AkpDZ7X1R6w8a/H356PmnU1hW28UFvZwP0+71YbVlQjAFxSqb/PP3kmNoCdwQmz44x9l+8+NhUtc+qNsXzW51TbzSLe/JEGYiE64U7oSSLEEA= ARC-Message-Signature: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1758319180; c=relaxed/simple; bh=TqI0m8cUaosO9YvbAzshCBHwQ31eU9/jNocSpeBH9U4=; h=Date:In-Reply-To:Mime-Version:References:Message-ID:Subject:From: To:Cc:Content-Type; b=LwQe3Gf9oOabuNMIutWAqacOkZDVLsrE+WDFIYVTO0EvV0zItyEogqYUIHqVaA/+toFMllc5HiF7A6azfqj5/9DEplPYiWi4g+hHMWNHSBvqhrSRq0wySPbrdj2dvoHLKi54ehO4CvWlJ4x/oHb/JvZjiXgR0nhvE8gLkVGp25k= ARC-Authentication-Results: i=1; smtp.subspace.kernel.org; dmarc=pass (p=reject dis=none) header.from=google.com; spf=pass smtp.mailfrom=flex--seanjc.bounces.google.com; dkim=pass (2048-bit key) header.d=google.com header.i=@google.com header.b=CORnEqVX; arc=none smtp.client-ip=209.85.215.202 Authentication-Results: smtp.subspace.kernel.org; dmarc=pass (p=reject dis=none) header.from=google.com Authentication-Results: smtp.subspace.kernel.org; spf=pass smtp.mailfrom=flex--seanjc.bounces.google.com Authentication-Results: smtp.subspace.kernel.org; dkim=pass (2048-bit key) header.d=google.com header.i=@google.com header.b="CORnEqVX" Received: by mail-pg1-f202.google.com with SMTP id 41be03b00d2f7-b552f91033cso506722a12.1 for ; Fri, 19 Sep 2025 14:59:38 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=20230601; t=1758319178; x=1758923978; darn=vger.kernel.org; h=cc:to:from:subject:message-id:references:mime-version:in-reply-to :date:reply-to:from:to:cc:subject:date:message-id:reply-to; bh=z4vvZVviAKykztVzh+1RERrWNNzj6PiZBM3YIdtRxzo=; b=CORnEqVXy/CBfO9EvtPZujCzaza/3sXxgAThywMPIxptlX1nGM3/5iMhH7M6jix8eq PgORSV1S+8JAr0OUbPReSInmMEQBd48UPwX7WV9On6vF0LXYN3GjW71dILRzjMRV0egw nG7fQ4CqTqyuwySPGyKnqnSoq9k6pR5FDYI2mmv2v18Wslwg1z3CSYsr7Z3i3boCD4zu EgCSReL17N794uaFT+o7tzblWok55ZBzQTV27mLw0UZBiCcE6o9AHk/vcM1ly0Z0qMQx wRoj1kp4BPDHlSagiDu72eb0gGEzV6O9+PT2M4YpvjyiqaQOIj2yNbJVlmOxCSBhQrWI TEWA== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20230601; t=1758319178; x=1758923978; h=cc:to:from:subject:message-id:references:mime-version:in-reply-to :date:reply-to:x-gm-message-state:from:to:cc:subject:date:message-id :reply-to; bh=z4vvZVviAKykztVzh+1RERrWNNzj6PiZBM3YIdtRxzo=; b=BEa7WvErDP5kO1IY2NbAMgnjSCkPzROkmaeo4jwz91UUlK3Twd5YZIpfiA5elJ++aB lgVgW3K0FsG/7QPulyti+eqmaNaaEQGJ4p51i4S7RigGsQzZhNfbldlsAgFq4Ll+j4m8 vpd9T4GDe5YJAWFoH3Re+sSeBPkeBm8yDejrilRC9M+QGOeFhvJU5p+F7XEVsbgroQ+O IPPq7JkcSuAcUNaJXa4vfb1oG+B6cswSdkQE02WUSWZeCNaAN7YV+o2z4t+k3uuGM/t7 IgwYZZqvPvMaLmLBTEeG0RB1EucpZ04QTG9Y6kW+uDTcdY6yWViCG+SNk8mY81DsJRXg 02Kw== X-Forwarded-Encrypted: i=1; AJvYcCWrk0Mx8lvR+03ONS48zXMhuQ19oqKtkCAE7iClktbWwb6i9nGgSLgnHdB8qyH6pOAvYZuuE/YQgz7fnIQ=@vger.kernel.org X-Gm-Message-State: AOJu0Yxj2LFs3ZI6o1ARh96tpLYGbZEE1N7+A1t5G4EbXi4CryqfXTQs 9Erm79SxJYPO6Gq1IOmg2aRoDlLoDo3BBOHTZS4Fa6mS87A3PDZrWCZoV2EoSuj+CYpZJsce/fH KBSW/lQ== X-Google-Smtp-Source: AGHT+IHA4KH8oOcK/PIZhKxCn6eWhYsPqQGFXHEna4LG8tEcBbH3eiAyVFCZTr7RiTvr1YV2pXKjJCl0ut0= X-Received: from pji16.prod.google.com ([2002:a17:90b:3fd0:b0:32d:7097:81f1]) (user=seanjc job=prod-delivery.src-stubby-dispatcher) by 2002:a17:903:2ecf:b0:267:776b:a31a with SMTP id d9443c01a7336-269ba517048mr59720995ad.29.1758319178239; Fri, 19 Sep 2025 14:59:38 -0700 (PDT) Reply-To: Sean Christopherson Date: Fri, 19 Sep 2025 14:59:28 -0700 In-Reply-To: <20250919215934.1590410-1-seanjc@google.com> Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: Mime-Version: 1.0 References: <20250919215934.1590410-1-seanjc@google.com> X-Mailer: git-send-email 2.51.0.470.ga7dc726c21-goog Message-ID: <20250919215934.1590410-2-seanjc@google.com> Subject: [PATCH v4 1/7] KVM: SVM: Make svm_x86_ops globally visible, clean up on-HyperV usage From: Sean Christopherson To: Sean Christopherson , Paolo Bonzini , Vitaly Kuznetsov Cc: kvm@vger.kernel.org, linux-kernel@vger.kernel.org, Naveen N Rao Content-Transfer-Encoding: quoted-printable Content-Type: text/plain; charset="utf-8" Make svm_x86_ops globally visible in anticipation of modifying the struct in avic.c, and clean up the KVM-on-HyperV usage, as declaring _and using_ a local variable in a header that's only defined in one specific .c-file is all kinds of ugly. Opportunistically make svm_hv_enable_l2_tlb_flush() local to svm_onhyperv.c, as the only reason it was visible was due to the aforementioned shenanigans in svm_onhyperv.h. Alternatively, svm_x86_ops could be explicitly passed to svm_hv_hardware_setup() as a parameter. While that approach is slightly safer, e.g. avoids "hidden" updates, for better or worse, the Intel side of KVM has already chosen to expose vt_x86_ops (and vt_init_ops). Given that svm_x86_ops is only truly consumed by kvm_ops_update, the odds of a "hidden" update causing problems are extremely low. So, absent a strong reason to rework the VMX/TDX code, make svm_x86_ops visible, as having all updates use exactly "svm_x86_ops." is advantageous in its own right. No functional change intended. Signed-off-by: Sean Christopherson --- arch/x86/kvm/svm/svm.c | 2 +- arch/x86/kvm/svm/svm.h | 2 ++ arch/x86/kvm/svm/svm_onhyperv.c | 28 +++++++++++++++++++++++++++- arch/x86/kvm/svm/svm_onhyperv.h | 31 +------------------------------ 4 files changed, 31 insertions(+), 32 deletions(-) diff --git a/arch/x86/kvm/svm/svm.c b/arch/x86/kvm/svm/svm.c index 67f4eed01526..8117d79036bb 100644 --- a/arch/x86/kvm/svm/svm.c +++ b/arch/x86/kvm/svm/svm.c @@ -5032,7 +5032,7 @@ static void *svm_alloc_apic_backing_page(struct kvm_v= cpu *vcpu) return page_address(page); } =20 -static struct kvm_x86_ops svm_x86_ops __initdata =3D { +struct kvm_x86_ops svm_x86_ops __initdata =3D { .name =3D KBUILD_MODNAME, =20 .check_processor_compatibility =3D svm_check_processor_compat, diff --git a/arch/x86/kvm/svm/svm.h b/arch/x86/kvm/svm/svm.h index 5d39c0b17988..1652a868c578 100644 --- a/arch/x86/kvm/svm/svm.h +++ b/arch/x86/kvm/svm/svm.h @@ -52,6 +52,8 @@ extern bool x2avic_enabled; extern bool vnmi; extern int lbrv; =20 +extern struct kvm_x86_ops svm_x86_ops __initdata; + /* * Clean bits in VMCB. * VMCB_ALL_CLEAN_MASK might also need to diff --git a/arch/x86/kvm/svm/svm_onhyperv.c b/arch/x86/kvm/svm/svm_onhyper= v.c index 3971b3ea5d04..a8e78c0e5956 100644 --- a/arch/x86/kvm/svm/svm_onhyperv.c +++ b/arch/x86/kvm/svm/svm_onhyperv.c @@ -15,7 +15,7 @@ #include "kvm_onhyperv.h" #include "svm_onhyperv.h" =20 -int svm_hv_enable_l2_tlb_flush(struct kvm_vcpu *vcpu) +static int svm_hv_enable_l2_tlb_flush(struct kvm_vcpu *vcpu) { struct hv_vmcb_enlightenments *hve; hpa_t partition_assist_page =3D hv_get_partition_assist_page(vcpu); @@ -35,3 +35,29 @@ int svm_hv_enable_l2_tlb_flush(struct kvm_vcpu *vcpu) return 0; } =20 +__init void svm_hv_hardware_setup(void) +{ + if (npt_enabled && + ms_hyperv.nested_features & HV_X64_NESTED_ENLIGHTENED_TLB) { + pr_info(KBUILD_MODNAME ": Hyper-V enlightened NPT TLB flush enabled\n"); + svm_x86_ops.flush_remote_tlbs =3D hv_flush_remote_tlbs; + svm_x86_ops.flush_remote_tlbs_range =3D hv_flush_remote_tlbs_range; + } + + if (ms_hyperv.nested_features & HV_X64_NESTED_DIRECT_FLUSH) { + int cpu; + + pr_info(KBUILD_MODNAME ": Hyper-V Direct TLB Flush enabled\n"); + for_each_online_cpu(cpu) { + struct hv_vp_assist_page *vp_ap =3D + hv_get_vp_assist_page(cpu); + + if (!vp_ap) + continue; + + vp_ap->nested_control.features.directhypercall =3D 1; + } + svm_x86_ops.enable_l2_tlb_flush =3D + svm_hv_enable_l2_tlb_flush; + } +} diff --git a/arch/x86/kvm/svm/svm_onhyperv.h b/arch/x86/kvm/svm/svm_onhyper= v.h index f85bc617ffe4..08f14e6f195c 100644 --- a/arch/x86/kvm/svm/svm_onhyperv.h +++ b/arch/x86/kvm/svm/svm_onhyperv.h @@ -13,9 +13,7 @@ #include "kvm_onhyperv.h" #include "svm/hyperv.h" =20 -static struct kvm_x86_ops svm_x86_ops; - -int svm_hv_enable_l2_tlb_flush(struct kvm_vcpu *vcpu); +__init void svm_hv_hardware_setup(void); =20 static inline bool svm_hv_is_enlightened_tlb_enabled(struct kvm_vcpu *vcpu) { @@ -40,33 +38,6 @@ static inline void svm_hv_init_vmcb(struct vmcb *vmcb) hve->hv_enlightenments_control.msr_bitmap =3D 1; } =20 -static inline __init void svm_hv_hardware_setup(void) -{ - if (npt_enabled && - ms_hyperv.nested_features & HV_X64_NESTED_ENLIGHTENED_TLB) { - pr_info(KBUILD_MODNAME ": Hyper-V enlightened NPT TLB flush enabled\n"); - svm_x86_ops.flush_remote_tlbs =3D hv_flush_remote_tlbs; - svm_x86_ops.flush_remote_tlbs_range =3D hv_flush_remote_tlbs_range; - } - - if (ms_hyperv.nested_features & HV_X64_NESTED_DIRECT_FLUSH) { - int cpu; - - pr_info(KBUILD_MODNAME ": Hyper-V Direct TLB Flush enabled\n"); - for_each_online_cpu(cpu) { - struct hv_vp_assist_page *vp_ap =3D - hv_get_vp_assist_page(cpu); - - if (!vp_ap) - continue; - - vp_ap->nested_control.features.directhypercall =3D 1; - } - svm_x86_ops.enable_l2_tlb_flush =3D - svm_hv_enable_l2_tlb_flush; - } -} - static inline void svm_hv_vmcb_dirty_nested_enlightenments( struct kvm_vcpu *vcpu) { --=20 2.51.0.470.ga7dc726c21-goog