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([2a01:e0a:f:6020:9dd0:62bf:d369:14ce]) by smtp.gmail.com with ESMTPSA id ffacd0b85a97d-3ee07407fa3sm8367224f8f.21.2025.09.19.08.58.22 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Fri, 19 Sep 2025 08:58:23 -0700 (PDT) From: Vincent Guittot To: chester62515@gmail.com, mbrugger@suse.com, ghennadi.procopciuc@oss.nxp.com, s32@nxp.com, bhelgaas@google.com, jingoohan1@gmail.com, lpieralisi@kernel.org, kwilczynski@kernel.org, mani@kernel.org, robh@kernel.org, krzk+dt@kernel.org, conor+dt@kernel.org, Ionut.Vicovan@nxp.com, larisa.grigore@nxp.com, Ghennadi.Procopciuc@nxp.com, ciprianmarian.costea@nxp.com, bogdan.hamciuc@nxp.com, Frank.li@nxp.com, linux-arm-kernel@lists.infradead.org, linux-pci@vger.kernel.org, devicetree@vger.kernel.org, linux-kernel@vger.kernel.org, imx@lists.linux.dev Cc: cassel@kernel.org Subject: [PATCH 1/3 v2] dt-bindings: PCI: s32g: Add NXP PCIe controller Date: Fri, 19 Sep 2025 17:58:19 +0200 Message-ID: <20250919155821.95334-2-vincent.guittot@linaro.org> X-Mailer: git-send-email 2.43.0 In-Reply-To: <20250919155821.95334-1-vincent.guittot@linaro.org> References: <20250919155821.95334-1-vincent.guittot@linaro.org> Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Content-Type: text/plain; charset="utf-8" Describe the PCIe controller available on the S32G platforms. Co-developed-by: Ionut Vicovan Signed-off-by: Ionut Vicovan Co-developed-by: Bogdan-Gabriel Roman Signed-off-by: Bogdan-Gabriel Roman Co-developed-by: Larisa Grigore Signed-off-by: Larisa Grigore Co-developed-by: Ghennadi Procopciuc Signed-off-by: Ghennadi Procopciuc Co-developed-by: Ciprian Marian Costea Signed-off-by: Ciprian Marian Costea Co-developed-by: Bogdan Hamciuc Signed-off-by: Bogdan Hamciuc Signed-off-by: Vincent Guittot --- .../devicetree/bindings/pci/nxp,s32-pcie.yaml | 131 ++++++++++++++++++ 1 file changed, 131 insertions(+) create mode 100644 Documentation/devicetree/bindings/pci/nxp,s32-pcie.yaml diff --git a/Documentation/devicetree/bindings/pci/nxp,s32-pcie.yaml b/Docu= mentation/devicetree/bindings/pci/nxp,s32-pcie.yaml new file mode 100644 index 000000000000..cabb8b86c042 --- /dev/null +++ b/Documentation/devicetree/bindings/pci/nxp,s32-pcie.yaml @@ -0,0 +1,131 @@ +# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause) +%YAML 1.2 +--- +$id: http://devicetree.org/schemas/pci/nxp,s32-pcie.yaml# +$schema: http://devicetree.org/meta-schemas/core.yaml# + +title: NXP S32G2xx/S32G3xx PCIe controller + +maintainers: + - Bogdan Hamciuc + - Ionut Vicovan + +description: + This PCIe controller is based on the Synopsys DesignWare PCIe IP. + The S32G SoC family has two PCIe controllers, which can be configured as + either Root Complex or Endpoint. + +properties: + compatible: + oneOf: + - enum: + - nxp,s32g2-pcie # S32G2 SoCs RC mode + - items: + - const: nxp,s32g3-pcie + - const: nxp,s32g2-pcie + + reg: + maxItems: 7 + + reg-names: + items: + - const: dbi + - const: dbi2 + - const: atu + - const: dma + - const: ctrl + - const: config + - const: addr_space + + interrupts: + maxItems: 8 + + interrupt-names: + items: + - const: link-req-stat + - const: dma + - const: msi + - const: phy-link-down + - const: phy-link-up + - const: misc + - const: pcs + - const: tlp-req-no-comp + +required: + - compatible + - reg + - reg-names + - interrupts + - interrupt-names + - ranges + - phys + +allOf: + - $ref: /schemas/pci/snps,dw-pcie-common.yaml# + - $ref: /schemas/pci/pci-bus.yaml# + +unevaluatedProperties: false + +examples: + - | + #include + #include + + bus { + #address-cells =3D <2>; + #size-cells =3D <2>; + + pcie@40400000 { + compatible =3D "nxp,s32g3-pcie", + "nxp,s32g2-pcie"; + reg =3D <0x00 0x40400000 0x0 0x00001000>, /* dbi registers */ + <0x00 0x40420000 0x0 0x00001000>, /* dbi2 registers */ + <0x00 0x40460000 0x0 0x00001000>, /* atu registers */ + <0x00 0x40470000 0x0 0x00001000>, /* dma registers */ + <0x00 0x40481000 0x0 0x000000f8>, /* ctrl registers */ + /* + * RC configuration space, 4KB each for cfg0 and cfg1 + * at the end of the outbound memory map + */ + <0x5f 0xffffe000 0x0 0x00002000>, + <0x58 0x00000000 0x0 0x40000000>; /* 1GB EP addr space */ + reg-names =3D "dbi", "dbi2", "atu", "dma", "ctrl", + "config", "addr_space"; + dma-coherent; + #address-cells =3D <3>; + #size-cells =3D <2>; + device_type =3D "pci"; + ranges =3D + /* + * downstream I/O, 64KB and aligned naturally just + * before the config space to minimize fragmentation + */ + <0x81000000 0x0 0x00000000 0x5f 0xfffe0000 0x0 0x0001000= 0>, + /* + * non-prefetchable memory, with best case size and + * alignment + */ + <0x82000000 0x0 0x00000000 0x58 0x00000000 0x7 0xfffe000= 0>; + + bus-range =3D <0x0 0xff>; + interrupts =3D , + , + , + , + , + , + , + ; + interrupt-names =3D "link-req-stat", "dma", "msi", + "phy-link-down", "phy-link-up", "misc", + "pcs", "tlp-req-no-comp"; + #interrupt-cells =3D <1>; + interrupt-map-mask =3D <0 0 0 0x7>; + interrupt-map =3D <0 0 0 1 &gic 0 0 GIC_SPI 128 IRQ_TYPE_LEVEL= _HIGH>, + <0 0 0 2 &gic 0 0 GIC_SPI 129 IRQ_TYPE_LEVEL_H= IGH>, + <0 0 0 3 &gic 0 0 GIC_SPI 130 IRQ_TYPE_LEVEL_H= IGH>, + <0 0 0 4 &gic 0 0 GIC_SPI 131 IRQ_TYPE_LEVEL_H= IGH>; + + phys =3D <&serdes0 PHY_TYPE_PCIE 0 0>; + }; + }; --=20 2.43.0