From nobody Thu Oct 2 06:18:02 2025 Received: from layka.disroot.org (layka.disroot.org [178.21.23.139]) (using TLSv1.2 with cipher ECDHE-RSA-AES128-GCM-SHA256 (128/128 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id 8AFBD313D50; Fri, 19 Sep 2025 14:27:32 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=none smtp.client-ip=178.21.23.139 ARC-Seal: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1758292056; cv=none; b=EjQLl/D1L4k/88jlJ2hew1sBpQffAkeq81rGWHB9CJbF1DqcM6r0Ja9FKTxOsBaN1DTbNQL+HxM1XKVL2ECYp2yxvlOkte+VOHB93DJjGNOegn2ms/S+1AllnEcr8eOD6bpQCPBs/j2TdeEn1aof2gDudUku+9zf1mo5HMh2I6w= ARC-Message-Signature: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1758292056; c=relaxed/simple; bh=HDC+FIgeNyad364xEx3KiNn1Bk4hVY6oVcX1miWEhkY=; h=From:To:Cc:Subject:Date:Message-ID:In-Reply-To:References: MIME-Version; b=kRZjShCPF6GdtnyPm7/h73EHpJHuTdaG7jpqocsDocNh3fIBwxoJ6xbgKIDWmaZyiJSdlty+ZxagJjPCN2qQO7+6phtrgq3/Jma2nIbQOwkyI6ZSmwQjWxDYUluZHdwbFSfq0FvAqQZBkZ93DIl6oleDWTNOIczyquPN9KU6tIo= ARC-Authentication-Results: i=1; smtp.subspace.kernel.org; dmarc=pass (p=reject dis=none) header.from=disroot.org; spf=pass smtp.mailfrom=disroot.org; dkim=pass (2048-bit key) header.d=disroot.org header.i=@disroot.org header.b=FdAyhHC/; arc=none smtp.client-ip=178.21.23.139 Authentication-Results: smtp.subspace.kernel.org; dmarc=pass (p=reject dis=none) header.from=disroot.org Authentication-Results: smtp.subspace.kernel.org; spf=pass smtp.mailfrom=disroot.org Authentication-Results: smtp.subspace.kernel.org; dkim=pass (2048-bit key) header.d=disroot.org header.i=@disroot.org header.b="FdAyhHC/" Received: from mail01.disroot.lan (localhost [127.0.0.1]) by disroot.org (Postfix) with ESMTP id 0CD0725CEF; Fri, 19 Sep 2025 16:27:31 +0200 (CEST) X-Virus-Scanned: SPAM Filter at disroot.org Received: from layka.disroot.org ([127.0.0.1]) by localhost (disroot.org [127.0.0.1]) (amavis, port 10024) with ESMTP id 3FyU9Pw9wWud; Fri, 19 Sep 2025 16:27:30 +0200 (CEST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=disroot.org; s=mail; t=1758292050; bh=HDC+FIgeNyad364xEx3KiNn1Bk4hVY6oVcX1miWEhkY=; h=From:To:Cc:Subject:Date:In-Reply-To:References; b=FdAyhHC//9GesHwQL5DGinQdskum5HshY8FyJTeuDqiRNDpLxhQJNHVBrrk/q4DjT 9NB96oP384nABNWUr8G+HZ5yWwLJt5Tx8O0wzFbZsCJvhOCkU898RXaUg/bY05+0x0 Gm6dzCJ9OkW2ccyDiQSud5rnWhsAhhzFDqjaii46paznZu68wA3occh2Ja2Xci3GDZ kwI2D/KKXvG3dBtNwpZ6o342/AJyj/m9LHUq/3KuuJIz/LOCgzakCSvJAmGx11taV6 1RsJx2/RjKcCz0Soh7t0aUZXfvUx5M9FZCs89QlfvrHQQzXAlIuVdPyfiQC4g9G/9C ZLz2An/qny2OA== From: Yao Zi To: Yinbo Zhu , Michael Turquette , Stephen Boyd , Rob Herring , Krzysztof Kozlowski , Conor Dooley , Huacai Chen , WANG Xuerui Cc: linux-clk@vger.kernel.org, devicetree@vger.kernel.org, linux-kernel@vger.kernel.org, loongarch@lists.linux.dev, Mingcong Bai , Kexy Biscuit , Yao Zi , Krzysztof Kozlowski , Yanteng Si Subject: [PATCH v4 1/8] dt-bindings: clock: loongson2: Add Loongson-2K0300 compatible Date: Fri, 19 Sep 2025 14:26:42 +0000 Message-ID: <20250919142649.58859-2-ziyao@disroot.org> In-Reply-To: <20250919142649.58859-1-ziyao@disroot.org> References: <20250919142649.58859-1-ziyao@disroot.org> Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Content-Type: text/plain; charset="utf-8" Document the clock controller shipped in Loongson-2K0300 SoC, which generates various clock signals for SoC peripherals. Differing from previous generations of SoCs, LS2K0300 requires a 120MHz external clock input. Signed-off-by: Yao Zi Reviewed-by: Krzysztof Kozlowski Reviewed-by: Yanteng Si --- .../bindings/clock/loongson,ls2k-clk.yaml | 18 ++++++++-- include/dt-bindings/clock/loongson,ls2k-clk.h | 36 +++++++++++++++++++ 2 files changed, 51 insertions(+), 3 deletions(-) diff --git a/Documentation/devicetree/bindings/clock/loongson,ls2k-clk.yaml= b/Documentation/devicetree/bindings/clock/loongson,ls2k-clk.yaml index 4f79cdb417ab..c07ad1f85857 100644 --- a/Documentation/devicetree/bindings/clock/loongson,ls2k-clk.yaml +++ b/Documentation/devicetree/bindings/clock/loongson,ls2k-clk.yaml @@ -16,6 +16,7 @@ description: | properties: compatible: enum: + - loongson,ls2k0300-clk - loongson,ls2k0500-clk - loongson,ls2k-clk # This is for Loongson-2K1000 - loongson,ls2k2000-clk @@ -24,8 +25,7 @@ properties: maxItems: 1 =20 clocks: - items: - - description: 100m ref + maxItems: 1 =20 clock-names: items: @@ -38,11 +38,23 @@ properties: ID in its "clocks" phandle cell. See include/dt-bindings/clock/loong= son,ls2k-clk.h for the full list of Loongson-2 SoC clock IDs. =20 +allOf: + - if: + properties: + compatible: + contains: + const: loongson,ls2k0300-clk + then: + properties: + clock-names: false + else: + required: + - clock-names + required: - compatible - reg - clocks - - clock-names - '#clock-cells' =20 additionalProperties: false diff --git a/include/dt-bindings/clock/loongson,ls2k-clk.h b/include/dt-bin= dings/clock/loongson,ls2k-clk.h index 4279ba595f1e..8cbb86b2cf1e 100644 --- a/include/dt-bindings/clock/loongson,ls2k-clk.h +++ b/include/dt-bindings/clock/loongson,ls2k-clk.h @@ -43,4 +43,40 @@ #define LOONGSON2_I2S_CLK 33 #define LOONGSON2_MISC_CLK 34 =20 +#define LS2K0300_CLK_STABLE 0 +#define LS2K0300_NODE_PLL 1 +#define LS2K0300_DDR_PLL 2 +#define LS2K0300_PIX_PLL 3 +#define LS2K0300_CLK_THSENS 4 +#define LS2K0300_CLK_NODE_DIV 5 +#define LS2K0300_CLK_NODE_PLL_GATE 6 +#define LS2K0300_CLK_NODE_SCALE 7 +#define LS2K0300_CLK_NODE_GATE 8 +#define LS2K0300_CLK_GMAC_DIV 9 +#define LS2K0300_CLK_GMAC_GATE 10 +#define LS2K0300_CLK_I2S_DIV 11 +#define LS2K0300_CLK_I2S_SCALE 12 +#define LS2K0300_CLK_I2S_GATE 13 +#define LS2K0300_CLK_DDR_DIV 14 +#define LS2K0300_CLK_DDR_GATE 15 +#define LS2K0300_CLK_NET_DIV 16 +#define LS2K0300_CLK_NET_GATE 17 +#define LS2K0300_CLK_DEV_DIV 18 +#define LS2K0300_CLK_DEV_GATE 19 +#define LS2K0300_CLK_PIX_DIV 20 +#define LS2K0300_CLK_PIX_PLL_GATE 21 +#define LS2K0300_CLK_PIX_SCALE 22 +#define LS2K0300_CLK_PIX_GATE 23 +#define LS2K0300_CLK_GMACBP_DIV 24 +#define LS2K0300_CLK_GMACBP_GATE 25 +#define LS2K0300_CLK_USB_SCALE 26 +#define LS2K0300_CLK_USB_GATE 27 +#define LS2K0300_CLK_APB_SCALE 28 +#define LS2K0300_CLK_APB_GATE 29 +#define LS2K0300_CLK_BOOT_SCALE 30 +#define LS2K0300_CLK_BOOT_GATE 31 +#define LS2K0300_CLK_SDIO_SCALE 32 +#define LS2K0300_CLK_SDIO_GATE 33 +#define LS2K0300_CLK_GMAC_IN 34 + #endif --=20 2.50.1 From nobody Thu Oct 2 06:18:02 2025 Received: from layka.disroot.org (layka.disroot.org [178.21.23.139]) (using TLSv1.2 with cipher ECDHE-RSA-AES128-GCM-SHA256 (128/128 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id 07EE5313D50; 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arc=none smtp.client-ip=178.21.23.139 Authentication-Results: smtp.subspace.kernel.org; dmarc=pass (p=reject dis=none) header.from=disroot.org Authentication-Results: smtp.subspace.kernel.org; spf=pass smtp.mailfrom=disroot.org Authentication-Results: smtp.subspace.kernel.org; dkim=pass (2048-bit key) header.d=disroot.org header.i=@disroot.org header.b="FKN0ZR6n" Received: from mail01.disroot.lan (localhost [127.0.0.1]) by disroot.org (Postfix) with ESMTP id 7841720CA1; Fri, 19 Sep 2025 16:27:40 +0200 (CEST) X-Virus-Scanned: SPAM Filter at disroot.org Received: from layka.disroot.org ([127.0.0.1]) by localhost (disroot.org [127.0.0.1]) (amavis, port 10024) with ESMTP id eeExqzb8AmV2; Fri, 19 Sep 2025 16:27:39 +0200 (CEST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=disroot.org; s=mail; t=1758292059; bh=W3t9oodd0h8mbXHDxSoPHsP9rVuywlZj0hRu4ydwEWo=; h=From:To:Cc:Subject:Date:In-Reply-To:References; b=FKN0ZR6n/og1Oo1c8HN37DVf7lMad1bmDYxi+TKbsgM9hUGqpJbqssZ1CaiCGu4i9 0KHUzbKoT2ZoSoqzZjr5a6uCIO9mpeqQv99MvqCp0KMd87u3URf/l/ufw/4qDts0W7 DER6fy6FO44M8bZVOmiTQMcfjH5ZRfxu0X0ZY5Lq2ZtryWSr70LE9UfjNbFuCe26T1 jOlrq7yOwAT+8I/cwUzu+oKGpdyYSjwj4dZHyrO0yy9PS0Ji+7+Yvp0HWd+lKlkYQY RuaXLq6dl+GpW5X64ssXYe8h1wb/jCjL6DDIK2XiTJDGwpjHz+Fz00OvOkJ1FNDB1r 865SzWLRFxJWg== From: Yao Zi To: Yinbo Zhu , Michael Turquette , Stephen Boyd , Rob Herring , Krzysztof Kozlowski , Conor Dooley , Huacai Chen , WANG Xuerui Cc: linux-clk@vger.kernel.org, devicetree@vger.kernel.org, linux-kernel@vger.kernel.org, loongarch@lists.linux.dev, Mingcong Bai , Kexy Biscuit , Yao Zi Subject: [PATCH v4 2/8] clk: loongson2: Allow specifying clock flags for gate clock Date: Fri, 19 Sep 2025 14:26:43 +0000 Message-ID: <20250919142649.58859-3-ziyao@disroot.org> In-Reply-To: <20250919142649.58859-1-ziyao@disroot.org> References: <20250919142649.58859-1-ziyao@disroot.org> Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Content-Type: text/plain; charset="utf-8" Some gate clocks need to be supplied with flags, e.g., it may be required to specify CLK_IS_CRTICAL for CPU clocks. Add a field to loongson2_clk_board_info for representing clock flags, and specify it when registering gate clocks. A new helper macro, CLK_GATE_FLAGS, is added to simplify definitions. Signed-off-by: Yao Zi --- drivers/clk/clk-loongson2.c | 16 +++++++++++++++- 1 file changed, 15 insertions(+), 1 deletion(-) diff --git a/drivers/clk/clk-loongson2.c b/drivers/clk/clk-loongson2.c index 27e632edd484..cc3fb13e770f 100644 --- a/drivers/clk/clk-loongson2.c +++ b/drivers/clk/clk-loongson2.c @@ -50,6 +50,7 @@ struct loongson2_clk_board_info { const char *name; const char *parent_name; unsigned long fixed_rate; + unsigned long flags; u8 reg_offset; u8 div_shift; u8 div_width; @@ -105,6 +106,18 @@ struct loongson2_clk_board_info { .bit_idx =3D _bidx, \ } =20 +#define CLK_GATE_FLAGS(_id, _name, _pname, _offset, _bidx, \ + _flags) \ + { \ + .id =3D _id, \ + .type =3D CLK_TYPE_GATE, \ + .name =3D _name, \ + .parent_name =3D _pname, \ + .reg_offset =3D _offset, \ + .bit_idx =3D _bidx, \ + .flags =3D _flags \ + } + #define CLK_FIXED(_id, _name, _pname, _rate) \ { \ .id =3D _id, \ @@ -332,7 +345,8 @@ static int loongson2_clk_probe(struct platform_device *= pdev) &clp->clk_lock); break; case CLK_TYPE_GATE: - hw =3D devm_clk_hw_register_gate(dev, p->name, p->parent_name, 0, + hw =3D devm_clk_hw_register_gate(dev, p->name, p->parent_name, + p->flags, clp->base + p->reg_offset, p->bit_idx, 0, &clp->clk_lock); --=20 2.50.1 From nobody Thu Oct 2 06:18:02 2025 Received: from layka.disroot.org (layka.disroot.org [178.21.23.139]) (using TLSv1.2 with cipher ECDHE-RSA-AES128-GCM-SHA256 (128/128 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id E8359311598; Fri, 19 Sep 2025 14:28:29 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=none smtp.client-ip=178.21.23.139 ARC-Seal: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1758292111; cv=none; b=sdAbZSjCp9o3BoNyDjMRcViVpSF5sj9DPxPqCp4sy86huyaZ1l2e/7r3Q5JI7fTpyATtl2BcVvS4GZ8rv7Kc21AEGBtxx2dyaRklsfYp9pXoR3kRug+mU86Iu2hw1IfyI75c19JTNdc/D31NPMA3FtkNCj4DusZO9vtmjicLkSQ= ARC-Message-Signature: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1758292111; c=relaxed/simple; bh=n1QnYDVCfHltlrVwLHzffulyUTZaDsxj2VCKz6sGX0E=; h=From:To:Cc:Subject:Date:Message-ID:In-Reply-To:References: MIME-Version; b=h6tam5Af1chebZzkTgBEkgJKwzhrzM/P05zogxc0Gq8nd37EWUYKC8IZH5Obop8C5xmGQScJ5+4bT2Je/pXqIUSPGEafywejE6fXuXJyoKDgfngrRe8Nrj2syoNajB+IxRaHoqTpFWWpJtXBUCkU4Ek3HO+EyjduwZ3cKYqNTqk= ARC-Authentication-Results: i=1; smtp.subspace.kernel.org; dmarc=pass (p=reject dis=none) header.from=disroot.org; spf=pass smtp.mailfrom=disroot.org; dkim=pass (2048-bit key) header.d=disroot.org header.i=@disroot.org header.b=VGS1tB3a; arc=none smtp.client-ip=178.21.23.139 Authentication-Results: smtp.subspace.kernel.org; dmarc=pass (p=reject dis=none) header.from=disroot.org Authentication-Results: smtp.subspace.kernel.org; spf=pass smtp.mailfrom=disroot.org Authentication-Results: smtp.subspace.kernel.org; dkim=pass (2048-bit key) header.d=disroot.org header.i=@disroot.org header.b="VGS1tB3a" Received: from mail01.disroot.lan (localhost [127.0.0.1]) by disroot.org (Postfix) with ESMTP id 9500420CA1; Fri, 19 Sep 2025 16:28:28 +0200 (CEST) X-Virus-Scanned: SPAM Filter at disroot.org Received: from layka.disroot.org ([127.0.0.1]) by localhost (disroot.org [127.0.0.1]) (amavis, port 10024) with ESMTP id tSjKgGo6epkK; Fri, 19 Sep 2025 16:28:28 +0200 (CEST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=disroot.org; s=mail; t=1758292108; bh=n1QnYDVCfHltlrVwLHzffulyUTZaDsxj2VCKz6sGX0E=; h=From:To:Cc:Subject:Date:In-Reply-To:References; b=VGS1tB3aQwDZB70EIbUG5O5mhxHj6j5XQ0/aEEmVE3BSht6uczZiSnLhYXcikkbaj LjGS3Eq677BSSnIWRNLWPNPwyUJcwgXoMQhbEDPFH9Hhbl46Ffp5+MI714ktzm/4qM Uios1HSKWREG1ilyZUIXijN/KM7+gPw0WkK86u4GVQqM3jOb+5ts8/bIio2HzRYTrL 1ydPwnN+1ocuz+ep1ZKVVkVO6FLnX4J8vXkMDYRehfaziyzHITFldCdb38dGHh9Snc YQnwRhfn1kD74Ou1wDXhdz+W58qw6VEFa7jeWkh+meCUzBuwI1jMWeCq1M17wo0y2h RIJi1fEaX/rwA== From: Yao Zi To: Yinbo Zhu , Michael Turquette , Stephen Boyd , Rob Herring , Krzysztof Kozlowski , Conor Dooley , Huacai Chen , WANG Xuerui Cc: linux-clk@vger.kernel.org, devicetree@vger.kernel.org, linux-kernel@vger.kernel.org, loongarch@lists.linux.dev, Mingcong Bai , Kexy Biscuit , Yao Zi Subject: [PATCH v4 3/8] clk: loongson2: Support scale clocks with an alternative mode Date: Fri, 19 Sep 2025 14:26:44 +0000 Message-ID: <20250919142649.58859-4-ziyao@disroot.org> In-Reply-To: <20250919142649.58859-1-ziyao@disroot.org> References: <20250919142649.58859-1-ziyao@disroot.org> Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Content-Type: text/plain; charset="utf-8" LS2K0300 and LS2K1500 ship scale clocks with an alternative mode. There's one mode bit in clock configuration register indicating the operation mode. When mode bit is unset, the scale clock acts the same as previous generation of scale clocks. When it's set, a different equation for calculating result frequency, Fout =3D Fin / (scale + 1), is used. This patch adds frequency calculation support for the scale clock variant. A helper macro, CLK_SCALE_MODE, is added to simplify definitions. Signed-off-by: Yao Zi --- drivers/clk/clk-loongson2.c | 26 +++++++++++++++++++++++--- 1 file changed, 23 insertions(+), 3 deletions(-) diff --git a/drivers/clk/clk-loongson2.c b/drivers/clk/clk-loongson2.c index cc3fb13e770f..bba97270376c 100644 --- a/drivers/clk/clk-loongson2.c +++ b/drivers/clk/clk-loongson2.c @@ -42,6 +42,7 @@ struct loongson2_clk_data { u8 div_width; u8 mult_shift; u8 mult_width; + u8 bit_idx; }; =20 struct loongson2_clk_board_info { @@ -96,6 +97,19 @@ struct loongson2_clk_board_info { .div_width =3D _dwidth, \ } =20 +#define CLK_SCALE_MODE(_id, _name, _pname, _offset, \ + _dshift, _dwidth, _midx) \ + { \ + .id =3D _id, \ + .type =3D CLK_TYPE_SCALE, \ + .name =3D _name, \ + .parent_name =3D _pname, \ + .reg_offset =3D _offset, \ + .div_shift =3D _dshift, \ + .div_width =3D _dwidth, \ + .bit_idx =3D _midx + 1, \ + } + #define CLK_GATE(_id, _name, _pname, _offset, _bidx) \ { \ .id =3D _id, \ @@ -243,13 +257,18 @@ static const struct clk_ops loongson2_pll_recalc_ops = =3D { static unsigned long loongson2_freqscale_recalc_rate(struct clk_hw *hw, unsigned long parent_rate) { - u64 val, mult; + u64 val, scale; + u32 mode =3D 0; struct loongson2_clk_data *clk =3D to_loongson2_clk(hw); =20 val =3D readq(clk->reg); - mult =3D loongson2_rate_part(val, clk->div_shift, clk->div_width) + 1; + scale =3D loongson2_rate_part(val, clk->div_shift, clk->div_width) + 1; + + if (clk->bit_idx) + mode =3D val & BIT(clk->bit_idx - 1); =20 - return div_u64((u64)parent_rate * mult, 8); + return mode =3D=3D 0 ? div_u64((u64)parent_rate * scale, 8) : + div_u64((u64)parent_rate, scale); } =20 static const struct clk_ops loongson2_freqscale_recalc_ops =3D { @@ -284,6 +303,7 @@ static struct clk_hw *loongson2_clk_register(struct loo= ngson2_clk_provider *clp, clk->div_width =3D cld->div_width; clk->mult_shift =3D cld->mult_shift; clk->mult_width =3D cld->mult_width; + clk->bit_idx =3D cld->bit_idx; clk->hw.init =3D &init; =20 hw =3D &clk->hw; --=20 2.50.1 From nobody Thu Oct 2 06:18:02 2025 Received: from layka.disroot.org (layka.disroot.org [178.21.23.139]) (using TLSv1.2 with cipher ECDHE-RSA-AES128-GCM-SHA256 (128/128 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id EC36A314B72; Fri, 19 Sep 2025 14:28:37 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=none smtp.client-ip=178.21.23.139 ARC-Seal: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1758292119; cv=none; b=F46qfK2qIHkTWp9KBF4Q6xCD++Yg80h2NM5oL73sI4M/WDiQlafszbFWur0kt3TDPhaNSdZ66N9aukFCSxhZXh1ZQ5TPrDvooIif1riFRjSfJ8sDy5ZIrP1ag5IKhLxC+HpXNG4Tr9HhoO4MvaR6oflvjIt49jFDx2aoTZY6xKo= ARC-Message-Signature: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1758292119; c=relaxed/simple; bh=Y3RUvEleICamic1h3jwv0FpTcfcTlZFisBVgwNksYhc=; h=From:To:Cc:Subject:Date:Message-ID:In-Reply-To:References: MIME-Version; b=J+fH5otofsKGcm1Rqjf3wmZYQzreQ59Ygy+Fzde0iZl8LcbCONTFYTr4p1We2w9XftD7OVHB+J72EVMRKBCJccUPgJHOO59o2zj/Ks91UXjMF6zJTrRP2nuK/5aowoygx/tdLBMaW3ccpuow93W/xYyLB+1X+Cglw2Enu4SgYk8= ARC-Authentication-Results: i=1; smtp.subspace.kernel.org; dmarc=pass (p=reject dis=none) header.from=disroot.org; spf=pass smtp.mailfrom=disroot.org; dkim=pass (2048-bit key) header.d=disroot.org header.i=@disroot.org header.b=bH6+Isni; arc=none smtp.client-ip=178.21.23.139 Authentication-Results: smtp.subspace.kernel.org; dmarc=pass (p=reject dis=none) header.from=disroot.org Authentication-Results: smtp.subspace.kernel.org; spf=pass smtp.mailfrom=disroot.org Authentication-Results: smtp.subspace.kernel.org; dkim=pass (2048-bit key) header.d=disroot.org header.i=@disroot.org header.b="bH6+Isni" Received: from mail01.disroot.lan (localhost [127.0.0.1]) by disroot.org (Postfix) with ESMTP id AEECB25D0C; Fri, 19 Sep 2025 16:28:36 +0200 (CEST) X-Virus-Scanned: SPAM Filter at disroot.org Received: from layka.disroot.org ([127.0.0.1]) by localhost (disroot.org [127.0.0.1]) (amavis, port 10024) with ESMTP id 9o14jLHSxmyC; Fri, 19 Sep 2025 16:28:36 +0200 (CEST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=disroot.org; s=mail; t=1758292115; bh=Y3RUvEleICamic1h3jwv0FpTcfcTlZFisBVgwNksYhc=; h=From:To:Cc:Subject:Date:In-Reply-To:References; b=bH6+Isni55SWXplpfjf+SwaM99R7vyC2kP9tfxGjvfzIvxcbgGGFg5NTqbn5FpPJx un+lVX6VK0p5u3Wbvgu41QypQqIH+ChBLeIZtF9FPJ9sQoq5OXWulPwhc3jxb1vp87 zQehbABX7hp/ynRq7tu5SZK+BJ2kWgyMaWp64gQJhtRPJAHgI7vu7U9FABl/wIuHPh TCDpmBQyvvAXNMcWAxCALGQnoNuxLUNqbbr2PC4AqE9380nESkPWIMKBxAFKJ7Fg7d LLX/X9CzTheq+fFPXTmyjta9pK8oe1YhIzorB5PNLJRBtFunzLJbDPszrxmWZGOvXW HOH4H9A9d59zQ== From: Yao Zi To: Yinbo Zhu , Michael Turquette , Stephen Boyd , Rob Herring , Krzysztof Kozlowski , Conor Dooley , Huacai Chen , WANG Xuerui Cc: linux-clk@vger.kernel.org, devicetree@vger.kernel.org, linux-kernel@vger.kernel.org, loongarch@lists.linux.dev, Mingcong Bai , Kexy Biscuit , Yao Zi Subject: [PATCH v4 4/8] clk: loongson2: Allow zero divisors for dividers Date: Fri, 19 Sep 2025 14:26:45 +0000 Message-ID: <20250919142649.58859-5-ziyao@disroot.org> In-Reply-To: <20250919142649.58859-1-ziyao@disroot.org> References: <20250919142649.58859-1-ziyao@disroot.org> Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Content-Type: text/plain; charset="utf-8" LS2K0300 and LS2K0500 ship divider clocks which allows zero divisors, in which case the divider acts the same as one is specified. Let's pass CLK_DIVIDER_ALLOW_ZERO when registering divider clocks to prepare for future introduction of these clocks. Signed-off-by: Yao Zi --- drivers/clk/clk-loongson2.c | 3 ++- 1 file changed, 2 insertions(+), 1 deletion(-) diff --git a/drivers/clk/clk-loongson2.c b/drivers/clk/clk-loongson2.c index bba97270376c..7a916c7d2718 100644 --- a/drivers/clk/clk-loongson2.c +++ b/drivers/clk/clk-loongson2.c @@ -361,7 +361,8 @@ static int loongson2_clk_probe(struct platform_device *= pdev) p->parent_name, 0, clp->base + p->reg_offset, p->div_shift, p->div_width, - CLK_DIVIDER_ONE_BASED, + CLK_DIVIDER_ONE_BASED | + CLK_DIVIDER_ALLOW_ZERO, &clp->clk_lock); break; case CLK_TYPE_GATE: --=20 2.50.1 From nobody Thu Oct 2 06:18:02 2025 Received: from layka.disroot.org (layka.disroot.org [178.21.23.139]) (using TLSv1.2 with cipher ECDHE-RSA-AES128-GCM-SHA256 (128/128 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id 2382E31328D; Fri, 19 Sep 2025 14:28:45 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=none smtp.client-ip=178.21.23.139 ARC-Seal: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1758292128; cv=none; b=sVcjTd+v55A94d44vWIitDOVfUsXM/6WWzIVKkGHep+atN9soqHq8Zc2XsRZbpX02B9tjK/MKCnwNBPjDcFLMFGyS/Nb1aPKUklQRNKeiwFegbCB/1UBAVIY1V8JLBuuVKcshAJW+eE6LTPOI1uY/juuz0C1g5YkDC7hS7AD9eU= ARC-Message-Signature: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1758292128; c=relaxed/simple; bh=fXriGpas1T/jPUZ6vBPoj62Ye2txanRp2HpIWpZxBeU=; h=From:To:Cc:Subject:Date:Message-ID:In-Reply-To:References: MIME-Version; b=qXVA/zc8+d2TlMAAaGfmgPcaxzycCAA7y06rwFphqFvFWtD4Uy+j/k2gpUnbl/gNeAVDS/vDF2wKLIn/TXFwgLQzvEanmrXeUAg2yYr/2RIIwStdhjQdKhQsF7Byl9hXb7xnts+vk6x0scXH2Oi4etyHxLNwdxsDv37Zyhcg7AQ= ARC-Authentication-Results: i=1; smtp.subspace.kernel.org; dmarc=pass (p=reject dis=none) header.from=disroot.org; spf=pass smtp.mailfrom=disroot.org; dkim=pass (2048-bit key) header.d=disroot.org header.i=@disroot.org header.b=hpLN04iC; arc=none smtp.client-ip=178.21.23.139 Authentication-Results: smtp.subspace.kernel.org; dmarc=pass (p=reject dis=none) header.from=disroot.org Authentication-Results: smtp.subspace.kernel.org; spf=pass smtp.mailfrom=disroot.org Authentication-Results: smtp.subspace.kernel.org; dkim=pass (2048-bit key) header.d=disroot.org header.i=@disroot.org header.b="hpLN04iC" Received: from mail01.disroot.lan (localhost [127.0.0.1]) by disroot.org (Postfix) with ESMTP id AC4BB25EE0; Fri, 19 Sep 2025 16:28:44 +0200 (CEST) X-Virus-Scanned: SPAM Filter at disroot.org Received: from layka.disroot.org ([127.0.0.1]) by localhost (disroot.org [127.0.0.1]) (amavis, port 10024) with ESMTP id TKAIbFlNk6pz; Fri, 19 Sep 2025 16:28:43 +0200 (CEST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=disroot.org; s=mail; t=1758292123; bh=fXriGpas1T/jPUZ6vBPoj62Ye2txanRp2HpIWpZxBeU=; h=From:To:Cc:Subject:Date:In-Reply-To:References; b=hpLN04iCgxBMMbR/GjM6ZZKPgnBHOBlldL7xMOB64U4WZr6H5Dka9G34gYKDizpv8 RKM/W0sKMAqnxPAKniXBGGZZ+WE0/pxs4ZQOEz3N+hN/k2Eor7oFAG/xXo8OZWO5Ej AhIezE/NytzTGMPl4+PQkJJ1IySEoqsPvCAG1W7VcJKpqg5T7lCyZS8TlwKVTVveJd awN4ntCYBN1nLmsh3gDfMHp6jXTyo4OUVSfctWhGVagXTkurS6JMfenCI3QCeRQclV EcRoDIDBRFk+/p8S1CSo8FNptkHMVmL4HlAttcXa9Mz+tH2GZd75nNBPsbJpcUoYqu dKCEdY70WkCyw== From: Yao Zi To: Yinbo Zhu , Michael Turquette , Stephen Boyd , Rob Herring , Krzysztof Kozlowski , Conor Dooley , Huacai Chen , WANG Xuerui Cc: linux-clk@vger.kernel.org, devicetree@vger.kernel.org, linux-kernel@vger.kernel.org, loongarch@lists.linux.dev, Mingcong Bai , Kexy Biscuit , Yao Zi Subject: [PATCH v4 5/8] clk: loongson2: Avoid hardcoding firmware name of the reference clock Date: Fri, 19 Sep 2025 14:26:46 +0000 Message-ID: <20250919142649.58859-6-ziyao@disroot.org> In-Reply-To: <20250919142649.58859-1-ziyao@disroot.org> References: <20250919142649.58859-1-ziyao@disroot.org> Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Content-Type: text/plain; charset="utf-8" Loongson-2K0300 requires a reference clock with a frequency different from previous SoCs (120MHz v.s. 100MHz), thus hardcoding the firmware name of the reference clock as ref_100m isn't a good idea. This patch retrives the clock name of the reference clock dynamically during probe, avoiding the hardcoded pdata structure and preparing for support of future SoCs. Signed-off-by: Yao Zi --- drivers/clk/clk-loongson2.c | 33 +++++++++++++++++---------------- 1 file changed, 17 insertions(+), 16 deletions(-) diff --git a/drivers/clk/clk-loongson2.c b/drivers/clk/clk-loongson2.c index 7a916c7d2718..52a9f1c2794a 100644 --- a/drivers/clk/clk-loongson2.c +++ b/drivers/clk/clk-loongson2.c @@ -13,10 +13,6 @@ #include #include =20 -static const struct clk_parent_data pdata[] =3D { - { .fw_name =3D "ref_100m", }, -}; - enum loongson2_clk_type { CLK_TYPE_PLL, CLK_TYPE_SCALE, @@ -275,7 +271,8 @@ static const struct clk_ops loongson2_freqscale_recalc_= ops =3D { .recalc_rate =3D loongson2_freqscale_recalc_rate, }; =20 -static struct clk_hw *loongson2_clk_register(struct loongson2_clk_provider= *clp, +static struct clk_hw *loongson2_clk_register(const char *parent, + struct loongson2_clk_provider *clp, const struct loongson2_clk_board_info *cld, const struct clk_ops *ops) { @@ -292,11 +289,7 @@ static struct clk_hw *loongson2_clk_register(struct lo= ongson2_clk_provider *clp, init.ops =3D ops; init.flags =3D 0; init.num_parents =3D 1; - - if (!cld->parent_name) - init.parent_data =3D pdata; - else - init.parent_names =3D &cld->parent_name; + init.parent_names =3D &parent; =20 clk->reg =3D clp->base + cld->reg_offset; clk->div_shift =3D cld->div_shift; @@ -321,11 +314,17 @@ static int loongson2_clk_probe(struct platform_device= *pdev) struct device *dev =3D &pdev->dev; struct loongson2_clk_provider *clp; const struct loongson2_clk_board_info *p, *data; + const char *refclk_name, *parent_name; =20 data =3D device_get_match_data(dev); if (!data) return -EINVAL; =20 + refclk_name =3D of_clk_get_parent_name(dev->of_node, 0); + if (IS_ERR(refclk_name)) + return dev_err_probe(dev, PTR_ERR(refclk_name), + "failed to get refclk name\n"); + for (p =3D data; p->name; p++) clks_num =3D max(clks_num, p->id + 1); =20 @@ -347,18 +346,20 @@ static int loongson2_clk_probe(struct platform_device= *pdev) =20 for (i =3D 0; i < clks_num; i++) { p =3D &data[i]; + parent_name =3D p->parent_name ? p->parent_name : refclk_name; + switch (p->type) { case CLK_TYPE_PLL: - hw =3D loongson2_clk_register(clp, p, + hw =3D loongson2_clk_register(parent_name, clp, p, &loongson2_pll_recalc_ops); break; case CLK_TYPE_SCALE: - hw =3D loongson2_clk_register(clp, p, + hw =3D loongson2_clk_register(parent_name, clp, p, &loongson2_freqscale_recalc_ops); break; case CLK_TYPE_DIVIDER: hw =3D devm_clk_hw_register_divider(dev, p->name, - p->parent_name, 0, + parent_name, 0, clp->base + p->reg_offset, p->div_shift, p->div_width, CLK_DIVIDER_ONE_BASED | @@ -366,15 +367,15 @@ static int loongson2_clk_probe(struct platform_device= *pdev) &clp->clk_lock); break; case CLK_TYPE_GATE: - hw =3D devm_clk_hw_register_gate(dev, p->name, p->parent_name, + hw =3D devm_clk_hw_register_gate(dev, p->name, parent_name, p->flags, clp->base + p->reg_offset, p->bit_idx, 0, &clp->clk_lock); break; case CLK_TYPE_FIXED: - hw =3D devm_clk_hw_register_fixed_rate_parent_data(dev, p->name, pdata, - 0, p->fixed_rate); + hw =3D devm_clk_hw_register_fixed_rate(dev, p->name, parent_name, + 0, p->fixed_rate); break; default: return dev_err_probe(dev, -EINVAL, "Invalid clk type\n"); --=20 2.50.1 From nobody Thu Oct 2 06:18:02 2025 Received: from layka.disroot.org (layka.disroot.org [178.21.23.139]) (using TLSv1.2 with cipher ECDHE-RSA-AES128-GCM-SHA256 (128/128 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id 7839B23A9AC; Fri, 19 Sep 2025 14:29:34 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=none smtp.client-ip=178.21.23.139 ARC-Seal: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1758292176; cv=none; b=JOwSh2cCcwsnN8u4VViJR6MWUVpDqLoSs1/9j+5w/lmdgwMvqfNzQWwt5XyJYGvdebRxB7Unk8fLfqX5/iSRjF4U2qH4GfV1OyNmf9Qn9LIgSdOzDvDbdt8KU8p/AAQy5EdJ6/d+QNTIbk9+mB2hj1hiXy1F3/Gg2tkImmQNzR4= ARC-Message-Signature: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1758292176; c=relaxed/simple; bh=rkiaPWg7Eq83couSMaMiPo8zFCv01nHTaMo5FT+mw8o=; h=From:To:Cc:Subject:Date:Message-ID:In-Reply-To:References: MIME-Version; b=Y9Hf5+sOUopNooaN0PQVMwEXVXTE22HQG1KEzrrNcx2Bm1PVRYbszoE1ow/fD4AgaVCIisv233spr3Bzrn+ONBww0v/r7bu3POrPiQIc3ZVJZ2f9hrQO+sothyDZ7U8iIfBVA9eHticznnXfh63Mt1d8c2cuKLKzzwZalq9pdQo= ARC-Authentication-Results: i=1; smtp.subspace.kernel.org; dmarc=pass (p=reject dis=none) header.from=disroot.org; spf=pass smtp.mailfrom=disroot.org; dkim=pass (2048-bit key) header.d=disroot.org header.i=@disroot.org header.b=ccmU0ebx; arc=none smtp.client-ip=178.21.23.139 Authentication-Results: smtp.subspace.kernel.org; dmarc=pass (p=reject dis=none) header.from=disroot.org Authentication-Results: smtp.subspace.kernel.org; spf=pass smtp.mailfrom=disroot.org Authentication-Results: smtp.subspace.kernel.org; dkim=pass (2048-bit key) header.d=disroot.org header.i=@disroot.org header.b="ccmU0ebx" Received: from mail01.disroot.lan (localhost [127.0.0.1]) by disroot.org (Postfix) with ESMTP id 0FA7C2054C; Fri, 19 Sep 2025 16:29:33 +0200 (CEST) X-Virus-Scanned: SPAM Filter at disroot.org Received: from layka.disroot.org ([127.0.0.1]) by localhost (disroot.org [127.0.0.1]) (amavis, port 10024) with ESMTP id 30aw1ciX8gjA; Fri, 19 Sep 2025 16:29:31 +0200 (CEST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=disroot.org; s=mail; t=1758292171; bh=rkiaPWg7Eq83couSMaMiPo8zFCv01nHTaMo5FT+mw8o=; h=From:To:Cc:Subject:Date:In-Reply-To:References; b=ccmU0ebxtB+npnOwEYQvNr2ryib7pPM+1K6Zm5VDN11rhGfxdcQRCgF16RN5sI/5b nxJLKsPr98SX/CRhWw5HSDQuWIz6KpJRaD2N6VBCfjUTn9+ozX47DS+UwCJhY9l7uw dqqk5BVJYxhbco6JtVWTyjAyBsC6cXjcHCjzGFuYIv0pGHdIdG+p2A2f7v3XnL969R kJflgCwgZLRA8GHKqjm0dagCnHvPNApBsy+tXgs3s2kD5tg7Up/TyFx1yJsf2JiRUn AQSxI6xb735QcGbSg3YdRDFGA0W/MGzh0IO0fKLH1Qe5nwTtw9XnmwYrzo2LvgVQ3X z0V1TmHtRzw8A== From: Yao Zi To: Yinbo Zhu , Michael Turquette , Stephen Boyd , Rob Herring , Krzysztof Kozlowski , Conor Dooley , Huacai Chen , WANG Xuerui Cc: linux-clk@vger.kernel.org, devicetree@vger.kernel.org, linux-kernel@vger.kernel.org, loongarch@lists.linux.dev, Mingcong Bai , Kexy Biscuit , Yao Zi Subject: [PATCH v4 6/8] clk: loongson2: Add clock definitions for Loongson-2K0300 SoC Date: Fri, 19 Sep 2025 14:26:47 +0000 Message-ID: <20250919142649.58859-7-ziyao@disroot.org> In-Reply-To: <20250919142649.58859-1-ziyao@disroot.org> References: <20250919142649.58859-1-ziyao@disroot.org> Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Content-Type: text/plain; charset="utf-8" The clock controller of Loongson-2K0300 consists of three PLLs, requires an 120MHz external reference clock to function, and generates clocks in various frequencies for SoC peripherals. Clock definitions for previous SoC generations could be reused for most clock hardwares. There're two gates marked as critical, clk_node_gate and clk_boot_gate, which supply the CPU cores and the system configuration bus. Disabling them leads to a SoC hang. Signed-off-by: Yao Zi --- drivers/clk/clk-loongson2.c | 46 +++++++++++++++++++++++++++++++++++++ 1 file changed, 46 insertions(+) diff --git a/drivers/clk/clk-loongson2.c b/drivers/clk/clk-loongson2.c index 52a9f1c2794a..9c4c6c99db3e 100644 --- a/drivers/clk/clk-loongson2.c +++ b/drivers/clk/clk-loongson2.c @@ -137,6 +137,51 @@ struct loongson2_clk_board_info { .fixed_rate =3D _rate, \ } =20 +static const struct loongson2_clk_board_info ls2k0300_clks[] =3D { + /* Reference Clock */ + CLK_PLL(LS2K0300_NODE_PLL, "pll_node", 0x00, 15, 9, 8, 7), + CLK_PLL(LS2K0300_DDR_PLL, "pll_ddr", 0x08, 15, 9, 8, 7), + CLK_PLL(LS2K0300_PIX_PLL, "pll_pix", 0x10, 15, 9, 8, 7), + CLK_FIXED(LS2K0300_CLK_STABLE, "clk_stable", NULL, 100000000), + CLK_FIXED(LS2K0300_CLK_THSENS, "clk_thsens", NULL, 10000000), + /* Node PLL */ + CLK_DIV(LS2K0300_CLK_NODE_DIV, "clk_node_div", "pll_node", 0x00, 24, 7), + CLK_DIV(LS2K0300_CLK_GMAC_DIV, "clk_gmac_div", "pll_node", 0x04, 0, 7), + CLK_DIV(LS2K0300_CLK_I2S_DIV, "clk_i2s_div", "pll_node", 0x04, 8, 7), + CLK_GATE(LS2K0300_CLK_NODE_PLL_GATE, "clk_node_pll_gate", "clk_node_div= ", 0x00, 0), + CLK_GATE(LS2K0300_CLK_GMAC_GATE, "clk_gmac_gate", "clk_gmac_div= ", 0x00, 1), + CLK_GATE(LS2K0300_CLK_I2S_GATE, "clk_i2s_gate", "clk_i2s_div",= 0x00, 2), + CLK_GATE_FLAGS(LS2K0300_CLK_NODE_GATE, "clk_node_gate", "clk_node_sca= le", 0x24, 0, + CLK_IS_CRITICAL), + CLK_SCALE_MODE(LS2K0300_CLK_NODE_SCALE, "clk_node_scale", "clk_node_pll_g= ate", 0x20, 0, 3, + 3), + /* DDR PLL */ + CLK_DIV(LS2K0300_CLK_DDR_DIV, "clk_ddr_div", "pll_ddr", 0x08, 24, 7), + CLK_DIV(LS2K0300_CLK_NET_DIV, "clk_net_div", "pll_ddr", 0x0c, 0, 7), + CLK_DIV(LS2K0300_CLK_DEV_DIV, "clk_dev_div", "pll_ddr", 0x0c, 8, 7), + CLK_GATE(LS2K0300_CLK_NET_GATE, "clk_net_gate", "clk_net_div", 0x08, 1), + CLK_GATE(LS2K0300_CLK_DEV_GATE, "clk_dev_gate", "clk_dev_div", 0x08, 2), + CLK_GATE_FLAGS(LS2K0300_CLK_DDR_GATE, "clk_ddr_gate", "clk_ddr_div", 0x08= , 0, + CLK_IS_CRITICAL), + /* PIX PLL */ + CLK_DIV(LS2K0300_CLK_PIX_DIV, "clk_pix_div", "pll_pix", 0x10, 24, 7), + CLK_DIV(LS2K0300_CLK_GMACBP_DIV, "clk_gmacbp_div", "pll_pix", 0x14, 0, 7), + CLK_GATE(LS2K0300_CLK_PIX_PLL_GATE, "clk_pix_pll_gate", "clk_pix_div", 0x= 10, 0), + CLK_GATE(LS2K0300_CLK_PIX_GATE, "clk_pix_gate", "clk_pix_scale", 0x24= , 6), + CLK_GATE(LS2K0300_CLK_GMACBP_GATE, "clk_gmacbp_gate", "clk_gmacbp_div", = 0x10, 1), + CLK_SCALE_MODE(LS2K0300_CLK_PIX_SCALE, "clk_pix_scale", "clk_pix_pll_gate= ", 0x20, 4, 3, 7), + /* clk_dev_gate */ + CLK_DIV(LS2K0300_CLK_SDIO_SCALE, "clk_sdio_scale", "clk_dev_gate", 0x20, = 24, 4), + CLK_GATE(LS2K0300_CLK_USB_GATE, "clk_usb_gate", "clk_usb_scale", 0x24, 2= ), + CLK_GATE(LS2K0300_CLK_SDIO_GATE, "clk_sdio_gate", "clk_sdio_scale", 0x24,= 4), + CLK_GATE(LS2K0300_CLK_APB_GATE, "clk_apb_gate", "clk_apb_scale", 0x24, 3= ), + CLK_GATE_FLAGS(LS2K0300_CLK_BOOT_GATE, "clk_boot_gate", "clk_boot_scale",= 0x24, 1, + CLK_IS_CRITICAL), + CLK_SCALE_MODE(LS2K0300_CLK_USB_SCALE, "clk_usb_scale", "clk_dev_gate",= 0x20, 12, 3, 15), + CLK_SCALE_MODE(LS2K0300_CLK_APB_SCALE, "clk_apb_scale", "clk_dev_gate",= 0x20, 16, 3, 19), + CLK_SCALE_MODE(LS2K0300_CLK_BOOT_SCALE, "clk_boot_scale", "clk_dev_gate",= 0x20, 8, 3, 11), +}; + static const struct loongson2_clk_board_info ls2k0500_clks[] =3D { CLK_PLL(LOONGSON2_NODE_PLL, "pll_node", 0, 16, 8, 8, 6), CLK_PLL(LOONGSON2_DDR_PLL, "pll_ddr", 0x8, 16, 8, 8, 6), @@ -393,6 +438,7 @@ static int loongson2_clk_probe(struct platform_device *= pdev) } =20 static const struct of_device_id loongson2_clk_match_table[] =3D { + { .compatible =3D "loongson,ls2k0300-clk", .data =3D &ls2k0300_clks }, { .compatible =3D "loongson,ls2k0500-clk", .data =3D &ls2k0500_clks }, { .compatible =3D "loongson,ls2k-clk", .data =3D &ls2k1000_clks }, { .compatible =3D "loongson,ls2k2000-clk", .data =3D &ls2k2000_clks }, --=20 2.50.1 From nobody Thu Oct 2 06:18:02 2025 Received: from layka.disroot.org (layka.disroot.org [178.21.23.139]) (using TLSv1.2 with cipher ECDHE-RSA-AES128-GCM-SHA256 (128/128 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id EE5C6313D5C; Fri, 19 Sep 2025 14:29:40 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=none smtp.client-ip=178.21.23.139 ARC-Seal: i=1; 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charset="utf-8" Describe the clock controller integrated in Loongson-2K0300 SoC and clocks for UARTs. Signed-off-by: Yao Zi --- arch/loongarch/boot/dts/loongson-2k0300.dtsi | 16 +++++++++++++--- 1 file changed, 13 insertions(+), 3 deletions(-) diff --git a/arch/loongarch/boot/dts/loongson-2k0300.dtsi b/arch/loongarch/= boot/dts/loongson-2k0300.dtsi index ce3574691aa9..ddc2e2697838 100644 --- a/arch/loongarch/boot/dts/loongson-2k0300.dtsi +++ b/arch/loongarch/boot/dts/loongson-2k0300.dtsi @@ -6,6 +6,7 @@ =20 /dts-v1/; =20 +#include #include =20 / { @@ -21,7 +22,7 @@ cpu0: cpu@0 { compatible =3D "loongson,la264"; reg =3D <0>; device_type =3D "cpu"; - clocks =3D <&cpu_clk>; + clocks =3D <&clk LS2K0300_CLK_NODE_GATE>; }; =20 }; @@ -32,9 +33,10 @@ cpuintc: interrupt-controller { #interrupt-cells =3D <1>; }; =20 - cpu_clk: clock-1000m { + refclk: clock-120m { compatible =3D "fixed-clock"; - clock-frequency =3D <1000000000>; + clock-frequency =3D <120000000>; + clock-output-names =3D "refclk_120m"; #clock-cells =3D <0>; }; =20 @@ -46,6 +48,13 @@ soc@10000000 { <0x00 0x02000000 0x00 0x02000000 0x0 0x04000000>, <0x00 0x40000000 0x00 0x40000000 0x0 0x40000000>; =20 + clk: clock-controller@16000400 { + compatible =3D "loongson,ls2k0300-clk"; + reg =3D <0x0 0x16000400 0x0 0x30>; + clocks =3D <&refclk>; + #clock-cells =3D <1>; + }; + liointc0: interrupt-controller@16001400 { compatible =3D "loongson,liointc-2.0"; reg =3D <0x0 0x16001400 0x0 0x40>, @@ -87,6 +96,7 @@ liointc1: interrupt-controller@16001440 { uart0: serial@16100000 { compatible =3D "ns16550a"; reg =3D <0 0x16100000 0 0x10>; + clocks =3D <&clk LS2K0300_CLK_APB_GATE>; interrupt-parent =3D <&liointc0>; interrupts =3D <0 IRQ_TYPE_LEVEL_HIGH>; no-loopback-test; --=20 2.50.1 From nobody Thu Oct 2 06:18:02 2025 Received: from layka.disroot.org (layka.disroot.org [178.21.23.139]) (using TLSv1.2 with cipher ECDHE-RSA-AES128-GCM-SHA256 (128/128 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id 716DA315783; Fri, 19 Sep 2025 14:29:49 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=none smtp.client-ip=178.21.23.139 ARC-Seal: i=1; a=rsa-sha256; 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spf=pass smtp.mailfrom=disroot.org Authentication-Results: smtp.subspace.kernel.org; dkim=pass (2048-bit key) header.d=disroot.org header.i=@disroot.org header.b="BQOMoimQ" Received: from mail01.disroot.lan (localhost [127.0.0.1]) by disroot.org (Postfix) with ESMTP id 059042054C; Fri, 19 Sep 2025 16:29:48 +0200 (CEST) X-Virus-Scanned: SPAM Filter at disroot.org Received: from layka.disroot.org ([127.0.0.1]) by localhost (disroot.org [127.0.0.1]) (amavis, port 10024) with ESMTP id tBBtd3IQlEy2; Fri, 19 Sep 2025 16:29:46 +0200 (CEST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=disroot.org; s=mail; t=1758292186; bh=81PMYlqM/y1cobIvGWv6NmLT8uHoL246gy0zJP1C1Hk=; h=From:To:Cc:Subject:Date:In-Reply-To:References; b=BQOMoimQpdAVlc0FjdRCdRXrc9RdGZlN5x5GcNVaZTZroEZ4irVCJF+dvkIeNZ4yd F+YHKnSE3/oSxm5E6USKGj4LaChrpfN4ZVmClHDRtvQYi/lQsUWKdf5zgwvbeXr4Gc r7An77PaG7TYJA8d1JqqQb/0Vi6DwVmSrOrtxAt+hc0KNtSCpnx/OagWgkMuOLfnR6 gJ1Q1bgfy1ckEjOzwlIdFrLVUwHNHtNiP+n/aQXZyR95JqDpP1e2ZnLlG6mmzIVkl0 J9k+g5S+DFWrc8P6KOteGN6FCPL1La1AHw9S6kbyJyMlS3OwghbVursrksVnp9MHjm d7vEjb8yD3Oyw== From: Yao Zi To: Yinbo Zhu , Michael Turquette , Stephen Boyd , Rob Herring , Krzysztof Kozlowski , Conor Dooley , Huacai Chen , WANG Xuerui Cc: linux-clk@vger.kernel.org, devicetree@vger.kernel.org, linux-kernel@vger.kernel.org, loongarch@lists.linux.dev, Mingcong Bai , Kexy Biscuit , Yao Zi Subject: [PATCH v4 8/8] LoongArch: dts: Remove clock-frquency from UART0 of CTCISZ Forever Pi Date: Fri, 19 Sep 2025 14:26:49 +0000 Message-ID: <20250919142649.58859-9-ziyao@disroot.org> In-Reply-To: <20250919142649.58859-1-ziyao@disroot.org> References: <20250919142649.58859-1-ziyao@disroot.org> Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Content-Type: text/plain; charset="utf-8" The property isn't required anymore as the supply clock of UART0 has been described. Signed-off-by: Yao Zi --- arch/loongarch/boot/dts/loongson-2k0300-ctcisz-forever-pi.dts | 1 - 1 file changed, 1 deletion(-) diff --git a/arch/loongarch/boot/dts/loongson-2k0300-ctcisz-forever-pi.dts = b/arch/loongarch/boot/dts/loongson-2k0300-ctcisz-forever-pi.dts index a033c086461f..1bdfff7fae92 100644 --- a/arch/loongarch/boot/dts/loongson-2k0300-ctcisz-forever-pi.dts +++ b/arch/loongarch/boot/dts/loongson-2k0300-ctcisz-forever-pi.dts @@ -40,6 +40,5 @@ linux,cma { }; =20 &uart0 { - clock-frequency =3D <100000000>; status =3D "okay"; }; --=20 2.50.1