From nobody Thu Oct 2 09:19:22 2025 Received: from fllvem-ot03.ext.ti.com (fllvem-ot03.ext.ti.com [198.47.19.245]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id 741AB261B9D; Fri, 19 Sep 2025 03:29:16 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=none smtp.client-ip=198.47.19.245 ARC-Seal: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1758252559; cv=none; b=LiGe43YVfriDXes+v3K68AEEQ87MvJkw3TB9HtI8ZKkMZ+uKT3sQUn/jgVr5Pb//6A8cA6xXrnzMWVYlQF/68tOhsy0NnjW5HvLHPmJFw5LkVJZtmw/k2AL7RdaJ3pUIn35N+Eza7yQ7O6LIQTbuJxRlFuwfTvX3Kzw0Ce2SAd0= ARC-Message-Signature: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1758252559; c=relaxed/simple; bh=XX/ETdVeB+tWiTK6nhzx1udiFh8XwGiFmQJIW3mpeHo=; h=From:To:CC:Subject:Date:Message-ID:In-Reply-To:References: MIME-Version:Content-Type; b=SQPFC58WHvzPKbjKocposzQz0nhuEPy3kd2gED4e57k4lN2v29V6pIX7ms/80bkcy/ytd1Vy9EPfHwGDwjABSwodwUrTnVb2KDBYVpSEClGpPt/8AhcZbitVrFig5yeHbWrK8KcQkjUSvPylblxCvARuBane5wDJ580wdddevvo= ARC-Authentication-Results: i=1; smtp.subspace.kernel.org; dmarc=pass (p=quarantine dis=none) header.from=ti.com; spf=pass smtp.mailfrom=ti.com; dkim=pass (1024-bit key) header.d=ti.com header.i=@ti.com header.b=Qdl8Y53U; arc=none smtp.client-ip=198.47.19.245 Authentication-Results: smtp.subspace.kernel.org; dmarc=pass (p=quarantine dis=none) header.from=ti.com Authentication-Results: smtp.subspace.kernel.org; spf=pass smtp.mailfrom=ti.com Authentication-Results: smtp.subspace.kernel.org; dkim=pass (1024-bit key) header.d=ti.com header.i=@ti.com header.b="Qdl8Y53U" Received: from lelvem-sh01.itg.ti.com ([10.180.77.71]) by fllvem-ot03.ext.ti.com (8.15.2/8.15.2) with ESMTP id 58J3TAdj151745; Thu, 18 Sep 2025 22:29:10 -0500 DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=ti.com; s=ti-com-17Q1; t=1758252550; bh=LY00hGaHj82HQ41hMnhsfZ2aVqFf+c85vwEv6CG/hV8=; h=From:To:CC:Subject:Date:In-Reply-To:References; b=Qdl8Y53USuhdTiunKo6fQa1kmkalr2rwMIlXc+e+xwlV5rBVYStbd6KMRaqkCHIhI xvgDXGuzujZKGsbjZ8iwDAnsul5PLLeukW07Sn5byg23qn2vigU6kSMm8JWWygBACh cZ1qUMb3TGHrPnPTvihf5GiYt2b01ReLPnFgxCRM= Received: from DLEE109.ent.ti.com (dlee109.ent.ti.com [157.170.170.41]) by lelvem-sh01.itg.ti.com (8.18.1/8.18.1) with ESMTPS id 58J3TAsQ2029083 (version=TLSv1.2 cipher=ECDHE-RSA-AES128-SHA256 bits=128 verify=FAIL); Thu, 18 Sep 2025 22:29:10 -0500 Received: from DLEE206.ent.ti.com (157.170.170.90) by DLEE109.ent.ti.com (157.170.170.41) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_128_CBC_SHA256_P256) id 15.1.2507.55; Thu, 18 Sep 2025 22:29:10 -0500 Received: from lelvem-mr05.itg.ti.com (10.180.75.9) by DLEE206.ent.ti.com (157.170.170.90) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_256_GCM_SHA384) id 15.2.2562.20 via Frontend Transport; Thu, 18 Sep 2025 22:29:10 -0500 Received: from localhost (ula0502350.dhcp.ti.com [172.24.233.249]) by lelvem-mr05.itg.ti.com (8.18.1/8.18.1) with ESMTP id 58J3T8mY1901500; Thu, 18 Sep 2025 22:29:09 -0500 From: Paresh Bhagat To: , , CC: , , , , , , , , , , , Subject: [PATCH 2/2] arm64: dts: ti: k3-am62d2-evm: Enable PMIC Date: Fri, 19 Sep 2025 08:58:06 +0530 Message-ID: <20250919032806.707926-3-p-bhagat@ti.com> X-Mailer: git-send-email 2.34.1 In-Reply-To: <20250919032806.707926-1-p-bhagat@ti.com> References: <20250919032806.707926-1-p-bhagat@ti.com> Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable X-C2ProcessedOrg: 333ef613-75bf-4e12-a4b1-8e3623f5dcea Content-Type: text/plain; charset="utf-8" Add support for TPS65224 PMIC family on wakeup I2C0 bus. This=20 device provides regulators (bucks and LDOs), along with GPIOs,=20 and monitors SOC's MCU error signal. Signed-off-by: Paresh Bhagat --- arch/arm64/boot/dts/ti/k3-am62d2-evm.dts | 91 ++++++++++++++++++++++++ 1 file changed, 91 insertions(+) diff --git a/arch/arm64/boot/dts/ti/k3-am62d2-evm.dts b/arch/arm64/boot/dts= /ti/k3-am62d2-evm.dts index 9a74df221f2a..155abd97b799 100644 --- a/arch/arm64/boot/dts/ti/k3-am62d2-evm.dts +++ b/arch/arm64/boot/dts/ti/k3-am62d2-evm.dts @@ -214,6 +214,14 @@ AM62DX_MCU_IOPAD(0x0030, PIN_OUTPUT, 0) /* (C8) WKUP_U= ART0_RTSn */ >; bootph-all; }; + + wkup_i2c0_pins_default: wkup-i2c0-default-pins { + pinctrl-single,pins =3D < + AM62DX_MCU_IOPAD(0x004c, PIN_INPUT, 0) /* (D13) WKUP_I2C0_SCL */ + AM62DX_MCU_IOPAD(0x0050, PIN_INPUT, 0) /* (E13) WKUP_I2C0_SDA */ + >; + bootph-all; + }; }; =20 /* WKUP UART0 is used for DM firmware logs */ @@ -464,6 +472,89 @@ &main_i2c2 { status =3D "okay"; }; =20 +&wkup_i2c0 { + pinctrl-names =3D "default"; + pinctrl-0 =3D <&wkup_i2c0_pins_default>; + clock-frequency =3D <400000>; + status =3D "okay"; + + tps65224: pmic@48 { + compatible =3D "ti,tps65224-q1"; + reg =3D <0x48>; + pinctrl-names =3D "default"; + pinctrl-0 =3D <&pmic_irq_pins_default>; + interrupt-parent =3D <&main_gpio1>; + interrupts =3D <31 IRQ_TYPE_EDGE_FALLING>; + ti,primary-pmic; + + gpio-controller; + #gpio-cells =3D <2>; + + buck12-supply =3D <&vcc_3v3_sys>; + buck3-supply =3D <&vcc_3v3_sys>; + buck4-supply =3D <&vcc_3v3_sys>; + ldo1-supply =3D <&vcc_3v3_sys>; + ldo2-supply =3D <&vcc_3v3_sys>; + ldo3-supply =3D <&vcc_3v3_sys>; + + regulators { + buck12: buck12 { + regulator-name =3D "vdd_core"; + regulator-min-microvolt =3D <850000>; + regulator-max-microvolt =3D <850000>; + regulator-boot-on; + regulator-always-on; + bootph-all; + }; + + buck3: buck3 { + regulator-name =3D "dvdd1v8"; + regulator-min-microvolt =3D <1800000>; + regulator-max-microvolt =3D <1800000>; + regulator-boot-on; + regulator-always-on; + bootph-all; + }; + + buck4: buck4 { + regulator-name =3D "vdds_ddr"; + regulator-min-microvolt =3D <1100000>; + regulator-max-microvolt =3D <1100000>; + regulator-boot-on; + regulator-always-on; + bootph-all; + }; + + ldo1: ldo1 { + regulator-name =3D "vdda_1v8"; + regulator-min-microvolt =3D <1800000>; + regulator-max-microvolt =3D <1800000>; + regulator-boot-on; + regulator-always-on; + bootph-all; + }; + + ldo2: ldo2 { + regulator-name =3D "dvdd3v3"; + regulator-min-microvolt =3D <3300000>; + regulator-max-microvolt =3D <3300000>; + regulator-boot-on; + regulator-always-on; + bootph-all; + }; + + ldo3: ldo3 { + regulator-name =3D "vddr_core"; + regulator-min-microvolt =3D <850000>; + regulator-max-microvolt =3D <850000>; + regulator-boot-on; + regulator-always-on; + bootph-all; + }; + }; + }; +}; + &sdhci0 { /* eMMC */ non-removable; --=20 2.34.1