From nobody Thu Oct 2 09:22:07 2025 Received: from mail-pl1-f201.google.com (mail-pl1-f201.google.com [209.85.214.201]) (using TLSv1.2 with cipher ECDHE-RSA-AES128-GCM-SHA256 (128/128 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id 99D4E18C2C for ; Fri, 19 Sep 2025 00:45:20 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=none smtp.client-ip=209.85.214.201 ARC-Seal: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1758242722; cv=none; b=joRGH3+9iCEAJaP3dUQMVcBINRVQ8okeiELW5KMlamYyGmMj66htznBlLPDU+i4hD3uvlBH6vEaYCgYhb0q6f53+zGMuiusjlqfwk2P7Urt+x57MDdfqEOaQ4EyQN5BZvP7GqzONSD4PvvlEKqT3gQvpV38p0efYgw18FYmBxOY= ARC-Message-Signature: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1758242722; c=relaxed/simple; bh=G6eMhQa9bWNC+XplAop1XK+Xh9jgbUrMu5W7u7341tE=; h=Date:In-Reply-To:Mime-Version:References:Message-ID:Subject:From: To:Cc:Content-Type; b=k0+B6NHDOGtxp/tn1ej/7hFwMPKicGGTf1Yfb4wzKe6xOQ1bQihyzhoDbX2gcghXhBQV9UesA5Sg36MpfuwdcheVkBsO/3QfSlgK8+VyDEDvhd7JlFJ1nOfZBn+AKi+vobfs2S2I8lOfGzI7hGdy19CcdYSUUEM2Grlr99joP+M= ARC-Authentication-Results: i=1; smtp.subspace.kernel.org; dmarc=pass (p=reject dis=none) header.from=google.com; spf=pass smtp.mailfrom=flex--seanjc.bounces.google.com; dkim=pass (2048-bit key) header.d=google.com header.i=@google.com header.b=a9sUMLYD; arc=none smtp.client-ip=209.85.214.201 Authentication-Results: smtp.subspace.kernel.org; dmarc=pass (p=reject dis=none) header.from=google.com Authentication-Results: smtp.subspace.kernel.org; spf=pass smtp.mailfrom=flex--seanjc.bounces.google.com Authentication-Results: smtp.subspace.kernel.org; dkim=pass (2048-bit key) header.d=google.com header.i=@google.com header.b="a9sUMLYD" Received: by mail-pl1-f201.google.com with SMTP id d9443c01a7336-2445805d386so17578475ad.1 for ; Thu, 18 Sep 2025 17:45:20 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=20230601; t=1758242720; x=1758847520; darn=vger.kernel.org; h=cc:to:from:subject:message-id:references:mime-version:in-reply-to :date:reply-to:from:to:cc:subject:date:message-id:reply-to; bh=vXIBv0GQwub5RA4uH8L4E8fQo/KxZfvrFKX34u31kBs=; b=a9sUMLYDx+78mOE2FcKlLpy4gjpX1fu9Gxwi0jp/nJMQqf2mnWabqaM9MViPJc/63k 6rZZnG+8FOcWMMe6S4SlZ92JeQ4LLO83U2JN+33RWw+D0bC0tVrD5+qeOCr1QkpIKr9b qPk1eJpHspO4i15kmQS6EFuWzhxmAO2/bHemtFLG7YriZUZHWk5hNd4K243PSvQoMXeQ m7GPu7C+VGvKVYgoSOn3Hrb+iQjlQsyssYEyVXxkiBXZaTSq7P/Z/XXpRucfEMy9TbnF 0A63Knh8O3KkQp8nWpPiU6zZN8kSd/wxlRlUd41WFc4UVQDW+8uGYJdqSk8iEi3DUgoI mkaQ== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20230601; t=1758242720; x=1758847520; h=cc:to:from:subject:message-id:references:mime-version:in-reply-to :date:reply-to:x-gm-message-state:from:to:cc:subject:date:message-id :reply-to; bh=vXIBv0GQwub5RA4uH8L4E8fQo/KxZfvrFKX34u31kBs=; b=nen9yWuSf7LWoyU+zD20stljq37B5erDXPcl/RJe2U4hhgCH5drB/jOmiDrkgxc753 M0F6iVuB35HJ25jklznS8R4hj9A2hTeyvNQzMCYUB7u4KEt9l7/0byIgY2QQVFpzr7yC 95qI06UIQJi+Hs7y+S6ZUCl0Zz/uguur+SczgS7Bl9r/G7ETjQK3XN6pqn2FkydZwGBu +jvC9m6BBStKJUzJu6AiBMfbo0VzMLR/KkkEVSYbNpG6UxVtWTm4VWKmGWrUkC5rvBdW NrJ4qv3MtLFjrPIsSA07tydS92KVJ9uHw5gHjHvwKLhilE2Isq9SlzyK3/YvZkOACPVD 2ZQQ== X-Forwarded-Encrypted: i=1; AJvYcCXTqpV050jRzWMggkbRj9xi/1e6KU3tr+nf6xMbvQs3OCinG/GIA9kDlHME9lBtWeyeL6WhZs24ZOr6icU=@vger.kernel.org X-Gm-Message-State: AOJu0Ywc9/U8Uk+dvMMDpNxnMMaprxLFXf2xKo9gD9RSUCfZae26Mjxu G8uJ9iBmPmdyoXngI7JioQzhCPNnsZjyasQQ8aleQ8c59f6yyXCAgFfRDmVM0XMPgci9W7jdEfC jGHuqYA== X-Google-Smtp-Source: AGHT+IH4P8o7YsHg2AvqNf6MyeD4mOg5GT4mfEZFfwOPrDg+yC4Lmup3ALcz80Gr9PLAOz55sh2XicSWDG0= X-Received: from pjc6.prod.google.com ([2002:a17:90b:2f46:b0:329:d461:9889]) (user=seanjc job=prod-delivery.src-stubby-dispatcher) by 2002:a17:903:2ac7:b0:264:4e4a:904d with SMTP id d9443c01a7336-269ba431f33mr17669575ad.15.1758242719892; Thu, 18 Sep 2025 17:45:19 -0700 (PDT) Reply-To: Sean Christopherson Date: Thu, 18 Sep 2025 17:45:10 -0700 In-Reply-To: <20250919004512.1359828-1-seanjc@google.com> Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: Mime-Version: 1.0 References: <20250919004512.1359828-1-seanjc@google.com> X-Mailer: git-send-email 2.51.0.470.ga7dc726c21-goog Message-ID: <20250919004512.1359828-4-seanjc@google.com> Subject: [PATCH v3 3/5] KVM: selftests: Reduce number of "unavailable PMU events" combos tested From: Sean Christopherson To: Sean Christopherson , Paolo Bonzini Cc: kvm@vger.kernel.org, linux-kernel@vger.kernel.org, Dapeng Mi , Yi Lai , dongsheng Content-Transfer-Encoding: quoted-printable Content-Type: text/plain; charset="utf-8" Reduce the number of combinations of unavailable PMU events masks that are testing by the PMU counters test. In reality, testing every possible combination isn't all that interesting, and certainly not worth the tens of seconds (or worse, minutes) of runtime. Fully testing the N^2 space will be especially problematic in the near future, as 5! new arch events are on their way. Use alternating bit patterns (and 0 and -1u) in the hopes that _if_ there is ever a KVM bug, it's not something horribly convoluted that shows up only with a super specific pattern/value. Reported-by: Dapeng Mi Signed-off-by: Sean Christopherson Reviewed-by: Dapeng Mi --- .../selftests/kvm/x86/pmu_counters_test.c | 38 +++++++++++-------- 1 file changed, 23 insertions(+), 15 deletions(-) diff --git a/tools/testing/selftests/kvm/x86/pmu_counters_test.c b/tools/te= sting/selftests/kvm/x86/pmu_counters_test.c index cfeed0103341..e805882bc306 100644 --- a/tools/testing/selftests/kvm/x86/pmu_counters_test.c +++ b/tools/testing/selftests/kvm/x86/pmu_counters_test.c @@ -577,6 +577,26 @@ static void test_intel_counters(void) PMU_CAP_FW_WRITES, }; =20 + /* + * To keep the total runtime reasonable, test only a handful of select, + * semi-arbitrary values for the mask of unavailable PMU events. Test + * 0 (all events available) and all ones (no events available) as well + * as alternating bit sequencues, e.g. to detect if KVM is checking the + * wrong bit(s). + */ + const uint32_t unavailable_masks[] =3D { + 0x0, + 0xffffffffu, + 0xaaaaaaaau, + 0x55555555u, + 0xf0f0f0f0u, + 0x0f0f0f0fu, + 0xa0a0a0a0u, + 0x0a0a0a0au, + 0x50505050u, + 0x05050505u, + }; + /* * Test up to PMU v5, which is the current maximum version defined by * Intel, i.e. is the last version that is guaranteed to be backwards @@ -614,16 +634,7 @@ static void test_intel_counters(void) =20 pr_info("Testing arch events, PMU version %u, perf_caps =3D %lx\n", v, perf_caps[i]); - /* - * To keep the total runtime reasonable, test every - * possible non-zero, non-reserved bitmap combination - * only with the native PMU version and the full bit - * vector length. - */ - if (v =3D=3D pmu_version) { - for (k =3D 1; k < (BIT(NR_INTEL_ARCH_EVENTS) - 1); k++) - test_arch_events(v, perf_caps[i], NR_INTEL_ARCH_EVENTS, k); - } + /* * Test single bits for all PMU version and lengths up * the number of events +1 (to verify KVM doesn't do @@ -632,11 +643,8 @@ static void test_intel_counters(void) * ones i.e. all events being available and unavailable. */ for (j =3D 0; j <=3D NR_INTEL_ARCH_EVENTS + 1; j++) { - test_arch_events(v, perf_caps[i], j, 0); - test_arch_events(v, perf_caps[i], j, -1u); - - for (k =3D 0; k < NR_INTEL_ARCH_EVENTS; k++) - test_arch_events(v, perf_caps[i], j, BIT(k)); + for (k =3D 1; k < ARRAY_SIZE(unavailable_masks); k++) + test_arch_events(v, perf_caps[i], j, unavailable_masks[k]); } =20 pr_info("Testing GP counters, PMU version %u, perf_caps =3D %lx\n", --=20 2.51.0.470.ga7dc726c21-goog