From nobody Thu Oct 2 07:43:59 2025 Received: from mail-pf1-f201.google.com (mail-pf1-f201.google.com [209.85.210.201]) (using TLSv1.2 with cipher ECDHE-RSA-AES128-GCM-SHA256 (128/128 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id 5E9311F12E9 for ; Fri, 19 Sep 2025 00:21:41 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=none smtp.client-ip=209.85.210.201 ARC-Seal: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1758241302; cv=none; b=iMUlCP8XRYyRD0NI0hhoUpg/TXszsJGz/JHQ5ELAf2/Q8aMtmuFio/mJavCT8S3+50BDDSjJdFoo9nSyBIj0x3V1DWctZBymPrxAPzX1BNkA0QwxFbAepMQ1vWgPrBRrTCYTSEyQCqKfkDvixIN8im6ERO3W+iyDwZ5fy5sV16U= ARC-Message-Signature: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1758241302; c=relaxed/simple; bh=/XQgV9lw0lISZp958KTVvYPoycL/V0iemplIXqSLSwE=; h=Date:In-Reply-To:Mime-Version:References:Message-ID:Subject:From: To:Cc:Content-Type; b=eRb33iJOdX6rAg0vHyfDa460QAJzaVU8/GAO6QIKypIf9oB7khafiyrMlvzxICr61v+xfLCTbuhsVLq68k6KH1UIHuRA5OrEPlgumgw1MejqvTb9Ckt4vtmVuGvoXcreCoGZkZB56eEgK0LbRb4e3XJTaUeHSLHD7BzktqtQHJM= ARC-Authentication-Results: i=1; smtp.subspace.kernel.org; dmarc=pass (p=reject dis=none) header.from=google.com; spf=pass smtp.mailfrom=flex--seanjc.bounces.google.com; dkim=pass (2048-bit key) header.d=google.com header.i=@google.com header.b=Co6YmxRO; arc=none smtp.client-ip=209.85.210.201 Authentication-Results: smtp.subspace.kernel.org; dmarc=pass (p=reject dis=none) header.from=google.com Authentication-Results: smtp.subspace.kernel.org; spf=pass smtp.mailfrom=flex--seanjc.bounces.google.com Authentication-Results: smtp.subspace.kernel.org; dkim=pass (2048-bit key) header.d=google.com header.i=@google.com header.b="Co6YmxRO" Received: by mail-pf1-f201.google.com with SMTP id d2e1a72fcca58-77e7808cf4bso177017b3a.0 for ; Thu, 18 Sep 2025 17:21:41 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=20230601; t=1758241301; x=1758846101; darn=vger.kernel.org; h=cc:to:from:subject:message-id:references:mime-version:in-reply-to :date:reply-to:from:to:cc:subject:date:message-id:reply-to; bh=VT6pMOa7Bss0kSmnUFjjTDbwGWcOEihwse0RPF9AM0Y=; b=Co6YmxRO17XWkuLfGIGOHZ7J1p0ePfyrSXkyNe0UWxQmtAxUfpDILJX0lEg+yPq4GQ UZx9S86+qdGWpUJRxP4OwMeqT2zO2b4VOZMIhtI3KGF0LhLe5CJPbH8zwYrL5ZoP9zKB jbPOAlg/il5XQ096PrRoXKBJ16xCC456AmfcO1OZAr5ilw7ERbkr0inN/YHGoKtqs1kk L/VBSn5N+UyTVN4vO6QukHC+qdUVFg4NdCXzD4CnfRxSlR0/nSaJS21OxN88JGJKR7f7 UtHKWY9W8SUZPj0ISJLBo0yMlJeb73ecZx/gtMyoGxvPLWnQ4AZbkxDSVMSfA54ZeJRD Fz7Q== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20230601; t=1758241301; x=1758846101; h=cc:to:from:subject:message-id:references:mime-version:in-reply-to :date:reply-to:x-gm-message-state:from:to:cc:subject:date:message-id :reply-to; bh=VT6pMOa7Bss0kSmnUFjjTDbwGWcOEihwse0RPF9AM0Y=; b=EekR2oVACJkVVcB7jjhAUDUM71h0f/OLlItYff4JXm31zxXuwDw34KuLdpaa3bwhtS opUknDX4Ke4M1tVGXTchMSXH6aJ4YSYDUCb2WwHFgQcYjvcja3sJDzTsgqPteDIkbizx 4XHRzXhoyR9t99vo+Ub/v0MJqR+RSFMGODr+SxH0XDESRA67mScEbDZLlX0kUUf5nCC4 rGkD2OydsLuxHRNRYo2+8HRbSeGhLnJJqq6K6mXN6sIgvS5APCYtcEj8KTi4oaBCjKSk Kpsi56IGuHex+55Tc2sA7ybjRMoSoDpkdRNGPJigO0NCgb+XK5XWbMTyh+X3N279XzEo ZoDg== X-Forwarded-Encrypted: i=1; AJvYcCUvJKjVw324x+4Zmd1zkp8/vJ2pkE6pFv5Q1YHsoLFzx1WgV7qAlO6aWdhDMwD78hUliNW47qm1t23b1cw=@vger.kernel.org X-Gm-Message-State: AOJu0YxCWoeeiaVDD/l37r01D7joeToS9yGveuVQhx+SxbhU/UXvpfJO l44WkScio1USy9747b8IWD/XZMR/rNY1atHb7GM3gCNUgCAwTGGkNWqL6wP5vzmuoaAzh/C/YYa rNijRkQ== X-Google-Smtp-Source: AGHT+IGrCgRfUl52q+9Dm1SUPPCGRTzb2repp5WB05Y7Tt3MOB2S+vnmenaNajU41khUfolPBUODsZW1t3U= X-Received: from pjl5.prod.google.com ([2002:a17:90b:2f85:b0:32e:2405:c7ab]) (user=seanjc job=prod-delivery.src-stubby-dispatcher) by 2002:a05:6a20:914d:b0:27b:dcba:a8f3 with SMTP id adf61e73a8af0-2925f76be25mr2050578637.15.1758241300709; Thu, 18 Sep 2025 17:21:40 -0700 (PDT) Reply-To: Sean Christopherson Date: Thu, 18 Sep 2025 17:21:31 -0700 In-Reply-To: <20250919002136.1349663-1-seanjc@google.com> Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: Mime-Version: 1.0 References: <20250919002136.1349663-1-seanjc@google.com> X-Mailer: git-send-email 2.51.0.470.ga7dc726c21-goog Message-ID: <20250919002136.1349663-2-seanjc@google.com> Subject: [PATCH v3 1/6] KVM: SVM: Move x2AVIC MSR interception helper to avic.c From: Sean Christopherson To: Sean Christopherson , Paolo Bonzini Cc: kvm@vger.kernel.org, linux-kernel@vger.kernel.org, Naveen N Rao Content-Transfer-Encoding: quoted-printable Content-Type: text/plain; charset="utf-8" Move svm_set_x2apic_msr_interception() to avic.c as it's only relevant when x2AVIC is enabled/supported and only called by AVIC code. In addition to scoping AVIC code to avic.c, this will allow burying the global x2avic_enabled variable in avic. Opportunistically rename the helper to explicitly scope it to "avic". No functional change intended. Signed-off-by: Sean Christopherson Reviewed-by: Naveen N Rao (AMD) Tested-by: Naveen N Rao (AMD) --- arch/x86/kvm/svm/avic.c | 57 ++++++++++++++++++++++++++++++++++++++--- arch/x86/kvm/svm/svm.c | 49 ----------------------------------- arch/x86/kvm/svm/svm.h | 1 - 3 files changed, 54 insertions(+), 53 deletions(-) diff --git a/arch/x86/kvm/svm/avic.c b/arch/x86/kvm/svm/avic.c index a34c5c3b164e..478a18208a76 100644 --- a/arch/x86/kvm/svm/avic.c +++ b/arch/x86/kvm/svm/avic.c @@ -79,6 +79,57 @@ static bool next_vm_id_wrapped =3D 0; static DEFINE_SPINLOCK(svm_vm_data_hash_lock); bool x2avic_enabled; =20 + +static void avic_set_x2apic_msr_interception(struct vcpu_svm *svm, + bool intercept) +{ + static const u32 x2avic_passthrough_msrs[] =3D { + X2APIC_MSR(APIC_ID), + X2APIC_MSR(APIC_LVR), + X2APIC_MSR(APIC_TASKPRI), + X2APIC_MSR(APIC_ARBPRI), + X2APIC_MSR(APIC_PROCPRI), + X2APIC_MSR(APIC_EOI), + X2APIC_MSR(APIC_RRR), + X2APIC_MSR(APIC_LDR), + X2APIC_MSR(APIC_DFR), + X2APIC_MSR(APIC_SPIV), + X2APIC_MSR(APIC_ISR), + X2APIC_MSR(APIC_TMR), + X2APIC_MSR(APIC_IRR), + X2APIC_MSR(APIC_ESR), + X2APIC_MSR(APIC_ICR), + X2APIC_MSR(APIC_ICR2), + + /* + * Note! Always intercept LVTT, as TSC-deadline timer mode + * isn't virtualized by hardware, and the CPU will generate a + * #GP instead of a #VMEXIT. + */ + X2APIC_MSR(APIC_LVTTHMR), + X2APIC_MSR(APIC_LVTPC), + X2APIC_MSR(APIC_LVT0), + X2APIC_MSR(APIC_LVT1), + X2APIC_MSR(APIC_LVTERR), + X2APIC_MSR(APIC_TMICT), + X2APIC_MSR(APIC_TMCCT), + X2APIC_MSR(APIC_TDCR), + }; + int i; + + if (intercept =3D=3D svm->x2avic_msrs_intercepted) + return; + + if (!x2avic_enabled) + return; + + for (i =3D 0; i < ARRAY_SIZE(x2avic_passthrough_msrs); i++) + svm_set_intercept_for_msr(&svm->vcpu, x2avic_passthrough_msrs[i], + MSR_TYPE_RW, intercept); + + svm->x2avic_msrs_intercepted =3D intercept; +} + static void avic_activate_vmcb(struct vcpu_svm *svm) { struct vmcb *vmcb =3D svm->vmcb01.ptr; @@ -99,7 +150,7 @@ static void avic_activate_vmcb(struct vcpu_svm *svm) vmcb->control.int_ctl |=3D X2APIC_MODE_MASK; vmcb->control.avic_physical_id |=3D X2AVIC_MAX_PHYSICAL_ID; /* Disabling MSR intercept for x2APIC registers */ - svm_set_x2apic_msr_interception(svm, false); + avic_set_x2apic_msr_interception(svm, false); } else { /* * Flush the TLB, the guest may have inserted a non-APIC @@ -110,7 +161,7 @@ static void avic_activate_vmcb(struct vcpu_svm *svm) /* For xAVIC and hybrid-xAVIC modes */ vmcb->control.avic_physical_id |=3D AVIC_MAX_PHYSICAL_ID; /* Enabling MSR intercept for x2APIC registers */ - svm_set_x2apic_msr_interception(svm, true); + avic_set_x2apic_msr_interception(svm, true); } } =20 @@ -130,7 +181,7 @@ static void avic_deactivate_vmcb(struct vcpu_svm *svm) return; =20 /* Enabling MSR intercept for x2APIC registers */ - svm_set_x2apic_msr_interception(svm, true); + avic_set_x2apic_msr_interception(svm, true); } =20 /* Note: diff --git a/arch/x86/kvm/svm/svm.c b/arch/x86/kvm/svm/svm.c index 67f4eed01526..3bcb88b2e617 100644 --- a/arch/x86/kvm/svm/svm.c +++ b/arch/x86/kvm/svm/svm.c @@ -736,55 +736,6 @@ static void svm_recalc_lbr_msr_intercepts(struct kvm_v= cpu *vcpu) svm_set_intercept_for_msr(vcpu, MSR_IA32_DEBUGCTLMSR, MSR_TYPE_RW, inter= cept); } =20 -void svm_set_x2apic_msr_interception(struct vcpu_svm *svm, bool intercept) -{ - static const u32 x2avic_passthrough_msrs[] =3D { - X2APIC_MSR(APIC_ID), - X2APIC_MSR(APIC_LVR), - X2APIC_MSR(APIC_TASKPRI), - X2APIC_MSR(APIC_ARBPRI), - X2APIC_MSR(APIC_PROCPRI), - X2APIC_MSR(APIC_EOI), - X2APIC_MSR(APIC_RRR), - X2APIC_MSR(APIC_LDR), - X2APIC_MSR(APIC_DFR), - X2APIC_MSR(APIC_SPIV), - X2APIC_MSR(APIC_ISR), - X2APIC_MSR(APIC_TMR), - X2APIC_MSR(APIC_IRR), - X2APIC_MSR(APIC_ESR), - X2APIC_MSR(APIC_ICR), - X2APIC_MSR(APIC_ICR2), - - /* - * Note! Always intercept LVTT, as TSC-deadline timer mode - * isn't virtualized by hardware, and the CPU will generate a - * #GP instead of a #VMEXIT. - */ - X2APIC_MSR(APIC_LVTTHMR), - X2APIC_MSR(APIC_LVTPC), - X2APIC_MSR(APIC_LVT0), - X2APIC_MSR(APIC_LVT1), - X2APIC_MSR(APIC_LVTERR), - X2APIC_MSR(APIC_TMICT), - X2APIC_MSR(APIC_TMCCT), - X2APIC_MSR(APIC_TDCR), - }; - int i; - - if (intercept =3D=3D svm->x2avic_msrs_intercepted) - return; - - if (!x2avic_enabled) - return; - - for (i =3D 0; i < ARRAY_SIZE(x2avic_passthrough_msrs); i++) - svm_set_intercept_for_msr(&svm->vcpu, x2avic_passthrough_msrs[i], - MSR_TYPE_RW, intercept); - - svm->x2avic_msrs_intercepted =3D intercept; -} - void svm_vcpu_free_msrpm(void *msrpm) { __free_pages(virt_to_page(msrpm), get_order(MSRPM_SIZE)); diff --git a/arch/x86/kvm/svm/svm.h b/arch/x86/kvm/svm/svm.h index 5d39c0b17988..1e612bbfd36d 100644 --- a/arch/x86/kvm/svm/svm.h +++ b/arch/x86/kvm/svm/svm.h @@ -699,7 +699,6 @@ void svm_set_gif(struct vcpu_svm *svm, bool value); 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charset="utf-8" Set the "allow_apicv_in_x2apic_without_x2apic_virtualization" flag as part of avic_hardware_setup() instead of handling in svm_hardware_setup(), and make x2avic_enabled local to avic.c (setting the flag was the only use in svm.c). Opportunistically tag avic_hardware_setup() with __init to make it clear that nothing untoward is happening with svm_x86_ops. No functional change intended (aside from the side effects of tagging avic_hardware_setup() with __init). Signed-off-by: Sean Christopherson Acked-by: Naveen N Rao (AMD) Tested-by: Naveen N Rao (AMD) --- arch/x86/kvm/svm/avic.c | 6 ++++-- arch/x86/kvm/svm/svm.c | 4 +--- arch/x86/kvm/svm/svm.h | 3 +-- 3 files changed, 6 insertions(+), 7 deletions(-) diff --git a/arch/x86/kvm/svm/avic.c b/arch/x86/kvm/svm/avic.c index 478a18208a76..683411442476 100644 --- a/arch/x86/kvm/svm/avic.c +++ b/arch/x86/kvm/svm/avic.c @@ -77,7 +77,7 @@ static DEFINE_HASHTABLE(svm_vm_data_hash, SVM_VM_DATA_HAS= H_BITS); static u32 next_vm_id =3D 0; static bool next_vm_id_wrapped =3D 0; static DEFINE_SPINLOCK(svm_vm_data_hash_lock); -bool x2avic_enabled; +static bool x2avic_enabled; =20 =20 static void avic_set_x2apic_msr_interception(struct vcpu_svm *svm, @@ -1147,7 +1147,7 @@ void avic_vcpu_unblocking(struct kvm_vcpu *vcpu) * - Hypervisor can support both xAVIC and x2AVIC in the same guest. * - The mode can be switched at run-time. */ -bool avic_hardware_setup(void) +bool __init avic_hardware_setup(struct kvm_x86_ops *svm_ops) { if (!npt_enabled) return false; @@ -1182,6 +1182,8 @@ bool avic_hardware_setup(void) x2avic_enabled =3D boot_cpu_has(X86_FEATURE_X2AVIC); if (x2avic_enabled) pr_info("x2AVIC enabled\n"); + else + svm_ops->allow_apicv_in_x2apic_without_x2apic_virtualization =3D true; =20 /* * Disable IPI virtualization for AMD Family 17h CPUs (Zen1 and Zen2) diff --git a/arch/x86/kvm/svm/svm.c b/arch/x86/kvm/svm/svm.c index 3bcb88b2e617..d4643dce7c91 100644 --- a/arch/x86/kvm/svm/svm.c +++ b/arch/x86/kvm/svm/svm.c @@ -5354,15 +5354,13 @@ static __init int svm_hardware_setup(void) goto err; } =20 - enable_apicv =3D avic =3D avic && avic_hardware_setup(); + enable_apicv =3D avic =3D avic && avic_hardware_setup(&svm_x86_ops); =20 if (!enable_apicv) { enable_ipiv =3D false; svm_x86_ops.vcpu_blocking =3D NULL; svm_x86_ops.vcpu_unblocking =3D NULL; svm_x86_ops.vcpu_get_apicv_inhibit_reasons =3D NULL; - } else if (!x2avic_enabled) { - svm_x86_ops.allow_apicv_in_x2apic_without_x2apic_virtualization =3D true; } =20 if (vls) { diff --git a/arch/x86/kvm/svm/svm.h b/arch/x86/kvm/svm/svm.h index 1e612bbfd36d..811513c8b566 100644 --- a/arch/x86/kvm/svm/svm.h +++ b/arch/x86/kvm/svm/svm.h @@ -48,7 +48,6 @@ extern bool npt_enabled; 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Thu, 18 Sep 2025 17:21:44 -0700 (PDT) Reply-To: Sean Christopherson Date: Thu, 18 Sep 2025 17:21:33 -0700 In-Reply-To: <20250919002136.1349663-1-seanjc@google.com> Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: Mime-Version: 1.0 References: <20250919002136.1349663-1-seanjc@google.com> X-Mailer: git-send-email 2.51.0.470.ga7dc726c21-goog Message-ID: <20250919002136.1349663-4-seanjc@google.com> Subject: [PATCH v3 3/6] KVM: SVM: Always print "AVIC enabled" separately, even when force enabled From: Sean Christopherson To: Sean Christopherson , Paolo Bonzini Cc: kvm@vger.kernel.org, linux-kernel@vger.kernel.org, Naveen N Rao Content-Transfer-Encoding: quoted-printable Content-Type: text/plain; charset="utf-8" Print the customary "AVIC enabled" informational message even when AVIC is force enabled on a system that doesn't advertise supported for AVIC in CPUID, as not printing the standard message can confuse users and tools. Opportunistically clean up the scary message when AVIC is force enabled, but keep it as separate message so that it is printed at level "warn", versus the standard message only being printed for level "info". Suggested-by: Naveen N Rao Signed-off-by: Sean Christopherson Reviewed-by: Naveen N Rao (AMD) Tested-by: Naveen N Rao (AMD) --- arch/x86/kvm/svm/avic.c | 19 +++++++++---------- 1 file changed, 9 insertions(+), 10 deletions(-) diff --git a/arch/x86/kvm/svm/avic.c b/arch/x86/kvm/svm/avic.c index 683411442476..bafef2f75af2 100644 --- a/arch/x86/kvm/svm/avic.c +++ b/arch/x86/kvm/svm/avic.c @@ -1167,16 +1167,15 @@ bool __init avic_hardware_setup(struct kvm_x86_ops = *svm_ops) return false; } =20 - if (boot_cpu_has(X86_FEATURE_AVIC)) { - pr_info("AVIC enabled\n"); - } else if (force_avic) { - /* - * Some older systems does not advertise AVIC support. - * See Revision Guide for specific AMD processor for more detail. - */ - pr_warn("AVIC is not supported in CPUID but force enabled"); - pr_warn("Your system might crash and burn"); - } + /* + * Print a scary message if AVIC is force enabled to make it abundantly + * clear that ignoring CPUID could have repercussions. See Revision + * Guide for specific AMD processor for more details. + */ + if (!boot_cpu_has(X86_FEATURE_AVIC)) + pr_warn("AVIC unsupported in CPUID but force enabled, your system might = crash and burn\n"); + + pr_info("AVIC enabled\n"); =20 /* AVIC is a prerequisite for x2AVIC. */ x2avic_enabled =3D boot_cpu_has(X86_FEATURE_X2AVIC); --=20 2.51.0.470.ga7dc726c21-goog From nobody Thu Oct 2 07:44:00 2025 Received: from mail-pj1-f74.google.com (mail-pj1-f74.google.com [209.85.216.74]) (using TLSv1.2 with cipher ECDHE-RSA-AES128-GCM-SHA256 (128/128 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id 441B21DF27F for ; Fri, 19 Sep 2025 00:21:46 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=none smtp.client-ip=209.85.216.74 ARC-Seal: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1758241307; cv=none; b=C8J05aro7ycF9pQhd/IokfE5/VA2qEul6KQIsPQQDd1WIjwDoO9J1hH8rGj2BrDjW3bNCUJJzBRRxhqM5aaVPBaAZAtlu3Bu9dczwWilYIBNYxk39Rcn5CS5GCqcboJeSQi76UInjRkqeP9iDNVusXcCRAoUtWvMKFzqQIuITjI= ARC-Message-Signature: i=1; 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charset="utf-8" Don't advise the end user to try to force enable AVIC when x2AVIC is reported as supported in CPUID, as forcefully enabling AVIC isn't something that should be done lightly. E.g. some Zen4 client systems hide AVIC but leave x2AVIC behind, and while such a configuration is indeed due to buggy firmware in the sense the reporting x2AVIC without AVIC is nonsensical, KVM has no idea _why_ firmware disabled AVIC in the first place. Suggesting that the user try to run with force_avic=3Dy is sketchy even if the user explicitly tries to enable AVIC, and will be downright irresponsible once KVM starts enabling AVIC by default. Alternatively, KVM could print the message only when the user explicitly asks for AVIC, but running with force_avic=3Dy isn't something that should be encouraged for random users. force_avic is a useful knob for developers and perhaps even advanced users, but isn't something that KVM should advertise broadly. Opportunistically append a newline to the pr_warn() so that it prints out immediately, and tweak the message to say that AVIC is unsupported instead of disabled (disabled suggests that the kernel/KVM is somehow responsible). Suggested-by: Naveen N Rao Signed-off-by: Sean Christopherson Reviewed-by: Naveen N Rao (AMD) Suggested-by: Naveen N Rao (AMD) Tested-by: Naveen N Rao (AMD) --- arch/x86/kvm/svm/avic.c | 6 ++---- 1 file changed, 2 insertions(+), 4 deletions(-) diff --git a/arch/x86/kvm/svm/avic.c b/arch/x86/kvm/svm/avic.c index bafef2f75af2..497d755c206f 100644 --- a/arch/x86/kvm/svm/avic.c +++ b/arch/x86/kvm/svm/avic.c @@ -1154,10 +1154,8 @@ bool __init avic_hardware_setup(struct kvm_x86_ops *= svm_ops) =20 /* AVIC is a prerequisite for x2AVIC. */ if (!boot_cpu_has(X86_FEATURE_AVIC) && !force_avic) { - if (boot_cpu_has(X86_FEATURE_X2AVIC)) { - pr_warn(FW_BUG "Cannot support x2AVIC due to AVIC is disabled"); - pr_warn(FW_BUG "Try enable AVIC using force_avic option"); - } + if (boot_cpu_has(X86_FEATURE_X2AVIC)) + pr_warn(FW_BUG "Cannot enable x2AVIC, AVIC is unsupported\n"); return false; } =20 --=20 2.51.0.470.ga7dc726c21-goog From nobody Thu Oct 2 07:44:00 2025 Received: from mail-pj1-f74.google.com (mail-pj1-f74.google.com [209.85.216.74]) (using TLSv1.2 with cipher ECDHE-RSA-AES128-GCM-SHA256 (128/128 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id CE283242D90 for ; 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Thu, 18 Sep 2025 17:21:47 -0700 (PDT) Reply-To: Sean Christopherson Date: Thu, 18 Sep 2025 17:21:35 -0700 In-Reply-To: <20250919002136.1349663-1-seanjc@google.com> Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: Mime-Version: 1.0 References: <20250919002136.1349663-1-seanjc@google.com> X-Mailer: git-send-email 2.51.0.470.ga7dc726c21-goog Message-ID: <20250919002136.1349663-6-seanjc@google.com> Subject: [PATCH v3 5/6] KVM: SVM: Move global "avic" variable to avic.c From: Sean Christopherson To: Sean Christopherson , Paolo Bonzini Cc: kvm@vger.kernel.org, linux-kernel@vger.kernel.org, Naveen N Rao Content-Transfer-Encoding: quoted-printable Content-Type: text/plain; charset="utf-8" Move "avic" to avic.c so that it's colocated with the other AVIC specific globals and module params, and so that avic_hardware_setup() is a bit more self-contained, e.g. similar to sev_hardware_setup(). Deliberately set enable_apicv in svm.c as it's already globally visible (defined by kvm.ko, not by kvm-amd.ko), and to clearly capture the dependency on enable_apicv being initialized (svm_hardware_setup() clears several AVIC-specific hooks when enable_apicv is disabled). Alternatively, clearing of the hooks (and enable_ipiv) could be moved to avic_hardware_setup(), but that's not obviously better, e.g. it's helpful to isolate the setting of enable_apicv when reading code from the generic x86 side of the world. No functional change intended. Cc: Naveen N Rao (AMD) Signed-off-by: Sean Christopherson Acked-by: Naveen N Rao (AMD) Tested-by: Naveen N Rao (AMD) --- arch/x86/kvm/svm/avic.c | 32 ++++++++++++++++++++++++-------- arch/x86/kvm/svm/svm.c | 11 +---------- 2 files changed, 25 insertions(+), 18 deletions(-) diff --git a/arch/x86/kvm/svm/avic.c b/arch/x86/kvm/svm/avic.c index 497d755c206f..e059dcae6945 100644 --- a/arch/x86/kvm/svm/avic.c +++ b/arch/x86/kvm/svm/avic.c @@ -64,6 +64,14 @@ =20 static_assert(__AVIC_GATAG(AVIC_VM_ID_MASK, AVIC_VCPU_IDX_MASK) =3D=3D -1u= ); =20 +/* + * enable / disable AVIC. Because the defaults differ for APICv + * support between VMX and SVM we cannot use module_param_named. + */ +static bool avic; +module_param(avic, bool, 0444); +module_param(enable_ipiv, bool, 0444); + static bool force_avic; module_param_unsafe(force_avic, bool, 0444); =20 @@ -1141,15 +1149,9 @@ void avic_vcpu_unblocking(struct kvm_vcpu *vcpu) avic_vcpu_load(vcpu, vcpu->cpu); } =20 -/* - * Note: - * - The module param avic enable both xAPIC and x2APIC mode. - * - Hypervisor can support both xAVIC and x2AVIC in the same guest. - * - The mode can be switched at run-time. - */ -bool __init avic_hardware_setup(struct kvm_x86_ops *svm_ops) +static bool __init avic_want_avic_enable(void) { - if (!npt_enabled) + if (!avic || !npt_enabled) return false; =20 /* AVIC is a prerequisite for x2AVIC. */ @@ -1174,6 +1176,20 @@ bool __init avic_hardware_setup(struct kvm_x86_ops *= svm_ops) pr_warn("AVIC unsupported in CPUID but force enabled, your system might = crash and burn\n"); =20 pr_info("AVIC enabled\n"); + return true; +} + +/* + * Note: + * - The module param avic enable both xAPIC and x2APIC mode. + * - Hypervisor can support both xAVIC and x2AVIC in the same guest. + * - The mode can be switched at run-time. + */ +bool __init avic_hardware_setup(struct kvm_x86_ops *svm_ops) +{ + avic =3D avic_want_avic_enable(); + if (!avic) + return false; =20 /* AVIC is a prerequisite for x2AVIC. */ x2avic_enabled =3D boot_cpu_has(X86_FEATURE_X2AVIC); diff --git a/arch/x86/kvm/svm/svm.c b/arch/x86/kvm/svm/svm.c index d4643dce7c91..c473246f8881 100644 --- a/arch/x86/kvm/svm/svm.c +++ b/arch/x86/kvm/svm/svm.c @@ -158,14 +158,6 @@ module_param(lbrv, int, 0444); static int tsc_scaling =3D true; module_param(tsc_scaling, int, 0444); =20 -/* - * enable / disable AVIC. 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Thu, 18 Sep 2025 17:21:50 -0700 (PDT) Reply-To: Sean Christopherson Date: Thu, 18 Sep 2025 17:21:36 -0700 In-Reply-To: <20250919002136.1349663-1-seanjc@google.com> Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: Mime-Version: 1.0 References: <20250919002136.1349663-1-seanjc@google.com> X-Mailer: git-send-email 2.51.0.470.ga7dc726c21-goog Message-ID: <20250919002136.1349663-7-seanjc@google.com> Subject: [PATCH v3 6/6] KVM: SVM: Enable AVIC by default for Zen4+ if x2AVIC is support From: Sean Christopherson To: Sean Christopherson , Paolo Bonzini Cc: kvm@vger.kernel.org, linux-kernel@vger.kernel.org, Naveen N Rao Content-Transfer-Encoding: quoted-printable Content-Type: text/plain; charset="utf-8" From: Naveen N Rao AVIC and x2AVIC are fully functional since Zen 4, with no known hardware errata. Enable AVIC and x2AVIC by default on Zen4+ so long as x2AVIC is supported (to avoid enabling partial support for APIC virtualization by default). Internally, convert "avic" to an integer so that KVM can identify if the user has asked to explicitly enable or disable AVIC, i.e. so that KVM doesn't override an explicit 'y' from the user. Arbitrarily use -1 to denote auto-mode, and accept the string "auto" for the module param in addition to standard boolean values, i.e. continue to allow to the user configure the "avic" module parameter to explicitly enable/disable AVIC. To again maintain backward compatibility with a standard boolean param, set KERNEL_PARAM_OPS_FL_NOARG, which tells the params infrastructure to allow empty values for %true, i.e. to interpret a bare "avic" as "avic=3Dy". Take care to check for a NULL @val when looking for "auto"! Lastly, always print "avic" as a boolean, since auto-mode is resolved during module initialization, i.e. the user should never see "auto" in sysfs. Signed-off-by: Naveen N Rao (AMD) Co-developed-by: Sean Christopherson Signed-off-by: Sean Christopherson Tested-by: Naveen N Rao (AMD) --- arch/x86/kvm/svm/avic.c | 39 +++++++++++++++++++++++++++++++++++---- 1 file changed, 35 insertions(+), 4 deletions(-) diff --git a/arch/x86/kvm/svm/avic.c b/arch/x86/kvm/svm/avic.c index e059dcae6945..5cccee755213 100644 --- a/arch/x86/kvm/svm/avic.c +++ b/arch/x86/kvm/svm/avic.c @@ -64,12 +64,31 @@ =20 static_assert(__AVIC_GATAG(AVIC_VM_ID_MASK, AVIC_VCPU_IDX_MASK) =3D=3D -1u= ); =20 +#define AVIC_AUTO_MODE -1 + +static int avic_param_set(const char *val, const struct kernel_param *kp) +{ + if (val && sysfs_streq(val, "auto")) { + *(int *)kp->arg =3D AVIC_AUTO_MODE; + return 0; + } + + return param_set_bint(val, kp); +} +static const struct kernel_param_ops avic_ops =3D { + .flags =3D KERNEL_PARAM_OPS_FL_NOARG, + .set =3D avic_param_set, + .get =3D param_get_bool, +}; + /* - * enable / disable AVIC. Because the defaults differ for APICv - * support between VMX and SVM we cannot use module_param_named. + * Enable / disable AVIC. In "auto" mode (default behavior), AVIC is enab= led + * for Zen4+ CPUs with x2AVIC (and all other criteria for enablement are m= et). */ -static bool avic; -module_param(avic, bool, 0444); +static int avic =3D AVIC_AUTO_MODE; +module_param_cb(avic, &avic_ops, &avic, 0444); +__MODULE_PARM_TYPE(avic, "bool"); + module_param(enable_ipiv, bool, 0444); =20 static bool force_avic; @@ -1151,6 +1170,18 @@ void avic_vcpu_unblocking(struct kvm_vcpu *vcpu) =20 static bool __init avic_want_avic_enable(void) { + /* + * In "auto" mode, enable AVIC by default for Zen4+ if x2AVIC is + * supported (to avoid enabling partial support by default, and because + * x2AVIC should be supported by all Zen4+ CPUs). Explicitly check for + * family 0x19 and later (Zen5+), as the kernel's synthetic ZenX flags + * aren't inclusive of previous generations, i.e. the kernel will set + * at most one ZenX feature flag. + */ + if (avic =3D=3D AVIC_AUTO_MODE) + avic =3D boot_cpu_has(X86_FEATURE_X2AVIC) && + (boot_cpu_data.x86 > 0x19 || cpu_feature_enabled(X86_FEATURE_ZEN4= )); + if (!avic || !npt_enabled) return false; =20 --=20 2.51.0.470.ga7dc726c21-goog